AD9481-PCB

8-Bit, 250 MSPS 3.3 V A/D Converter AD9481 FEATURES DNL = ±0.35 LSB INL = ±0.26 LSB Single 3.3 V supply operation (3.0 V to 3.6 V) Power dissipation of 439 mW at 250 MSPS 1 V p-p analog input range Internal 1.0 V reference Single-ended or differential analog inputs De-multiplexed CMOS outputs Power-down mode Clock duty cycle stabilizer FUNCTIONAL BLOCK DIAGRAM VREF SENSE AGND DRGND DRVDD AVDD REFERENCE AD9481 PORT A 8 D7A TO D0A VIN+ VIN– DS+ DS– CLK+ CLK– T AND H 8-BIT ADC PIPELINE CORE 8 PORT B 8 D7B TO D0B CLOCK MGMT DCO+ DCO– LOGIC 05045-001 APPLICATIONS Digital oscilloscopes Instrumentation and measurement Communications Point-to-point radios Digital predistortion loops PDWN S1 Figure 1. GENERAL DESCRIPTION The AD9481 is an 8-bit, monolithic analog-to-digital converter (ADC) optimized for high speed and low power consumption. Small in size and easy to use, the product operates at a 250 MSPS conversion rate, with excellent linearity and dynamic performance over its full operating range. To minimize system cost and power dissipation, the AD9481 includes an internal reference and track-and-hold circuit. The user only provides a 3.3 V power supply and a differential encode clock. No external reference or driver components are required for many applications. The digital outputs are TTL/CMOS-compatible with an option of twos complement or binar y output format. The output data bits are provided in an interleaved fashion along with output clocks that simplifies data capture. The AD9481 is available in a Pb-free, 44-lead, surface-mount package (TQFP-44) specified over the industrial temperature range (−40°C to +85°C). PRODUCT HIGHLIGHTS 1. Superior linearity. A DNL of ±0.35 makes the AD9481 suitable for many instrumentation and measurement applications 2. Power-down mode. A power-down function may be exercised to bring total consumption down to 15 mW. 3. De-multiplexed CMOS outputs allow for easy interfacing with low cost FPGAs and standard logic. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD9481 TABLE OF CONTENTS DC Specifications ............................................................................. 3 Digital Specifications........................................................................ 4 AC Specifications .............................................................................. 5 Switching Specifications .................................................................. 6 Timing Diagram ........................................................................... 7 Absolute Maximum Ratings............................................................ 8 Explanation of Test Levels ........................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Descriptions ............................. 9 Terminology .................................................................................... 10 Typical Performance Characteristics ........................................... 12 Equivalent Circuits ......................................................................... 16 Applications ..................................................................................... 17 Analog Inputs .............................................................................. 17 Voltage Reference ....................................................................... 17 Clocking the AD9481................................................................. 19 DS Inputs ..................................................................................... 19 Digital Outputs ........................................................................... 20 Interleaving Two AD9481s ........................................................ 20 Data Clock Out ........................................................................... 20 Power-Down Input..................................................................... 20 AD9481 Evaluation Board ............................................................ 21 Power Connector........................................................................ 21 Analog Inputs.............................................................................. 21 Gain .............................................................................................. 21 Optional Operational Amplifier ............................................... 21 Clock ............................................................................................ 21 Optional Clock Buffer ............................................................... 21 DS ................................................................................................. 21 Optional XTAL ........................................................................... 22 Voltage Reference ....................................................................... 22 Data Outputs ............................................................................... 22 Evaluation Board Bill of Materials (BOM) ................................. 23 PCB Schematics .............................................................................. 24 PCB Layers ...................................................................................... 26 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28 REVISION HISTORY 10/04—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD9481 DC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference REFERENCE Internal Reference Voltage Output Current2 IVREF Input Current3 ISENSE Input Current2 ANALOG INPUTS (VIN+, VIN−) Differential Input Voltage Range4 Common-Mode Voltage Input Resistance Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD Supply Currents IAVDD5 IDRVDD5 Power Dissipation5 Power-Down Dissipation Power Supply Rejection Ratio (PSRR) Temp Test Level Min AD9481-250 Typ 8 Guaranteed −40 −6.0 −0.85 −0.9 40 6.0 0.85 0.9 mV % FS LSB LSB µV/°C % FS/°C mV/°C 1.03 1.5 100 10 V mA µA µA V p-p V kΩ pF MHz V V Max Unit Bits Full 25°C 25°C Full Full Full Full Full Full 25°C 25°C 25°C Full Full Full 25°C 25°C Full Full VI I I VI VI V V V VI IV I I V VI VI V V IV IV ±0.35 ±0.26 30 0.03 ±0.025 0.97 1.0 1.6 8.4 1 1.9 10 4 750 3.3 3.3 2.1 11.2 3.0 3.0 3.6 3.6 Full Full 25°C 25°C 25°C VI VI V V V 133 39 439 15 −4.2 145 42.5 37 mA mA mW mW mV/V 1 2 3 Gain error and gain temperature coefficients are based on the ADC only (with a fixed 1 V external reference and 1 V p-p input range). Internal reference mode; SENSE = AGND. External reference mode; VREF driven by external 1.0 V reference; SENSE = AVDD. 4 In FS = 1 V, both analog inputs are 500 mV p-p and out of phase with each other. 5 Supply current measured with rated encode and a 20 MHz analog input. Power dissipation measured with dc input, see the Terminology section for power vs. clock rate. Rev. 0 | Page 3 of 28 AD9481 DIGITAL SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 2. Parameter CLOCK AND DS INPUTS (CLK+, CLK−, DS+, DS−) Differential Input Common-Mode Voltage1 Input Resistance Input Capacitance LOGIC INPUTS (PDWN, S1) Logic 1 Voltage Logic 0 Voltage Logic 1 Input Current Logic 0 input Current Input Resistance Input Capacitance DIGITAL OUTPUTS Logic 1 Voltage2 Logic 0 Voltage Output Coding Temp Full Full Full 25°C Full Full Full Full 25°C 25°C Full Full Full Test Level IV VI VI V IV IV VI VI V V VI VI IV Min 200 1.38 4.2 AD9481-250 Typ Max Unit mV p-p V kΩ pF V V µA µA kΩ pF mV V 1.5 5.5 4 1.68 6.0 2.0 0.8 ±160 10 30 4 DRVDD − 0.05 0.05 Twos complement or binary 1 2 The common mode for CLOCK inputs can be externally set, such that 0.9 V < CLK ± < 2.6 V. Capacitive loading only. Rev. 0 | Page 4 of 28 AD9481 AC SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; TMIN = −40°C, TMAX = +85°C, AIN = −1 dBFS, full scale = 1.0 V, internal reference, differential analog and clock inputs, unless otherwise noted. Table 3. Parameter SIGNAL-TO-NOISE RATIO (SNR) fIN = 19.7 MHz fIN = 70.1 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 19.7 MHz fIN = 70.1 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 19.7 MHz fIN = 70.1 MHz WORST SECOND OR THIRD HARMONIC DISTORTION fIN = 19.7 MHz fIN = 70.1 MHz WORST OTHER fIN = 19.7 MHz fIN = 70.1 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR)1 fIN = 19.7 MHz fIN = 70.1 MHz TWO-TONE INTERMODULATION DISTORTION (IMD) fIN1 = 69.3 MHz, fIN2 = 70.3 MHz Temp 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Test Level V I V I V I V I V I V I V Min AD9481-250 Typ Max 46 45.7 45.9 45.7 7.5 7.5 −64.8 −64.8 −68 −65.8 −64.8 −64.8 −64.9 Unit dB dB dB dB Bits Bits dBc dBc dBc dBc dBc dBc dBc 44.5 44.4 7.2 −54 −56 −54 1 DC and Nyquist bin energy ignored. Rev. 0 | Page 5 of 28 AD9481 SWITCHING SPECIFICATIONS AVDD = 3.3 V, DRVDD = 3.3 V; differential encode input, duty cycle stabilizer enabled, unless otherwise noted. Table 4. Parameter CLOCK Maximum Conversion Rate Minimum Conversion Rate Clock Pulse-Width High (tEH) Clock Pulse-Width Low (tEL) DS Input Setup Time (tSDS) DS Input Hold Time (tHDS) OUTPUT PARAMETERS1 Valid Time (tV)2 Propagation Delay (tPD) Rise Time (tR) 10% to 90% Fall Time (tF) 10% to 90% DCO Propagation Delay (tCPD) 3 Data-to-DCO Skew (tPD − tCPD)4 A Port Data to DCO− Rising (tSKA)5 B Port Data to DCO+ Rising (tSKB) Pipeline Latency (A, B) APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) OUT-OF-RANGE RECOVERY TIME Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C 25°C Test Level VI IV IV IV IV IV VI VI V V VI VI IV IV IV V V V Min 250 20 1.2 1.2 0.5 0.5 2.5 4 670 360 3.9 4 4 8 1.5 0.25 1 5.4 2 2 AD9481-250 Typ Max Unit MSPS MSPS ns ns ns ns ns ns ps ps ns ns ns ns Cycles ns ps rms Cycle 2.5 −0.5 5.3 +0.5 1 2 CLOAD equals 5 pF maximum for all output switching specifications. Valid time is approximately equal to minimum tPD. 3 TCPD equals clock rising edge to DCO (+ or −) rising edge delay. 4 Data changing to (DCO+ or DCO−) rising edge delay. 5 TSKA, TSKB are both clock rate dependent delays equal to TCYCLE − (Data to DCO skew). Rev. 0 | Page 6 of 28 AD9481 TIMING DIAGRAM N–1 N VIN tA N+8 N+1 8 CYCLES N+9 N+10 N+7 tEH CLK+ CLK– tEL 1/fS tHDS DS+ DS– tSDS tPD INVALID N tV INTERLEAVED DATA OUT PORT A STATIC D7A TO D0A PORT B D7B TO D0B STATIC INVALID INVALID N+1 tSKA tCPD DCO+ DCO– STATIC tSKB 05045-002 Figure 2. Timing Diagram Rev. 0 | Page 7 of 28 AD9481 ABSOLUTE MAXIMUM RATINGS Thermal impedance (θJA) = 46.4°C/W (4-layer PCB). Table 5. Parameter ELECTRICAL AVDD (With respect to AGND) DRVDD (With respect to DRGND) AGND (With respect to DRGND) Digital I/0 (With respect to DRGND) Analog Inputs (With respect to AGND) ENVIRONMENTAL Operating Temperature Junction Temperature Storage Temperature Min. Rating −0.5 V −0.5 V −0.5 V −0.5 V −0.5 V Max. Rating +4.0 V +4.0 V +0.5 V DRVDD + 0.5 V AVDD + 0.5 V EXPLANATION OF TEST LEVELS Table 6. Level I II III IV V VI Description 100% production tested. 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. −40°C +85°C 150°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 8 of 28 AD9481 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AGND AGND AGND AVDD AVDD 44 43 42 41 40 39 38 37 36 35 34 CLK+ 1 PIN 1 VREF 33 32 31 VIN+ VIN– DS+ DS– S3 SENSE AGND AVDD AVDD PDWN S1 DRGND D7B (MSB) D6B D5B D4B CLK– 2 AVDD 3 AGND 4 DRVDD 5 DRGND 6 D7A (MSB) 7 D6A 8 D5A 9 D4A 10 D3A 11 AD9481 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 D2A D1A D1B D2B DCO– D0A (LSB) DCO+ D0B (LSB) DRGND DRVDD D3B Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name CLK+ CLK− AVDD AGND DRVDD DRGND D7A D6A D5A D4A D3A D2A D1A D0A DRGND DCO− DCO+ DRVDD D0B D1B D2B D3B D4B D5B Description Input Clock—True Input Clock—Complement 3.3 V Analog Supply Analog Ground 3.3 V Digital Output Supply Digital Ground Data Output Bit 7—Channel A (MSB) Data Output Bit 6—Channel A Data Output Bit 5—Channel A Data Output Bit 4—Channel A Data Output Bit 3—Channel A Data Output Bit 2—Channel A Data Output Bit 1—Channel A Data Output Bit 0—Channel A (LSB) Digital Ground Data Clock Output—Complement Data Clock Output—True 3.3 V Digital Output Supply Data Output Bit 0—Channel B (LSB) Data Output Bit 1—Channel B Data Output Bit 2—Channel B Data Output Bit 3—Channel B Data Output Bit 4—Channel B Data Output Bit 5—Channel B Pin No. 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Name D6B D7B DRGND S1 PDWN AVDD AVDD AGND SENSE VREF AGND AVDD AGND VIN− VIN+ AGND AVDD S3 DS− DS+ Description Data Output Bit 6—Channel B Data Output Bit 7—Channel B (MSB) Digital Ground Data Format Select and Duty Cycle Stabilizer Select Power-Down Selection 3.3 V Analog Supply 3.3 V Analog Supply Analog Ground Reference Mode Selection Voltage Reference Input/Output Analog Ground 3.3 V Analog Supply Analog Ground Analog Input—Complement Analog Input—True Analog Ground 3.3 V Analog Supply DCO Enable Select (Tie to AVDD for DCO Active) Data Sync Complement (If Unused, Tie to DRVDD) Data Sync True (If Unused, Tie to DGND) Rev. 0 | Page 9 of 28 05045-003 AD9481 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the encode command and the instant the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Clock Pulse-Width/Duty Cycle Pulse-width high is the minimum amount of time that the clock pulse should be left in a Logic 1 state to achieve rated performance; pulse-width low is the minimum time clock pulse should be left in a low state. See timing implications of changing tEH in the Clocking the AD9481 section. At a given clock rate, these specifications define an acceptable clock duty cycle. Crosstalk Coupling onto one channel being driven by a low level (−40 dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by obser ving the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the inputs phase 180° and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) ENOB is calculated from the measured SINAD based on the equation (assuming full-scale input) Full-Scale Input Power Expressed in dBm. Computed using the following equation ⎛ V 2 FULLSCALE rms ⎜ Z INPUT ⎜ PowerFULLSCALE = 10 log ⎜ 0.001 ⎜ ⎜ ⎝ ⎞ ⎟ ⎟ ⎟ ⎟ ⎟ ⎠ Gain Error Gain error is the difference between the measured and ideal full-scale input voltage range of the ADC. Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square cur ve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK− and the time when all output data bits are within valid logic levels. Noise (for Any Range within the ADC) This value includes both thermal and quantization noise. − SNRdBc − SignaldBFS ⎛ FS Vnoise = Z × 0 .001 × 10 ⎜ dBm ⎜ 10 ⎝ where: Z is the input impedance. ⎞ ⎟ ⎟ ⎠ SINADMEASURED − 1.76 dB ENOB = 6.02 FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in dB below full scale. Rev. 0 | Page 10 of 28 AD9481 Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (degrades as signal level is lowered) or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. It also may be reported in dBc (degrades as signal level is lowered) or in dBFS (always relates back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonic), reported in dBc. Transient Response Time The time it takes for the ADC to reacquire the analog input after a transient from 10% above negative full scale to 10% below positive full scale. Out-of-Range Recovery Time This is the time it takes for the ADC to reacquire the analog input after a transient from 10% above positive full scale to 10% above negative full scale, or from 10% below negative full scale to 10% below positive full scale. Rev. 0 | Page 11 of 28 AD9481 TYPICAL PERFORMANCE CHARACTERISTICS AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, FS = 1, internal reference mode, unless other wise noted. 0 –10 –20 –30 –40 (dB) 0 SNR = 45.8dB H2 = –65.2dBc H3 = –63.2dBc SFDR = 63.2dBc –10 –20 –30 –40 (dB) SNR = 45.6dB H2 = –72.9dBc H3 = –65.2dBc SFDR = 59.6dBc –50 –60 –70 05045-004 –50 –60 –70 –80 –90 0 20 40 60 (MHz) 80 100 120 05045-007 –80 –90 0 20 40 60 (MHz) 80 100 120 Figure 4. FFT: fS = 250 MSPS, AIN = 10.3 MHz @ −1 dBFS 0 –10 –20 –30 –40 (dB) (dB) 65 60 90 Figure 7. FFT: fS = 250 MSPS, AIN = 170 MHz @ −1 dBFS SNR = 45.8dB H2 = –68.5dBc H3 = –63.5dBc SFDR = 63.8dBc 85 80 H3 75 70 H2 –50 –60 –70 –80 –90 0 20 40 60 (MHz) 80 100 120 05045-005 55 SFDR 50 45 40 0 50 100 150 SINAD 200 250 AIN (MHz) 300 350 05045-008 SNR 400 Figure 5. FFT: fS = 250 MSPS, AIN = 70 MHz @ −1 dBFS Figure 8. Analog Input Frequency Sweep, AIN = −1 dBFS, FS = 1 V, fS = 250 MSPS 90 0 –10 –20 –30 –40 (dB) (dB) SNR = 45.9dB H2 = –66.6dBc H3 = –70.1dBc SFDR = 65.9dBc 85 80 75 70 65 60 H3 H2 –50 –60 –70 –80 –90 0 20 40 60 (MHz) 80 100 120 05045-006 SFDR 55 50 45 40 0 50 100 150 05045-009 SNR SINAD 200 250 AIN (MHz) 300 350 400 Figure 6. FFT: fS = 250 MSPS, AIN = 70 MHz @ −1 dBFS, Single-Ended Input Figure 9. Analog Input Frequency Sweep, AIN =−1 dBFS, FS = 0.75 V, fS = 250 MSPS, External VREF Mode Rev. 0 | Page 12 of 28 AD9481 75 140 70 SFDR 65 60 (dB) CURRENT (mA) IAVDD 120 100 80 60 40 SNR SINAD 05045-010 55 50 IDRVDD 05045-013 45 40 0 50 20 0 0 50 100 150 200 SAMPLE CLOCK (MSPS) 250 100 150 200 SAMPLE CLOCK (MHz) 250 300 300 Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency, AIN = 70 MHz @ −1 dB 80 70 SFDR (dBFS) 60 Figure 13. IAVDD and IDRVDD vs. Clock Rate, CLOAD = 5 pF AIN = 70 MHz @ −1 dBFS 50 49 48 DCS ON 47 50 (dB) 46 (dB) 40 SFDR (dBc) 30 20 05045-011 45 44 DCS OFF 43 41 40 20 30 40 50 60 70 CLOCK POSITIVE DUTY CYCLE (%) 80 0 –70 –60 –50 –40 –30 –20 –10 ANALOG INPUT DRIVE LEVEL (dBFS) 0 Figure 11. SFDR vs. AIN Input Level; AIN = 70 MHz @ 250 MSPS Figure 14. SNR, SINAD vs. Clock Pulse-Width High, AIN = 70 MHz @ −1 dBFS, 250 MSPS, DCS On/Off 50.0 75 0 –10 –20 F1, F2 = –7dBFS 2F2–F1 = –65.9dBc 2F1–F2 = –64.9dBc 47.5 SNR 70 SNR, SINAD (dB) –30 –40 (dB) SINAD 45.0 SFDR 42.5 60 65 –50 –60 –70 05045-012 –80 –90 0 20 40 60 (MHz) 80 100 120 40.0 0.5 55 0.7 0.9 1.1 1.3 1.5 1.7 EXTERNAL VREF VOLTAGE (V) 1.9 Figure 12. Two-Tone Intermodulation Distortion (69.3 MHz and 70.3 MHz; fS = 250 MSPS) Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode, AIN = 70 MHz @ −1 dBFS, 250 MSPS Rev. 0 | Page 13 of 28 05045-015 SFDR (dBc) 05045-014 10 60dB REFERENCE LINE 42 AD9481 2.0 1.5 FS = 1V EXTERNAL REFERENCE 1.0 GAIN ERROR (%) 70 65 SFDR 60 (dB) 0.5 0 –0.5 –1.0 FS = 1V INTERNAL REFERENCE 05045-016 55 50 SINAD 05045-019 –1.5 –2.0 –40 SNR –20 0 20 40 TEMPERATURE (°C) 60 80 45 3.0 3.1 3.2 3.3 AVDD (V) 3.4 3.5 3.6 Figure 16. Full-Scale Gain Error vs. Temperature, AIN = 70.3 MHz @ −0.5 dBFS, 250 MSPS 70 0.5 0.4 65 SFDR 60 0.3 0.2 0.1 (dB) Figure 19. SNR, SINAD, and SFDR vs. Supply Voltage, AIN = 70.3 MHz @ −1 dBFS, 250 MSPS 55 LSB 0 –0.1 50 SINAD 45 05045-017 –0.2 –0.3 –0.4 –0.5 0 50 100 CODE 150 200 250 05045-020 40 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 Figure 17. SINAD, SFDR vs. Temperature, AIN = 70 MHz @ −1 dBFS, 250 MSPS 0.10 0.50 Figure 20. Typical DNL Plot, AIN = 10.3 MHz @ −0.5 dBFS, 250 MSPS 0.05 0.25 CHANGE IN VREF (%) 0 LSB 05045-018 0 –0.05 –0.25 –0.10 05045-021 –0.15 2.7 –0.50 0 50 100 CODE 150 200 250 2.8 2.9 3.0 3.1 3.2 AVDD (V) 3.3 3.4 3.5 3.6 Figure 18. VREF Sensitivity to AVDD Figure 21. Typical INL Plot, AIN = 10.3 MHz @ −0.5 dBFS, 250 MSPS Rev. 0 | Page 14 of 28 AD9481 0.2 TPD_F 0.1 DELAY CHANGE (ps) TCPD_F 0 –0.1 –0.2 TCPD_R –0.3 TPD_R –0.4 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 05045-048 Figure 22. Propagation Delay Sensitivity vs. Temperature Rev. 0 | Page 15 of 28 AD9481 EQUIVALENT CIRCUITS AVDD AVDD 16.7kΩ 150Ω VIN+ 25kΩ 1.2pF 16.7kΩ 150Ω VIN– 25kΩ 1.2pF 05045-023 PDWN 30kΩ 05045-026 Figure 23. Analog Inputs AVDD Figure 26. Power-Down Input DRVDD 12kΩ CLK+ 12kΩ CLK– 05045-027 150Ω 150Ω 10kΩ 10kΩ Figure 27. Data, DCO Outputs 05045-024 Figure 24. Clock Inputs VDD 30kΩ S1 Figure 25. S1 Input 05045-025 Rev. 0 | Page 16 of 28 AD9481 APPLICATIONS The AD9481 uses a 1.5 bit per stage architecture. The analog inputs drive an integrated high bandwidth track-and-hold circuit that samples the signal prior to quantization by the 8-bit core. For ease of use, the part includes an on-board reference and input logic that accepts TTL, CMOS, or LVPECL levels. The digital output logic levels are CMOS-compatible. 49.9Ω 499Ω 1.3kΩ 523Ω 0.1µF 2kΩ 499Ω 499Ω 33Ω AVDD VIN+ AD8138 20pF 33Ω AD9481 VIN– 05045-030 AGND ANALOG INPUTS The analog input to the AD9481 is a differential buffer. For best dynamic performance, impedances at VIN+ and VIN− should match. Optimal performance is obtained when the analog inputs are driven differentially. SNR and SINAD performance can degrade if the analog input is driven with a single-ended signal. The analog inputs self-bias to approximately 1.9 V; this common-mode voltage can be externally overdriven by approximately ±300 mV if required. A wideband transformer, such as the Mini-Circuits ADT1-1WT, can provide the differential analog inputs for applications that require a single-ended-to-differential conversion. Note that the filter and center-tap capacitor on the secondar y side is optional and dependent on application requirements. An RC filter at the secondar y side helps reduce any wideband noise getting aliased by the ADC. (R, C OPTIONAL) 33Ω 49.9Ω 10pF 33Ω AVDD VIN+ Figure 29. Driving the ADC with the AD8138 The AD9481 can be easily configured for different full-scale ranges. See the Voltage Reference section for more information. Optimal performance is achieved with a 1 V p-p analog input. SENSE = GND VIN+ 500mV 2.0V 2.0V VIN– DIGITALOUT = ALL 1s DIGITALOUT = ALL 0s 05045-031 Figure 30. Analog Input Full Scale AD9481 VIN– AGND 05045-029 VOLTAGE REFERENCE A stable and accurate 1.0 V reference is built into the AD9481. Users can choose this internal reference or provide an external reference for greater accuracy and flexibility. Figure 32 shows the typical reference variation with temperature. Table 8 summarizes the available reference configurations. VIN+ VIN– 0.1µF Figure 28. Driving the ADC with an RF Transformer For dc-coupled applications, the AD8138/AD8139 or AD8351 can ser ve as a convenient ADC driver, depending on requirements. Figure 29 shows an example with the AD8138. The AD9481 PCB has an optional AD8351 on board, as shown in Figure 39 and Figure 40. The AD8351 typically yields better performance for frequencies greater than 30 MHz to 40 MHz. The AD9481’s linearity and SFDR start to degrade at higher analog frequencies (see the Typical Performance Characteristics section). For higher frequency applications, the AD9480 with LVDS outputs and superior AC performance should be considered. ADC CORE VREF 10µF + 0.1µF 7kΩ SELECT LOGIC SENSE Figure 31. Internal Reference Equivalent Circuit Rev. 0 | Page 17 of 28 05045-032 7kΩ 0.5V AD9481 Fixed Reference The internal reference can be configured for a differential span of 1 V p-p (see Figure 34). It is recommended to place a 0.1 µF capacitor as close as possible to the VREF pin; a 10 µF capacitor is also required (see the PCB layout for guidance). If the internal reference of the AD9481 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 34 depicts how the internal reference voltage is affected by loading. 1.0085 % CHANGE IN VREF VOLTAGE VREF 10µF 0.1µF Figure 33. Internal Fixed Reference (1 V p-p) 0 1.0080 1.0075 1.0070 VREF (V) –0.1 –0.2 1.0065 1.0060 1.0055 1.0050 1.0045 1.0040 1.0035 –40 –20 0 20 40 TEMPERATURE (°C) 60 80 05045-033 –0.3 –0.4 05045-035 –0.5 0 0.5 1.0 1.5 IREF (mA) 2.0 2.5 05045-034 SENSE 3.0 Figure 34. Internal VREF vs. Load Current Figure 32. Typical Reference Variation with Temperature Table 8. Reference Configurations SENSE Voltage AVDD 0.5 V (Self-Biased) AGND to 0.2 V Resulting VREF N/A (external reference input) 0.5 × (1 + R1/R2) V 1.0 V Reference External Programmable Internal fixed Differential Span 1 × external reference voltage 1 × VREF (0.75 V p-p to 1.5 V p-p) 1 V p-p Rev. 0 | Page 18 of 28 AD9481 External Reference An external reference can be used for greater accuracy and temperature stability when required. The gain of the AD9481 can also be varied using this configuration. A voltage output DAC can be used to set VREF, providing for a means to digitally adjust the full-scale voltage. VREF can be externally set to voltages from 0.75 V to 1.5 V; optimum performance is typically obtained at VREF = 1 V. (See the Typical Performance Characteristics section.) MAY REQUIRE RC FILTER EXTERNAL REFERENCE OR DAC INPUT AVDD SENSE 05045--036 change dynamically, requiring a wait time of 5 µs after a dynamic clock frequency increase before valid data is available. The clock duty cycle stabilizer can be disabled at Pin 28 (S1). The clock inputs are internally biased to 1.5 V (nominal) and support either differential or single-ended signals. For best dynamic performance, a differential signal is recommended. An MC100LVEL16 performs well in the circuit to drive the clock inputs (ac coupling is optional). If the clock buffer is greater than two inches from the ADC, a standard LVPECL termination may be required instead of the simple pull-down termination shown in Figure 37. 0.1µF PECL GATE CLK– 0.1µF 05045-028 VREF AD9481 CLK+ Figure 35. External Reference 510kΩ 510kΩ Programmable Reference The programmable reference can be used to set a differential input span anywhere between 0.75 V p-p and 1.5 V p-p by using an external resistor divider. The SENSE pin self-biases to 0.5 V, and the resulting VREF is equal to 0.5 × (1 + R1/R2). It is recommended to keep the sum of R1 + R2 ≥ 10 kΩ to limit VREF loading (for VREF = 1.5 V, set R1 equal to 7 kΩ and R2 equal to 3.5 kΩ). Figure 37. Clocking the AD9481 DS INPUTS The data sync inputs (DS+, DS−) can be used in applications which require that a given sample appear at a specific output port (A or B) relative to a given external timing signal. The DS inputs can also be used to synchronize two or more ADCs in a system to maintain phasing between Ports A and B on separate ADCs (in effect, synchronizing multiple DCO outputs). The DS inputs are internally biased to 1.5 V (nominal) and support either differential or single-ended signals. When DS+ is held high (DS− low), the ADC data outputs and DCO outputs do not switch and are held static. Synchronization is accomplished by the assertion (falling edge) of DS+ within the timing constraints tSDS and tHDS, relative to a clock rising edge. (On initial synchronization, tHDS is not relevant.) If DS+ falls within the required setup time (tSDS) before a given clock rising edge N, the analog value at that point in time is digitized and available at Port A, eight cycles later in interleaved mode. The next sample, N + 1, is sampled by the next rising clock edge and available at Port B, eight cycles after that clock edge. Driving each ADC’s DS inputs by the same sync signal accomplishes synchronization between multiple ADCs. In applications which require synchronization, one-shot synchronization is recommended. An easy way to accomplish synchronization is by a one-time sync at power-on reset. VREF 10µF 0.1µF R1 R2 Figure 36. Programmable Reference CLOCKING THE AD9481 Any high speed ADC is extremely sensitive to the quality of the sampling clock provided by the user. A track-and-hold circuit is essentially a mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the A/D output. Considerable care has been taken in the design of the CLOCK input of the AD9481, and the user is advised to give commensurate thought to the clock source. The AD9481 has an internal clock duty cycle stabilization circuit that locks to the rising edge of CLOCK and optimizes timing internally for sample rates between 100 MSPS and 250 MSPS. This allows for a wide range of input duty cycles at the input without degrading performance. Jitter on the rising edge of the input is still of paramount concern and is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 70 MHz nominally. The loop has a time constant associated with it that needs to be considered in applications where the clock rate can 05045-037 SENSE Rev. 0 | Page 19 of 28 AD9481 Table 9. S1 Voltage Levels S1 Voltage (0.9 × AVDD) → AVDD (2/3 × AVDD) ± (0.1 × AVDD) (1/3 × AVDD) ± (0.1 × AVDD) AGND → (0.1 × AVDD) Data Format Offset binary Offset binary Twos complement Twos complement Duty Cycle Stabilizer Disabled Enabled Enabled Disabled INTERLEAVING TWO AD9481s Instrumentation applications may prefer to interleave (or pingpong) two AD9481s to achieve twice the sample rate, or 500 MSPS. In these applications, it is important to match the gain and offset of the two ADCs. Var ying the reference voltage allows the gain of the ADCs to be adjusted; external dc offset compensation can be used to reduce offset mismatch between two ADCs. The sampling phase offset between the two ADCs is extremely important as well and requires ver y low skew between clock signals driving the ADCs (< 2 ps clock skew for a 100 MHz analog input frequency). DIGITAL OUTPUTS The CMOS digital outputs are TTL-/CMOS-compatible for lower power consumption. The outputs are biased from a separate supply (DRVDD), allowing easy interface to external logic. The outputs are CMOS devices that swing from ground to DRVDD (with no dc load). It is recommended to minimize the capacitive load the ADC drives by keeping the output traces short (< 2 inch, for a total CLOAD < 5 pF). When operating in CMOS mode, it is also recommended to place low value series damping resistors on the data lines close to the ADC to reduce switching transient effects on performance. Table 10. Output Coding (FS = 1 V) Code 255 255 254 • • 129 128 127 • • 2 1 0 0 (VIN+) − (VIN−) > +0.512 V +0.512 V +0.508 V • • +0.004 V +0.0 V −0.004 V • • −0.504 V −0.508 V −0.512 V < −0.512 V Offset Binary 1111 1111 1111 1111 1111 1110 • • 1000 0001 1000 0000 0111 1111 • • 0000 0010 0000 0001 0000 0000 0000 0000 Twos Complement 0111 1111 0111 1111 0111 1110 • • 0000 0001 0000 0000 1111 1111 • • 1000 0010 1000 0001 1000 0000 1000 0000 DATA CLOCK OUT A data clock is available at DCO+ and DCO−. These clocks can facilitate latching off-chip, providing a low skew clocking solution. The on-chip delay of the DCO clocks tracks with the on-chip delay of the data bits, (under similar loading) such that the variation between tPD and tCPD is minimized. It is recommended to keep the trace lengths on the data and DCO pins matched and 2 inches maximum. A series damping resistor at the clock outputs is also recommended. The DCO outputs can be disabled and placed in a high impedance state by tying S3 to ground (tie to AVDD for DCO active). Switching both into and out of high impedance is accomplished in 4 ns from S3 switching. POWER-DOWN INPUT The ADC can be placed into a low power state by setting the PDWN pin to AVDD. Time to go into (or come out of ) power down equals 30 ns typically from PDWN switching. Rev. 0 | Page 20 of 28 AD9481 AD9481 EVALUATION BOARD The AD9481 evaluation board offers an easy way to test the device. It requires a clock source, an analog input signal, and a 3.3 V power supply. The clock source is buffered on the board to provide the clocks for the ADC and a data-ready signal. The digital outputs and output clocks are available at an 80-pin output connector, P3, P23. (Note that P3, P23 are represented schematically as two 40-pin connectors, and this connector is implemented as one 80-pin connector on the PCB.) The board has several different modes of operation and is shipped in the following configuration: • • ANALOG INPUTS The evaluation board accepts a 700 mV p-p analog input signal centered at ground at SMB Connector J3. This signal is terminated to ground through 50 Ω by R22. The input can be alternatively terminated at the T1 transformer secondary by R21 and R28. T1 is a wideband RF transformer that provides the single-ended-to-differential conversion, allowing the ADC to be driven differentially, minimizing even-order harmonics. An optional transformer, T4, can be placed if desired (remove T1, as shown in Figure 39 and Figure 40). The analog signal can be low-pass filtered by R21, C8 and R28, C9 at the ADC input. Offset binary Internal voltage reference POWER CONNECTOR Power is supplied to the board via two detachable 4-pin power strips. Table 11. Power Connector Terminal VDL (3.3 V) AVDD1 3.3 V DRVDD1 3.3 V VCTRL1 3.3 V Op amp, ext. ref Comments Output supply for external latches and data ready clock buffer ~ 30 mA Analog supply for ADC ~ 140 mA Output supply for ADC ~ 30 mA Supply for support clock circuitry ~ 60 mA Optional supply for op amp and ADR510 reference GAIN Full scale is set by the sense jumper. This jumper applies a bias to the SENSE pin to vary the full-scale range; the default position is SENSE = ground, setting the full scale to 1 V p-p. OPTIONAL OPERATIONAL AMPLIFIER The PCB has been designed to accommodate an optional AD8351 op amp that can serve as a convenient solution for dccoupled applications. To use the AD8351 op amp, remove R29, R31, and C3. Populate R12, R17, and R36 with 25 Ω resistors, and populate C1, C21, C23, C31, C39, and C30 with 0.1 µF capacitors. Populate R54, R10, and R11 with 10 Ω resistors, and R34 and R32 with 1 kΩ resistors. Populate R15 with a 1.2 kΩ resistor and R14 with a 100 Ω resistor. Populate R37 with a 10 kΩ resistor. 1 AVDD, DRVDD, VDL, and VCTRL are the minimum required power connections. CLOCK The clock input is terminated to ground through 50 Ω at SMA Connector J1. The input is ac-coupled to a high speed differential receiver (LVEL16) that provides the required low jitter, fast edge rates needed for best performance. J1 input should be > 0.5 V p-p. Power to the LVEL16 is set to VCTRL (default) or AVDD by jumper placement at the device. OPTIONAL CLOCK BUFFER The PCB has been designed to accommodate the SNLVDS1 line driver. The SNLVDS1 is used as a high speed LVDS-level optional encode clock. To use this clock, please remove C2, C5, and C6. Place 0.1 µF capacitors on C34, C35, and C26. Place a 10 Ω resistor on R48, and place a 100 Ω resistor on R6. Place a 0 Ω resistor on both R49 and R53. For best results using the line driver, J1 input should be > 2.5 V p-p. DS The DS inputs are available on the PCB at J2 and J4. If driving DS+ externally, place a 0 Ω resistor at C48 and remove R53. Rev. 0 | Page 21 of 28 AD9481 OPTIONAL XTAL The PCB has been designed to accommodate an optional cr ystal oscillator that can ser ve as a convenient clock source. The footprint can accept both through-hole and surface-mount devices, including Vectron XO-400 and Vectron VCC6 family oscillators. To use either cr ystal, populate C38 and C40 with 0.1 µF capacitors. Populate R48 and R49 with 0 Ω resistors. Place R50, R51, R59, and R60 with 1 kΩ resistors. Remove C6 and C5. If the Vectron VCC6 family cr ystal is being used, populate R57 with a 10 Ω resistor. If using the XO-400 cr ystal, place jumper E21 or E22 to E23. VOLTAGE REFERENCE VCC OUT+ OUT– GND 05045-038 The AD9481 has an internal 1 V reference mode. The ADC uses the internal 1 V reference as the default when sense is set to ground. An optional on-board external 1.0 V reference (ADR510) can be used by setting the sense jumper to AVDD, by placing a jumper on E5 to E3, and by placing a 0 Ω resistor on R55. When using an external programmable reference, (R20, R30) remove the sense jumper. DATA OUTPUTS VCC The ADC outputs are buffered on the PCB by LVT574 latches on the data outputs. The latch outputs have series terminating resistors at the output pins to minimize reflections. Figure 38. XTAL Footprint Rev. 0 | Page 22 of 28 AD9481 EVALUATION BOARD BILL OF MATERIALS (BOM) Table 12. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Quantity 24 1 5 4 3 3 2 7 8 7 2 2 2 2 2 1 3 1 3 2 4 2 1 1 1 1 1 1 1 1 11 18 16 Reference Designator C1 to C6, C10 to C12, C14 to C15, C17 to C19, C22 to C29, C31, C48 to C49 C13 C32 to C36 J1 to J4 P1, P12 to P13 P1, P12 to P13 P3, P23 R1, R5, R19, R22, R27, R35, R53 R2 to R4, R6 to R9, R18, R14 R13, R42 to R45, R32, R34 R16, R52 R23, R24 R25, R26 R29, R31 R33, R37 R46 R12, R17, R36 R15 R54, R10 to R11 RP1 to RP2 U3, U5 to U6, U8 U4, U7 T1 U1 U2 U101 U9 1 U12 U11 T21 C1, C7 to C9, C16, C20, C30, C31, C38 to C40 R20 to R21, R28, R30, R38 to R41, R48 to R51, R55 to R60 E98 to E102, E73 to E84 Device Capacitors Capacitor Capacitors SMA 4-pin power connectors 4-pin power connectors 80-pin connectors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistors Resistor Resistors Resistor Resistors Resistor Pack Resistor Pack 100 Ω 74LVT574 Transformer AD8351 74VCX86 ADR510 VCC6PECL6 AD9481 MC100-LVEL16D ETC1-1-13 Capacitors Resistors Jumpers Package 0402 Tantalum (3528) Tantalum (6032) SMA Post Detachable connector Connector 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 0603 100 Ω Res. Array 100 Ω Res. Array SO20 CD542 MSOP-10 SO-14 SOT-23 VCC6-QAB-250M000 TQFP-44 S08NB 1-1 TX 0402 0603 Value 0.1 µF 10 µF 10 µF Degrees Z5.531.3425.0 25.602.5453.0 TSW-140-08-L-D-RA 50 Ω 100 Ω 1 kΩ 130 Ω 510 Ω 82 Ω 00 Ω 10 kΩ 2 kΩ 25 Ω 1.2 kΩ 10 Ω 742C163100JTR EXB-38V101JV 74LVT574WM ADT1-1WT Op Amp XOR Voltage Regulator Vectron Crystal ADC Clock Buffer M/A-COM/ETC 1-1-13 X1 X1 1 Not placed. Rev. 0 | Page 23 of 28 AD9481 P13 P4 P3 P2 P1 P4 P4 P3 P2 P1 4 3 2 1 1 P3 3 4 3 2 2 1 P2 P1 4 P12 U4 74LVT574 100Ω RP1 GND 16 15 14 13 12 11 10 9 20 P1 GND VAMP GND 2 19 1 2 3 4 5 6 7 8 18 17 16 15 14 13 12 11 3 4 5 6 7 8 9 8 7 6 5 PCB SCHEMATICS GND DB7 DB6 DB5 DB4 U8 1 2 3 4 GND AVDD GND VCTRL 100Ω RPAK_4 VDL E25 DB7 DB6 DB5 DB4 1 2 3 4 8 7 6 5 GND VDL GND DRVDD 1 OUTPUT CONNECTOR R33 E5 E3 10kΩ 33 32 31 30 29 28 27 26 25 24 23 U10 ADR510 TRIM/NC VDL 22 21 20 19 18 17 16 15 34 AVDD GND E15 E2 R30 XX SENSE AGND AVDD AVDD PWDN S1 DRGND D7B D6B D5B D4B U3 RPAK_4 GND CLKLAT+ R40 X GND 10 E16 E1 GND AVDD AVDD PWDN S1 GND E13 DB3 DB2 DB1 DB0 E14 R20 XX VAMP 3 1 V+ 2 VCC OUT_EN Q0 D0 Q1 D1 Q2 D2 Q3 D3 Q4 D4 Q5 D5 Q6 D6 Q7 D7 GND CLOCK DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X GND DR+ GND DB7X DB6X DB5X DB4X DB3X DB2X DB1X DB0X V– 35 36 37 38 39 40 41 GND R55 X C13 10µF GND GND U12 C20 X COUT+ COUT– E18 GND U7 74LVT574 GND 2 3 4 5 6 7 8 9 1 20 19 18 17 16 15 14 13 12 R1 50Ω C14 0.1µF + C12 0.1µF GND AVDD GND J4 DS– GND DB3 DB2 DB1 E19 R2 DB0 100Ω DRVDD GND C49 0.1µF AD9481 14 13 12 R41 X 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1 P23 E27 S3 43 44 42 GND R3 100Ω C16 X GND AVDD GND DA0 DA1 DA2 J2 DS+ E26 1 2 3 4 5 6 78 9 10 11 VREF AGND AVDD AGND VIN– VIN+ AGND AVDD S3 DS– DS+ D3B D2B D1B D0B DRVDD DCO+ DCO– DRGND D0A D1A D2A NOTE: TWO 40 PIN OUTPUT CONNECTOR IMPLEMENTED AS ONE 80 PIN CONNECTOR 100Ω RP2 VDL 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 CLK+ CLK– AVDD AGND DRVDD DRGND D7A D6A D5A D4A D3A GND 100Ω RPAK_4 DA0 DA1 DA2 DA3 U6 DA4 DA5 DA6 DA7 U5 RPAK_4 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 C48 R35 0.1µF 50Ω AMPOUT E28 C8 X GND T1– R28 C10 X 0.1µF AVDD GND DRVDD GND CM CM R31 0Ω AMPOUT E29 C9 X GND R53 50Ω GND OUTPUT CONNECTOR GND GND 05045-040 Figure 39. PCB Schematic (1 of 2) 4 2 6 Rev. 0 | Page 24 of 28 DA3 DA4 DA5 DA6 DA7 T1+ VCTRL R16 130Ω VCTRL Q CLK+ E8 CLK– C5 0.1µF OPTIONAL TRANSFORMER T2 ETC1-1-13 TIN1 CM GND 4 5 2 3 6 1 J3 ANALOG INPUT GND E30 PRI SEC CM 3 5 1 R22 50Ω GND GND R21 R29 X 0Ω C3 0.1µF T1-1T T1 TIN1 DA0X DA1X DA2X DA3X DA4X DA5X DA6X DA7X GND 10 11 AMPIN VCC OUT_EN Q0 D0 Q1 D1 Q2 D2 Q3 D3 Q4 D4 Q5 D5 Q6 D6 Q7 D7 GND CLOCK GND DR– GND DA7X DA6X DA5X DA4X DA3X DA2X DA1X DA0X VDL AVDD GND C6 E6 0.1µF E9 E10 C11 0.1µF OP AMP CONFIGURATION REMOVE C3 REMOVE R29 AND R31 CLKLAT– R38 X VCTRL J1 E11 1 8 CLK 6 2 R39 X GND 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 P40 P38 P36 P34 P32 P30 P28 P26 P24 P22 P20 P18 P16 P14 P12 P10 P8 P6 P4 P2 P39 P37 P35 P33 P31 P29 P27 P25 P23 P21 P19 P17 P15 P13 P11 P9 P7 P5 P3 P1 P3 R VCC 7 CLK Q R25 82Ω R52 130Ω R26 Q– 82Ω GND 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 100LVEL16 C2 0.1µF GND T1+ CM T1– 3 GND R27 50Ω CLKN Q VBB VEE GND R23 510Ω R24 4 510Ω 5 U11 C4 0.1µF GND PADS FOR SHORTING EL16, USED IF BYPASSING EL16 P14 P15 CLK Q P16 P17 CLKN Q– PRI SEC X = NOT NORMALLY POPULATED XX = NOT POPULATED, USER SELECTED VCTRL VDL DRVDD AVDD AVDD DRVDD E72 E7 E12 E4 E70 E71 U2 74VCX86 VAMP CLKLAT+ GND AVDD C33 + 10µF C25 0.1µF C18 0.1µF C24 0.1µF C17 0.1µF GND CLKAT– DRVDD C34 + 10µF C19 0.1µF C22 0.1µF GND VCTRL C35 + 10µF C15 0.1µF GND PWDN R58 X VDL DR+ C36 + 10µF C1 X GND VAMPF 1 2 4 2A 2B 3A 3B 4A 4B 14 7 GND E20 S3 AVDD E88 GND GND GND C31 X GND R32 X VAMPF 10 VOCM R17 X VAMPF R56 X C7 X AMPOUT C30 X 9 VPOS 8 OPHI 7 OPLO R36 X GND 6 COMM GND C39 X AMPOUT U1 AD8351 R34 X AVDD VCTRL E24 E22 E23 GND GND C38 X VCTRL R57 X GND R59 X VCC 6 PECL6 1 NC VC 2 E/D OUTPUTB 3 GND OUTPUT 6 5 4 R60 X C40 X 14 7 U13 XO-400 VCC OUT VEE –OUT 8 1 VCTRL GND E89 OPTIONAL XTALS E90 R44 1kΩ E21 GND PWR VDL 4Y 11 DR– R5 50Ω 3Y 8 R4 100Ω 2Y 6 5 9 10 12 13 R19 50Ω 1B 1Y 3 1A R18 100Ω C32 + 10µF C26 0.1µF C27 0.1µF C28 0.1µF C29 0.1µF R54 X VDL VDL E56 R9 COUT+ E54 100Ω GND E55 VDL E53 R8 COUT+ E51 100Ω GND E52 VDL E50 R6 COUT– E45 100Ω GND E46 VDL E49 R7 COUT– E48 100Ω GND E47 VCTRL VCTRL VCTRL R45 X R46 X E35 E36 R42 1kΩ E32 E39 R43 1kΩ E33 E38 S1 05045-041 Figure 40. PCB Schematic (2 of 2) Rev. 0 | Page 25 of 28 R15 X R13 1kΩ E34 E37 GND VAMPF R37 X C21 X PWUP 1 RGP1 2 AMPIN INHI 3 R10 X INLO 4 R48 X CLK– CLK+ R50 XX X = NOT NORMALLY POPULATED XX = NOT POPULATED, USER SELECTED VCTRL R51 XX GND R49 X R12 X C23 R11 X X RPG2 5 GND R14 X AD9481 AD9481 PCB LAYERS 05045-042 Figure 41. PCB Top-Side Silkscreen Figure 43. PCB Ground Layer 05045-043 Figure 42. PCB Top-Side Copper Routing Figure 44. PCB Split Power Plane Rev. 0 | Page 26 of 28 05045-045 05045-044 August 3, 2004 AD9481 05045-046 Figure 45. PCB Bottom-Side Copper Routing Figure 46. PCB Bottom-Side Silkscreen Rev. 0 | Page 27 of 28 05045-047 AD9481 OUTLINE DIMENSIONS 1.20 MAX 0.75 0.60 0.45 44 1 PIN 1 12.00 SQ 34 33 TOP VIEW (PINS DOWN) 10.00 SQ 1.05 1.00 0.95 0° MIN 0.15 0.05 SEATING PLANE 0.20 0.09 VIEW A 7° 3. 5 ° 0° 0.08 MAX COPLANARITY 11 12 22 23 0.80 BSC VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026ACB 0.45 0.37 0.30 Figure 47. 44-Lead Thin Plastic Quad Flat Package [ TQFP] (SU-44)—Dimensions shown in millimeters ORDERING GUIDE Model AD9481BSUZ-2501 AD9481-PCB2 Temperature Range –40°C to +85°C Package Description 44-Lead Thin Plastic Quad Flat Package (TQFP) Evaluation Board Package Option SU-44 1 2 Z = Pb-free part. Evaluation board shipped with AD9481BSUZ-250 installed. © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05045–0–10/04(0) Rev. 0 | Page 28 of 28