AD9500BQ

a FEATURES 10 ps Delay Resolution 2.5 ns to 10 s Full-Scale Range Fully Differential Inputs Separate Trigger and Reset Inputs Low Power Dissipation—310 mW MIL-STD-883 Compliant Versions Available APPLICATIONS ATE Pulse Deskewing Arbitrary Waveform Generators High Stability Timing Source Multiple Phase Clock Generators TRIGGER TRIGGER RESET RESET Digitally Programmable Delay Generator AD9500 FUNCTIONAL BLOCK DIAGRAM CEXT +VS CS ECL COMMON AD9500 DIFFERENTIAL ANALOG INPUT STAGE ECL VOLTAGE REFERENCE TIMING CONTROL CIRCUIT Q Q INTERNAL DAC QR TTL LATCHES ECLREF RS REFERENCE CURRENT RSET –VS GROUND D0 D1 D2 D3 D4 D5 D6 D7 (LSB) (MSB) LATCH OFFSET ENABLE ADJUST GENERAL DESCRIPTION –VS The AD9500 is a digitally programmable delay generator, which provides programmed delays, selected through an 8-bit digital code, in resolutions as small as 10 ps. The AD9500 is constructed in a high performance bipolar process, designed to provide high speed operation for both digital and analog circuits. The AD9500 employs differential TRIGGER and RESET inputs which are designed primarily for ECL signal levels but function with analog and TTL input levels. An onboard ECL reference midpoint allows both of the inputs to be driven by either single ended or differential ECL circuits. The AD9500 output is a complementary ECL stage, which also provides a Q R parallel output circuit to facilitate reset timing implementations. The digital control data is passed to the AD9500 through a transparent latch controlled by the LATCH ENABLE signal. In the transparent mode, the internal DAC of the AD9500 will attempt to follow changes at the inputs. The LATCH ENABLE is otherwise used to strobe the digital data into the AD9500 latches. The AD9500 is available as an industrial temperature range device, –25°C to +85°C, and as an extended temperature range device, –55°C to +125°C. Both grades are packaged in a 24-lead cerdip (0.3" package width), as well as 28-leaded and leadless surface mount packages. The AD9500 is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9500/883B data sheet for detailed specifications. PIN CONFIGURATIONS D4 D5 D6 D7 (MSB) ECLREF OFFSET ADJUST CS +VS TRIGGER 1 2 3 4 5 6 7 8 9 24 23 22 D3 D2 D1 21 D 0 (LSB) AD9500 TOP VIEW (Not to Scale) 20 19 18 17 16 15 14 13 LATCH ENABLE GROUND RS –VS ECL COMMON QR Q Q TRIGGER 10 RESET 11 RESET 12 D6 NC D4 D5 4 D7 (MSB) 5 ECLREF 6 OFFSET ADJUST 7 NC 8 CS 9 +VS 10 TRIGGER 11 3 2 1 28 D3 27 D2 26 25 D (LSB) 0 24 LATCH ENABLE AD9500 TOP VIEW (Not to Scale) D1 23 GROUND 22 NC 21 RS 20 –VS 19 ECL COMMON 18 QR 12 TRIGGER 13 RESET 14 RESET 15 NC 16 Q 17 Q R EV. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. NC = NO CONNECT One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9500–SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS 1 Positive Supply Voltage (+VS) . . . . . . . . . . . . . . . . . . . . . +7 V Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . –7 V ECL COMMON to Ground Differential . . . . –2.0 V to +5.0 V Digital Input Voltage Range . . . . . . . . . . . . . –3.5 V to +5.0 V Trigger/Reset Input Voltage Range . . . . . . . . . . . . . . . ± 5.0 V Trigger/Reset Differential Voltage . . . . . . . . . . . . . . . . . .5.0 V Minimum RSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Ω Digital Output Current (Q and Q) . . . . . . . . . . . . . . . 30 mA Digital Output Current ( Q R ) . . . . . . . . . . . . . . . . . . . . 2 mA Offset Adjust Current (Sinking) . . . . . . . . . . . . . . . . . . . 4 mA Operating Temperature Range AD9500BP/BQ . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C AD9500TE/TQ . . . . . . . . . . . . . . . . . . . . –55° C to +125°C Storage Temperature Range . . . . . . . . . . . . –65° C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+175°C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C ELECTRICAL CHARACTERISTICS2 (Supply Voltages +V = +5.0 V, V = –5.2 V; C S S EXT = 0 pF; RSET = 500 unless otherwise noted) Parameter RESOLUTION ACCURACY Differential Linearity Integral Linearity Monotonicity DIGITAL INPUT Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Digital Input Capacitance Data Setup Time4 Data Hold Time5 Latch Pulsewidth (tLPW) RESET/TRIGGER INPUTS TRIGGER Input Voltage Range RESET Input Voltage Range Differential Switching Voltage Input Bias Current Input Resistance Input Capacitance Minimum Input Pulsewidth tTPW, tRPW DYNAMIC PERFORMANCE Maximum Trigger Rate Minimum Propagation Delay (tPD)8 Minimum Propagation Delay TC Full-Scale Range TC9 Delay Uncertainty (Jitter) Reset Propagation Delay (tRD)10 Reset-to-Trigger Holdoff (tTHO )11 Trigger-to-Reset Holdoff (tRHO)12 Minimum Output Pulsewidth Output Rise Time7 Output Fall Time7 Delay Coefficient Settling Time (tDAC)13 Linear Ramp Settling Time (tLRS) 7 6 3 Test Level Temp –25 C to +85 C AD9500BP/BQ Min Typ Max 8 –55 C to +125 C AD9500TE/TQ Min Typ Max 8 Units Bits I I I VI VI VI VI VI V V V IV IV IV I VI IV IV V IV I V V V I IV IV V I I V V +25°C +25°C +25°C Full Full Full Full +25°C +25°C +25°C +25°C Full Full Full +25°C Full +25°C +25°C +25°C +25°C +25°C Full Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C 2.0 0.5 1.0 Guaranteed 2.0 0.8 5 5 5.5 0.75 0.75 3.0 –2.5; 4.5 –2.5; 2.0 40 300 40 50 75 4 6.5 7.25 2.0 60 6.4 7.5 0.5 10 6.4 0 1.5 3.3 Guaranteed 0.5 1.0 LSB LSB 0.4 0.4 3.0 0.4 0.4 0.8 5 5 5.5 0.75 0.75 V V µA µA pF ns ns ns V V mV µA µA kΩ pF ns MHz ns ps/°C ps/°C ps ns ns ns ns ns ns ns ns –2.5; 4.5 –2.5; 2.0 40 300 40 50 75 4 6.5 7.25 2.0 60 6.4 7.5 0.5 10 6.4 0 1.5 3.3 5.4 7.4 5.4 7.4 5.4 0.2 2.0 7.4 5.4 0.2 2.0 7.4 2.0 2.0 29 22 29 22 2.0 2.0 –2– REV. D AD9500 Parameter SUPPORT FUNCTIONS ECLREF ECLREF Voltage Drift14 Offset Adjust Range DIGITAL OUTPUTS7 Logic “1” Voltage Logic “0” Voltage POWER SUPPLY15 Positive Supply Current (+5.0 V) Negative Supply Current (–5.2 V) Nominal Power Dissipation Power Supply Rejection Ratio16 Full-Scale Range Sensitivity Minimum Propagation Delay Sensitivity Test Level IV V V VI VI I VI I VI V I I Temp +25°C Full Full Full Full +25°C Full +25°C Full +25°C +25°C +25°C –25 C to +85 C AD9500BP/BQ Min Typ Max –1.4 –1.3 1.1 –2 –1.2 –55 C to +125 C AD9500TE/TQ Min Typ Max –1.4 –1.3 1.1 –2 –1.2 Units V mV/°C mA V V mA mA mA mA mW ps/V ps/V –1.1 –1.5 24 37 312 70 150 300 500 28 30 42 44 –1.1 –1.5 24 37 312 70 150 300 500 28 30 42 44 NOTES 1 Absolute maximum ratings are limiting values, to be applied individually, and beyond which serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Typical thermal impedance 24-Lead Cerdip θJA = 56 °C/W; θ JC = 16°C/W 28-Leadless PLCC (Plastic) θJA = 60 °C/W; θ JC = 22 °C/W 28-Leaded Ceramic LCC θJA = 69 °C/W; θ JC = 25°C/W 3 RSET = 10 kΩ (Full-scale delay = 100 ns). 4 The digital data inputs must remain stable for the specified time prior to the LATCH ENABLE signal. 5 The digital data inputs must remain stable for the specified time after the LATCH ENABLE signal. 6 The TRIGGER and RESET inputs are differential and must be driven relative to one another. Both of these inputs are ECL compatible, but can also be used with TTL logic families in a limited fashion. 7 Outputs terminated through 50 Ω resistors to –2.0 V. 8 Program Delay = 0.0 ps (Digital Data = 00H). In Operation, any programmed delays are in addition to the Minimum Propagation Delay. 9 Change in total delay through AD9500, exclusive of changes in minimum propagation delay t PD. 10 Measured from the 50% transition point of the reset signal input, to the 50% transition point of the resetting output. 11 Minimum time from falling edge of RESET to triggering input, to ensure a valid output event. 12 Minimum time from triggering event to rising edge of RESET, to ensure a valid output event. 13 Measured from the LATCH ENABLE input to the point when the AD9500 becomes 8-bit accurate again, after a full-scale change in the programmed delay. 14 Standard 10K and 10KH ECL families operate with a 1.1 mV/ °C drift by design. 15 Supply voltages should remain stable within ± 5% for normal operation. 16 Measured at ± 5% of –VS and +VS. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS ORDERING GUIDE Model Temperature Ranges Package Descriptions Package Options P-28A Q-24 E-28A Q-24 Test Level I – 100% production tested. II – 100% production tested at +25°C, and sample tested at specified temperatures. III – Periodically sample tested. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25°C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. AD9500BP –25°C to +85 °C 28-Leadless PLCC (Plastic), Industrial Temperature AD9500BQ –25°C to +85 °C 24-Lead Cerdip, Industrial Temperature AD9500TE –55°C to +125° C 28-Leaded LCC, Extended Temperature AD9500TQ –55°C to +125° C 24-Lead Cerdip, Extended Temperature REV. D –3– AD9500 PIN FUNCTION DESCRIPTIONS Pin Name D4–D6 D7 (MSB) ECLREF OFFSET ADJUST CS Description One of eight digital inputs used to set the programmed delay. One of eight digital inputs used to set the programmed delay. D7 (MSB) is the most significant bit of the digital input word. ECL midpoint reference, nominally –1.3 V. Use of the ECL REF allows either of the TRIGGER or RESET inputs to be configured for single-ended ECL inputs. The OFFSET ADJUST is used to adjust the minimum propagation delay (tPD), by pulling or pushing a small current out of or into the pin. CS allows the full-scale range to be extended by using an external timing capacitor. The value of CEXT, connected between CS and +VS, may range from no external capacitance to 0.1 µF+. See RS (CINTERNAL = 10 pF). Positive supply terminal, nominally +5.0 V. Noninverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by the programmed delay, after the triggering event. The programmed delay is set by the digital input word. The TRIGGER input must be driven in conjunction with the TRIGGER input. Inverted input of the edge-sensitive differential trigger input stage. The output at Q will be delayed by the programmed delay, after the triggering event. The programmed delay is set by the digital input word. The TRIGGER input must be driven in conjunction with the TRIGGER input. Inverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a signal is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will be equal to the “reset propagation delay,” tRD. The RESET input must be driven in conjunction with the RESET input. Noninverted input of the level-sensitive differential reset input stage. The output at Q will be reset after a signal is received at the reset inputs. In the “minimum configuration,” the minimum output pulsewidth will be equal to the “reset propagation delay,” tRD. The RESET input must be driven in conjunction with the RESET input. One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic HIGH on the Q output. A “resetting” event at the inputs will produce a logic LOW on the Q output. One of two complementary ECL outputs. A “triggering” event at the inputs will produce a logic LOW on the Q output. A “resetting” event at the inputs will produce a logic HIGH on the Q output. Q R output is parallel to the Q output. The Q R output is typically used to drive delaying circuits for extending output pulsewidths. A “triggering” event at the inputs will produce a logic LOW on the Q R output. A “resetting” event at the inputs will produce a logic HIGH on the Q R output. +VS TRIGGER TRIGGER RESET RESET Q Q QR ECL COMMON –VS RS GROUND LATCH ENABLE The collector common for the ECL output stage. The collector common may be tied to +5.0 V, but normally it is tied to the circuit ground for standard ECL outputs. Negative supply terminal, nominally –5.2 V. RS is the reference current setting terminal. An external setting resistor, RSET , connected between RS and –VS determines the internal reference current. See CS (250 Ω ≤ RSET ≤ 50 kΩ). The ground return for the TTL and analog inputs. Transparent TTL latch control line. A logic HIGH on the LATCH ENABLE freezes the digital code at the logic inputs. A logic LOW on the LATCH ENABLE allows the internal current levels to be continuously updated through the logic inputs D0 thru D7. One of eight digital inputs used to set the programmed delay. D0 (LSB) is the least significant bit of the digital input word. One of eight digital inputs used to set the programmed delay. D0 (LSB) D3–D1 –4– REV. D AD9500 Figure 1. System Timing Diagram DIE LAYOUT MECHANICAL INFORMATION Die Dimensions . . . . . . . . . . . . . . . 104 103 18 (max) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . 4 4 (min) mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oxynitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Gold Eutectic Bond Wire . . . . . . . . 1.25 mil, Aluminum; Ultrasonic Bonding or 1 mil, Gold; Gold Ball Bonding REV. D –5– AD9500 Figure 2. Input/Output Circuits –6– REV. D AD9500 INSIDE THE AD9500 The heart of the AD9500 is the linear ramp generator. A triggering event at the input of the AD9500 initiates the ramp cycle. As the ramp voltage falls, it will eventually go below the threshold set up by the internal DAC (digital-to-analog converter). A comparator monitors both the linear ramp voltage and the DAC threshold level. The output of the comparator serves as the output for the AD9500, and the interval from the trigger until the output switches is the total delay time of the AD9500. The total delay through the AD9500 is made up of two components. The first is the full-scale programmed delay, tD (max), determined by RSET and CEXT. The second component of the total delay is the minimum propagation delay through the AD9500 (tPD). The full-scale delay is variable from 2.5 ns to greater than 1 ms. The internal DAC is capable of generating 256 separate programmed delays within the full-scale range (this gives 10 ps increments for a 2.5 ns full-scale setting). The actual programmed delay is directly related to both the digital control data (digital data to the internal DAC) and the RC time constant established by RSET and CEXT. The specific relationship is as follows: Total Delay = Minimum Propagation Delay + Programmed Delay = tPD + (digital value/256) RSET (CEXT + 10 pF) Figure 4. Internal Timing Diagram On resetting, the ramp voltage held in the timing capacitor (CEXT + 10 pF) is discharged. The AD9500 discharges the bulk of the ramp voltage very quickly, but to maintain absolute accuracy, subsequent triggering events should be held off until after the linear ramp settling time (tLRS). Applications which employ high frequency triggering at a constant rate will not be affected by the slight settling errors since they will be constant for fixed reset-to-trigger cycles. The RESET and TRIGGER inputs of the AD9500 are differential and must be driven relative to one another. Accordingly, the TRIGGER and RESET inputs are ideally suited for analog or complementary input signals. Single-ended ECL input signals can be accommodated by using the ECL midpoint reference (ECLREF) to drive one side of the differential inputs. The output of the AD9500 consists of both Q and Q driver stages, as well as the Q R output which is used primarily for extending the output pulsewidth. In the most direct reset configuration, either the Q or the Q output is tied to the respective RESET input. This generates a delayed output pulse with a duration equal to the reset delay time (tRD) of approximately 6 ns. Note that the reset delay time (tRD) becomes extended for very small programmed delay settings. The duration of the output pulse can be extended by driving the reset inputs with the Q R output through an RC network (see “Extended Output Pulsewidth” application). Using the Q R output to drive the reset circuit avoids loading the Q or Q outputs. Values in the specification table are based on 5 ns FSR test conditions. Nearly all dynamic specifications degrade for longer full scales. For details of performance change, request the application note “Using Digitally Programmable Delay Generators.” Figure 3. Typical Programmed Delay Ranges The internal DAC determines the programmed delay by way of the threshold level at its output. The LATCH ENABLE control for the onboard latch is active (latches) logic “HIGH.” In the logic “LOW” state, the latch is transparent, and the internal DAC will attempt to follow changes at the digital data inputs. Both the LATCH ENABLE control and the data inputs are TTL compatible. The internal DAC may be updated at any time, but full timing accuracy may not be attained unless triggering events are held off until after the DAC settling time (tDAC). REV. D –7– AD9500 APPLICATIONS The AD9500 is a very versatile device that is not difficult to use. Essentially there are only a few basic configurations which can be extended into a number of applications. The TRIGGER and RESET inputs of the AD9500 can be treated as single ended, or as differential, which allows the AD9500 to operate with a wide range of signal sources. The output pulse from the AD9500 can be reset in one of two ways, either immediately by driving the RESET inputs with the output itself, or in a delayed mode. MINIMUM CONFIGURATION the Q and the Q outputs are completely free for other uses. Q has limited current drive; the minimum resistance for RD should be 4 kΩ. The minimum configuration uses only one of the TRIGGER inputs. The other is connected to the ECL reference midpoint, ECLREF. This allows the AD9500 to be triggered with standard 10K or 10KH ECL signals. Once a triggering event occurs, the Q output will go into the logic HIGH state, and the Q output will go into the logic LOW state after the programmed delay. The Q output is then used to drive the RESET input, causing the AD9500 to reset itself. The result is a delayed output pulse which is only as wide as the reset propagation delay (tRD). Figure 6. Extended Output Pulsewidth Configuration MULTICHANNEL DESKEWING Perhaps the most appropriate use of the AD9500 is in multiple delay matching applications. Slight differences in impedance and cable length can create large timing skews within a highspeed system. Much of this skew can be eliminated by running each signal through an AD9500. With one line used as a standard, the programmed delays of the other AD9500s are adjusted to eliminate the timing skews. With the very fine timing adjustments possible from the AD9500 (as small as 10 ps), nearly any high-speed system should be able to automatically adjust itself to extremely tight tolerances. Figure 5. Single Input–Minimum Timing Configuration EXTENDED OUTPUT PULSEWIDTHS The extended pulse configuration is similar to the minimum configuration. The difference here is that the output pulsewidth has been extended. Operation is identical in terms of triggering the AD9500; the functional difference is in the resetting circuit. In this case the Q R output is used to drive the RESET input through a resistor/capacitor charging network. The charging network will cause the signal at the RESET input to fall more slowly, which will extend the output pulsewidth. An added benefit of the extended pulsewidth configurations is that both Figure 7. Multiple Delay Matching –8– REV. D AD9500 MEASURING UNKNOWN DELAYS Two AD9500s can be combined to measure delays with a high degree of precision. One AD9500 is set with little or no programmed delay, and its output is used to drive the unknown delay circuit, which in turn drives the input of a “D” type flipflop. The second AD9500 is triggered along with the first, and its output provides a clocking signal for the flip-flop. The programmed delay of the second AD9500 is then varied to detect the output edge from the unknown delay circuit. Detecting the output edge is relatively straightforward. If the programmed delay through the second AD9500 is too long, the flip-flop output will be at logic HIGH. If, on the other hand, the programmed delay through the second AD9500 is too short, the flip-flop output will be at logic LOW. When the programmed delay is properly adjusted, the flip-flop will likely bounce between logic HIGH and logic LOW. The digital code value used to create the second programmed delay is a direct indication of the delay through the unknown circuit. The most accurate results can only be attained by calibrating the system without the unknown delay circuit in place. equals the DAC threshold. By varying the DAC threshold level and adjusting the second AD9500 programmed delay, a point by point reconstruction of the ac waveform can be created. Figure 9. Measuring AC Waveforms PROGRAMMABLE OSCILLATOR Another interesting use of the AD9500 is in a digitally programmable oscillator. The highly accurate delays generated by the AD9500 can be exploited to create a ring oscillator with variable duty cycle. The delayed output of the first AD9500 is used to drive the TRIGGER input of the second AD9500. The output of the second AD9500, in turn, is used to drive the TRIGGER input of the first AD9500. Together the two devices will alternately trigger each other creating two pulse chains on the outputs. The total delay through both AD9500s combined, determines the period of the oscillation frequency. The duty cycle can be controlled by using the outputs to drive the SET and RESET inputs of a flip-flop. The total delay through the first AD9500 will control the flip-flop logic LOW output pulsewidth, and the second AD9500 will control the flip-flop logic HIGH output pulsewidth. Figure 8. Measuring Unknown Delays MEASURING HIGH SPEED AC WAVEFORMS The same circuitry used to measure unknown delays can be extended to measure the time response of high speed ac waveforms. With the addition of a digital-to-analog converter and an analog comparator, the circuit functions very much like the previous application. The DAC sets a threshold level which drives one of the differential comparator inputs. The other comparator input is driven by the device under test (DUT). The output of the first AD9500 causes the DUT to produce an output. The second AD9500, which is also triggered along with the first AD9500, strobes the comparator latch enable. If the DUT output is greater than the DAC threshold when the comparator is latched, the comparator output will be at logic HIGH. If the output is below the DAC threshold, the comparator will be at logic LOW. The programmed delay setting of the second AD9500 is adjusted to the point where the DUT output Figure 10. Ring Oscillator REV. D –9– AD9500 LAYOUT CONSIDERATIONS GENERAL PERFORMANCE ENHANCEMENTS The AD9500 is a precision timing device, and as such high frequency design techniques must be employed to achieve the best performance. The use of a low impedance ground plane is particularly important. Ideally the ground plane should be on the component side of the layout and extend under the AD9500, to shield it from system timing signals. Sockets pose a special problem for a circuit like the AD9500 because of the additional inter-lead capacitance they create. If sockets must be used, pin sockets are generally preferred. Power supply decoupling is also critical to a high-speed design; a 0.1 µF ceramic capacitor and a 0.01 µF mica capacitor for both power supplies should be very effective. DAC threshold stability can be improved by decoupling the OFFSET ADJUST pin to +5.0 V (note that this will lengthen the DAC settling time, tDAC) DELAY OFFSET ADJUSTMENTS High speed operation is generally more consistent if CEXT is kept small (i.e., no external capacitor) to maintain small discharge time constants. Integral linearity, however, benefits from larger values of CEXT by buffering small system spikes and surges. Another means of improving integral linearity is to draw a small current (≈200 µA) out of the OFFSET ADJUST pin with a 47 kΩ pull-down resistor. This has the effect of moving the internal DAC reference levels into a relatively more linear region of the ramp. This technique is generally only useful for small full-scale delay configurations. Its use with larger full-scale delays will extend the minimum propagation delay (tPD). A pullup resistor to +5.0 V creates the opposite effect by reducing the minimum propagation delay (tPD) at the expense of increased reset propagation delay (tRD) and degraded linearity (see OFFSET matching circuit). Caution should be used when applying high slew rate data at the inputs of the AD9500. For data inputs with slew rates in excess of 1 V/ns, a 100 Ω series resistor should be utilized in the data path. An external DAC can be used with the AD9500 for increased resolution and higher update rates. For the most part, a standard ECL DAC, operating between +5.0 V and ground, should work with the AD9500. The output of the external DAC must be connected to the OFFSET ADJUST pin of the AD9500 with the internal DAC turned off (D0 thru D 7 at logic LOW). For normal operation, the external DAC output should range from 0 mA to –2 mA (sinking). As the full-scale delay is increased, a component of the minimum propagation delay also increases. This is caused by the additional time required by the ramp (now with a much “flatter” slope) to fall below the DAC threshold corresponding to the minimum propagation delay (tPD). One means of decreasing the minimum propagation delay (when the full-scale delay, set by RSET and CEXT is large) is to offset the internal DAC threshold toward the initial ramp levels, thus reducing the time for the internal ramp to cross the threshold once the AD9500 is triggered. Figure 11. The Offset Adjust Pin Can Be Used to Match Several AD9500s Figure 12. Operation with External DAC The DAC levels are offset toward the initial ramp level by injecting a small current into the offset adjust pin. Note, however, that the ramp start-up region is less linear than the later portions of the ramp, which is the primary reason for the built-in offset. If the minimum propagation delay is kept above 5 ns (the linear portion of the ramp), no significant degradation in linearity should result. This concept can be extended to match the actual propagation delays of several AD9500s, by injecting or sinking a small current (