AD9511BCPZ-REEL7

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs AD9511 FEATURES FUNCTIONAL BLOCK DIAGRAM VS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure GENERAL DESCRIPTION The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.6 GHz may be synchronized to the input reference. There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels. CPRSET VCP DISTRIBUTION REF REFIN R DIVIDER REFINB N DIVIDER FUNCTION AD9511 PHASE FREQUENCY DETECTOR SYNCB, RESETB PDB PLL REF CHARGE PUMP PLL SETTINGS CLK1 CP STATUS CLK2 CLK1B CLK2B PROGRAMMABLE DIVIDERS AND PHASE ADJUST LVPECL OUT0 /1, /2, /3... /31, /32 OUT0B LVPECL OUT1 /1, /2, /3... /31, /32 OUT1B LVPECL OUT2 /1, /2, /3... /31, /32 OUT2B SCLK SDIO APPLICATIONS RSET GND SDO LVDS/CMOS SERIAL CONTROL PORT OUT3 /1, /2, /3... /31, /32 OUT3B CSB LVDS/CMOS /1, /2, /3... /31, /32 T OUT4 OUT4B DELAY ADJUST Figure 1. Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function that serves as a coarse timing adjustment. One of the LVDS/CMOS outputs features a programmable delay element with full-scale ranges up to 10 ns of delay. This fine tuning delay block has 5-bit resolution, giving 32 possible delays from which to choose for each fullscale setting. The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9511 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is −40°C to +85°C. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 05286-001 Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual-modulus prescaler Programmable charge pump (CP) current Separate CP supply (VCPS) extends tuning range Two 1.6 GHz, differential clock inputs 5 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 3 independent 1.2 GHz LVPECL outputs Additive output jitter 225 fs rms 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 275 fs rms Fine delay adjust on 1 LVDS/CMOS output Serial control port Space-saving 48-lead LFCSP One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113©2005–2020 Analog Devices, Inc. All rights reserved. AD9511 TABLE OF CONTENTS Specifications .................................................................................... 4  A and B Counters ................................................................... 30  PLL Characteristics ...................................................................... 4  Determining Values for P, A, B, and R ............................... 30  Clock Inputs .................................................................................. 5  Phase Frequency Detector (PFD) and Charge Pump ....... 31  Clock Outputs ............................................................................... 6  Antibacklash Pulse ................................................................. 31  Timing Characteristics ................................................................ 7  STATUS Pin ........................................................................... 31  Clock Output Phase Noise .......................................................... 9  PLL Digital Lock Detect ........................................................ 31  Clock Output Additive Time Jitter .......................................... 12  PLL Analog Lock Detect ....................................................... 32  PLL and Distribution Phase Noise and Spurious .................. 14  Loss of Reference.................................................................... 32  Serial Control Port ..................................................................... 15  FUNCTION Pin ......................................................................... 32  FUNCTION Pin ......................................................................... 15  RESETB: 58h = 00b (Default) .................................... 32  STATUS Pin ................................................................................ 16  SYNCB: 58h = 01b ....................................................... 32  Power ........................................................................................... 16  PDB: 58h = 11b ............................................................ 33  Timing Diagrams............................................................................ 17  Distribution Section................................................................... 33  Absolute Maximum Ratings ......................................................... 18  CLK1 and CLK2 Clock Inputs ................................................. 33  Thermal Characteristics ............................................................ 18  Dividers ....................................................................................... 33  ESD Caution................................................................................ 18  Setting the Divide Ratio ........................................................ 33  Pin Configuration and Function Descriptions .......................... 19  Setting the Duty Cycle ........................................................... 33  Terminology .................................................................................... 21  Divider Phase Offset .............................................................. 37  Typical Performance Characteristics ........................................... 22  Delay Block ................................................................................. 38  Typical Modes of Operation ......................................................... 26  Calculating the Delay ............................................................ 38  PLL with External VCXO/VCO Followed by Clock Distribution ................................................................................. 26  Outputs ........................................................................................ 38  Power-Down Modes .................................................................. 39  Clock Distribution Only............................................................ 26  Chip Power-Down or Sleep Mode—PDB .......................... 39  PLL with External VCO and Band-Pass Filter Followed by Clock Distribution ..................................................................... 27  PLL Power-Down .................................................................. 39  Functional Description .................................................................. 29  Distribution Power-Down .................................................... 39  Overall .......................................................................................... 29  Individual Clock Output Power-Down .............................. 39  PLL Section ................................................................................. 29  Individual Circuit Block Power-Down ............................... 39  PLL Reference Input—REFIN.............................................. 29  Reset Modes ................................................................................ 40  VCO/VCXO Clock Input—CLK2 ....................................... 29  Power-On Reset—Start-Up Conditions when VS is Applied .................................................................................... 40  PLL Reference Divider—R .................................................... 29  VCO/VCXO Feedback Divider—N (P, A, B) .................... 29  Rev. B | Page 2 of 60 Asynchronous Reset via the FUNCTION Pin ................... 40  Soft Reset via the Serial Port ................................................. 40  AD9511 Single-Chip Synchronization ....................................................40  Summary Table ........................................................................... 45  SYNCB—Hardware SYNC ....................................................40  Register Map Description .......................................................... 47  Soft SYNC—Register 58h ...............................................40  Power Supply ................................................................................... 54  Multichip Synchronization ........................................................40  Power Management .................................................................... 54  Serial Control Port ..........................................................................41  Applications ..................................................................................... 55  Serial Control Port Pin Descriptions .......................................41  Using the AD9511 Outputs for ADC Clock Applications .... 55  General Operation of Serial Control Port ...............................41  CMOS Clock Distribution ......................................................... 55  Framing a Communication Cycle with CSB .......................41  LVPECL Clock Distribution ..................................................... 56  Communication Cycle—Instruction Plus Data .................41  LVDS Clock Distribution .......................................................... 56  Write .........................................................................................41  Power and Grounding Considerations and Power Supply Rejection....................................................................................... 56  Read ..........................................................................................42  The Instruction Word (16 Bits) ................................................42  MSB/LSB First Transfers ...........................................................42  Outline Dimensions ....................................................................... 57  Ordering Guide ........................................................................... 57  Register Map and Description.......................................................45  REVISION HISTORY 11/2020—Rev. A to Rev. B Changed CP-48-1 to CP-48-4 ..................................... Throughout Changes to Figure 6 ........................................................................19 Updated Outline Dimensions .......................................................57 Changes to Ordering Guide...........................................................57 6/2005—Rev. 0 to Rev. A Changes to Features .......................................................................... 1 Changes to General Description ..................................................... 1 Changes to Table 1 and Table 2 ...................................................... 5 Changes to Table 4 ............................................................................ 7 Changes to Table 5 ............................................................................ 9 Changes to Table 6 ..........................................................................14 Changes to Table 8 and Table 9 ....................................................15 Changes to Table 11 ........................................................................16 Changes to Table 13 ........................................................................20 Changes to Figure 19 to Figure 23 ................................................24 Changes to Figure 30 and Figure 31 .............................................26 Changes to Figure 32 ......................................................................27 Changes to Figure 33 ......................................................................28 Changes to VCO/VCXO Clock Input—CLK2 Section .............29 Changes to PLL Reference Divider—P Section ..........................29 Changes to A and B Counters Section .........................................30 Changes to PLL Digital Lock Detect Section ..............................31 Changes to PLL Analog Lock Detect Section ..............................32 Changes to Loss of Reference Section ..........................................32 Changes to FUNCTION Pin Section ...........................................32 Changes to RESETB: 58h = 00b (Default) Section ...........32 Changes to SYNCB: 58h = 01b Section ............................. 32 Changes to CLK1 and CLK2 Clock Inputs Section ................... 33 Changes to Divider Phase Offset Section .................................... 37 Changes to Individual Clock Output Power-Down Section .... 39 Changes to Individual Circuit Block Power-Down Section ..... 39 Changes to Soft Reset via the Serial Port Section ....................... 40 Changes to Multichip Synchronization Section ......................... 40 Changes to Serial Control Port Section ....................................... 41 Changes to Serial Control Port Pin Descriptions Section ......... 41 Changes to General Operation of Serial Control Port Section ....................................................................... 41 Added Framing a Communication Cycle with CSB Section .... 41 Added Communication Cycle—Instruction Plus Data Section ..................................................................................... 41 Changes to Write Section .............................................................. 41 Changes to Read Section ................................................................ 42 Changes to Instruction Word (16 Bits) Section ......................... 42 Changes to Table 20........................................................................ 42 Changes to MSB/LSB First Transfers Section ............................. 42 Added Figure 52; Renumbered Sequentially .............................. 44 Changes to Table 23........................................................................ 45 Changes to Table 24........................................................................ 47 Changes to Power Supply .............................................................. 54 4/2005—Revision 0: Initial Version Rev. B | Page 3 of 60 AD9511 SPECIFICATIONS Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCPS ≤ 5.5 V, TA = 25°C, RSET = 4.12 kΩ, CPRSET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. PLL CHARACTERISTICS Table 1. Parameter REFERENCE INPUTS (REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFINB Input Resistance, REFIN Input Resistance, REFINB Input Capacitance PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency PFD Input Frequency PFD Input Frequency Antibacklash Pulse Width Antibacklash Pulse Width Antibacklash Pulse Width CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP Three-State Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs. Temperature RF CHARACTERISTICS (CLK2)2 Input Frequency Input Sensitivity Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance CLK2 VS. REFIN DELAY PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM (16/17) P = 32 DM (32/33) CLK2 Input Frequency for PLL Min Typ 0 1.45 1.40 4.0 4.5 150 1.60 1.50 4.9 5.4 2 Max Unit 250 MHz mV p-p V V kΩ kΩ pF 1.75 1.60 5.8 6.3 100 100 45 1.5 1.3 1.3 2.9 6.0 MHz MHz MHz ns ns ns 4.8 0.60 2.5 2.7/10 1 2 1.5 2 mA mA % kΩ nA % % % 150 1.6 1.6 GHz 1.7 1.8 mV p-p V V mV p-p 150 4.0 4.8 2 500 5.6 600 1000 1600 1600 1600 300 kΩ pF ps MHz MHz MHz MHz MHz MHz Rev. B | Page 4 of 60 Test Conditions/Comments Self-bias voltage of REFIN1. Self-bias voltage of REFINB1. Self-biased1. Self-biased1. Antibacklash pulse width 0Dh = 00b. Antibacklash pulse width 0Dh = 01b. Antibacklash pulse width 0Dh = 10b. 0Dh = 00b. (This is the default setting.) 0Dh = 01b. 0Dh = 10b. Programmable. With CPRSET = 5.1 kΩ. VCP = VCPS/2. 0.5 < VCP < VCPS − 0.5 V. 0.5 < VCP < VCPS − 0.5 V. VCP = VCPS/2 V. Frequencies > 1200 MHz (LVPECL) or 800 MHz (LVDS) require a minimum divide-by-2 (see the Distribution Section). Self-biased; enables ac coupling. With 200 mV p-p signal applied. CLK2 ac-coupled; CLK2B capacitively bypassed to RF ground. Self-biased. Difference at PFD. See the VCO/VCXO Feedback Divider—N (P, A, B) section. A, B counter input frequency. AD9511 Parameter NOISE CHARACTERISTICS In-Band Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) Min Typ Max Unit Test Conditions/Comments The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20logN (where N is the N divider value). @ 50 kHz PFD Frequency @ 2 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit −172 −156 −149 −142 −218 + 10 × log (fPFD) dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 3.5 7.5 3.5 ns ns ns 7 15 11 ns ns ns PLL DIGITAL LOCK DETECT WINDOW4 Required to Lock (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns Only) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns) To Unlock After Lock (Hysteresis)4 Low Range (ABP 1.3 ns, 2.9 ns Only) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns) Approximation of the PFD/CP phase noise floor (in the flat region) inside the PLL loop bandwidth. When running closed loop this phase noise is gained up by 20 × log(N)3. Signal available at STATUS pin when selected by 08h. Selected by Register ODh. = 1b. = 0b. = 0b. Selected by Register 0Dh. = 1b. = 0b. = 0b. 1 REFIN and REFINB self-bias points are offset slightly to avoid chatter on an open input condition. CLK2 is electrically identical to CLK1; the distribution only input can be used as differential or single-ended input (see the Clock Inputs section). 3 Example: −218 + 10 × log(fPFD) + 20 × log(N) should give the values for the in-band noise at the VCO output. 4 For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time. 2 CLOCK INPUTS Table 2. Parameter CLOCK INPUTS (CLK1, CLK2)1 Input Frequency Input Sensitivity Min Typ 0 Unit 1.6 GHz mV p-p 1502 Input Level Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Max 1.5 1.3 4.0 1.6 150 4.8 2 23 V p-p 1.7 1.8 V V mV p-p kΩ pF 5.6 1 Test Conditions/Comments Jitter performance can be improved with higher slew rates (greater swing). Larger swings turn on the protection diodes and can degrade jitter performance. Self-biased; enables ac coupling. With 200 mV p-p signal applied; dc-coupled. CLK2 ac-coupled; CLK2B ac bypassed to RF ground. Self-biased. CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input. With a 50 Ω termination, this is −12.5 dBm. 3 With a 50 Ω termination, this is +10 dBm. 2 Rev. B | Page 5 of 60 AD9511 CLOCK OUTPUTS Table 3. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2; Differential Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) LVDS CLOCK OUTPUTS OUT3, OUT4; Differential Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) CMOS CLOCK OUTPUTS OUT3, OUT4 Output Frequency Output Voltage High (VOH) Output Voltage Low (VOL) Min Typ Max Unit VS − 1.22 VS − 2.10 660 VS − 0.98 VS − 1.80 810 1200 VS − 0.93 VS − 1.67 965 MHz V V mV 250 360 1.125 1.23 14 800 450 25 1.375 25 24 250 VS-0.1 0.1 Rev. B | Page 6 of 60 MHz mV mV V mV mA MHz V V Test Conditions/Comments Termination = 50 Ω to VS − 2 V Output level 3Dh (3Eh) (3Fh) = 10b See Figure 21 Termination = 100 Ω differential; default Output level 40h (41h) = 01b 3.5 mA termination current See Figure 22 Output shorted to GND Single-ended measurements; B outputs: inverted, termination open With 5 pF load each output; see Figure 23 @ 1 mA load @ 1 mA load AD9511 TIMING CHARACTERISTICS Table 4. Parameter LVPECL Output Rise Time, tRP Output Fall Time, tFP PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT1 Divide = Bypass Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS OUT1 to OUT0 on Same Part, tSKP2 OUT1 to OUT2 on Same Part, tSKP2 OUT0 to OUT2 on Same Part, tSKP2 All LVPECL OUT Across Multiple Parts, tSKP_AB3 Same LVPECL OUT Across Multiple Parts, tSKP_AB3 LVDS Output Rise Time, tRL Output Fall Time, tFL PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT1 OUT3 to OUT4 Divide = Bypass Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, LVDS OUTPUTS OUT3 to OUT4 on Same Part, tSKV2 All LVDS OUTs Across Multiple Parts, tSKV_AB3 Same LVDS OUT Across Multiple Parts, tSKV_AB3 CMOS Output Rise Time, tRC Output Fall Time, tFC PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT1 Divide = Bypass Divide = 2 − 32 Variation with Temperature OUTPUT SKEW, CMOS OUTPUTS OUT3 to OUT4 on Same Part, tSKC2 All CMOS OUT Across Multiple Parts, tSKC_AB3 Same CMOS OUT Across Multiple Parts, tSKC_AB3 LVPECL-TO-LVDS OUT Output Skew, tSKP_V LVPECL-TO-CMOS OUT Output Skew, tSKP_C LVDS-TO-CMOS OUT Output Skew, tSKV_C Min Typ Max Unit 130 130 180 180 ps ps 335 375 490 545 0.5 635 695 ps ps ps/°C 70 15 45 100 45 65 140 80 90 275 130 ps ps Ps ps ps 200 210 350 350 ps ps 1.33 1.38 0.9 1.59 1.64 ns ns ps/°C +270 450 325 ps ps ps 681 646 865 992 ps ps 1.02 1.07 1.39 1.44 1 1.71 1.76 ns ns ps/°C −140 +145 +300 650 500 ps ps 0.99 1.04 Test Conditions/Comments Termination = 50 Ω to VS − 2 V Output level 3Dh (3Eh) (3Fh) = 10b 20% to 80%, measured differentially 80% to 20%, measured differentially Termination = 100 Ω differential Output level 40h (41h) = 01b 3.5 mA termination current 20% to 80%, measured differentially 80% to 20%, measured differentially Delay off on OUT4 Delay off on OUT4 −85 B outputs are inverted; termination = open 20% to 80%; CLOAD = 3 pF 80% to 20%; CLOAD = 3 pF Delay off on OUT4 Delay off on OUT4 0.74 0.92 1.14 ns 0.88 1.14 1.43 ns 158 353 506 ps Rev. B | Page 7 of 60 Everything the same; different logic type LVPECL to LVDS on same part Everything the same; different logic type LVPECL to CMOS on same part Everything the same; different logic type LVDS to CMOS on same part AD9511 Parameter DELAY ADJUST Shortest Delay Range4 Zero Scale Full Scale Linearity, DNL Linearity, INL Longest Delay Range4 Zero Scale Full Scale Linearity, DNL Linearity, INL Delay Variation with Temperature Long Delay Range, 10 ns5 Zero Scale Full Scale Short Delay Range, 1 ns5 Zero Scale Full Scale Min Typ Max Unit 0.05 0.72 0.36 1.12 0.5 0.8 0.68 1.51 ns ns LSB LSB 0.20 9.0 0.57 10.2 0.3 0.6 0.95 11.6 ns ns LSB LSB 0.35 −0.14 ps/°C ps/°C 0.51 0.67 ps/°C ps/°C 1 Test Conditions/Comments OUT4; LVDS and CMOS 35h 11111b 36h 00000b 36h 11111b 35h 00000b 36h 00000b 36h 11111b The measurements are for CLK1. For CLK2, add approximately 25 ps. This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. 3 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. 4 Incremental delay; does not include propagation delay. 5 All delays between zero scale and full scale can be estimated by linear interpolation. 2 Rev. B | Page 8 of 60 AD9511 CLOCK OUTPUT PHASE NOISE Table 5. Parameter CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 38.88 MHz Divide Ratio = 16 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 491.52 MHz, OUT = 61.44 MHz Divide Ratio = 8 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset Min Typ Max Unit −125 −132 −140 −148 −153 −154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −128 −140 −148 −155 −161 −161 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −135 −145 −158 −165 −165 −166 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −131 −142 −153 −160 −165 −165 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −125 −132 −140 −151 −157 −158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −138 −144 −154 −163 −164 −165 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. B | Page 9 of 60 Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO Input slew rate > 1 V/ns AD9511 Parameter CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT= 622.08 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset Min Typ Max Unit −100 −110 −118 −129 −135 −140 −148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −112 −122 −132 −142 −148 −152 −155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −108 −118 −128 −138 −145 −148 −154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −118 −129 −136 −147 −153 −156 −158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −108 −118 −128 −138 −145 −148 −155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −118 −127 −137 −147 dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. B | Page 10 of 60 Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO AD9511 Parameter @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset > 10 MHz Offset CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset >1 MHz Offset Min Typ −154 −156 −158 Max Unit dBc/Hz dBc/Hz dBc/Hz Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO −110 −121 −130 −140 −145 −149 −156 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −122 −132 −143 −152 −158 −160 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −122 −132 −140 −150 −155 −158 −160 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −128 −136 −146 −155 −161 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. B | Page 11 of 60 AD9511 CLOCK OUTPUT ADDITIVE TIME JITTER Table 6. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 155.52 MHz Divide Ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 100 MHz Both LVDS (OUT3, OUT4) = 100 MHz CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Both LVDS (OUT3, OUT4) = 50 MHz CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off) CLK1 = 400 MHz Min Typ Max 40 fs rms Test Conditions/Comments Distribution Section only; does not include PLL or external VCO/VCXO BW = 12 kHz − 20 MHz (OC-12) 55 fs rms BW = 12 kHz − 20 MHz (OC-3) 215 fs rms Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz 215 fs rms Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz 222 225 225 Unit fs rms fs rms fs rms Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On) LVDS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz 264 fs rms LVDS (OUT3) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 319 fs rms LVDS (OUT4) = 100 MHz Divide Ratio = 4 Rev. B | Page 12 of 60 Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Distribution Section only; does not include PLL or external VCO/VCXO Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz AD9511 Parameter CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 LVDS (OUT4) = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3) = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs Off) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs On) All LVPECL = 50 MHz CLK1 = 400 MHz Min Typ 395 Max 395 367 367 548 548 Unit fs rms fs rms fs rms fs rms fs rms fs rms LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs On) All LVPECL = 50 MHz CMOS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz 275 fs rms Both CMOS (OUT3, OUT4) = 100 MHz (B Output On) Divide Ratio = 4 CLK1 = 400 MHz 400 fs rms CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz LVDS (OUT4) = 50 MHz CLK1 = 400 MHz 374 CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz CMOS (OUT4) = 50 MHz (B Output Off) fs rms Test Conditions/Comments Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Distribution Section only; does not include PLL or external VCO/VCXO Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Rev. B | Page 13 of 60 AD9511 Parameter CLK1 = 400 MHz Min CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz CMOS (OUT4) = 50 MHz (B Output On) DELAY BLOCK ADDITIVE TIME JITTER1 100 MHz Output Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000 Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111 Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000 Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111 Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000 Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111 Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000 Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111 Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000 Delay FS = 5 ns (200 μA, 1C) Fine Adj. 11111 Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00000 Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00100 1 Typ 555 Max Unit fs rms Test Conditions/Comments Calculated from SNR of ADC method; FC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Incremental additive jitter1 0.61 0.73 0.71 1.2 0.86 1.8 1.2 2.1 1.3 2.7 2.0 2.8 ps ps ps ps ps ps ps ps ps ps ps ps This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method. PLL AND DISTRIBUTION PHASE NOISE AND SPURIOUS Table 7. Parameter PHASE NOISE AND SPURIOUS Min Typ Max Unit VCXO = 245.76 MHz, FPFD = 1.2288 MHz; R = 25, N = 200 245.76 MHz Output Phase Noise @100 kHz Offset Spurious