1.6 GHz Clock Distribution IC,
Dividers, Delay Adjust, Three Outputs
AD9514
FEATURES
1.6 GHz differential clock input
3 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
2 independent 1.6 GHz LVPECL clock outputs
Additive broadband output jitter 225 fs rms
1 independent 800 MHz/250 MHz LVDS/CMOS clock output
Additive broadband output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
FUNCTIONAL BLOCK DIAGRAM
RSET
VS
GND
AD9514
LVPECL
OUT0
/1. . . /32
OUT0B
LVPECL
CLK
OUT1
/1. . . /32
CLKB
OUT1B
LVDS/CMOS
OUT2
t
/1. . . /32
SYNCB
OUT2B
APPLICATIONS
SETUP LOGIC
VREF
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
05596-001
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
Figure 1.
GENERAL DESCRIPTION
The AD9514 features a multi-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with
demanding phase noise and jitter requirements also benefit from
this part.
There are three independent clock outputs. Two of the outputs
are LVPECL, and the third output can be set to either LVDS or
CMOS levels. The LVPECL outputs operate to 1.6 GHz, and
the third output operates to 800 MHz in LVDS mode and to
250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to another clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
The LVDS/CMOS output features a delay element with three
selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each
with 16 steps of fine adjustment.
The AD9514 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to ⅓ VS. The VREF pin provides a level of
⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
The AD9514 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9514 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is −40°C to
+85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005–2020 Analog Devices, Inc. All rights reserved.
AD9514
TABLE OF CONTENTS
Features .............................................................................................. 1
Power-On SYNC .................................................................... 18
Applications ...................................................................................... 1
SYNCB ..................................................................................... 18
Functional Block Diagram .............................................................. 1
RSET Resistor ................................................................................ 19
General Description ......................................................................... 1
VREF ............................................................................................ 19
Revision History ............................................................................... 2
Setup Configuration .................................................................. 19
Specifications .................................................................................... 3
Divider Phase Offset .................................................................. 22
Clock Input ................................................................................... 3
Delay Block ................................................................................. 22
Clock Outputs ............................................................................... 3
Outputs ........................................................................................ 23
Timing Characteristics ................................................................ 4
Power Supply .............................................................................. 23
Clock Output Phase Noise .......................................................... 5
Exposed Metal Paddle ........................................................... 24
Clock Output Additive Time Jitter ............................................ 8
Power Management ................................................................... 24
SYNCB, VREF, and Setup Pins ................................................ 10
Applications .................................................................................... 25
Power ........................................................................................... 10
Using the AD9514 Outputs for ADC Clock Applications ... 25
Timing Diagrams............................................................................ 11
LVPECL Clock Distribution..................................................... 25
Absolute Maximum Ratings ......................................................... 12
LVDS Clock Distribution.......................................................... 26
Thermal Characteristics ............................................................ 12
CMOS Clock Distribution ........................................................ 26
ESD Caution................................................................................ 12
Setup Pins (S0 to S10) ................................................................ 26
Pin Configuration and Function Descriptions .......................... 13
Power and Grounding Considerations and Power Supply
Rejection ...................................................................................... 26
Terminology .................................................................................... 14
Typical Performance Characteristics ........................................... 15
Functional Description .................................................................. 18
Overall .......................................................................................... 18
Phase Noise and Jitter Measurement Setups .......................... 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 28
CLK, CLKB—Differential Clock Input ................................... 18
Synchronization.......................................................................... 18
REVISION HISTORY
11/2020—Rev. 0 to Rev. A
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Figure 6........................................................................ 13
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
7/2005—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD9514
SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V ± 5%, TA = 25°C, RSET = 4.12 kΩ, LVPECL VOD = 790 mV, unless otherwise noted. Minimum (min)
and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
CLOCK INPUT
Table 1.
Parameter
CLOCK INPUT (CLK)
Input Frequency1
Input Sensitivity1
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
1
Min
Typ
0
1.5
1.3
4.0
150
1.6
150
4.8
2
Max
Unit
1.6
GHz
mV p-p
V
V
mV p-p
kΩ
pF
1.7
1.8
5.6
Test Conditions/Comments
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLKB ac-bypassed to RF ground
Self-biased
A slew rate of 1 V/ns is required to meet jitter, phase noise, and propagation delay specifications.
CLOCK OUTPUTS
Table 2.
Parameter
LVPECL CLOCK OUTPUTS
(OUT0, OUT1) Differential
Output Frequency
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
LVDS CLOCK OUTPUT
(OUT2) Differential
Output Frequency
Differential Output Voltage (VOD)
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
CMOS CLOCK OUTPUT
(OUT2) Single-Ended
Output Frequency
Output Voltage High (VOH)
Output Voltage Low (VOL)
Min
Typ
Max
Unit
0
VS − 1.1
VS − 1.90
640
VS − 0.96
VS − 1.76
790
1.6
VS − 0.82
VS − 1.52
960
GHz
V
V
mV
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Termination = 100 Ω differential
0
250
350
1.125
1.23
14
0
VS − 0.1
800
450
30
1.375
25
24
MHz
mV
mV
V
mV
mA
250
MHz
V
V
0.1
Rev. A | Page 3 of 28
Output shorted to GND
Single-ended measurements; termination open
Complementary output on (OUT2B)
With 5 pF load
@ 1 mA load
@ 1 mA load
AD9514
TIMING CHARACTERISTICS
CLK input slew rate = 1 V/ns or greater.
Table 3.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVPECL
OUT0 to OUT1 on Same Part, tSKP1
Both LVPECL Outputs Across Multiple Parts, tSKP_AB2
Same LVPECL Output Across Multiple Parts, tSKP_AB2
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVDS
LVDS Output Across Multiple Parts, tSKV_AB2
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT
Divide = 1
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, CMOS
CMOS Output Across Multiple Parts, tSKC_AB2
LVPECL-TO-LVDS OUT
Output Delay, tSKV_C
LVPECL-TO-CMOS OUT
Output Delay, tSKV_C
DELAY ADJUST (OUT2; LVDS and CMOS)
S0 = 1/3
Zero Scale Delay Time3
Zero Scale Variation with Temperature
Full Scale Time Delay3
Full Scale Variation with Temperature
S0 = 2/3
Zero Scale Delay Time3
Zero Scale Variation with Temperature
Full Scale Time Delay3
Full Scale Variation with Temperature
Min
Typ
Max
Unit
60
60
100
100
ps
ps
355
395
480
530
0.5
635
710
ps
ps
ps/°C
−50
0
+55
125
125
ps
ps
ps
200
210
350
350
ps
ps
1.25
1.30
0.9
1.55
1.60
ns
ns
ps/°C
230
ps
650
650
865
990
ps
ps
1.45
1.50
1
1.75
1.80
ns
ns
ps/°C
300
ps
1.00
1.05
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 100 Ω differential, 3.5 mA
20% to 80%, measured differentially
80% to 20%, measured differentially
Optional delay off
Optional delay off
1.10
1.15
B outputs are inverted; termination = open
20% to 80%; CLOAD = 3 pF single-ended
80% to 20%; CLOAD = 3 pF single-ended
Optional delay off
Optional delay off
560
790
950
ps
700
970
1150
ps
0.34
0.20
1.7
−0.38
ns
ps/°C
ns
ps/°C
0.45
0.31
5.9
−1.3
ns
ps/°C
ns
ps/°C
Rev. A | Page 4 of 28
AD9514
Parameter
S0 = 1
Zero Scale Delay Time3
Zero Scale Variation with Temperature
Full Scale Time Delay3
Full Scale Variation with Temperature
Linearity, DNL
Linearity, INL
1
2
3
Min
Typ
Max
0.56
0.47
11.4
−5
0.2
0.2
Unit
Test Conditions/Comments
ns
ps/°C
ns
ps/°C
LSB
LSB
This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.
This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.
Incremental delay; does not include propagation delay.
CLOCK OUTPUT PHASE NOISE
CLK input slew rate = 1 V/ns or greater.
Table 4.
Parameter
CLK-TO-LVPECL ADDITIVE PHASE NOISE
CLK = 622.08 MHz, OUT = 622.08 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 622.08 MHz, OUT = 155.52 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 622.08 MHz, OUT = 38.88 MHz
Divide = 16
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 491.52 MHz, OUT = 61.44 MHz
Divide = 8
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Typ
Max
Unit
−125
−132
−140
−148
−153
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−128
−140
−148
−155
−161
−161
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−135
−145
−158
−165
−165
−166
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−131
−142
−153
−160
−165
−165
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 5 of 28
Test Conditions/Comments
AD9514
Parameter
CLK = 491.52 MHz, OUT = 245.76 MHz
Divide = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK = 245.76 MHz, OUT = 61.44 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK-TO-LVDS ADDITIVE PHASE NOISE
CLK = 622.08 MHz, OUT= 622.08 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 622.08 MHz, OUT = 155.52 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 491.52 MHz, OUT = 245.76 MHz
Divide = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
Min
Typ
Max
Unit
−125
−132
−140
−151
−157
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−138
−144
−154
−163
−164
−165
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−100
−110
−118
−129
−135
−140
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−112
−122
−132
−142
−148
−152
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−108
−118
−128
−138
−145
−148
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 6 of 28
Test Conditions/Comments
AD9514
Parameter
CLK = 491.52 MHz, OUT = 122.88 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 245.76 MHz, OUT = 245.76 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 245.76 MHz, OUT = 122.88 MHz
Divide = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK-TO-CMOS ADDITIVE PHASE NOISE
CLK = 245.76 MHz, OUT = 245.76 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 245.76 MHz, OUT = 61.44 MHz
Divide = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
Min
Typ
Max
Unit
−118
−129
−136
−147
−153
−156
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−108
−118
−128
−138
−145
−148
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−118
−127
−137
−147
−154
−156
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−110
−121
−130
−140
−145
−149
−156
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−125
−132
−143
−152
−158
−160
−162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 7 of 28
Test Conditions/Comments
AD9514
Parameter
CLK = 78.6432 MHz, OUT = 78.6432 MHz
Divide = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK = 78.6432 MHz, OUT = 39.3216 MHz
Divide = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Typ
Max
Unit
−122
−132
−140
−150
−155
−158
−160
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−128
−136
−146
−155
−161
−162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 5.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz
LVPECL (OUT0 and OUT1) = 622.08 MHz
Divide = 1
CLK = 622.08 MHz
LVPECL (OUT0 and OUT1) = 155.52 MHz
Divide = 4
CLK = 400 MHz
LVPECL (OUT0 and OUT1) = 100 MHz
Divide = 4
CLK = 400 MHz
LVPECL (OUT0, OUT1) = 100 MHz
Divide = 4
CLK = 400 MHz
LVPECL (OUT0 or OUT1) = 100 MHz
Divide = 4
Other LVPECL = 50 MHz
LVDS (OUT2) = 50 MHz
CLK = 400 MHz
LVPECL (OUT0 or OUT1) = 100 MHz
Divide = 4
Other LVPECL = 50 MHz
CMOS (OUT2) = 50 MHz
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 400 MHz
LVDS (OUT2) = 100 MHz
Divide = 4
Min
Typ
Unit
Test Conditions/Comments
40
fs rms
BW = 12 kHz − 20 MHz
OUT2 off
55
fs rms
BW = 12 kHz − 20 MHz
OUT2 off
215
fs rms
Calculated from SNR of ADC method;
OUT2 off
215
fs rms
Calculated from SNR of ADC method;
Other LVPECL and OUT2 LVDS at same frequency
225
fs rms
Calculated from SNR of ADC method;
fs rms
Interferer
Interferer
Calculated from SNR of ADC method;
230
300
Max
fs rms
Rev. A | Page 8 of 28
Interferer
Interferer
Delay off
Calculated from SNR of ADC method;
OUT0 at same frequency; OUT1 off
AD9514
Parameter
CLK = 400 MHz
LVDS (OUT2) = 100 MHz
Divide = 4
Both LVPECL = 50 MHz
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 400 MHz
CMOS (OUT2) = 100 MHz
Divide = 4
CLK = 400 MHz
CMOS (OUT2) = 100 MHz
Divide = 4
Both LVPECL = 50 MHz
DELAY BLOCK ADDITIVE TIME JITTER1
Delay FS = 1.5 ns Fine Adj. 00000
Delay FS = 1.5 ns Fine Adj. 11111
Delay FS = 5 ns Fine Adj. 00000
Delay FS = 5 ns Fine Adj. 11111
Delay FS = 10 ns Fine Adj. 00000
Delay FS = 10 ns Fine Adj. 11111
1
Min
Typ
350
Max
Unit
fs rms
290
fs rms
315
fs rms
Test Conditions/Comments
Calculated from SNR of ADC method
Interferer(s)
Delay off
Calculated from SNR of ADC method
OUT0 at same frequency; OUT1 off
Calculated from SNR of ADC method
Interferer(s)
100 MHz output; incremental additive jitter1
0.71
1.2
1.3
2.7
2.0
2.8
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
Rev. A | Page 9 of 28
AD9514
SYNCB, VREF, AND SETUP PINS
Table 6.
Parameter
SYNCB
Logic High
Logic Low
Capacitance
VREF
Output Voltage
S0 TO S10
Levels
0
1/3
2/3
1
Min
Typ
Max
Unit
0.40
V
V
pF
0.76 VS
V
0.1 VS
0.45 VS
0.8 VS
V
V
V
V
2.7
2
0.62 VS
0.2 VS
0.55 VS
0.9 VS
Test Conditions/Comments
Minimum − maximum from 0 mA to 1 mA load
POWER
Table 7.
Parameter
POWER-ON SYNCHRONIZATION1
VS Transit Time from 2.2 V to 3.1
V
POWER DISSIPATION
POWER DELTA
Divider (Divide = 2 to Divide = 1)
LVPECL Output
LVDS Output
CMOS Output (Static)
CMOS Output (@ 62.5 MHz)
CMOS Output (@ 125 MHz)
Delay Block
1
Min
Typ
Max
35
Unit
ms
Test Conditions/Comments
See Figure 24.
295
405
550
mW
380
490
635
mW
410
525
680
mW
All outputs on. 2 LVPECL (divide = 2), 1 LVDS (divide = 2). No clock.
Does not include power dissipated in external resistors.
All outputs on. 2 LVPECL (divide = 2), 1 CMOS (divide = 2);
at 62.5 MHz out (5 pF load).
All outputs on. 2 LVPECL, 1 CMOS (divide = 2); At 125 MHz out (5 pF load).
15
65
20
30
80
110
30
30
90
50
40
110
150
45
45
125
85
50
140
190
65
mW
mW
mW
mW
mW
mW
mW
For each divider. No clock.
For each output. No clock.
No clock.
No clock.
Single-ended. At 62.5 MHz out with 5 pF load.
Single-ended. At 125 MHz out with 5 pF load.
Off to 1.5 ns fs, delay word = 60; output clocking at 62.5 MHz.
This is the rise time of the VS supply that is required to ensure that a synchronization of the outputs occurs on power-up. The critical factor is the time it takes the VS to
transition the range from 2.2 V to 3 .1 V. If the rise time is too slow, the outputs will not be synchronized.
Rev. A | Page 10 of 28
AD9514
TIMING DIAGRAMS
tCLK
CLK
DIFFERENTIAL
80%
tPECL
LVDS
tRL
05596-002
tCMOS
Figure 2. CLK/CLKB to Clock Output Timing, Divide = 1 Mode
tFL
05596-003
20%
tLVDS
Figure 4. LVDS Timing, Differential
SINGLE-ENDED
DIFFERENTIAL
80%
80%
CMOS
3pF LOAD
LVPECL
tFP
05596-099
tRP
tRC
tFC
Figure 5. CMOS Timing, Single-Ended, 3 pF Load
Figure 3. LVPECL Timing, Differential
Rev. A | Page 11 of 28
05596-004
20%
20%
AD9514
ABSOLUTE MAXIMUM RATINGS
Table 8.
Parameter or Pin
VS
RSET
CLK
CLK
OUT0, OUT1, OUT2
FUNCTION
STATUS
Junction Temperature1
Storage Temperature
Lead Temperature (10 sec)
With
Respect
to
GND
GND
GND
CLKB
GND
GND
GND
Min
−0.3
−0.3
−0.3
−1.2
−0.3
−0.3
−0.3
−65
Max
+3.6
VS + 0.3
VS + 0.3
+1.2
VS + 0.3
VS + 0.3
VS + 0.3
150
+150
300
Unit
V
V
V
V
V
V
V
°C
°C
°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS2
Thermal Resistance
32-Lead LFCSP3
θJA = 36.6°C/W
1
See Thermal Characteristics for θJA.
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-7.
3
The external pad of this package must be soldered to adequate copper land
on board.
2
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 12 of 28
AD9514
25 S0
26 VS
28 OUT0
27 OUT0B
29 VS
30 VS
31 GND
32 RSET
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VS 1
THE EXPOSED PADDLE
IS AN ELECTRICAL AND
THERMAL CONNECTION
24 VS
CLK 2
23 OUT1
CLKB 3
22 OUT1B
AD9514
VS 4
SYNCB 5
25
24
21 VS
TOP VIEW
(Not to Scale)
32
1
20 VS
VREF 6
19 OUT2
S10 7
18 OUT2B
S9 8
EXPOSED PAD
(BOTTOM VIEW)
GND
17
16
9
8
05596-005
NOTES
1. NOTE THAT THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL
CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE
TO FUNCTION PROPERLY, THE PADDLE MUST BE SOLDERED TO A PCB
LAND THAT FUNCTIONS AS BOTH A HEAT DISSIPATION PATH AS WELL AS
AN ELECTRICAL GROUND (ANALOG).
05596-006
S1 16
S2 15
S3 14
S4 13
S5 12
S6 11
S7 10
S8 9
17 VS
Figure 7. Exposed Paddle
Figure 6. 32-Lead LFCSP Pin Configuration
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be soldered to a PCB land that functions as both a heat dissipation path as well as an electrical
ground (analog).
Table 9. Pin Function Descriptions
Pin No.
1, 4 ,17, 20, 21,
24, 26, 29, 30
2
3
5
6
7 to 16, 25
Mnemonic
VS
Description
Power Supply (3.3 V).
CLK
CLKB
SYNCB
VREF
S10 to S0
18
19
22
23
27
28
31, Exposed Paddle
32
OUT2B
OUT2
OUT1B
OUT1
OUT0B
OUT0
GND
RSET
Clock Input.
Complementary Clock Input.
Used to Synchronize Outputs; Do Not Let Float.
Provides 2/3 VS for Use as One of the Four Logic Levels on S0 to S10.
Setup Select Pins. These are 4-state logic. The logic levels are VS, GND, 1/3 VS, and 2/3 VS.
The VREF pin provides 2/3 VS. Each pin is internally biased to 1/3 VS so that a pin requiring
that logic level should be left no connection (NC).
Complementary LVDS/Inverted CMOS Output.
LVDS/CMOS Output.
Complementary LVPECL Output.
LVPECL Output.
Complementary LVPECL Output.
LVPECL Output.
Ground. The exposed paddle on the back of the chip is also GND.
Current Sets Resistor to Ground. Nominal value = 4.12 kΩ.
Rev. A | Page 13 of 28
AD9514
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0 to 360 degrees
for each cycle. Actual signals, however, display a certain
amount of variation from ideal phase progression over time.
This phenomenon is called phase jitter. Although there are
many causes that can contribute to phase jitter, one major
component is due to random noise that is characterized
statistically as being Gaussian (normal) in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is also meaningful to integrate the total power contained
within some interval of offset frequencies (for example, 10 kHz
to 10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency
interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the
time domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings is
seen to vary. For a square wave, the time jitter is seen as a
displacement of the edges from their ideal (regular) times of
occurrence. In both cases, the variations in timing from the
ideal are the time jitter. Since these variations are random in
nature, the time jitter is specified in units of seconds root mean
square (rms) or 1 sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the SNR and dynamic range of the converter.
A sampling clock with the lowest possible jitter provides the
highest performance from a given converter.
Additive Phase Noise
It is the amount of phase noise that is attributable to the device
or subsystem being measured. The phase noise of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device affects the
total system phase noise when used in conjunction with the
various oscillators and clock sources, each of which contribute
their own phase noise to the total. In many cases, the phase
noise of one element dominates the system phase noise.
Additive Time Jitter
It is the amount of time jitter that is attributable to the device
or subsystem being measured. The time jitter of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device will affect the
total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contribute
their own time jitter to the total. In many cases, the time jitter
of the external oscillators and clock sources dominates the
system time jitter.
Rev. A | Page 14 of 28
AD9514
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
0.4
2 LVPECL (DIV ON)
2 LVPECL (DIV ON) + 1 CMOS (DIV ON)
0.3
0.5
POWER (W)
400
800
1200
OUTPUT FREQUENCY (MHz)
1600
Figure 8. Power vs. Frequency—LVPECL, LVDS
START 300kHz
STOP 5GHz
2 LVPECL (DIV OFF) + 1 CMOS (DIV OFF)
0.3
0
20
40
60
80
OUTPUT FREQUENCY (MHz)
100
Figure 10. Power vs. Frequency—LVPECL, CMOS
Figure 9. CLK Smith Chart (Evaluation Board)
Rev. A | Page 15 of 28
05596-096
0.1
0.4
1 LVDS (DIV ON)
05596-098
0.2
05596-097
POWER (W)
2 LVPECL (DIV = 1)
120
AD9514
DIFFERENTIAL SWING (V p-p)
1.8
1.7
1.6
1.5
1.4
VERT 500mV/DIV
05596-012
05596-095
1.3
1.2
100
HORIZ 200ps/DIV
600
1100
1600
OUTPUT FREQUENCY (MHz)
Figure 14. LVPECL Differential Peak-to-Peak Output Swing vs. Frequency
Figure 11. LVPECL Differential Output @ 1600 MHz
VERT 100mV/DIV
700
650
600
550
500
100
HORIZ 500ps/DIV
Figure 12. LVDS Differential Output @ 800 MHz
05596-013
05596-010
DIFFERENTIAL SWING (mV p-p)
750
300
500
700
OUTPUT FREQUENCY (MHz)
900
Figure 15. LVDS Differential Peak-to-Peak Output Swing vs. Frequency
3.5
2pF
3.0
2.5
OUTPUT (VPK)
10pF
2.0
1.5
1.0
20pF
VERT 500mV/DIV
0
HORIZ 1ns/DIV
Figure 13. CMOS Single-Ended Output @ 250 MHz with 10 pF Load
05596-014
05596-011
0.5
0
100
200
300
400
OUTPUT FREQUENCY (MHz)
500
600
Figure 16. CMOS Single-Ended Output Swing vs. Frequency and Load
Rev. A | Page 16 of 28
–110
–120
–120
–130
–130
–140
–140
–150
–150
–160
–160
1k
10k
100k
OFFSET (Hz)
1M
–170
10
10M
–80
–90
–90
–100
–100
–110
–110
L(f) (dBc/Hz)
–80
–120
–130
–150
–150
–160
–160
1k
10k
100k
OFFSET (Hz)
1M
–170
10
10M
–100
–110
–110
–120
–120
L(f) (dBc/Hz)
–100
–130
–140
–160
–160
10k
100k
OFFSET (Hz)
1M
1k
10k
100k
OFFSET (Hz)
1M
10M
–140
–150
1k
100
–130
–150
100
10M
Figure 21. Additive Phase Noise—LVDS Divide = 2, 122.88 MHz
05596-017
L(f) (dBc/Hz)
Figure 18. Additive Phase Noise—LVDS Divide = 1, 245.76 MHz
–170
10
1M
–130
–140
100
10k
100k
OFFSET (Hz)
–120
–140
–170
10
1k
Figure 20. Additive Phase Noise—LVPECL Divide = 1, 622.08 MHz
05596-016
L(f) (dBc/Hz)
Figure 17. Additive Phase Noise—LVPECL Divide = 1, 245.76 MHz
100
05596-019
100
10M
–170
10
Figure 19. Additive Phase Noise—CMOS Divide = 1, 245.76 MHz
05596-020
–170
10
05596-018
L(f) (dBc/Hz)
–110
05596-015
L(f) (dBc/Hz)
AD9514
100
1k
10k
100k
OFFSET (Hz)
1M
Figure 22. Additive Phase Noise—CMOS Divide = 4, 61.44 MHz
Rev. A | Page 17 of 28
10M
AD9514
FUNCTIONAL DESCRIPTION
3.3V
OVERALL
3.1V
2.2V
35ms
MAX
VS
0V
CLK
CLOCK FREQUENCY
IS EXAMPLE ONLY
OUT
DIVIDE = 2
PHASE = 0
OUT2 includes an analog delay block that can be set to add an
additional delay of 1.5 ns, 5 ns, or 10 ns full scale, each with
16 levels of fine adjustment.
< 65ms
05596-094
The AD9514 provides for the distribution of its input clock
on up to three outputs simultaneously. OUT0 and OUT1 are
LVPECL levels. OUT2 can be set to either LVDS or CMOS
levels. Each output has its own divider that can be set for a
divide ratio selected from a list of integer values from 1
(bypassed) to 32.
INTERNAL SYNC NODE
Figure 24. Power-On Sync Timing
CLK, CLKB—DIFFERENTIAL CLOCK INPUT
The CLK and CLKB pins are differential clock input pins.
This input works up to 1600 MHz. The jitter performance is
degraded by a slew rate below 1 V/ns. The input level should be
between approximately 150 mV p-p to no more than 2 V p-p.
Anything greater can result in turning on the protection diodes
on the input pins.
See Figure 23 for the CLK equivalent input circuit. This input
is fully differential and self-biased. The signal should be accoupled using capacitors. If a single-ended input must be used,
this can be accommodated by ac coupling to one side of the
differential input only. The other side of the input should be
bypassed to a quiet ac ground by a capacitor.
CLOCK INPUT
STAGE
VS
SYNCB
If the setup configuration of the AD9514 is changed during
operation, the outputs can become unsynchronized. The
outputs can be re-synchronized to each other at any time.
Synchronization occurs when the SYNCB pin is pulled low and
released. The clock outputs (except where divide = 1) are forced
into a fixed state (determined by the divide and phase settings)
and held there in a static condition until the SYNCB pin is
returned to high. Upon release of the SYNCB pin, after four
cycles of the clock signal at CLK, all outputs continue clocking
in synchronicity (except where divide = 1).
When divide = 1 for an output, that output is not affected by
SYNCB.
3 CLK CYCLES
4 CLK CYCLES
CLK
OUT
EXAMPLE: DIVIDE 8
PHASE = 0
EXAMPLE DIVIDE
RATIO PHASE = 0
SYNCB
CLKB
05596-093
CLK
Figure 25. SYNCB Timing with Clock Present
2.5k
4 CLK CYCLES
5k
05596-021
5k
CLK
OUT DEPENDS ON PREVIOUS STATE
SYNCB
Figure 23 Clock Input Equivalent Circuit
MIN 5ns
§
§
§
EXAMPLE DIVIDE
RATIO PHASE = 0
§ DEPENDS ON PREVIOUS STATE AND DIVIDE RATIO
Figure 26. SYNCB Timing with No Clock Present
SYNCHRONIZATION
Power-On SYNC
SYNCB
05596-022
A power-on sync (POS) is issued when the VS power supply is
turned on to ensure that the outputs start in synchronization.
The power-on sync works only if the VS power supply transitions the region from 2.2 V to 3.1 V within 35 ms. The POS can
occur up to 65 ms after VS crosses 2.2 V. Only outputs which
are not divide = 1 are synchronized.
The outputs of the AD9514 can be synchronized by using the
SYNCB pin. Synchronization aligns the phases of the clock
outputs, respecting any phase offset that has been set on a
particular output’s divider.
Figure 27. SYNCB Equivalent Input Circuit
Rev. A | Page 18 of 28
05596-092
2.5k
AD9514
VS
Synchronization is initiated by pulling the SYNCB pin low for a
minimum of 5 ns. The input clock does not have to be present
at the time the command is issued. The synchronization occurs
after four input clock cycles.
60k
30k
that are not turned OFF
where the divider is not divide = 1 (divider bypassed)
05596-023
SETUP PIN
S0 TO S10
The synchronization applies to clock outputs:
Figure 28. Setup Pin (S0 to S10) Equivalent Circuit
An output with its divider set to divide = 1 (divider bypassed) is
always synchronized with the input clock, with a propagation
delay.
The SYNCB pin must be pulled up for normal operation. Do
not let the SYNCB pin float.
RSET RESISTOR
The internal bias currents of the AD9514 are set by the
RSET resistor. This resistor should be as close as possible to
the value given as a condition in the Specifications section
(RSET = 4.12 kΩ). This is a standard 1% resistor value and
should be readily obtainable. The bias currents set by this
resistor determine the logic levels and operating conditions
of the internal blocks of the AD9514. The performance figures
given in the Specifications section assume that this resistor
value is used for RSET.
VREF
The VREF pin provides a voltage level of ⅔ VS. This voltage is
one of the four logic levels used by the setup pins (S0 to S10).
These pins set the operation of the AD9514. The VREF pin
provides sufficient drive capability to drive as many of the setup
pins as necessary, up to all on a single part. The VREF pin
should be used for no other purpose.
SETUP CONFIGURATION
The specific operation of the AD9514 is set by the logic levels
applied to the setup pins (S0 to S10). These pins use four-state
logic. The logic levels used are VS and GND, plus ⅓ VS and
⅔ VS. The ⅓ VS level is provided by the internal self-biasing on
each of the setup pins (S0 to S10). This is the level seen by a
setup pin that is left not connected (NC). The ⅔ VS level is
provided by the VREF pin. All setup pins requiring the ⅔ VS
level must be tied to the VREF pin.
The AD9514 operation is determined by the combination of
logic levels present at the setup pins. The setup configurations
for the AD9514 are shown in Table 10 to Table 15. The four
logic levels are referred to as 0, ⅓, ⅔, and 1. These numbers
represent the fraction of the VS voltage that defines the logic
levels. See the setup pins thresholds in Table 6.
The meaning of some of the setup pins depends on the logic
level set on other pins. For example, the effect of the S3 to S4
pair of pins depends on whether S0 = 0. If S0 = 0, the delay
block for OUT2 is off, and the logic levels on S3 to S4 set the
phase word of the OUT2 divider. However, if S0 ≠ 0, then the
full-scale delay for OUT2 is set by the logic level on S0, and S3
to S4 sets the delay block fine adjust (fraction of full scale).
S1 and S2 together determine the logic level of each output or
whether a channel is off. An output that is set to OFF is
powered down, including the divider.
OUT0 and OUT1 are LVPECL. The LVPECL output
differential voltage (VOD) can have three possible levels: 410
mV, 790 mV, and 960 mV (limited to the available combinations,
see Table 11). OUT2 can be set to either LVDS or CMOS levels.
S5 and S6 effect depends on S2. If S2 = 0 (OUT2 is off), S5 and
S6 set the OUT1 phase word. If S2 ≠ 0, S5 and S6 set the OUT2
divide ratio. If S2 = ⅔, then the value in S9 and S10 overrides
the divide ratio for OUT2.
S7 and S8 depend on S2 and S0. If S2 ≠ 1, these pins set the
OUT1 divide ratio. However, if S2 = 1 (OUT1 is off) and S0 ≠
0, S7 and S8 set the phase word for OUT2.
S9 and S10 depend on S2. If S2 ≠ ⅔, these pins set the OUT0
divide ratio. If S2 = ⅔, they set the OUT2 divide ratio,
overriding S5 and S6.
Rev. A | Page 19 of 28
AD9514
Table 12. S3, S4—OUT2 Delay Fine Adjust or Phase
Table 10. S0—OUT2 Delay
S0
0
1/3
2/3
1
Delay Full Scale
Off (Bypassed)
1.5 ns
5 ns
10 ns
Table 11. S1, S2—Output Select
S1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
S2
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
OUT0
LVPECL
OFF
790 mV
410 mV
960 mV
790 mV
410 mV
410 mV
790 mV
OFF
OFF
OFF
OFF
410 mV
790 mV
410 mV
790 mV
OUT1
LVPECL
410 mV
790 mV
410 mV
960 mV
790 mV
410 mV
410 mV
790 mV
OFF
OFF
OFF
790 mV
OFF
OFF
OFF
OFF
OUT2
LVDS/CMOS
OFF
OFF
OFF
OFF
CMOS
LVDS
CMOS
LVDS
OFF
LVDS
CMOS
OFF
CMOS
LVDS
LVDS
CMOS
S3
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
Rev. A | Page 20 of 28
S4
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
S0 ≠ 0
OUT2 Delay Fine Adjust
(Fraction of FS)
0
1/16
1/8
3/16
1/4
5/16
3/8
7/16
1/2
9/16
5/8
11/16
3/4
13/16
7/8
15/16
S0 = 0
OUT2 Phase
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
AD9514
Table 13. S5, S6—OUT2 Divide or OUT1 Phase
S5
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
1
S6
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
S2 ≠ 0
OUT2
Divide (Duty Cycle1)
1
2 (50%)
3 (33%)
4 (50%)
5 (40%)
6 (50%)
8 (50%)
9 (44%)
10 (50%)
12 (50%)
15 (47%)
16 (50%)
18 (50%)
24 (50%)
30 (50%)
32 (50%)
Table 15. S9, S10—OUT0 Divide or OUT2 Divide
S2 = 0
OUT1
Phase
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S9
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
1
Duty cycle is the clock signal high time divided by the total period.
S7
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
0
1/3
2/3
1
1
S8
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
S2 = 2/3
OUT2
Divide (Duty Cycle1)
7 (43%)
11 (45%)
13 (46%)
14 (50%)
17 (47%)
19 (47%)
20 (50%)
21 (48%)
22 (50%)
23 (48%)
25 (48%)
26 (50%)
27 (48%)
28 (50%)
29 (48%)
31 (48%)
Duty cycle is the clock signal high time divided by the total period.
Table 14. S7, S8—OUT1 Divide or OUT2 Phase
S2 ≠ 1
OUT1
Divide (Duty Cycle1)
1
2 (50%)
3 (33%)
4 (50%)
5 (40%)
6 (50%)
8 (50%)
9 (44%)
10 (50%)
12 (50%)
15 (47%)
16 (50%)
18 (50%)
24 (50%)
30 (50%)
32 (50%)
S10
0
0
0
0
1/3
1/3
1/3
1/3
2/3
2/3
2/3
2/3
1
1
1
1
S2 ≠ 2/3
OUT0
Divide (Duty Cycle1)
1
2 (50%)
3 (33%)
4 (50%)
5 (40%)
6 (50%)
8 (50%)
9 (44%)
10 (50%)
12 (50%)
15 (47%)
16 (50%)
18 (50%)
24 (50%)
30 (50%)
32 (50%)
S2 = 1 and S0 ≠ 0
OUT2
Phase
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Duty cycle is the clock signal high time divided by the total period.
Rev. A | Page 21 of 28
AD9514
DIVIDER PHASE OFFSET
The phase of OUT1 or OUT2 can be selected, depending on the
divide ratio and output configuration chosen. This allows, for
example, the relative phase of OUT0 and OUT1 to be set.
After a SYNC operation (see the Synchronization section), the
phase offset word of each divider determines the number of
input clock (CLK) cycles to wait before initiating a clock output
edge. By giving each divider a different phase offset, output-tooutput delays can be set in increments of the fast clock period, tCLK.
Figure 29 shows four cases, each with the divider set to divide =
4. By incrementing the phase offset from 0 to 3, the output is
offset from the initial edge by a multiple of tCLK.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Phase Step = 360°/Divide Ratio
Using some of the same examples:
Divide = 4
Phase Step = 360°/4 = 90°
Unique Phase Offsets in Degrees Are Phase = 0°, 90°,
180°, 270°
15
CLOCK INPUT
CLK
DIVIDER OUTPUT
DIV = 4
Phase offsets can be related to degrees by calculating the phase
step for a particular divide ratio:
Divide = 9
tCLK
Phase Step = 360°/9 = 40°
PHASE = 0
Unique Phase Offsets in Degrees Are Phase = 0°, 40°, 80°,
120°, 160°, 200°, 240°, 280°, 320°
PHASE = 1
DELAY BLOCK
PHASE = 2
OUT2 includes an analog delay element that gives variable time
delays (ΔT) in the clock signal passing through that output.
PHASE = 3
CLOCK INPUT
tCLK
OUT2 ONLY
05596-024
2 × tCLK
3 × tCLK
N
SELECT
MUX
Figure 29. Phase Offset—Divider Set for Divide = 4, Phase Set from 0 to 2
For example:
LVDS
CMOS
T
OUTPUT
DRIVER
CLK = 491.52 MHz
FINE DELAY ADJUST
(16 STEPS)
FULL SCALE : 1.5ns, 5ns, 10ns
tCLK = 1/491.52 = 2.0345 ns
05596-025
0
The resolution of the phase offset is set by the fast clock period
(tCLK) at CLK. The maximum unique phase offset is less than
the divide ratio, up to a phase offset of 15.
Figure 30. Analog Delay Block
For Divide = 4:
The amount of delay that can be used is determined by the
output frequency. The amount of delay is limited to less than
one-half cycle of the clock period. For example, for a 10 MHz
clock, the delay can extend to the full 10 ns maximum.
However, for a 100 MHz clock, the maximum delay is less than
5 ns (or half of the period).
Phase Offset 0 = 0 ns
Phase Offset 1 = 2.0345 ns
Phase Offset 2 = 4.069 ns
Phase Offset 3 = 6.104 ns
The AD9514 allows for the selection of three full-scale delays,
1.5 ns, 5 ns, and 10 ns, set by delay full scale (see Table 10).
Each of these full-scale delays can be scaled by 16 fine
adjustment values, which are set by the delay word (see Table 12).
The outputs can also be described as:
Phase Offset 0 = 0°
Phase Offset 1 = 90°
Phase Offset 2 = 180°
Phase Offset 3 = 270°
Setting the phase offset to Phase = 4 results in the same relative
phase as Phase = 0° or 360°.
The delay block adds some jitter to the output. This means that
the delay function should be used primarily for clocking digital
chips, such as FPGA, ASIC, DUC, and DDC, rather than for
supplying a sample clock for data converters. The jitter is
higher for longer full scales because the delay block uses a ramp
and trip points to create the variable delay. A longer ramp
means more noise has a chance of being introduced.
Rev. A | Page 22 of 28
AD9514
When the delay block is OFF (bypassed), it is also powered
down.
POWER SUPPLY
OUTPUTS
The AD9514 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0/OUT0B and OUT1/
OUT1B are LVPECL differential outputs. There are three
amounts of LVPECL differential voltage swing (VOD) that can
be selected (410 mV, 790 mV, and 960 mV) within the choices
available in Table 11.
OUT2/OUT2B can be selected as either an LVDS differential
output or a pair of CMOS single-ended outputs. If selected as
CMOS, OUT2 is a noninverted, single-ended output, and
OUT2B is an inverted, single-ended output.
3.3V
The AD9514 requires a 3.3 V ± 5% power supply for VS. The
tables in the Specifications section give the performance
expected from the AD9514 with the power supply voltage
within this range. In no case should the absolute maximum
range of −0.3 V to +3.6 V, with respect to GND, be exceeded
on Pin VS.
Good engineering practice should be followed in the layout of
power supply traces and the ground plane of the PCB. The
power supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9514 should be bypassed with
adequate capacitors (0.1 μF) at all power pins as close as
possible to the part. The layout of the AD9514 evaluation board
(AD9514/PCB) is a good example.
OUT
05596-026
OUTB
GND
Figure 31. LVPECL Output Simplified Equivalent Circuit
3.5mA
OUT
05596-027
OUTB
3.5mA
Figure 32. LVDS Output Simplified Equivalent Circuit
VS
05596-028
OUT2/
OUT2B
Figure 33. CMOS Equivalent Output Circuit
Rev. A | Page 23 of 28
AD9514
Exposed Metal Paddle
POWER MANAGEMENT
The exposed metal paddle on the AD9514 package is an
electrical connection, as well as a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to ground (GND).
In some cases the AD9514 can be configured to use less power
by turning off functions that are not being used.
The exposed paddle of the AD9514 package must be soldered
down. The AD9514 must dissipate heat through its exposed
paddle. The PCB acts as a heat sink for the AD9514. The PCB
attachment must provide a good thermal path to a larger heat
dissipation area, such as a ground plane on the PCB. This
requires a grid of vias from the top layer down to the ground
plane (see Figure 34). The AD9514 evaluation board
(AD9514/PCB) provides a good example of how the part
should be attached to the PCB.
The power-saving options include the following:
Any divider is powered down when set to divide = 1
(bypassed).
Adjustable delay block on OUT2 is powered down when in
off mode (S0 = 0).
In some cases, an unneeded output can be powered down
(see Table 11). This also powers down the divider for that
output.
05596-035
VIAS TO GND PLANE
Figure 34. PCB Land for Attaching Exposed Paddle
Rev. A | Page 24 of 28
AD9514
APPLICATIONS
USING THE AD9514 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed, analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer, and any
noise, distortion, or timing jitter on the clock is combined with
the desired signal at the A/D output. Clock integrity requirements scale with the analog input frequency and resolution,
with higher analog input frequency applications at ≥14-bit
resolution being the most stringent. The theoretical SNR of an
ADC is limited by the ADC resolution and the jitter on the
sampling clock. Considering an ideal ADC of infinite
resolution where the step size and quantization error can be
ignored, the available SNR can be expressed approximately by
1
SNR 20 log
2πf ATJ
where fA is the highest analog frequency being digitized.
Tj is the rms jitter on the sampling clock.
Figure 35 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9514 provide the lowest jitter clock signals
available from the AD9514. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. The simplified equivalent circuit in Figure 31 shows
the LVPECL output stage.
In most applications, a standard LVPECL far-end termination
is recommended, as shown in Figure 36. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the switching threshold (VS − 1.3 V).
18
VS
16
VS
90
TJ =
100
fS
200
fS
12
1ps
60
2ps
50
40
10p
s
100
fA FULL-SCALE SINE WAVE ANALOG FREQUENCY (MHz)
LVPECL
127
SINGLE-ENDED
(NOT COUPLED)
10
VS
LVPECL
50
VT = VS – 1.3V
8
6
30
10
ENOB
400
70
127
14
fS
05596-091
SNR (dB)
80
50
83
83
05596-030
1
SNR = 20log 2f T
A J
100
LVPECL CLOCK DISTRIBUTION
Figure 36. LVPECL Far-End Termination
1k
VS
VS
Figure 35. ENOB and SNR vs. Analog Input Frequency
0.1nF
See Application Notes AN-756 and AN-501 at www.analog.com.
LVPECL
200
0.1nF
100 DIFFERENTIAL 100
(COUPLED)
200
Figure 37. LVPECL with Parallel Transmission Line
Rev. A | Page 25 of 28
LVPECL
05596-031
110
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9514 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the
best clocking/converter solution.
AD9514
The AD9514 provides one clock output (OUT2) that is
selectable as either CMOS or LVDS levels. Low voltage
differential signaling (LVDS) is a differential output option for
OUT2. LVDS uses a current mode output stage. The current is
3.5 mA, which yields 350 mV output swing across a 100 Ω
resistor. The LVDS output meets or exceeds all ANSI/TIA/EIA644 specifications.
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9514 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 40. The
far-end termination network should match the PCB trace
impedance and provide the desired switching point. The
reduced signal swing may still meet receiver input requirements
in some applications. This can be useful when driving long
trace lengths on less critical nets.
A recommended termination circuit for the LVDS outputs is
shown in Figure 38.
VS
VS
VS
CMOS
50
OUT2/OUT2B
SELECTED AS CMOS
LVDS
05596-032
LVDS
100
100
DIFFERENTIAL (COUPLED)
10
Figure 38. LVDS Output Termination
See Application Note AN-586 at www.analog.com for more
information on LVDS.
CMOS CLOCK DISTRIBUTION
100
100
3pF
05596-034
LVDS CLOCK DISTRIBUTION
Figure 40. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9514 offers both LVPECL and
LVDS outputs that are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
The AD9514 provides one output (OUT2) that is selectable as
either CMOS or LVDS levels. When selected as CMOS, this
output provides for driving devices requiring CMOS level logic
at their clock inputs.
SETUP PINS (S0 TO S10)
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be used.
The setup pins that require a logic level of ⅔ VS should be tied
together, along with the VREF pin, and bypassed to ground via
a capacitor.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are also limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
CMOS
10
The setup pins that require a logic level of ⅓ VS (internal selfbias) should be tied together and bypassed to ground via a
capacitor.
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as important
as the circuit design. Proper RF techniques must be used for
device selection, placement, and routing, as well as power
supply bypassing and grounding to ensure optimum
performance.
60.4
1.0 INCH
5pF
GND
05596-033
MICROSTRIP
Figure 39. Series Termination of CMOS Output
Rev. A | Page 26 of 28
AD9514
PHASE NOISE AND JITTER MEASUREMENT SETUPS
WENZEL
OSCILLATOR
EVALUATION BOARD
ZFL1000VH2
SPLITTER
ZESC-2-11
OUT1
TERM
AMP
OUT1B
TERM
+28dB
CLK1
ATTENUATOR
–12dB
SIG IN
ATTENUATOR
–7dB
REF IN
0
EVALUATION BOARD
ZFL1000VH2
OUT1
TERM
AMP
OUT1B
TERM
+28dB
CLK1
VARIABLE DELAY
COLBY PDL30A
0.01ns STEP
TO 10ns
05596-041
BALUN
AD9514
AGILENT E5500B
PHASE NOISE MEASUREMENT SYSTEM
BALUN
AD9514
Figure 41. Additive Phase Noise Measurement Configuration
WENZEL
OSCILLATOR
ANALOG
SOURCE
EVALUATION BOARD
PC
AD9514
BALUN
WENZEL
OSCILLATOR
OUT1
TERM
OUT1B
TERM
CLK
SNR
ADC
CLK1
FFT
tJ_RMS
05596-042
DATA CAPTURE CARD
FIFO
Figure 42. Jitter Determination by Measuring SNR of ADC
2
t J_RMS
V
A_RMS SND BW 2 θ QUANTIZATION 2 θ THERMAL 2 θ DNL 2
SNR
10 20
2
2π f A V A_PK
where:
tj_RMS is the rms time jitter.
SNR is the signal-to-noise ratio.
SND is the source noise density in nV/√Hz.
BW is the SND filter bandwidth.
VA is the analog source voltage.
fA is the analog frequency.
The θ terms are the quantization, thermal, and DNL errors.
Rev. A | Page 27 of 28
AD9514
OUTLINE DIMENSIONS
PIN 1
INDICATOR
AREA
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
25
PIN 1
IN D IC AT O R AR E A OP T IO N S
(SEE DETAIL A)
32
24
1
0.50
BSC
3.25
3.10 SQ
2.95
EXPOSED
PAD
17
0.50
0.40
0.30
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-003898
SEATING
PLANE
8
9
16
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD
09-12-2018-A
5.10
5.00 SQ
4.90
Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9514BCPZ1
AD9514BCPZ-REEL71
AD9514/PCB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package (LFCSP)
32-Lead Lead Frame Chip Scale Package (LFCSP)
Evaluation Board
Z = Pb-free part.
© 2005–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05596–11/20(A)
Rev. A | Page 28 of 28
Package Option
CP-32-7
CP-32-7
工商网监
湘ICP备2023018690号
