14-Output Clock Generator with Integrated 2.0 GHz VCO AD9516-3
FEATURES
Low phase noise, phase-locked loop On-chip VCO tunes from 1.75 GHz to 2.25 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Auto and manual reference switchover/holdover modes Autorecover from holdover Accepts references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable 3 pairs of 1.6 GHz LVPECL outputs Each pair shares 1 to 32 dividers with coarse phase delay Additive output jitter 225 fS rms Channel-to-channel skew paired outputs 1600 MHz ................................................................... 27 Internal VCO and Clock Distribution................................. 29 Clock Distribution or External VCO 50 V/μs Slew rate > 50 V/μs; CMOS levels Should not exceed VS p-p
Frequency Pushing (Open-Loop) Phase Noise @ 100 kHz Offset Phase Noise @ 1 MHz Offset REFERENCE INPUTS Differential Mode (REFIN, REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFIN Input Resistance, REFIN Input Resistance, REFIN Dual Single-Ended Mode (REF1, REF2) Input Frequency (AC-Coupled) Input Frequency (DC-Coupled) Input Sensitivity (AC-Coupled) Input Logic High Input Logic Low Input Current Input Capacitance 1.35 1.30 4.0 4.4 20 0 0
1 −108 −126
MHz/V dBc/Hz dBc/Hz
250 250 1.60 1.50 4.8 5.3 1.75 1.60 5.9 6.4 250 250 0.8
MHz mV p-p V V kΩ kΩ MHz MHz V p-p V V μA pF
2.0 −100 2 0.8 +100
Each pin, REFIN/REFIN (REF1/REF2)
Rev. 0 | Page 4 of 84
AD9516-3
Parameter PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency Antibacklash Pulse Width Min Typ Max 100 45 1.3 2.9 6.0 Unit MHz MHz ns ns ns Test Conditions/Comments Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash pulse width = 6.0 ns 0x17 = 01b 0x17 = 00b; 0x17 = 11b 0x17 = 10b Programmable With CPRSET = 5.1 kΩ VCP = VCP/2
CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs. Temperature PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD P = 2 FD P = 3 FD P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM (16/17) P = 32 DM (32/33) Prescaler Output Frequency PLL DIVIDER DELAYS 000 001 010 011 100 101 110 111 NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/Phase Frequency Detector (In-Band Means Within the LBW of the PLL) @ 500 kHz PFD Frequency @ 1 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit (FOM)
4.8 0.60 2.5 2.7/10 1 2 1.5 2
mA mA % kΩ nA % % %
0.5 < VCP < VCP − 0.5 V 0.5 < VCP < VCP − 0.5 V VCP = VCP/2 V
300 600 900 600 1000 2400 3000 3000 300
MHz MHz MHz MHz MHz MHz MHz MHz MHz
A, B counter input frequency (prescaler input frequency divided by P) Register 0x19: R, N; see Table 52
off 330 440 550 660 770 880 990
ps ps ps ps ps ps ps ps The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider)
−165 −162 −151 −143 −220
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Reference slew rate > 0.25 V/ns. FOM +10 log(fPFD) is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed loop, the phase noise, as observed at the VCO output, is increased by 20 log(N)
Rev. 0 | Page 5 of 84
AD9516-3
Parameter PLL DIGITAL LOCK DETECT WINDOW 2 Required to Lock (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns) To Unlock After Lock (Hysteresis)2 Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns)
1 2
Min
Typ
Max
Unit
3.5 7.5 3.5 7 15 11
ns ns ns ns ns ns
Test Conditions/Comments Signal available at LD, STATUS, and REFMON pins when selected by appropriate register settings Selected by 0x17 and 0x18 0x17 = 00b, 01b,11b; 0x18 = 1b 0x17 = 00b, 01b, 11b; 0x18 = 0b 0x17 = 10b; 0x18 = 0b 0x17 = 00b, 01b, 11b; 0x18 = 1b 0x17 = 00b, 01b, 11b; 0x18 = 0b 0x17 = 10b; 0x18 = 0b
REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
CLOCK INPUTS
Table 3.
Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Input Sensitivity, Differential Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance
1
Min 01 01
Typ
Max 2.4 1.6
Unit GHz GHz mV p-p V p-p V V mV p-p kΩ pF
150 2 1.3 1.3 3.9 1.57 150 4.7 2 1.8 1.8 5.7
Test Conditions/Comments Differential input High frequency distribution (VCO divider) Distribution only (VCO divider bypassed) Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Larger voltage swings may turn on the protection diodes and can degrade jitter performance Self-biased; enables ac coupling With 200 mV p-p signal applied; dc-coupled CLK ac-coupled; CLK ac-bypassed to RF ground Self-biased
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 Output Frequency, Maximum Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) LVDS CLOCK OUTPUTS OUT6, OUT7, OUT8, OUT9 Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Delta VOS Short-Circuit Current (ISA, ISB) Min Typ Max Unit Test Conditions/Comments Termination = 50 Ω to VS − 2 V Differential (OUT, OUT) Using direct to output; see Figure 25
2950 VS − 1.12 VS − 2.03 550
VS − 0.98 VS − 1.77 790
VS − 0.84 VS − 1.49 980
MHz V V mV
247 1.125
360 1.24 14
800 454 25 1.375 25 24
MHz mV mV V mV mA
Differential termination 100 Ω @ 3.5 mA Differential (OUT, OUT) See Figure 26
Output shorted to GND
Rev. 0 | Page 6 of 84
AD9516-3
Parameter CMOS CLOCK OUTPUTS OUT6A, OUT6B, OUT7A, OUT7B, OUT8A, OUT8B, OUT9A, OUT9B Output Frequency Output Voltage High (VOH) Output Voltage Low (VOL) Min Typ Max Unit Test Conditions/Comments Single-ended; termination = 10 pF 250 VS − 0.1 0.1 MHz V V see Figure 27 @ 1 mA load @ 1 mA load
TIMING CHARACTERISTICS
Table 5.
Parameter LVPECL Output Rise Time, tRP Output Fall Time, tFP PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT High Frequency Clock Distribution Configuration Clock Distribution Configuration Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS 1 LVPECL Outputs That Share the Same Divider LVPECL Outputs on Different Dividers All LVPECL Outputs Across Multiple Parts LVDS Output Rise Time, tRL Output Fall Time, tFL PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT OUT6, OUT7, OUT8, OUT9 For All Divide Values Variation with Temperature OUTPUT SKEW, LVDS OUTPUTS1 LVDS Outputs That Share the Same Divider LVDS Outputs on Different Dividers All LVDS Outputs Across Multiple Parts CMOS Output Rise Time, tRC Output Fall Time, tFC PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT For All Divide Values Variation with Temperature OUTPUT SKEW, CMOS OUTPUTS1 CMOS Outputs That Share the Same Divider All CMOS Outputs on Different Dividers All CMOS Outputs Across Multiple Parts DELAY ADJUST 3 Shortest Delay Range 4 Zero Scale Full Scale Longest Delay Range4 Zero Scale Quarter Scale Full Scale Min Typ 70 70 835 773 995 933 0.8 5 13 Max 180 180 1180 1090 Unit ps ps ps ps ps/°C ps ps ps ps ps Termination = 100 Ω differential; 3.5 mA 20% to 80%, measured differentially 2 20% to 80%, measured differentially2 Delay off on all outputs Test Conditions/Comments Termination = 50 Ω to VS − 2 V; level = 810 mV 20% to 80%, measured differentially 80% to 20%, measured differentially See Figure 42 See Figure 44
15 40 220 350 350
170 160
1.4
1.8 1.25 6 25
2.1
ns ps/°C Delay off on all outputs ps ps ps ps ps ns ps/°C Fine delay off ps ps ps LVDS and CMOS 0xA1 (0xA4) (0xA7) (0xAA) 101111b 0xA2 (0xA5) (0xA8) (0xAB) 000000b 0xA2 (0xA5) (0xA8) (0xAB) 101111b 0xA1 (0xA4) (0xA7) (0xAA) 000000b 0xA2 (0xA5) (0xA8) (0xAB) 000000b 0xA2 (0xA5) (0xA8) (0xAB) 001100b 0xA2 (0xA5) (0xA8) (0xAB) 101111b Termination = open 20% to 80%; CLOAD = 10 pF 80% to 20%; CLOAD = 10 pF Fine delay off
62 150 430 1000 985 2.6
495 475 1.6 2.1 2.6 4 28
66 180 675
50 540 200 1.72 5.7
315 880 570 2.31 8.0
680 1180 950 2.89 10.1
ps ps ps ns ns
Rev. 0 | Page 7 of 84
AD9516-3
Parameter Delay Variation with Temperature Short Delay Range5 Zero Scale Full Scale Long Delay Range 5 Zero Scale Full Scale
1 2 3
Min
Typ
Max
Unit
Test Conditions/Comments
0.23 −0.02 0.3 0.24
ps/°C ps/°C ps/°C ps/°C
This is the difference between any two similar delay paths while operating at the same voltage and temperature. Corresponding CMOS drivers set to A for noninverting, and B for inverting. The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output. 4 Incremental delay; does not include propagation delay. 5 All delays between zero scale and full scale can be estimated by linear interpolation.
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 1 GHz, OUTPUT = 1 GHz Divider = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset CLK = 1 GHz, OUTPUT = 200 MHz Divider = 5 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 1.6 GHz, OUTPUT = 800 MHz Divider = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns
−109 −118 −130 −139 −144 −146 −147 −149
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns
−120 −126 −139 −150 −155 −157 −157
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns
−103 −110 −120 −127 −133 −138 −147 −149
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Rev. 0 | Page 8 of 84
AD9516-3
Parameter CLK = 1.6 GHz, OUTPUT = 400 MHz Divider = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK-TO-CMOS ADDITIVE PHASE NOISE CLK = 1 GHz, OUTPUT = 250 MHz Divider = 4 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 1 GHz, OUTPUT = 50 MHz Divider = 20 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset Min Typ Max Unit Test Conditions/Comments Input slew rate > 1 V/ns
−114 −122 −132 −140 −146 −150 −155
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns
−110 −120 −127 −136 −144 −147 −154
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns
−124 −134 −142 −151 −157 −160 −163
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter LVPECL ABSOLUTE PHASE NOISE VCO = 2.25 GHz; OUTPUT = 2.25 GHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 2.00 GHz; OUTPUT = 2.00 GHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset Min Typ Max Unit Test Conditions/Comments Internal VCO; direct to LVPECL output
−49 −79 −104 −123 −143 −147 −53 −83 −108 −126 −142 −147
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
Rev. 0 | Page 9 of 84
AD9516-3
Parameter VCO = 1.75 GHz; OUTPUT = 1.75 GHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset Min Typ −54 −88 −112 −130 −143 −147 Max Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Test Conditions/Comments
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min Typ Max Unit Test Conditions/Comments Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R = 1 Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz
VCO = 1.97 GHz; LVPECL = 245.76 MHz; PLL LBW = 143 kHz VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 143 kHz VCO = 1.97 GHz; LVPECL = 61.44 MHz; PLL LBW = 143 kHz
129 303 135 302 179 343
fS rms fS rms fS rms fS rms fS rms fS rms
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min Typ Max Unit Test Conditions/Comments Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 10.0 MHz; R = 20 Integration BW = 12 kHz to 20 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 12 kHz to 20 MHz
VCO = 1.87 GHz; LVPECL = 622.08 MHz; PLL LBW = 125 Hz VCO = 1.87 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz
400 390 485
fS rms fS rms fS rms
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min Typ Max Unit Test Conditions/Comments Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R = 1 Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
54 77 109 79 114 163 124 176 259
fS rms fS rms fS rms fS rms fS rms fS rms fS rms fS rms fS rms
Rev. 0 | Page 10 of 84
AD9516-3
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter LVPECL OUTPUT ADDITIVE TIME JITTER Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO; rising edge of clock signal BW = 12 kHz to 20 MHz BW = 12 kHz to 20 MHz Calculated from SNR of ADC method; DCC not used for even divides Calculated from SNR of ADIC method; DCC on Distribution section only; does not include PLL and VCO; rising edge of clock signal BW = 12 kHz to 20 MHz BW = 12 kHz to 20 MHz Calculated from SNR of ADC method; DCC not used for even divides Distribution section only; does not include PLL and VCO; rising edge of clock signal Calculated from SNR of ADC method; DCC not used for even divides
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 LVDS OUTPUT ADDITIVE TIME JITTER
40 80 215 245
fS rms fS rms fS rms fS rms
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2; VCO Divider Not Used CLK = 1 GHz; LVDS = 200 MHz; Divider = 5 CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16 CMOS OUTPUT ADDITIVE TIME JITTER
85 113 280
fS rms fS rms fS rms
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
365
fS rms
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz; Divider = 12; Duty-Cycle Correction = Off LVDS OUTPUT ADDITIVE TIME JITTER CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz; Divider = 12; Duty-Cycle Correction = Off CMOS OUTPUT ADDITIVE TIME JITTER CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz; Divider = 12; Duty-Cycle Correction = Off Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO; uses rising edge of clock signal Calculated from SNR of ADC method Distribution section only; does not include PLL and VCO; rising edge of clock signal Calculated from SNR of ADC method Distribution section only; does not include PLL and VCO; rising edge of clock signal Calculated from SNR of ADC method
210
fS rms
285
fS rms
350
fS rms
Rev. 0 | Page 11 of 84
AD9516-3
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter DELAY BLOCK ADDITIVE TIME JITTER 1 100 MHz Output Delay (1600 μA, 1C) Fine Adj. 000000 Delay (1600 μA, 1C) Fine Adj. 101111 Delay (800 μA, 1C) Fine Adj. 000000 Delay (800 μA, 1C) Fine Adj. 101111 Delay (800 μA, 4C) Fine Adj. 000000 Delay (800 μA, 4C) Fine Adj. 101111 Delay (400 μA, 4C) Fine Adj. 000000 Delay (400 μA, 4C) Fine Adj. 101111 Delay (200 μA, 1C) Fine Adj. 000000 Delay (200 μA, 1C) Fine Adj. 101111 Delay (200 μA, 4C) Fine Adj. 000000 Delay (200 μA, 4C) Fine Adj. 101111
1
Min
Typ
Max
Unit
Test Conditions/Comments Incremental additive jitter
0.54 0.60 0.65 0.85 0.79 1.2 1.2 2.0 1.3 2.5 1.9 3.8
ps rms ps rms ps rms ps rms ps rms ps rms ps rms ps rms ps rms ps rms ps rms ps rms
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter should be added to this value using the root sum of the squares (RSS) method.
SERIAL CONTROL PORT
Table 14.
Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage Min 2.0 0.8 3 110 2 2.0 0.8 110 1 2 2.0 0.8 10 20 2 2.7 0.4 Typ Max Unit V V μA μA pF SCLK has an internal 30 kΩ pull-down resistor V V μA μA pF V V nA nA pF V V Test Conditions/Comments CS has an internal 30 kΩ pull-up resistor
Rev. 0 | Page 12 of 84
AD9516-3
Parameter TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tHI Pulse Width Low, tLO SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup and Hold, tS, tH CS Minimum Pulse Width High, tPWH Min Typ Max 25 16 16 2 1.1 8 2 3 Unit MHz ns ns ns ns ns ns ns Test Conditions/Comments
PD, SYNC, AND RESET PINS
Table 15.
Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low SYNC TIMING Pulse Width Low Min 2.0 0.8 110 1 2 50 1.5 Typ Max Unit V V μA μA pF ns High speed clock cycles High speed clock is CLK input signal Test Conditions/Comments These pins each have a 30 kΩ internal pull-up resistor
LD, STATUS, REFMON PINS
Table 16.
Parameter OUTPUT CHARACTERISTICS Min Typ Max Unit Test Conditions/Comments When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 53, 0x17, 0x1A, and 0x1B
Output Voltage High (VOH) Output Voltage Low (VOL) MAXIMUM TOGGLE RATE
2.7 0.4 100
V V MHz
Applies when mux is set to any divider or counter output, or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor Frequency above which the monitor indicates the presence of the reference Frequency above which the monitor indicates the presence of the reference
ANALOG LOCK DETECT Capacitance REF1, REF2, AND VCO FREQUENCY STATUS MONITOR Normal Range Extended Range LD PIN COMPARATOR Trip Point Hysteresis
3
pF
1.02 8
MHz kHz
1.6 260
V mV
Rev. 0 | Page 13 of 84
AD9516-3
POWER DISSIPATION
Table 17.
Parameter POWER DISSIPATION, CHIP Power-On Default Full Operation; CMOS Outputs at 225 MHz Min Typ 1.0 1.6 Max 1.2 2.2 Unit W W Test Conditions/Comments No clock; no programming; default register values; does not include power dissipated in external resistors PLL on; internal VCO = 2250 MHz; VCO divider = 2; all channel dividers on; six LVPECL outputs @ 562.5 MHz; eight CMOS outputs (10 pF load) @ 225 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors PLL on; internal VCO = 2250 MHz, VCO divider = 2; all channel dividers on; six LVPECL outputs @ 562.5 MHz; four LVDS outputs @ 225 MHz; all fine delay on, maximum current; does not include power dissipated in external resistors PD pin pulled low; does not include power dissipated in terminations PD pin pulled low; PLL power-down 0x10 = 01b; SYNC power-down 0x230 = 1b; REF for distribution power-down 0x230 = 1b PLL operating; typical closed loop configuration Power delta when a function is enabled/disabled VCO divider not used All references off to differential reference enabled All references off to REF1 or REF2 enabled; differential reference not enabled CLK input selected to VCO selected PLL off to PLL on, normal operation; no reference enabled Divider bypassed to divide-by-2 to 32 No LVPECL output on to one LVPECL output on Second LVPECL output turned on, same channel No LVDS output on to one LVDS output on Second LVDS output turned on, same channel Static; no CMOS output on to one CMOS output on Static; second CMOS output, same pair, turned on Static; first output, second pair, turned on Delay block off to delay block enabled; maximum current setting
Full Operation; LVDS Outputs at 225 MHz
1.6
2.3
W
PD Power-Down PD Power-Down, Maximum Sleep
75 31
185
mW mW
VCP Supply POWER DELTAS, INDIVIDUAL FUNCTIONS VCO Divider REFIN (Differential) REF1, REF2 (Single-Ended) VCO PLL Channel Divider LVPECL Channel (Divider Plus Output Driver) LVPECL Driver LVDS Channel (Divider Plus Output Driver) LVDS Driver CMOS Channel (Divider Plus Output Driver) CMOS Driver (Second in Pair) CMOS Driver (First in Second Pair) Fine Delay Block
1.5 30 20 4 70 75 30 160 90 120 50 100 0 30 50
mW mW mW mW mW mW mW mW mW mW mW mW mW mW mW
Rev. 0 | Page 14 of 84
AD9516-3 TIMING DIAGRAMS
tCLK
CLK
DIFFERENTIAL
tPECL
80% LVDS
tLVDS
06422-060
20%
06422-062
06422-063
tRL
tFL
tCMOS
Figure 2. CLK/CLK to Clock Output Timing, DIV = 1
DIFFERENTIAL 80% LVPECL 20%
06422-061
Figure 4. LVDS Timing, Differential
SINGLE-ENDED 80% CMOS 10pF LOAD 20%
tRP
tFP
tRC
tFC
Figure 3. LVPECL Timing, Differential
Figure 5. CMOS Timing, Single-Ended, 10 pF Load
Rev. 0 | Page 15 of 84
AD9516-3 ABSOLUTE MAXIMUM RATINGS
Table 18.
Parameter or Pin VS, VS_LVPECL VCP REFIN, REFIN REFIN RSET CPRSET CLK, CLK CLK SCLK, SDIO, SDO, CS OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9 SYNC REFMON, STATUS, LD Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec)
1
With Respect To GND GND GND REFIN GND GND GND CLK GND GND
Rating −0.3 V to +3.6 V −0.3 V to + 5.8 V −0.3 V to VS + 0.3 V −3.3 V to +3.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −1.2 V to +1.2 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE 1
Table 19.
Package Type 64-Lead LFCSP θJA 24 Unit °C/W
ESD CAUTION
GND GND
−0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V 150°C −65°C to +150°C 300°C
1
See Table 19 for θJA.
Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-7.
Rev. 0 | Page 16 of 84
AD9516-3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFIN (REF1) REFIN (REF2) CPRSET VS VS GND RSET VS OUT0 OUT0 VS_LVPECL OUT1 OUT1 VS VS VS
LVPECL LVPECL
LVDS/CMOS w/FINE DELAY ADJUST
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
LVPECL LVPECL
NC = NO CONNECT
CS NC NC NC SDO SDIO RESET PD OUT4 OUT4 VS_LVPECL OUT5 OUT5 VS VS VS 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
LVDS/CMOS w/FINE DELAY ADJUST
VS REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS VS VS CLK CLK NC SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
AD9516-3
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B) GND OUT2 OUT2 VS_LVPECL OUT3 OUT3 VS GND OUT9 (OUT9B) OUT9 (OUT9A) OUT8 (OUT8B) OUT8 (OUT8A)
LVPECL LVPECL
Figure 6. Pin Configuration
Table 20. Pin Function Descriptions
Pin No. 1, 11, 12, 30, 31, 32, 38, 49, 50, 51, 57, 60, 61 2 3 4 5 6 7 8 9 10 13 14 15, 18, 19, 20 16 17 21 22 23 24 27, 41, 54 37, 44, 59, EPAD 56 Mnemonic VS Description 3.3 V Power Pins.
REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS CLK CLK NC SCLK CS SDO SDIO RESET PD VS_LVPECL GND OUT0
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 53 0x1B. Lock Detect (Output). This pin has multiple selectable outputs; see Table 53 0x1A. Power Supply for Charge Pump (CP); VS < VCP < 5.0 V. Charge Pump (Output). Connects to external loop filter. Status (Output). This pin has multiple selectable outputs; see Table 53 0x17. Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor. Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is also used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. Loop Filter (Input). Connects to VCO control voltage node internally. This pin is for bypassing the LDO to ground with a capacitor. Along with CLK, this is the differential input for the clock distribution section. Along with CLK, this is the differential input for the clock distribution section. No Connection. Serial Control Port Data Clock Signal. Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor. Serial Control Port Unidirectional Serial Data Out. Serial Control Port Bidirectional Serial Data In/Out. Chip Reset; Active Low. This pin has an internal 30 kΩ pull-up resistor. Chip Power Down; Active Low. This pin has an internal 30 kΩ pull-up resistor. Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. Ground Pins; Includes External Paddle (EPAD). LVPECL Output; One Side of a Differential LVPECL Output.
Rev. 0 | Page 17 of 84
06422-003
AD9516-3
Pin No. 55 53 52 43 42 40 39 25 26 28 29 48 47 46 45 33 34 35 36 58 62 63 64 Mnemonic OUT0 OUT1 OUT1 OUT2 OUT2 OUT3 OUT3 OUT4 OUT4 OUT5 OUT5 OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B) OUT8 (OUT8A) OUT8 (OUT8B) OUT9 (OUT9A) OUT9 (OUT9B) RSET CPRSET REFIN (REF2) REFIN (REF1) Description LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS Output. Resistor Connected Here Sets Internal Bias Currents. Nominal value = 4.12 kΩ. Resistor Connected Here Sets the CP Current Range. Nominal value = 5.1 kΩ. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1.
Rev. 0 | Page 18 of 84
AD9516-3 TYPICAL PERFORMANCE CHARACTERISTICS
300 280 260 240
CURRENT (mA)
70 3 CHANNELS—6 LVPECL 65 60 55
KVCO (MHz/V)
06422-007
220 200 180 160 140 120 100 0 500 1 CHANNEL—1 LVPECL 1000 1500 2000 2500 3000 FREQUENCY (MHz) 2 CHANNELS—2 LVPECL 3 CHANNELS—3 LVPECL
50 45 40 35 30
06422-010 06422-012 06422-011
25 1.7
1.8
1.9
2.0
2.1
2.2
2.3
VCO FREQUENCY (GHz)
Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs
180 2 CHANNELS—4 LVDS
CURRENT FROM CP PIN (mA)
Figure 10. VCO KVCO vs. Frequency
5.0 4.5 4.0 3.5
PUMP DOWN PUMP UP
160
CURRENT (mA)
140 2 CHANNELS—2 LVDS 120
3.0 2.5 2.0 1.5 1.0 0.5
100 1 CHANNEL—1 LVDS
06422-008
80 0 200 400 FREQUENCY (MHz) 600 800
0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOLTAGE ON CP PIN (V)
Figure 8. Current vs. Frequency—LVDS Outputs
240 220 200 2 CHANNELS—8 CMOS
CURRENT (mA)
CURRENT FROM CP PIN (mA)
Figure 11. Charge Pump Characteristics @ VCP = 3.3 V
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 PUMP DOWN PUMP UP
180 2 CHANNELS—2 CMOS 160 140 120 1 CHANNEL—2 CMOS 100 80 0 50 100 1 CHANNEL—1 CMOS 150 200 250
06422-009
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOLTAGE ON CP PIN (V)
FREQUENCY (MHz)
Figure 9. Current vs. Frequency—CMOS Outputs
Figure 12. Charge Pump Characteristics @ VCP = 5.0 V
Rev. 0 | Page 19 of 84
AD9516-3
–140
PFD PHASE NOISE REFERRED TO PFD INPUT (dBc/Hz)
10 0
–145
RELATIVE POWER (dB)
–10 –20 –30 –40 –50 –60 –70 –80 –90 –100
06422-137 06422-134 06422-135
–150
–155
–160
–165
1
10
100
06422-013
–170 0.1
–110
CENTER 122.88MHz 5MHz/DIV SPAN 50MHz
PFD FREQUENCY (MHz)
Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
–210 –212
PLL FIGURE OF MERIT (dBc/Hz)
Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz
10 0 –10
RELATIVE POWER (dB)
–214 –216 –218 –220 –222 –224 0 0.5 1.0 1.5 2.0 2.5 SLEW RATE (V/ns)
–20 –30 –40 –50 –60 –70 –80 –90 –100
06422-136
–110
CENTER 122.88MHz 100kHz/DIV SPAN 1MHz
Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN
1.9
Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz
10
1.7
VCO TUNING VOLTAGE (V)
0 –10
RELATIVE POWER (dB)
–20 –30 –40 –50 –60 –70 –80 –90
1.5
1.3
1.1
1.8
1.9
2.0
2.1
2.2
2.3
06422-138
0.9 1.7
–100
VCO FREQUENCY (GHz)
–110
CENTER 122.88MHz 100kHz/DIV SPAN 1MHz
Figure 15. VCO Tuning Voltage vs. Frequency
Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz
Rev. 0 | Page 20 of 84
AD9516-3
1.0 0.4
DIFFERENTIAL OUTPUT (V)
DIFFERENTIAL OUTPUT (V)
0.6
0.2
0.2
0
–0.2
–0.2
–0.6
0
5
10 TIME (ns)
15
20
25
0
1 TIME (ns)
2
Figure 19. LVPECL Output (Differential) @ 100 MHz
1.0 2.8
DIFFERENTIAL OUTPUT (V) DIFFERENTIAL OUTPUT (V)
Figure 22. LVDS Output (Differential) @ 800 MHz
0.6
0.2
1.8
–0.2
0.8
–0.6
0
1 TIME (ns)
2
06422-015
0
20
40 TIME (ns)
60
80
100
Figure 20. LVPECL Output (Differential) @ 1600 MHz
0.4 2.8
DIFFERENTIAL OUTPUT (V)
Figure 23. CMOS Output @ 25 MHz
0.2
OUTPUT (V)
1.8
0
0.8 –0.2
0
5
10 TIME (ns)
15
20
25
06422-016
0
2
4
6 TIME (ns)
8
10
12
Figure 21. LVDS Output (Differential) @ 100 MHz
Figure 24. CMOS Output @ 250 MHz
Rev. 0 | Page 21 of 84
06422-019
–0.4
–0.2
06422-018
–1.0
–0.2
06422-017
06422-014
–1.0
–0.4
AD9516-3
1600
–80 –90
DIFFERENTIAL SWING (mV p-p)
1400
PHASE NOISE (dBc/Hz)
06422-020
–100 –110 –120 –130 –140
1200
1000
0
1 FREQUENCY (GHz)
2
3
100k
1M FREQUENCY (Hz)
10M
100M
Figure 25. LVPECL Differential Swing vs. Frequency
Figure 28. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2250 MHz
–80
700
DIFFERENTIAL SWING (mV p-p)
–90
PHASE NOISE (dBc/Hz)
–100 –110 –120 –130 –140
600
FREQUENCY (MHz)
100k
1M FREQUENCY (Hz)
10M
100M
Figure 26. LVDS Differential Swing vs. Frequency
Figure 29. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 2000 MHz
–80 –90
CL = 2pF 3
2
PHASE NOISE (dBc/Hz)
OUTPUT SWING (V)
CL = 10pF
–100 –110 –120 –130 –140
CL = 20pF 1
OUTPUT FREQUENCY (MHz)
100k
1M FREQUENCY (Hz)
10M
100M
Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load
Figure 30. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 1750 MHz
Rev. 0 | Page 22 of 84
06422-025
0
100
200
300
400
500
600
06422-133
0
–150 10k
06422-024
0
100
200
300
400
500
600
700
800
06422-021
500
–150 10k
06422-023
800
–150 10k
AD9516-3
–120 –125 –120 –130 –135 –140 –145 –150 –155 –160 10 –160 10 –110
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
06422-026
–130
–140
–150
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 31. Phase Noise (Additive) LVPECL @ 245.76 MHz, Divide-by-1
–110
Figure 34. Phase Noise (Additive) LVDS @ 200 MHz, Divide-by-1
–100
–120
–110
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–130
–120
–140
–130
–150
–140
06422-027
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 32. Phase Noise (Additive) LVPECL @ 200 MHz, Divide-by-5
–100
Figure 35. Phase Noise (Additive) LVDS @ 800 MHz, Divide-by-2
–120
–110
–130
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–120
–140
–130
–150
–140
–160
06422-128
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 33. Phase Noise (Additive) LVPECL @ 1600 MHz, Divide-by-1
Figure 36. Phase Noise (Additive) CMOS @ 50 MHz, Divide-by-20
Rev. 0 | Page 23 of 84
06422-131
–150 10
–170 10
06422-130
–160 10
–150 10
06422-142
AD9516-3
–100 –90 –100
–110
PHASE NOISE (dBc/Hz)
–120
PHASE NOISE (dBc/Hz)
06422-132
–110 –120 –130 –140 –150 –160 1k
–130
–140
–150
100
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 37. Phase Noise (Additive) CMOS @ 250 MHz, Divide-by-4
–100
Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 1.87 GHz; PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
–120
–110
PHASE NOISE (dBc/Hz)
–120
–130
PHASE NOISE (dBc/Hz)
–130
–140
–140
–150
–150
06422-141
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO @ 1.97 GHz; PFD = 15.36 MHz; LBW = 143 kHz; LVPECL Output = 122.88 MHz
Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
Rev. 0 | Page 24 of 84
06422-140
–160 1k
–160 1k
06422-139
–160 10
AD9516-3 TERMINOLOGY
Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources are subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contribute its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources are subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contribute its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
Rev. 0 | Page 25 of 84
AD9516-3 DETAILED BLOCK DIAGRAM
REF_ SEL VS GND RSET DISTRIBUTION REFERENCE LD LOCK DETECT STATUS STATUS R DIVIDER VCO STATUS LOW DROPOUT REGULATOR (LDO) PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR PROGRAMMABLE R DELAY REFMON CPRSET VCP REFERENCE SWITCHOVER REF1 REF2 REFIN (REF1) REFIN (REF2) BYPASS
PLL REFERENCE
HOLD
P, P + 1 PRESCALER
A/B COUNTERS
CHARGE PUMP
CP
N DIVIDER LF VCO DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 DIVIDE BY 1 TO 32 DIGITAL LOGIC OUT0 OUT0 LVPECL OUT1 OUT1 OUT2 DIVIDE BY 1 TO 32 SCLK SDIO SDO CS SERIAL CONTROL PORT DIVIDE BY 1 TO 32 OUT2 LVPECL OUT3 OUT3 OUT4 OUT4 LVPECL OUT5 OUT5 STATUS
PD SYNC RESET
ΔT DIVIDE BY 1 TO 32 DIVIDE BY 1 TO 32 ΔT LVDS/CMOS
OUT6 (OUT6A) OUT6 (OUT6B)
OUT7 (OUT7A) OUT7 (OUT7B)
ΔT DIVIDE BY 1 TO 32 DIVIDE BY 1 TO 32 ΔT LVDS/CMOS
OUT8 (OUT8A) OUT8 (OUT8B)
AD9516-3
OUT9 (OUT9A) OUT9 (OUT9B)
06422-002
Figure 41. Detailed Block Diagram
Rev. 0 | Page 26 of 84
AD9516-3 THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9516 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 51 and Table 52 through Table 61). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. Table 21. Default Settings of Some PLL Registers
Register 0x10 = 01b 0x1E0 = 010b 0x1E1 = 0b 0x1E1 = 0b Function PLL asynchronous power-down (PLL off ) Set VCO divider = 4 Use the VCO divider CLK selected as the source
High Frequency Clock Distribution—CLK or External VCO >1600 MHz
The AD9516 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/CLK input is connected to the distribution section through the VCO divider (divide-by-2/ divide-by-3/divide-by-4/ divide-by-5/divide-by-6). This is a distribution only mode that allows for an external input up to 2400 MHz (see Table 3). The maximum frequency that can be applied to the channel dividers is 1600 MHz; therefore, higher input frequencies must be divided down before reaching the channel dividers. This input routing can also be used for lower input frequencies, but the minimum divide is 2 before the channel dividers. When the PLL is enabled, this routing also allows the use of the PLL with an external VCO or VCXO with a frequency less than 2400 MHz. In this configuration, the internal VCO is not used and is powered off. The external VCO/VCXO feeds directly into the prescaler. The register settings shown in Table 21 are the default values of these registers at power-up or after a reset operation. If the contents of the registers are altered by prior programming after power-up or reset, these registers may also be set intentionally to these values.
When using the internal PLL with an external VCO, the PLL must be turned on. Table 22. Settings When Using an External VCO
Register 0x10 to 0x1E 0x1E1 = 0b Function PLL normal operation (PLL on). PLL settings. Select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration.
An external VCO requires an external loop filter that must be connected between CP and the tuning pin of the VCO. This loop filter determines the loop bandwidth and stability of the PLL. Make sure to select the proper PFD polarity for the VCO being used. Table 23. Setting the PFD Polarity
Register 0x10 = 0b 0x10 = 1b Function PFD polarity positive (higher control voltage produces higher frequency) PFD polarity negative (higher control voltage produces lower frequency)
Rev. 0 | Page 27 of 84
AD9516-3
REF_SEL VS GND RSET DISTRIBUTION REFERENCE LD LOCK DETECT STATUS STATUS R DIVIDER VCO STATUS LOW DROPOUT REGULATOR (LDO) PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR PROGRAMMABLE R DELAY PLL REFERENCE REFMON CPRSET VCP
REFERENCE SWITCHOVER REF1 REF2 REFIN (REF1) REFIN (REF2) BYPASS
HOLD
P, P + 1 PRESCALER
A/B COUNTERS
CHARGE PUMP
CP
N DIVIDER LF VCO DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 DIVIDE BY 1 TO 32 DIGITAL LOGIC OUT0 OUT0 LVPECL OUT1 OUT1 OUT2 DIVIDE BY 1 TO 32 SCLK SDIO SDO CS SERIAL CONTROL PORT DIVIDE BY 1 TO 32 OUT2 LVPECL OUT3 OUT3 OUT4 OUT4 LVPECL OUT5 OUT5 STATUS
PD SYNC RESET
ΔT DIVIDE BY 1 TO 32 DIVIDE BY 1 TO 32 ΔT LVDS/CMOS
OUT6 (OUT6A) OUT6 (OUT6B)
OUT7 (OUT7A) OUT7 (OUT7B)
ΔT DIVIDE BY 1 TO 32 DIVIDE BY 1 TO 32 ΔT LVDS/CMOS
OUT8 (OUT8A) OUT8 (OUT8B)
AD9516-3
OUT9 (OUT9A) OUT9 (OUT9B)
06422-029
Figure 42. High Frequency Clock Distribution or External VCO > 1600 MHz
Rev. 0 | Page 28 of 84
AD9516-3
Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must be employed to ensure that the frequency presented to the channel dividers does not exceed its specified maximum frequency (1600 MHz, see Table 3). The internal PLL uses an external loop filter to set the loop bandwidth. The external loop filter is also crucial to the loop stability. When using the internal VCO, it is necessary to calibrate the VCO (0x18) to ensure optimal performance. For internal VCO and clock distribution applications, the register settings shown in Table 24 should be used. Table 24. Settings When Using Internal VCO
Register 0x10 = 00b 0x10 to 0x1E Function PLL normal operation (PLL on). PLL settings. Select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration. Reset VCO calibration (first time after power-up, this does not have to be done, but must be done subsequently). Initiate VCO calibration. VCO divider set to divide-by-2, divide-by-3, divide-by-4, divide-by-5, and divide-by-6. Use the VCO divider as source for distribution section. VCO selected as the source.
0x18 = 0, 0x232 = 1 0x18 = 1, 0x232 = 1 0x1E0 0x1E1 = 0b 0x1E1 = 1b
Rev. 0 | Page 29 of 84
AD9516-3
REF_SEL VS GND RSET DISTRIBUTION REFERENCE LD LOCK DETECT STATUS STATUS R DIVIDER VCO STATUS LOW DROPOUT REGULATOR (LDO) PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR PROGRAMMABLE R DELAY PLL REFERENCE REFMON CPRSET VCP
REFERENCE SWITCHOVER REF1 REF2 REFIN (REF1) REFIN (REF2) BYPASS
HOLD
P, P + 1 PRESCALER
A/B COUNTERS
CHARGE PUMP
CP
N DIVIDER LF VCO DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 DIVIDE BY 1 TO 32 DIGITAL LOGIC OUT0 OUT0 LVPECL OUT1 OUT1 OUT2 DIVIDE BY 1 TO 32 SCLK SDIO SDO CS SERIAL CONTROL PORT DIVIDE BY 1 TO 32 OUT2 LVPECL OUT3 OUT3 OUT4 OUT4 LVPECL OUT5 OUT5 STATUS
PD SYNC RESET
ΔT DIVIDE BY 1 TO 32 DIVIDE BY 1 TO 32 ΔT LVDS/CMOS
OUT6 (OUT6A) OUT6 (OUT6B)
OUT7 (OUT7A) OUT7 (OUT7B)
ΔT DIVIDE BY 1 TO 32 DIVIDE BY 1 TO 32 ΔT LVDS/CMOS
OUT8 (OUT8A) OUT8 (OUT8B)
AD9516-3
OUT9 (OUT9A) OUT9 (OUT9B)
06422-030
Figure 43. Internal VCO and Clock Distribution
Rev. 0 | Page 30 of 84
AD9516-3
Clock Distribution or External VCO 1600 MHz section in that the VCO divider (divide-by-2, divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed. This limits the frequency of the clock source to Threshold REF2 Frequency > Threshold REF1 Frequency > Threshold Digital Lock Detect
1F
1F
1F
1F
Rev. 0 | Page 67 of 84
AD9516-3
Table 54. Fine Delay Adjust: OUT6 to OUT9
Reg. Addr (Hex) Bit(s) Name A0 OUT6 Delay Bypass A1 OUT6 Ramp Capacitors
A1
OUT6 Ramp Current
A2
OUT6 Delay Fraction OUT7 Delay Bypass
A3
A4
OUT7 Ramp Capacitors
Description Bypass or use the delay function. = 0; use delay function. = 1; bypass delay function. Selects the number of ramp capacitors used by the delay function. The combination of the number of the capacitors and the ramp current sets the delay full scale. Number of Capacitors 0 0 0 4 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. Current (μA) 0 0 0 200 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 Selects the fraction of the full-scale delay desired (6-bit binary). 000000 gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported. Bypass or use the delay function. = 0; use delay function. = 1; bypass delay function. Selects the number of ramp capacitors used by the delay function. The combination of the number of the capacitors and the ramp current sets the delay full scale. Number of Capacitors 0 0 0 4 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1
Rev. 0 | Page 68 of 84
AD9516-3
Reg. Addr (Hex) Bit(s) Name A4 OUT7 Ramp Current Description Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. Current (μA) 0 0 0 200 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 Selects the fraction of the full-scale delay desired (6-bit binary). 000000 give zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported. Bypass or use the delay function. = 0; use delay function. = 1; bypass delay function. Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. Number of Capacitors 0 0 0 4 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. Current (μA) 0 0 0 200 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 Selects the fraction of the full-scale delay desired (6-bit binary). 000000 gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported. Bypass or use the delay function. = 0; use delay function. = 1; bypass delay function.
A5
OUT7 Delay Fraction OUT8 Delay Bypass
A6
A7
OUT8 Ramp Capacitors
A7
OUT8 Ramp Current
A8
OUT8 Delay Fraction OUT9 Delay Bypass
A9
Rev. 0 | Page 69 of 84
AD9516-3
Reg. Addr (Hex) Bit(s) Name AA OUT9 Ramp Capacitors Description Selects the number of ramp capacitors used by the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. Number of Capacitors 0 0 0 4 0 0 1 3 0 1 0 3 0 1 1 2 1 0 0 3 1 0 1 2 1 1 0 2 1 1 1 1 Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale. Current Value (μA) 0 0 0 200 0 0 1 400 0 1 0 600 0 1 1 800 1 0 0 1000 1 0 1 1200 1 1 0 1400 1 1 1 1600 Selects the fraction of the full-scale delay desired (6-bit binary). 000000 gives zero delay. Only delay values up to 47 decimals (101111b; 0x2F) are supported.
AA
OUT9 Ramp Current
AB
OUT9 Delay Fraction
Table 55. LVPECL Outputs
Reg. Addr (Hex) Bit(s) Name F0 OUT0 Invert
F0
F0
F1
Description Sets the output polarity. = 0; noninverting. = 1; inverting. OUT0 LVPECL Sets the LVPECL output differential voltage (VOD). Differential VOD (mV) Voltage 0 0 400 0 1 600 1 0 780 1 1 960 OUT0 LVPECL power-down modes. Power-Down Mode 0 0 Normal operation. 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. 1 1 Total power-down, reference off; use only if there are no external load resistors. OUT1 Invert Sets the output polarity. = 0; noninverting. = 1; inverting.
Output On Off Off Off
Rev. 0 | Page 70 of 84
AD9516-3
Reg. Addr (Hex) Bit(s) Name F1 OUT1 LVPECL Differential Voltage Description Sets the LVPECL output differential voltage (VOD). VOD (mV) 0 0 400 0 1 600 1 0 780 1 1 960 LVPECL power-down modes. Mode 0 0 Normal operation. 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. 1 1 Total power-down, reference off; use only if there are no external load resistors. Sets the output polarity. = 0; noninverting. = 1; inverting. Sets the LVPECL output differential voltage (VOD). VOD (mV) 0 0 400 0 1 600 1 0 780 1 1 960 LVPECL power-down modes. Mode 0 0 Normal operation. 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. 1 1 Total power-down, reference off; use only if there are no external load resistors. Sets the output polarity. = 0; noninverting. = 1; inverting. Sets the LVPECL output differential voltage (VOD). VOD (mV) 0 0 400 0 1 600 1 0 780 1 1 960 LVPECL power-down modes. Mode 0 0 Normal operation. 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. 1 1 Total power-down, reference off; use only if there are no external load resistors. Sets the output polarity. = 0; noninverting. = 1; inverting. Sets the LVPECL output differential voltage (VOD). VOD (mV) 0 0 400 0 1 600 1 0 780 1 1 960
Rev. 0 | Page 71 of 84
F1
OUT1 Power-Down
Output On Off Off Off
F2
OUT2 Invert
F2
OUT2 LVPECL Differential Voltage
F2
OUT2 Power-Down
Output On Off Off Off
F3
OUT3 Invert
F3
OUT3 LVPECL Differential Voltage
F3
OUT3 Power-Down
Output On Off Off Off
F4
OUT4 Invert
F4
OUT4 LVPECL Differential Voltage
AD9516-3
Reg. Addr (Hex) Bit(s) Name Description F4 OUT4 LVPECL power-down modes. Power-Down Mode 0 0 Normal operation. 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. 1 1 Total power-down, reference off; use only if there are no external load resistors. F5 OUT5 Invert Sets the output polarity. = 0; noninverting. = 1; inverting. F5 OUT5 LVPECL Sets the LVPECL output differential voltage (VOD). Differential VOD (mV) Voltage 0 0 400 0 1 600 1 0 780 1 1 960 F5 OUT5 LVPECL power-down modes. Power-Down Mode 0 0 Normal operation. 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. 1 1 Total power-down, reference off; use only if there are no external load resistors.
Output On Off Off Off
Output On Off Off Off
Table 56. LVDS/CMOS Outputs
Reg. Addr (Hex) Bit(s) Name 140 OUT6 Output Polarity
140
OUT6 CMOS B
140
OUT6 Select LVDS/CMOS
140
OUT6 LVDS Output Current
Description In CMOS mode, select the output polarity of each CMOS output. In LVDS mode, only determines LVDS polarity. OUT6A (CMOS) OUT6B (CMOS) OUT6 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode. = 0; turn off the CMOS B output. = 1; turn on the CMOS B output. Select LVDS or CMOS logic levels. = 0; LVDS. = 1; CMOS. Set output current level in LVDS mode. This has no effect in CMOS mode. Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 1 0 5.25 50 1 1 7 50
Rev. 0 | Page 72 of 84
AD9516-3
Reg. Addr (Hex) Bit(s) Name 140 OUT6 Power-Down Description Power-down output (LVDS/CMOS). = 0; power on. = 1; power off. In CMOS mode, select the output polarity of each CMOS output. In LVDS mode, only determines LVDS polarity. OUT7A (CMOS) OUT7B (CMOS) OUT7 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode. = 0; turn off the CMOS B output. = 1; turn on the CMOS B output. Select LVDS or CMOS logic levels. = 0; LVDS. = 1; CMOS. Set output current level in LVDS mode. This has no effect in CMOS mode. Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 1 0 5.25 50 1 1 7 50 Power-down output (LVDS/CMOS). = 0; power on. = 1; power off. In CMOS mode, select the output polarity of each CMOS output. In LVDS mode, only determines LVDS polarity. OUT8A (CMOS) OUT8B (CMOS) OUT8 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode. = 0; turn off the CMOS B output. = 1; turn on the CMOS B output. Select LVDS or CMOS logic levels. = 0; LVDS. = 1; CMOS. Set output current level in LVDS mode. This has no effect in CMOS mode. Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 1 0 5.25 50 1 1 7 50
Rev. 0 | Page 73 of 84
141
OUT7 Output Polarity
141
OUT7 CMOS B
141
OUT7 Select LVDS/CMOS
141
OUT7 LVDS Output Current
141
OUT7 Power-Down
142
OUT8 Output Polarity
142
OUT8 CMOS B
142
OUT8 Select LVDS/CMOS
142
OUT8 LVDS Output Current
AD9516-3
Reg. Addr (Hex) Bit(s) Name 142 OUT8 Power-Down Description Power-down output (LVDS/CMOS). = 0; power on. = 1; power off. In CMOS mode, select the output polarity of each CMOS output. In LVDS mode, only determines LVDS polarity. OUT9A (CMOS) OUT9B (CMOS) OUT9 (LVDS) 0 0 0 Noninverting Inverting Noninverting 0 1 0 Noninverting Noninverting Noninverting 1 0 0 Inverting Inverting Noninverting 1 1 0 Inverting Noninverting Noninverting 0 0 1 Inverting Noninverting Inverting 0 1 1 Inverting Inverting Inverting 1 0 1 Noninverting Noninverting Inverting 1 1 1 Noninverting Inverting Inverting In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode. = 0; turn off the CMOS B output. = 1; turn on the CMOS B output. Select LVDS or CMOS logic levels. = 0; LVDS. = 1; CMOS. Set output current level in LVDS mode. This has no effect in CMOS mode. Current (mA) Recommended Termination (Ω) 0 0 1.75 100 0 1 3.5 100 1 0 5.25 50 1 1 7 50 Power-down output (LVDS/CMOS). = 0; power on. = 1; power off.
143
OUT9 Output Polarity
143
OUT9 CMOS B
143
OUT9 Select LVDS/CMOS
143
OUT9 LVDS Output Current
143
OUT9 Power-Down
Table 57. LVPECL Channel Dividers
Reg. Addr (Hex) Bit(s) Name 190 Divider 0 Low Cycles 190 191 Divider 0 High Cycles Divider 0 Bypass
Description Number of clock cycles of the divider input during which divider output stays low. Number of clock cycles of the divider input during which divider output stays high. Bypass and power-down the divider; route input to divider output. = 0; use divider. = 1; bypass divider. Nosync. = 0; obey chip-level SYNC signal. = 1; ignore chip-level SYNC signal. Force divider output to high. This requires that nosync also be set. = 0; divider output forced to low. = 1; divider output forced to high. Selects clock output to start high or start low. = 0; start low. = 1; start high. Phase offset.
191
Divider 0 Nosync
191
Divider 0 Force High
191
Divider 0 Start High
191
Divider 0 Phase Offset
Rev. 0 | Page 74 of 84
AD9516-3
Reg. Addr (Hex) Bit(s) Name 192 Divider 0 Direct to Output Description Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK. = 0: OUT0 and OUT1 are connected to Divider 0. = 1: If 0x1E1 = 10b, the VCO is routed directly to OUT0 and OUT1. If 0x1E1 = 00b, the CLK is routed directly to OUT0 and OUT1. If 0x1E1 = 01b, there is no effect. Duty-cycle correction function. = 0; enable duty-cycle correction. = 1; disable duty-cycle correction. Number of clock cycles of the divider input during which divider output stays low. Number of clock cycles of the divider input during which divider output stays high. Bypass and power-down the divider; route input to divider output. = 0; use divider. = 1; bypass divider. Nosync. = 0; obey chip-level SYNC signal. = 1; ignore chip-level SYNC signal. Force divider output to high. This requires that nosync also be set. = 0; divider output forced to low. = 1; divider output forced to high. Selects clock output to start high or start low. = 0; start low. = 1; start high. Phase offset. Connect OUT2 and OUT3 to Divider 1 or directly to VCO or CLK. = 0; OUT2 and OUT3 are connected to Divider 1. = 1: If 0x1E1 = 10b, the VCO is routed directly to OUT2 and OUT3. If 0x1E1 = 00b, the CLK is routed directly to OUT2 and OUT3. If 0x1E1 = 01b, there is no effect. Duty-cycle correction function. = 0; enable duty-cycle correction. = 1; disable duty-cycle correction. Number of clock cycles of the divider input during which divider output stays low. Number of clock cycles of the divider input during which divider output stays high. Bypass and power down the divider; route input to divider output. = 0; use divider. = 1; bypass divider. Nosync. = 0; obey chip-level SYNC signal. = 1; ignore chip-level SYNC signal. Force divider output to high. This requires that nosync also be set. = 0; divider output forced to low. = 1; divider output forced to high. Selects clock output to start high or start low. = 0; start low. = 1; start high. Phase offset.
192
Divider 0 DCCOFF
193 193 194
Divider 1 Low Cycles Divider 1 High Cycles Divider 1 Bypass
194
Divider 1 Nosync
194
Divider 1 Force High
194
Divider 1 Start High
194 195
Divider 1 Phase Offset Divider 1 Direct to Output
195
Divider 1 DCCOFF
196 196 197
Divider 2 Low Cycles Divider 2 High Cycles Divider 2 Bypass
197
Divider 2 Nosync
197
Divider 2 Force High
197
Divider 2 Start High
197
Divider 2 Phase Offset
Rev. 0 | Page 75 of 84
AD9516-3
Reg. Addr (Hex) Bit(s) Name 198 Divider 2 Direct to Output Description Connect OUT4 and OUT5 to Divider 2 or directly to VCO or CLK. = 0; OUT4 and OUT5 are connected to Divider 2. = 1: If 0x1E1 = 10b, the VCO is routed directly to OUT4 and OUT5. If 0x1E1 = 00b, the CLK is routed directly to OUT4 and OUT5. If 0x1E1 = 01b, there is no effect. Duty-cycle correction function. = 0; enable duty-cycle correction. = 1; disable duty-cycle correction.
198
Divider 2 DCCOFF
Table 58. LVDS/CMOS Channel Dividers
Reg. Addr (Hex) Bit(s) Name 199 Low Cycles Divider 3.1 199 19A 19A 19B 19B 19C High Cycles Divider 3.1 Phase Offset Divider 3.2 Phase Offset Divider 3.1 Low Cycles Divider 3.2 High Cycles Divider 3.2 Bypass Divider 3.2
Description Number of clock cycles of 3.1 divider input during which 3.1 output stays low. Number of clock cycles of 3.1 divider input during which 3.1 output stays high. Refer to LVDSCMOS channel divider function description. Refer to LVDSCMOS channel divider function description. Number of clock cycles of 3.2 divider input during which 3.2 output stays low. Number of clock cycles of 3.2 divider input during which 3.2 output stays high. Bypass (and power-down) 3.2 divider logic, route clock to 3.2 output. = 0; do not bypass. = 1; bypass. Bypass (and power-down) 3.1 divider logic, route clock to 3.1 output. = 0; do not bypass. = 1; bypass. Nosync. = 0; obey chip-level SYNC signal. = 1; ignore chip-level SYNC signal. Force Divider 3 output high. Requires that nosync also be set. = 0; force low. = 1; force high. Divider 3.2 start high/low. = 0; start low. = 1; start high. Divider 3.1 start high/low. = 0; start low. = 1; start high. Duty-cycle correction function. = 0; enable duty-cycle correction. = 1; disable duty-cycle correction. Number of clock cycles of divider 4.1 input during which 4.1 output stays low. Number of clock cycles of 4.1 divider input during which 4.1 output stays high. Refer to LVDSCMOS channel divider function description. Refer to LVDSCMOS channel divider function description. Number of clock cycles of 4.2 divider input during which 4.2 output stays low. Number of clock cycles of 4.2 divider input during which 4.2 output stays high.
19C
Bypass Divider 3.1
19C
Divider 3 Nosync
19C
Divider 3 Force High
19C
Start High Divider 3.2
19C
Start High Divider 3.1
19D
Divider 3 DCCOFF
19E 19E 19F 19F 1A0 1A0
Low Cycles Divider 4.1 High Cycles Divider 4.1 Phase Offset Divider 4.2 Phase Offset Divider 4.1 Low Cycles Divider 4.2 High Cycles Divider 4.2
Rev. 0 | Page 76 of 84
AD9516-3
Reg. Addr (Hex) Bit(s) 1A1 Name Bypass Divider 4.2 Description Bypass (and power down) 4.2 divider logic, route clock to 4.2 output. = 0; do not bypass. = 1; bypass. Bypass (and power down) 4.1 divider logic, route clock to 4.1 output. = 0; do not bypass. = 1; bypass. Nosync. = 0; obey chip-level SYNC signal. = 1; ignore chip-level SYNC signal. Force Divider 4 output high. Requires that nosync also be set. = 0; force low. = 1; force high. Divider 4.2 start high/low. = 0; start low. = 1; start high. Divider 4.1 start high/low. = 0; start low. = 1; start high. Duty-cycle correction function. = 0; enable duty-cycle correction. = 1; disable duty-cycle correction.
1A1
Bypass Divider 4.1
1A1
Divider 4 Nosync
1A1
Divider 4 Force High
1A1
Start High Divider 4.2
1A1
Start High Divider 4.1
1A2
Divider 4 DCCOFF
Table 59. VCO Divider and CLK Input
Reg. Addr (Hex) Bit(s) Name 1E0 VCO Divider
Description
Divide
1E1
1E1
1E1
1E1
1E1
0 0 0 2 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 Output static 1 1 0 Output static 1 1 1 Output static Power-Down Clock Input Section Power down the clock input section (including CLK buffer, VCO divider, and CLK tree). = 0; normal operation. = 1; power-down. Power-Down VCO Clock Interface Power down the interface block between VCO and clock distribution. = 0; normal operation. = 1; power-down. Power-Down VCO and CLK Power down both VCO and CLK input. = 0; normal operation. = 1; power-down. Select VCO or CLK Select either the VCO or the CLK as the input to VCO divider. = 0; select external CLK as input to VCO divider. = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is selected. Bypass VCO Divider Bypass or use the VCO divider. = 0; use VCO divider. = 1; bypass VCO divider; cannot select VCO as input when this is selected.
Rev. 0 | Page 77 of 84
AD9516-3
Table 60. System
Reg. Addr (Hex) Bit(s) Name 230 Power-Down SYNC
230
Power-Down Distribution Reference
230
Soft SYNC
Description Power down the SYNC function. = 0; normal operation of the SYNC function. = 1; power-down SYNC circuitry. Power down the reference for distribution section. = 0; normal operation of the reference for the distribution section. = 1; power down the reference for the distribution section. The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is reversed. That is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. = 0; same as SYNC high. = 1; same as SYNC low.
Table 61. Update All Registers
Reg. Addr (Hex) Bit(s) Name 232 Update All Registers
Description This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0. = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Rev. 0 | Page 78 of 84
AD9516-3 APPLICATION NOTES
USING THE AD9516 OUTPUTS FOR ADC CLOCK APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its sampling clock. An ADC can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at ≥14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by
level, termination) should be considered when selecting the best clocking/converter solution.
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9516 provide the lowest jitter clock signals available from the AD9516. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 57 shows the LVPECL output stage. In most applications, an LVPECL far-end Thevenin termination is recommended, as shown in Figure 69. The resistor network is designed to match the transmission line impedance (50 Ω) and the switching threshold (VS − 1.3 V).
VS_LVPECL VS_LVPECL 50Ω SINGLE-ENDED (NOT COUPLED) 50Ω
06422-045
⎛1 SNR(dB) = 20 × log ⎜ ⎜ 2πf t AJ ⎝
⎞ ⎟ ⎟ ⎠
127Ω
127Ω
VS
LVPECL
LVPECL
where: fA is the highest analog frequency being digitized. tJ is the rms jitter on the sampling clock. Figure 68 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB).
110 100 90 80 1 SNR = 20log 2πf t AJ 18 16
VT = VS – 1.3V
83Ω
83Ω
Figure 69. LVPECL Far-End Thevenin Termination
VS_LVPECL 0.1nF 100Ω DIFFERENTIAL 100Ω (COUPLED) 0.1nF TRANSMISSION LINE 200Ω VS_LVPECL
LVPECL
LVPECL
SNR (dB)
70 60 50 40 30 10
S
12 10 8 6
ENOB
400 f 1ps 2ps
Figure 70. LVPECL with Parallel Transmission Line
LVDS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9) that are selectable as either CMOS or LVDS level outputs. LVDS is a differential output option that uses a current mode output stage. The nominal current is 3.5 mA, which yields 350 mV output swing across a 100 Ω resistor. The LVDS output meets or exceeds all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 71.
VS VS
10p s
fA (MHz)
Figure 68. SNR and ENOB vs. Analog Input Frequency
See the AN-756 application note and the AN-501 application note at www.analog.com. Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. (Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment.) The AD9516 features both LVPECL and LVDS outputs that provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or single-ended, logic
06422-044
100
1k
LVDS
100Ω 100Ω DIFFERENTIAL (COUPLED)
LVDS
06422-047
Figure 71. LVDS Output Termination
See the AN-586 application note at www.analog.com for more information on LVDS.
Rev. 0 | Page 79 of 84
06422-046
tJ = 100 fS 200 fS
14
200Ω
AD9516-3
CMOS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9) that are selectable as either CMOS or LVDS level outputs. When selected as CMOS, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as noninverting or inverting. These outputs are 3.3 V CMOS compatible. Whenever single-ended CMOS clocking is used, some of the following general guidelines should be used. Point-to-point nets should be designed such that a driver has only one receiver on the net, if possible. This allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and preserve signal integrity.
06422-076
Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9516 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 73. The farend termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.
VS 50Ω 100Ω CMOS 100Ω
06422-077
CMOS
10Ω
Figure 73. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9516 offers both LVPECL and LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
CMOS
10Ω
60.4Ω (1.0 INCH) CMOS MICROSTRIP
Figure 72. Series Termination of CMOS Output
Rev. 0 | Page 80 of 84
AD9516-3 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
8.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
6.35 6.20 SQ 6.05
0.50 0.40 0.30
33 32
17 16
1.00 0.85 0.80
12° MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC 0.20 REF
7.50 REF
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 74. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad CP-64-4 Dimensions shown in millimeters
ORDERING GUIDE
Model AD9516-3BCPZ 1 AD9516-3BCPZ-REEL71 AD9516-3/PCBZ1
1
Temperature Range −40°C to +85°C −40°C to +85°C
Package Description 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board
063006-B
Package Option CP-64-4 CP-64-4
Z = RoHS Compliant Part.
Rev. 0 | Page 81 of 84
AD9516-3 NOTES
Rev. 0 | Page 82 of 84
AD9516-3 NOTES
Rev. 0 | Page 83 of 84
AD9516-3 NOTES
©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06422-0-6/07(0)
Rev. 0 | Page 84 of 84
工商网监
湘ICP备2023018690号
