14-Output Clock Generator with
Integrated 2.0 GHz VCO
AD9516-3
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Low jitter, low phase noise clock distribution
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
GENERAL DESCRIPTION
The AD9516-3 1 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an onchip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to
2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz
can be used.
The AD9516-3 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
Rev. C
CP
REFIN
REF2
LF
STATUS
MONITOR
PLL
REF1
SWITCHOVER
AND MONITOR
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.75 GHz to 2.25 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Automatic revertive and manual reference
switchover/holdover modes
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
6 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of 1600 MHz Section; Change to Table 22 .......... 27
Changes to Table 24 ........................................................................ 29
Change to Configuration and Register Settings Section............ 31
Change to Phase Frequency Detector (PFD) Section ................ 32
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections ......... 33
Change to Figure 47; Added Figure 48 ......................................... 33
Changes to Reference Switchover and VCXO/VCO
Feedback Divider N—P, A, B, R Sections .................................... 34
Changes to Table 28 ........................................................................ 35
Change to Holdover Section .......................................................... 37
Changes to VCO Calibration Section........................................... 39
Changes to Clock Distribution Section........................................ 40
Added Endnote to Table 34 ........................................................... 41
Changes to Channel Dividers—LVDS/CMOS Outputs
Section; Added Endnote to Table 39 ............................................ 43
Changes to Write Section ............................................................... 50
Change to the Instruction Word (16 Bits) Section ..................... 51
Change to Figure 65 ........................................................................ 52
Added Thermal Performance Section .......................................... 54
Changes to Register Address 0x003 in Table 52.......................... 55
Changes to Table 53 ........................................................................ 59
Changes to Table 54 ........................................................................ 60
Changes to Table 55 ........................................................................ 66
Changes to Table 56 ........................................................................ 68
Changes to Table 57 ........................................................................ 71
Changes to Table 58 ........................................................................ 73
Changes to Table 59 ........................................................................ 74
Changes to Table 60 and Table 61 ................................................. 76
Added Frequency Planning Using the AD9516 Section ............ 77
Changes to Figure 71 and Figure 73; Added Figure 72 .............. 78
Changes to LVPECL Clock Distribution and LVDS Clock
Distribution Sections ...................................................................... 78
Updated Outline Dimensions........................................................ 80
6/07—Revision 0: Initial Version
Rev. C | Page 3 of 80
AD9516-3
Data Sheet
SPECIFICATIONS
Typical is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum and maximum values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_LVPECL
VCP
RSET Pin Resistor
CPRSET Pin Resistor
Min
3.135
2.375
VS
2.7
BYPASS Pin Capacitor
Typ
3.3
4.12
5.1
Max
3.465
VS
5.25
10
220
Unit
V
V
V
kΩ
kΩ
nF
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 µA);
actual current can be calculated by: CP_lsb = 3.06/CPRSET; connect
to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Min
1750
0.5
Test Conditions/Comments
2250
MHz
MHz/V
V
See Figure 15
See Figure 10
VCP ≤ VS when using internal VCO; outside of this range, the CP
spurs may increase due to CP up/down mismatch
VCP −
0.5
0
MHz/V
dBc/Hz
dBc/Hz
250
250
MHz
mV p-p
1.35
1.30
1.60
1.50
1.75
1.60
V
V
4.0
4.4
4.8
5.3
5.9
6.4
kΩ
kΩ
250
250
MHz
MHz
V p-p
V
V
µA
pF
20
0
0.8
2.0
0.8
+100
−100
2
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
Unit
1
−108
−126
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Input Capacitance
Max
50
Frequency Pushing (Open-Loop)
Phase Noise at 100 kHz Offset
Phase Noise at 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Typ
100
45
1.3
2.9
6.0
MHz
MHz
ns
ns
ns
f = 2000 MHz
f = 2000 MHz
Differential mode (can accommodate single-ended input by
ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled; be careful
to match VCM (self-bias voltage)
PLL figure of merit (FOM) increases with increasing slew rate; see
Figure 14
Self-bias voltage of REFIN 1
Self-bias voltage of REFIN1
Self-biased1
Self-biased1
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/µs
Slew rate > 50 V/µs; CMOS levels
Should not exceed VS p-p
Each pin, REFIN/REFIN (REF1/REF2)
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
Register 0x017[1:0] = 10b
Rev. C | Page 4 of 80
Data Sheet
Parameter
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. CPV
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
At 500 kHz PFD Frequency
At 1 MHz PFD Frequency
At 10 MHz PFD Frequency
At 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
AD9516-3
Min
Typ
Max
4.8
0.60
2.5
2.7/10
1
2
1.5
2
mA
mA
%
kΩ
nA
%
%
%
300
600
900
200
1000
2400
3000
3000
300
Off
330
440
550
660
770
880
990
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1
2
Programmable
With CPRSET = 5.1 kΩ
CPV = VCP/2
0.5 < CPV < VCP − 0.5 V
0.5 < CPV < VCP − 0.5 V
CPV = VCP/2
See the VCXO/VCO Feedback Divider N—P, A, B, R section
A, B counter input frequency (prescaler input frequency divided
by P)
Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 54
ps
ps
ps
ps
ps
ps
ps
ps
The PLL in-band phase noise floor is estimated by measuring the
in-band phase noise at the output of the VCO and subtracting
20log(N) (where N is the value of the N divider)
−165
−162
−151
−143
−220
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
3.5
7.5
3.5
ns
ns
ns
Reference slew rate > 0.25 V/ns; FOM + 10log (fPFD) is an approximation of the PFD/CP in-band phase noise (in the flat region)
inside the PLL loop bandwidth; when running closed loop, the
phase noise, as observed at the VCO output, is increased by 20log(N)
Signal available at LD, STATUS, and REFMON pins when selected
by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
7
15
11
ns
ns
ns
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
PLL DIGITAL LOCK DETECT WINDOW 2
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
To Unlock After Lock (Hysteresis)2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Test Conditions/Comments
REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. C | Page 5 of 80
AD9516-3
Data Sheet
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Min
Typ
01
01
Input Sensitivity, Differential
1
Unit
2.4
1.6
GHz
GHz
mV p-p
2
V p-p
1.8
1.8
V
V
mV p-p
kΩ
pF
150
Input Level, Differential
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Max
1.3
1.3
3.9
1.57
150
4.7
2
5.7
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is
improved with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5
Output Frequency, Maximum
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
Min
Typ
2950
VS − 1.12
VS − 2.03
550
247
VS − 0.98
VS − 1.77
790
VS − 0.84
VS − 1.49
980
V
V
mV
800
MHz
454
mV
25
mV
1.24
1.375
25
V
mV
14
24
mA
360
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
CMOS CLOCK OUTPUTS
OUT6A, OUT6B, OUT7A, OUT7B,
OUT8A, OUT8B, OUT9A, OUT9B
Output Frequency
Output Voltage High (VOH)
Output Voltage Low (VOL)
1.125
Unit
MHz
LVDS CLOCK OUTPUTS
OUT6, OUT7, OUT8, OUT9
Output Frequency
Differential Output Voltage (VOD)
Max
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Differential (OUT, OUT)
Using direct to output; see Figure 25 for peak-topeak differential amplitude
VOH − VOL for each leg of a differential pair for
default amplitude setting with driver not toggling;
see Figure 25 for variation over frequency
Differential termination 100 Ω at 3.5 mA
Differential (OUT, OUT)
The AD9516 outputs toggle at higher frequencies,
but the output amplitude may not meet the VOD
specification; see Figure 26
VOH − VOL measurement across a differential pair at
the default amplitude setting with output driver
not toggling; see Figure 26 for variation over
frequency
This is the absolute value of the difference
between VOD when the normal output is high vs.
when the complementary output is high
(VOH + VOL)/2 across a differential pair
This is the absolute value of the difference
between VOS when the normal output is high vs.
when the complementary output is high
Output shorted to GND
Single-ended; termination = 10 pF
250
VS − 0.1
0.1
MHz
V
V
Rev. C | Page 6 of 80
See Figure 27
At 1 mA load
At 1 mA load
Data Sheet
AD9516-3
TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution Configuration
Clock Distribution Configuration
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS 1
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT
OUT6, OUT7, OUT8, OUT9
For All Divide Values
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS1
LVDS Outputs That Share the Same Divider
LVDS Outputs on Different Dividers
All LVDS Outputs Across Multiple Parts
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT
For All Divide Values
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS1
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
All CMOS Outputs Across Multiple Parts
DELAY ADJUST 3
Shortest Delay Range 4
Zero Scale
Full Scale
Longest Delay Range4
Zero Scale
Quarter Scale
Full Scale
Delay Variation with Temperature
Short Delay Range5
Zero Scale
Full Scale
Long Delay Range 5
Zero Scale
Full Scale
Min
835
773
1.4
Typ
Max
Unit
70
70
180
180
ps
ps
995
933
0.8
1180
1090
ps
ps
ps/°C
5
13
15
40
220
ps
ps
ps
170
160
350
350
ps
ps
1.8
1.25
2.1
ns
ps/°C
6
25
62
150
430
ps
ps
ps
495
475
1000
985
ps
ps
2.1
2.6
2.6
ns
ps/°C
4
28
66
180
675
ps
ps
ps
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V; level = 810 mV
20% to 80%, measured differentially
80% to 20%, measured differentially
See Figure 43
See Figure 45
Termination = 100 Ω differential; 3.5 mA
20% to 80%, measured differentially 2
20% to 80%, measured differentially2
Delay off on all outputs
Delay off on all outputs
1.6
Termination = open
20% to 80%; CLOAD = 10 pF
80% to 20%; CLOAD = 10 pF
Fine delay off
Fine delay off
50
540
315
880
680
1180
ps
ps
200
1.72
5.7
570
2.31
8.0
950
2.89
10.1
ps
ns
ns
0.23
−0.02
ps/°C
ps/°C
0.3
0.24
ps/°C
ps/°C
LVDS and CMOS
Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 101111b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b
Register 0xA1 (0xA4, 0xA7, 0xAA), Bits[5:0] = 000000b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 000000b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 001100b
Register 0xA2 (0xA5, 0xA8, 0xAB), Bits[5:0] = 101111b
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
Corresponding CMOS drivers set to A for noninverting and B for inverting.
3
The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.
4
Incremental delay; does not include propagation delay.
5
All delays between zero scale and full scale can be estimated by linear interpolation.
1
2
Rev. C | Page 7 of 80
AD9516-3
Data Sheet
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter
CLK-TO-LVPECL ADDITIVE PHASE NOISE
CLK = 1 GHz, Output = 1 GHz
Divider = 1
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 100 MHz Offset
CLK = 1 GHz, Output = 200 MHz
Divider = 5
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
CLK-TO-LVDS ADDITIVE PHASE NOISE
CLK = 1.6 GHz, Output = 800 MHz
Divider = 2
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 100 MHz Offset
CLK = 1.6 GHz, Output = 400 MHz
Divider = 4
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
CLK-TO-CMOS ADDITIVE PHASE NOISE
CLK = 1 GHz, Output = 250 MHz
Divider = 4
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
Min
Typ
−109
−118
−130
−139
−144
−146
−147
−149
Max
Unit
Test Conditions/Comments
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−120
−126
−139
−150
−155
−157
−157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
−103
−110
−120
−127
−133
−138
−147
−149
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−114
−122
−132
−140
−146
−150
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
−110
−120
−127
−136
−144
−147
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. C | Page 8 of 80
Data Sheet
Parameter
CLK = 1 GHz, Output = 50 MHz
Divider = 20
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
AD9516-3
Min
Typ
Max
−124
−134
−142
−151
−157
−160
−163
Unit
Test Conditions/Comments
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVPECL ABSOLUTE PHASE NOISE
VCO = 2.25 GHz; Output = 2.25 GHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
VCO = 2.00 GHz; Output = 2.00 GHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
VCO = 1.75 GHz; Output = 1.75 GHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
Min
Typ
Max
Unit
−49
−79
−104
−123
−143
−147
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−53
−83
−108
−126
−142
−147
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−54
−88
−112
−130
−143
−147
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
Internal VCO; direct to LVPECL output
Rev. C | Page 9 of 80
AD9516-3
Data Sheet
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
Min
VCO = 1.97 GHz; LVPECL = 245.76 MHz; PLL LBW = 143 kHz
Typ
Max
129
303
135
302
179
343
VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 143 kHz
VCO = 1.97 GHz; LVPECL = 61.44 MHz; PLL LBW = 143 kHz
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is clean,
so a wider PLL loop bandwidth is used;
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
Min
VCO = 1.87 GHz; LVPECL = 622.08 MHz; PLL LBW = 125 Hz
VCO = 1.87 GHz; LVPECL = 155.52 MHz; PLL LBW = 125 Hz
VCO = 1.97 GHz; LVPECL = 122.88 MHz; PLL LBW = 125 Hz
Typ
Max
400
390
485
Unit
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 10.0 MHz; R = 20
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Min
Typ
Max
54
77
109
79
114
163
124
176
259
Rev. C | Page 10 of 80
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical setup
using an external 245.76 MHz VCXO (Toyocom
TCO-2112); reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Data Sheet
AD9516-3
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
Typ
Max
Unit
40
80
215
fs rms
fs rms
fs rms
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
LVDS OUTPUT ADDITIVE TIME JITTER
245
fs rms
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;
VCO Divider Not Used
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16
85
fs rms
113
280
fs rms
fs rms
365
fs rms
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
Test Conditions/Comments
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method; DCC not used
for even divides
Calculated from SNR of ADC method; DCC on
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method; DCC not used
for even divides
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method; DCC not used
for even divides
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min
Typ
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
LVDS OUTPUT ADDITIVE TIME JITTER
210
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
CMOS OUTPUT ADDITIVE TIME JITTER
285
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
350
Max
Unit
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL and VCO;
uses rising edge of clock signal
Calculated from SNR of ADC method
Rev. C | Page 11 of 80
AD9516-3
Data Sheet
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter
DELAY BLOCK ADDITIVE TIME JITTER 1
100 MHz Output
Delay (1600 µA, 0x1C) Fine Adj. 000000
Delay (1600 µA, 0x1C) Fine Adj. 101111
Delay (800 µA, 0x1C) Fine Adj. 000000
Delay (800 µA, 0x1C) Fine Adj. 101111
Delay (800 µA, 0x4C) Fine Adj. 000000
Delay (800 µA, 0x4C) Fine Adj. 101111
Delay (400 µA, 0x4C) Fine Adj. 000000
Delay (400 µA, 0x4C) Fine Adj. 101111
Delay (200 µA, 0x1C) Fine Adj. 000000
Delay (200 µA, 0x1C) Fine Adj. 101111
Delay (200 µA, 0x4C) Fine Adj. 000000
Delay (200 µA, 0x4C) Fine Adj. 101111
1
Min
Typ
Max
0.54
0.60
0.65
0.85
0.79
1.2
1.2
2.0
1.3
2.5
1.9
3.8
Unit
Test Conditions/Comments
Incremental additive jitter
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SERIAL CONTROL PORT
Table 14.
Parameter
CS (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup and Hold, tS, tH
CS Minimum Pulse Width High, tPWH
Min
Typ
Max
2.0
0.8
3
110
2
Unit
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
V
V
µA
µA
pF
SCLK has an internal 30 kΩ pull-down resistor
2.0
0.8
110
1
2
2.0
0.8
10
20
2
2.7
0.4
25
16
16
2
1.1
8
2
3
V
V
µA
µA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Rev. C | Page 12 of 80
Data Sheet
AD9516-3
PD, RESET, AND SYNC PINS
Table 15.
Parameter
INPUT CHARACTERISTICS
Min
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
RESET TIMING
Pulse Width Low
SYNC TIMING
Pulse Width Low
2.0
Typ
Max
0.8
110
1
2
Unit
Test Conditions/Comments
These pins each have a 30 kΩ internal pull-up
resistor
V
V
µA
µA
pF
50
ns
1.5
High speed
clock cycles
High speed clock is CLK input signal
Max
Unit
Test Conditions/Comments
When selected as a digital output (CMOS);
there are other modes in which these pins
are not CMOS digital outputs; see Table 54,
Register 0x017, Register 0x01A, and Register 0x01B
0.4
100
V
V
MHz
3
pF
On-chip capacitance; used to calculate RC time
constant for analog lock detect readback; use a
pull-up resistor
1.02
MHz
8
kHz
Frequency above which the monitor always
indicates the presence of the reference
Frequency above which the monitor always
indicates the presence of the reference
LD, STATUS, AND REFMON PINS
Table 16.
Parameter
OUTPUT CHARACTERISTICS
Min
Output Voltage High (VOH)
Output Voltage Low (VOL)
MAXIMUM TOGGLE RATE
2.7
ANALOG LOCK DETECT
Capacitance
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range
Extended Range (REF1 and REF2 Only)
LD PIN COMPARATOR
Trip Point
Hysteresis
Typ
1.6
260
V
mV
Rev. C | Page 13 of 80
Applies when mux is set to any divider or
counter output or PFD up/down pulse; also
applies in analog lock detect mode; usually
debug mode only; beware that spurs may couple
to output when any of these pins are toggling
AD9516-3
Data Sheet
POWER DISSIPATION
Table 17.
Parameter
POWER DISSIPATION, CHIP
Power-On Default
Typ
Max
Unit
Test Conditions/Comments
1.0
1.2
W
Full Operation; CMOS Outputs at 225 MHz
1.6
2.2
W
Full Operation; LVDS Outputs at 225 MHz
1.6
2.3
W
PD Power-Down
75
185
mW
PD Power-Down, Maximum Sleep
31
No clock; no programming; default register values;
does not include power dissipated in external resistors
PLL on; internal VCO = 2250 MHz; VCO divider = 2;
all channel dividers on; six LVPECL outputs at 562.5 MHz;
eight CMOS outputs (10 pF load) at 225 MHz; all fine delay on,
maximum current; does not include power dissipated in
external resistors
PLL on; internal VCO = 2250 MHz, VCO divider = 2;
all channel dividers on; six LVPECL outputs at 562.5 MHz;
four LVDS outputs at 225 MHz; all fine delay on, maximum
current; does not include power dissipated in external
resistors
PD pin pulled low; does not include power dissipated
in terminations
PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
SYNC power-down, Register 0x230[2] = 1b; REF for distribution
power-down, Register 0x230[1] = 1b
PLL operating; typical closed loop configuration
Power delta when a function is enabled/disabled
VCO divider bypassed
All references off to differential reference enabled
All references off to REF1 or REF2 enabled; differential
reference not enabled
CLK input selected to VCO selected
PLL off to PLL on, normal operation; no reference enabled
Divider bypassed to divide-by-2 to divide-by-32
No LVPECL output on to one LVPECL output on,
independent of frequency
Second LVPECL output turned on, same channel
No LVDS output on to one LVDS output on; see Figure 8 for
dependence on output frequency
Second LVDS output turned on, same channel
Static; no CMOS output on to one CMOS output on;
see Figure 9 for variation over output frequency
Static; second CMOS output, same pair, turned on
Static; first output, second pair, turned on
Delay block off to delay block enabled; maximum current
setting
VCP Supply
POWER DELTAS, INDIVIDUAL FUNCTIONS
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
Min
4
mW
4.8
mW
30
20
4
mW
mW
mW
VCO
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
70
75
30
160
mW
mW
mW
mW
LVPECL Driver
LVDS Channel (Divider Plus Output Driver)
90
120
mW
mW
LVDS Driver
CMOS Channel (Divider Plus Output Driver)
50
100
mW
mW
CMOS Driver (Second in Pair)
CMOS Driver (First in Second Pair)
Fine Delay Block
0
30
50
mW
mW
mW
Rev. C | Page 14 of 80
Data Sheet
AD9516-3
TIMING DIAGRAMS
tCLK
CLK
DIFFERENTIAL
80%
tPECL
LVDS
06422-060
tCMOS
tRL
tFL
06422-062
20%
tLVDS
Figure 4. LVDS Timing, Differential
Figure 2. CLK/CLK to Clock Output Timing, DIV = 1
DIFFERENTIAL
SINGLE-ENDED
80%
80%
LVPECL
CMOS
10pF LOAD
20%
tFP
tRC
tFC
Figure 5. CMOS Timing, Single-Ended, 10 pF Load
Figure 3. LVPECL Timing, Differential
Rev. C | Page 15 of 80
06422-063
tRP
06422-061
20%
AD9516-3
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 18.
Parameter
VS, VS_LVPECL to GND
VCP to GND
REFIN, REFIN to GND
REFIN to REFIN
RSET to GND
CPRSET to GND
CLK, CLK to GND
CLK to CLK
SCLK, SDIO, SDO, CS to GND
OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,
OUT3, OUT3, OUT4, OUT4, OUT5, OUT5,
OUT6, OUT6, OUT7, OUT7, OUT8, OUT8,
OUT9, OUT9 to GND
SYNC to GND
REFMON, STATUS, LD to GND
Junction Temperature1
Storage Temperature Range
Lead Temperature (10 sec)
1
Rating
−0.3 V to +3.6 V
−0.3 V to+5.8 V
−0.3 V to VS + 0.3 V
−3.3 V to +3.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−1.2 V to +1.2 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 19.
Package Type1
64-Lead LFCSP
1
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
150°C
−65°C to +150°C
300°C
θJA
22
Unit
°C/W
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-2.
ESD CAUTION
See Table 19 for θJA.
Rev. C | Page 16 of 80
Data Sheet
AD9516-3
PIN 1
INDICATOR
AD9516-3
TOP VIEW
(Not to Scale)
LVPECL LVPECL
LVDS/CMOS
w/FINE DELAY ADJUST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LVDS/CMOS
w/FINE DELAY ADJUST
LVPECL LVPECL
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
VS
VS
CLK
CLK
NC
SCLK
LVPECL LVPECL
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
REFIN (REF1)
REFIN (REF2)
CPRSET
VS
VS
GND
RSET
VS
OUT0
OUT0
VS_LVPECL
OUT1
OUT1
VS
VS
VS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
GND
OUT2
OUT2
VS_LVPECL
OUT3
OUT3
VS
GND
OUT9 (OUT9B)
OUT9 (OUT9A)
OUT8 (OUT8B)
OUT8 (OUT8A)
NOTES
1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
2. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
06422-003
CS
NC
NC
NC
SDO
SDIO
RESET
PD
OUT4
OUT4
VS_LVPECL
OUT5
OUT5
VS
VS
VS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC = NO CONNECT
Figure 6. Pin Configuration
Table 20. Pin Function Descriptions
Input/
Output
I
Pin Type
Power
Mnemonic
VS
Description
3.3 V Power Pins.
I
3.3 V CMOS
REFMON
3
O
3.3 V CMOS
LD
4
5
6
7
I
O
O
I
Power
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
VCP
CP
STATUS
REF_SEL
8
I
3.3 V CMOS
SYNC
9
I
Loop filter
LF
10
13
O
I
BYPASS
CLK
14
I
Loop filter
Differential
clock input
Differential
clock input
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x1A.
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.0 V.
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
Loop Filter (Input). Connects to VCO control voltage node internally. This pin has
31 pF of internal capacitance to ground, which may influence the loop filter design
for large (>500 kHz) loop bandwidths.
This pin is for bypassing the LDO to ground with a capacitor.
Along with CLK, this is the differential input for the clock distribution section.
CLK
Along with CLK, this is the differential input for the clock distribution section.
Pin No.
1, 11, 12, 30,
31, 32, 38,
49, 50, 51,
57, 60, 61
2
Rev. C | Page 17 of 80
AD9516-3
Data Sheet
Input/
Output
N/A
I
I
Pin Type
NC
3.3 V CMOS
3.3 V CMOS
Mnemonic
NC
SCLK
CS
21
22
23
24
27, 41, 54
37, 44, 59,
EPAD
56
55
53
52
43
42
40
39
25
26
28
29
48
O
I/O
I
I
I
N/A
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Power
GND
SDO
SDIO
RESET
PD
VS_LVPECL
GND
O
O
O
O
O
O
O
O
O
O
O
O
O
47
O
46
O
45
O
33
O
34
O
35
O
36
O
58
O
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6
(OUT6A)
OUT6
(OUT6B)
OUT7
(OUT7A)
OUT7
(OUT7B)
OUT8
(OUT8A)
OUT8
(OUT8B)
OUT9
(OUT9A)
OUT9
(OUT9B)
RSET
62
O
CPRSET
A resistor connected to this pin sets the CP current range. Nominal value = 5.1 kΩ.
63
I
64
I
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
Current set
resistor
Current set
resistor
Reference
input
Reference
input
Description
No Connect. Do not connect to this pin.
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select, Active Low. This pin has an internal 30 kΩ pull-up
resistor.
Serial Control Port Unidirectional Serial Data Out.
Serial Control Port Bidirectional Serial Data In/Out.
Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
Ground Pins, Including External Paddle (EPAD). The external paddle on the bottom of
the package must be connected to ground for proper operation.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output, or a Single-Ended CMOS
Output.
A resistor connected to this pin sets internal bias currents. Nominal value = 4.12 kΩ.
REFIN
(REF2)
REFIN
(REF1)
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2.
Along with REFIN, this pin is the differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1.
Pin No.
15, 18, 19, 20
16
17
Rev. C | Page 18 of 80
Data Sheet
AD9516-3
TYPICAL PERFORMANCE CHARACTERISTICS
300
70
3 CHANNELS—6 LVPECL
280
65
260
60
55
KVCO (MHz/V)
220
200
3 CHANNELS—3 LVPECL
180
50
45
40
160
2 CHANNELS—2 LVPECL
35
140
30
120
1 CHANNEL—1 LVPECL
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
25
1.7
06422-007
100
1.8
Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs
2.0
2.1
2.2
2.3
Figure 10. VCO KVCO vs. Frequency
5.0
180
4.5
2 CHANNELS—4 LVDS
CURRENT FROM CP PIN (mA)
160
CURRENT (mA)
1.9
VCO FREQUENCY (GHz)
06422-010
CURRENT (mA)
240
140
2 CHANNELS—2 LVDS
120
100
4.0
3.5
PUMP DOWN
PUMP UP
3.0
2.5
2.0
1.5
1.0
0.5
1 CHANNEL—1 LVDS
200
400
600
800
FREQUENCY (MHz)
0
0
1.0
1.5
2.0
2.5
3.0
VOLTAGE ON CP PIN (V)
Figure 11. Charge Pump Characteristics at VCP = 3.3 V
Figure 8. Current vs. Frequency—LVDS Outputs
(Includes Clock Distribution Current Draw)
240
5.0
4.5
CURRENT FROM CP PIN (mA)
220
200
2 CHANNELS—8 CMOS
180
2 CHANNELS—2 CMOS
160
140
120
1 CHANNEL—2 CMOS
100
4.0
3.5
PUMP DOWN
PUMP UP
3.0
2.5
2.0
1.5
1.0
0.5
80
0
50
100
150
200
FREQUENCY (MHz)
250
Figure 9. Current vs. Frequency—CMOS Outputs
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VOLTAGE ON CP PIN (V)
Figure 12. Charge Pump Characteristics at VCP = 5.0 V
Rev. C | Page 19 of 80
5.0
06422-012
1 CHANNEL—1 CMOS
06422-009
CURRENT (mA)
0.5
06422-011
0
06422-008
80
Data Sheet
–140
10
–145
–10
RELATIVE POWER (dB)
0
–150
–155
–160
–20
–30
–40
–50
–60
–70
–80
–90
–165
–170
0.1
1
10
100
–110
PFD FREQUENCY (MHz)
CENTER 122.88MHz
5MHz/DIV
SPAN 50MHz
06422-137
–100
06422-013
PFD PHASE NOISE REFERRED TO PFD INPUT
(dBc/Hz)
AD9516-3
Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;
LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz
Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
–210
10
–212
–10
RELATIVE POWER (dB)
PLL FIGURE OF MERIT (dBc/Hz)
0
–214
–216
–218
–220
–20
–30
–40
–50
–60
–70
–80
–90
–222
0
0.5
2.0
1.5
1.0
2.5
SLEW RATE (V/ns)
–110
06422-136
–224
CENTER 122.88MHz
100kHz/DIV
SPAN 1MHz
06422-135
–100
Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;
LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz
Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN
1.9
10
0
RELATIVE POWER (dB)
–10
1.5
1.3
1.1
–20
–30
–40
–50
–60
–70
–80
–90
1.8
1.9
2.0
2.1
2.2
VCO FREQUENCY (GHz)
2.3
Figure 15. VCO Tuning Voltage vs. Frequency
(Note that VCO calibration centers the dc tuning voltage
for the PLL setup that is active during calibration.)
–100
–110
CENTER 122.88MHz
100kHz/DIV
SPAN 1MHz
06422-134
0.9
1.7
06422-138
VCO TUNING VOLTAGE (V)
1.7
Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz;
LBW = 127 kHz; ICP = 3.0 mA; FVCO = 2.21 GHz
Rev. C | Page 20 of 80
Data Sheet
AD9516-3
0.4
0.6
DIFFERENTIAL OUTPUT (V)
DIFFERENTIAL OUTPUT (V)
1.0
0.2
–0.2
0.2
0
–0.2
–0.6
5
10
15
20
25
TIME (ns)
–0.4
0
1
06422-017
0
06422-014
–1.0
2
TIME (ns)
Figure 19. LVPECL Output (Differential) at 100 MHz
Figure 22. LVDS Output (Differential) at 800 MHz
1.0
DIFFERENTIAL OUTPUT (V)
DIFFERENTIAL OUTPUT (V)
2.8
0.6
0.2
–0.2
1.8
0.8
1
0
2
TIME (ns)
06422-015
–0.2
–1.0
0
20
40
60
80
100
TIME (ns)
06422-018
–0.6
Figure 23. CMOS Output at 25 MHz
Figure 20. LVPECL Output (Differential) at 1600 MHz
0.4
OUTPUT (V)
0.2
0
1.8
0.8
–0.2
–0.4
0
5
10
15
20
TIME (ns)
25
Figure 21. LVDS Output (Differential) at 100 MHz
0
2
4
6
8
TIME (ns)
Figure 24. CMOS Output at 250 MHz
Rev. C | Page 21 of 80
10
12
06422-019
–0.2
06422-016
DIFFERENTIAL OUTPUT (V)
2.8
AD9516-3
Data Sheet
1600
–80
1400
PHASE NOISE (dBc/Hz)
DIFFERENTIAL SWING (mV p-p)
–90
1200
1000
–100
–110
–120
–130
0
1
2
3
FREQUENCY (GHz)
–150
10k
06422-020
800
Figure 25. LVPECL Differential Swing vs. Frequency
Using a Differential Probe Across the Output Pair
100k
1M
10M
100M
FREQUENCY (Hz)
06422-023
–140
Figure 28. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2250 MHz
–80
–90
PHASE NOISE (dBc/Hz)
DIFFERENTIAL SWING (mV p-p)
700
600
–100
–110
–120
–130
0
100
200
300
400
500
600
700
800
FREQUENCY (MHz)
–150
10k
06422-021
500
Figure 26. LVDS Differential Swing vs. Frequency
Using a Differential Probe Across the Output Pair
1M
10M
100M
FREQUENCY (Hz)
Figure 29. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 2000 MHz
–80
CL = 2pF
3
–90
CL = 10pF
PHASE NOISE (dBc/Hz)
OUTPUT SWING (V)
100k
06422-024
–140
2
CL = 20pF
1
–100
–110
–120
–130
0
100
200
300
400
500
600
OUTPUT FREQUENCY (MHz)
Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load
–150
10k
06422-133
0
100k
1M
FREQUENCY (Hz)
10M
100M
06422-025
–140
Figure 30. Internal VCO Phase Noise (Absolute) Direct to LVPECL at 1750 MHz
Rev. C | Page 22 of 80
Data Sheet
AD9516-3
–120
–110
–125
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–120
–130
–135
–140
–145
–150
–130
–140
–150
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–160
10
06422-026
–120
–110
PHASE NOISE (dBc/Hz)
1k
10k
100k
1M
10M
100M
10M
100M
–120
–130
–150
10
06422-027
100
FREQUENCY (Hz)
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 35. Phase Noise (Additive) LVDS at 800 MHz, Divide-by-2
Figure 32. Phase Noise (Additive) LVPECL at 200 MHz, Divide-by-5
–120
–110
–130
PHASE NOISE (dBc/Hz)
–100
–120
–130
–140
–150
–160
–140
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
06422-128
PHASE NOISE (dBc/Hz)
1M
–140
–150
–150
10
100k
06422-130
PHASE NOISE (dBc/Hz)
–100
–160
10
10k
Figure 34. Phase Noise (Additive) LVDS at 200 MHz, Divide-by-1
–110
–140
1k
FREQUENCY (Hz)
Figure 31. Phase Noise (Additive) LVPECL at 245.76 MHz, Divide-by-1
–130
100
–170
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 36. Phase Noise (Additive) CMOS at 50 MHz, Divide-by-20
Figure 33. Phase Noise (Additive) LVPECL at 1600 MHz, Divide-by-1
Rev. C | Page 23 of 80
06422-131
–160
10
06422-142
–155
AD9516-3
Data Sheet
–100
–120
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–110
–120
–130
–140
–130
–140
–150
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–160
1k
06422-132
–160
10
Figure 37. Phase Noise (Additive) CMOS at 250 MHz, Divide-by-4
10k
100k
1M
10M
FREQUENCY (Hz)
100M
06422-140
–150
Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
1000
–100
OC-48 OBJECTIVE MASK
AD9516
–120
–130
–140
–160
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
06422-141
–150
100
FOBJ
10
1
NOTE: 375UI MAX AT 10Hz OFFSET IS THE
MAXIMUM JITTER THAT CAN BE
GENERATED BY THE TEST EQUIPMENT.
FAILURE POINT IS GREATER THAN 375UI.
0.1
0.01
0.1
1
10
JITTER FREQUENCY (kHz)
Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO at
1.97 GHz; PFD = 15.36 MHz; LBW = 143 kHz; LVPECL Output = 122.88 MHz
–90
PHASE NOISE (dBc/Hz)
–100
–110
–120
–130
–140
–160
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
06422-139
–150
Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 1.87 GHz;
PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
Rev. C | Page 24 of 80
Figure 41. GR-253 Jitter Tolerance Plot
100
1000
06422-148
INPUT JITTER AMPLITUDE (UIPP)
PHASE NOISE (dBc/Hz)
–110
Data Sheet
AD9516-3
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings
varies. In a square wave, the time jitter is a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that can be
attributed to the device or subsystem being measured. The phase
noise of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
impacts the total system phase noise when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own phase noise to the total. In many cases, the
phase noise of one element dominates the system phase noise.
When there are multiple contributors to phase noise, the total
is the square root of the sum of squares of the individual
contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that can be
attributed to the device or subsystem being measured. The time
jitter of any external oscillators or clock sources is subtracted. This
makes it possible to predict the degree to which the device impacts
the total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contributes
its own time jitter to the total. In many cases, the time jitter of
the external oscillators and clock sources dominates the system
time jitter.
Rev. C | Page 25 of 80
AD9516-3
Data Sheet
DETAILED BLOCK DIAGRAM
REF_ SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
REF2
R
DIVIDER
STATUS
REFIN (REF1)
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
BYPASS
PLL
REFERENCE
LOCK
DETECT
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
OUT6 (OUT6A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT6 (OUT6B)
LVDS/CMOS
OUT7 (OUT7A)
∆t
OUT7 (OUT7B)
OUT8 (OUT8A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
AD9516-3
OUT8 (OUT8B)
LVDS/CMOS
∆t
OUT9 (OUT9A)
OUT9 (OUT9B)
06422-002
SCLK
SDIO
SDO
CS
OUT2
LVPECL
Figure 42. Detailed Block Diagram
Rev. C | Page 26 of 80
Data Sheet
AD9516-3
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
Table 21. Default Settings of Some PLL Registers
The AD9516 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 52 and Table 53 through Table 62). Each section
or function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
Register
0x010[1:0] = 01b
0x1E0[2:0] = 010b
0x1E1[0] = 0b
0x1E1[1] = 0b
High Frequency Clock Distribution—CLK or External
VCO > 1600 MHz
When using the internal PLL with an external VCO, the PLL
must be turned on.
The AD9516 power-up default configuration has the PLL
powered off and the routing of the input set so that the
CLK/CLK input is connected to the distribution section
through the VCO divider (divide-by-2/ divide-by-3/divide-by4/divide-by-5/divide-by-6). This is a distribution only mode
that allows for an external input up to 2400 MHz (see Table 3).
The maximum frequency that can be applied to the channel
dividers is 1600 MHz; therefore, higher input frequencies must
be divided down before reaching the channel dividers. This
input routing can also be used for lower input frequencies, but
the minimum divide is 2 before the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency of less
than 2400 MHz. In this configuration, the internal VCO is not
used and is powered off. The external VCO/VCXO feeds
directly into the prescaler.
The register settings shown in Table 21 are the default values of
these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers can also be set intentionally to
these values.
Function
PLL asynchronous power-down (PLL off ).
Set VCO divider = 4.
Use the VCO divider.
CLK selected as the source.
Table 22. Settings When Using an External VCO
Register
0x010[1:0] = 00b
0x010 to 0x01D
0x1E1[1] = 0b
Function
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP,
according to the intended loop configuration.
CLK selected as the source.
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 23. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Rev. C | Page 27 of 80
Function
PFD polarity positive (higher control
voltage produces higher frequency).
PFD polarity negative (higher control
voltage produces lower frequency).
AD9516-3
Data Sheet
REF_SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
REF2
R
DIVIDER
STATUS
REFIN (REF1)
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
BYPASS
PLL
REFERENCE
LOCK
DETECT
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
OUT6 (OUT6A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT6 (OUT6B)
LVDS/CMOS
OUT7 (OUT7A)
∆t
OUT7 (OUT7B)
OUT8 (OUT8A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
AD9516-3
OUT8 (OUT8B)
LVDS/CMOS
∆t
OUT9 (OUT9A)
OUT9 (OUT9B)
06422-029
SCLK
SDIO
SDO
CS
OUT2
LVPECL
Figure 43. High Frequency Clock Distribution or External VCO > 1600 MHz
Rev. C | Page 28 of 80
Data Sheet
AD9516-3
REF_SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
REF2
R
DIVIDER
STATUS
REFIN (REF1)
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
BYPASS
PLL
REFERENCE
LOCK
DETECT
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
OUT0
0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
SCLK
SDIO
SDO
CS
OUT2
LVPECL
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
OUT6 (OUT6A)
∆t
DIVIDE BY
1 TO 32
OUT6 (OUT6B)
LVDS/CMOS
OUT7 (OUT7A)
∆t
OUT7 (OUT7B)
OUT8 (OUT8A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
AD9516-3
OUT8 (OUT8B)
LVDS/CMOS
∆t
OUT9 (OUT9A)
OUT9 (OUT9B)
06422-030
DIVIDE BY
1 TO 32
Figure 44. Internal VCO and Clock Distribution
Table 24. Settings When Using Internal VCO
Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the
channel dividers does not exceed their specified maximum
frequency of 1600 MHz (see Table 3). The internal PLL uses an
external loop filter to set the loop bandwidth. The external loop
filter is also crucial to the loop stability.
Register
0x010[1:0] = 00b
0x010 to 0x01E
0x018[0] = 0b,
0x232[0] = 1b
When using the internal VCO, it is necessary to calibrate the
VCO (Register 0x018[0]) to ensure optimal performance.
0x1E0[2:0]
For internal VCO and clock distribution applications, use the
register settings that are shown in Table 24.
0x1E1[0] = 0b
0x1E1[1] = 1b
0x018[0] = 1b,
0x232[0] = 1b
Rev. C | Page 29 of 80
Function
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP,
according to the intended loop configuration.
Reset VCO calibration. This is not required
the first time after power-up, but it must
be performed subsequently.
Set VCO divider to divide-by-2, divide-by-3,
divide-by-4, divide-by-5, and divide-by-6.
Use the VCO divider as source for the
distribution section.
Select VCO as the source.
Initiate VCO calibration.
AD9516-3
Data Sheet
REF_SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
REF2
R
DIVIDER
STATUS
REFIN (REF1)
PROGRAMMABLE
R DELAY
VCO STATUS
REFIN (REF2)
BYPASS
PLL
REFERENCE
LOCK
DETECT
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4
DIVIDE BY
1 TO 32
OUT4
LVPECL
OUT5
OUT5
OUT6 (OUT6A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT6 (OUT6B)
LVDS/CMOS
OUT7 (OUT7A)
∆t
OUT7 (OUT7B)
OUT8 (OUT8A)
∆t
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
AD9516-3
OUT8 (OUT8B)
LVDS/CMOS
∆t
OUT9 (OUT9A)
OUT9 (OUT9B)
06422-028
SCLK
SDIO
SDO
CS
OUT2
LVPECL
Figure 45. Clock Distribution or External VCO < 1600 MHz
Rev. C | Page 30 of 80
Data Sheet
AD9516-3
Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is less than 1600 MHz, a configuration that bypasses
the VCO divider can be used. This configuration differs from the
High Frequency Clock Distribution—CLK or External VCO >
1600 MHz section only in that the VCO divider (divide-by-2,
divide-by-3, divide-by-4, divide-by-5, and divide-by-6) is bypassed.
This limits the frequency of the clock source to frequency >
finished
active
selected
frequency >
threshold
threshold
threshold
Blank
Blank
Blank
Rev. C | Page 55 of 80
0x01
0x00
0x7D
0x01
0x00
0x00
0x03
0x00
0x06
0x00
0x06
0x00
0x00
0x00
0x00
0x00
0x00
N/A
AD9516-3
Data Sheet
Reg.
Addr.
(Hex)
Parameter
Bit 7 (MSB) Bit 6
Fine Delay Adjust—OUT6 to OUT9
0x0A0 OUT6 delay
bypass
0x0A1 OUT6 delay
Blank
full-scale
0x0A2 OUT6 delay
Blank
fraction
0x0A3 OUT7 delay
bypass
0x0A4 OUT7 delay
Blank
full-scale
0x0A5 OUT7 delay
Blank
fraction
0x0A6 OUT8 delay
bypass
0x0A7 OUT8 delay
Blank
full-scale
0x0A8 OUT8 delay
Blank
fraction
0x0A9 OUT9 delay
bypass
0x0AA OUT9 delay
Blank
full-scale
0x0AB OUT9 delay
Blank
fraction
0x0AC
to
0x0EF
LVPECL Outputs
0x0F0
OUT0
Blank
0x0F1
OUT1
Blank
0x0F2
OUT2
Blank
0x0F3
OUT3
Blank
0x0F4
OUT4
Blank
0x0F5
OUT5
Blank
0x0F6
to
0x13F
LVDS/CMOS Outputs
0x140
OUT6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
OUT6 delay
bypass
OUT6 ramp current
Blank
OUT6 ramp capacitors
OUT6 delay fraction
OUT7 ramp capacitors
OUT7 delay fraction
OUT8 ramp capacitors
OUT8 delay fraction
OUT9 ramp capacitors
0x01
0x00
0x01
0x00
0x00
OUT9 delay
bypass
OUT9 ramp current
Blank
0x00
0x00
OUT8 delay
bypass
OUT8 ramp current
Blank
0x01
0x00
OUT7 delay
bypass
OUT7 ramp current
Blank
Default
Value
(Hex)
OUT9 delay fraction
0x01
0x00
0x00
Blank
OUT0
invert
OUT1
invert
OUT2
invert
OUT3
invert
OUT4
invert
OUT5
invert
OUT0 LVPECL
differential voltage
OUT1 LVPECL
differential voltage
OUT2 LVPECL
differential voltage
OUT3 LVPECL
differential voltage
OUT4 LVPECL
differential voltage
OUT5 LVPECL
differential voltage
OUT0 power-down
0x08
OUT1 power-down
0x0A
OUT2 power-down
0x08
OUT3 power-down
0x0A
OUT4 power-down
0x08
OUT5 power-down
0x0A
Blank
OUT6 CMOS
output polarity
0x141
OUT7
OUT7 CMOS
output polarity
0x142
OUT8
OUT8 CMOS
output polarity
0x143
OUT9
OUT9 CMOS
output polarity
OUT6 LVDS/
CMOS
output
polarity
OUT7 LVDS/
CMOS
output
polarity
OUT8 LVDS/
CMOS
output
polarity
OUT9 LVDS/
CMOS
output
polarity
OUT6
CMOS B
OUT6 select
LVDS/CMOS
OUT6 LVDS
output current
OUT6
power-down
0x42
OUT7
CMOS B
OUT7 select
LVDS/CMOS
OUT7 LVDS
output current
OUT7
power-down
0x43
OUT8
CMOS B
OUT8 select
LVDS/CMOS
OUT8 LVDS
output current
OUT8
power-down
0x42
OUT9
CMOS B
OUT9 select
LVDS/CMOS
OUT9 LVDS
output current
OUT9
power-down
0x43
Rev. C | Page 56 of 80
Data Sheet
AD9516-3
Reg.
Addr.
(Hex)
Parameter
Bit 7 (MSB)
0x144
to
0x18F
LVPECL Channel Dividers
Divider 0
0x190
(PECL)
Divider 0
0x191
bypass
0x192
Blank
0x193
Bit 4
Bit 3
Blank
Divider 0
no sync
Divider 0
force high
Divider 0
start high
Reserved
Divider 1 low cycles
Divider 1
bypass
0x195
Divider 1
no sync
Blank
Divider 2
(PECL)
Divider 1
force high
Divider 1
start high
Reserved
Divider 2 low cycles
Divider 2
bypass
0x197
Bit 5
Divider 0 low cycles
Divider 1
(PECL)
0x194
0x196
Bit 6
0x198
Divider 2
no sync
Blank
Divider 2
force high
Divider 2
start high
Reserved
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
Divider 0 high cycles
0x00
Divider 0 phase offset
0x80
Divider 0
direct to
output
Divider 1 high cycles
Divider 0
DCCOFF
0xBB
Divider 1 phase offset
Divider 1
direct to
output
Divider 2 high cycles
0x00
Divider 1
DCCOFF
0x00
0x00
Divider 2 phase offset
Divider 2
direct to
output
0x00
0x00
Divider 2
DCCOFF
0x00
LVDS/CMOS Channel Dividers
0x199
Divider 3
(LVDS/CMOS)
0x19A
0x19B
Low Cycles Divider 3.1
High Cycles Divider 3.1
0x22
Phase Offset Divider 3.2
Low Cycles Divider 3.2
Phase Offset Divider 3.1
High Cycles Divider 3.2
0x00
0x11
0x19C
Reserved
0x19D
Blank
0x19E
0x19F
0x1A0
0x1A1
Divider 4
(LVDS/CMOS)
Reserved
0x1A2
0x1A3
0x1A4
to
0x1DF
VCO Divider and CLK Input
0x1E0
VCO divider
0x1E1
Input CLKs
0x1E2
to
0x22A
Bypass
Divider 3.2
Bypass
Divider 3.1
Divider 3
no sync
Reserved
Divider 3
force high
Start High
Divider 3.2
Start High
Divider 3.1
Divider 3
DCCOFF
0x00
0x00
Low Cycles Divider 4.1
High Cycles Divider 4.1
0x22
Phase Offset Divider 4.2
Low Cycles Divider 4.2
Bypass
Divider 4.2
Phase Offset Divider 4.1
High Cycles Divider 4.2
Divider 4
Start High
force high
Divider 4.2
0x00
0x11
0x00
Blank
Bypass
Divider 4.1
Divider 4
no sync
Reserved
Start High
Divider 4.1
Divider 4
DCCOFF
0x00
Reserved
Blank
Blank
Reserved
Reserved
Power-down
PowerVCO clock
down
clock input interface
section
Blank
Rev. C | Page 57 of 80
Powerdown VCO
and CLK
VCO Divider
Select
Bypass VCO
VCO or CLK
divider
0x02
0x00
AD9516-3
Reg.
Addr.
(Hex)
Parameter
System
Power-down
0x230
and sync
0x231
Update All Registers
Update all
0x232
registers
Data Sheet
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Powerdown sync
Powerdown
distribution
reference
Reserved
Reserved
Blank
Blank
Rev. C | Page 58 of 80
Bit 0 (LSB)
Default
Value
(Hex)
Soft sync
0x00
0x00
Update all
registers (selfclearing bit)
0x00
Data Sheet
AD9516-3
REGISTER MAP DESCRIPTIONS
Table 53 through Table 62 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2].
Table 53. Serial Port Configuration
Reg.
Addr
(Hex)
0x000
Bits
[7:4]
Name
Mirrored, Bits[3:0]
3
Long instruction
2
Soft reset
1
LSB first
0
SDO active
0x003
[7:0]
Part ID (read only)
0x004
0
Read back active registers
Description
Bits[7:4] should always mirror Bits[3:0] so that it does not matter whether the part
is in MSB or LSB first mode (see Bit 1, Register 0x000). The user should set the bits as follows:
Bit 7 = Bit 0.
Bit 6 = Bit 1.
Bit 5 = Bit 2.
Bit 4 = Bit 3.
Short/long instruction mode. This part uses long instruction mode only, so this bit should
always be set to 1.
0: 8-bit instruction (short).
1: 16-bit instruction (long) (default).
Soft reset.
1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared to
0 to complete reset operation.
MSB or LSB data orientation.
0: data-oriented MSB first; addressing decrements (default).
1: data-oriented LSB first; addressing increments.
Selects unidirectional or bidirectional data transfer mode.
0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default).
1: SDO used for read, SDIO used for write; unidirectional mode.
Uniquely identifies the dash version (-0 through -4) of the AD9516.
AD9516-0: 0x01.
AD9516-1: 0x41.
AD9516-2: 0x81.
AD9516-3: 0x43.
AD9516-4: 0xC3.
Selects register bank used for a readback.
0: reads back buffer registers (default).
1: reads back active registers.
Rev. C | Page 59 of 80
AD9516-3
Data Sheet
Table 54. PLL
Reg.
Addr.
(Hex)
0x010
Bits
7
Name
PFD polarity
[6:4]
CP current
[3:2]
CP mode
[1:0]
PLL power-down
0x011
[7:0]
0x012
[5:0]
0x013
0x014
[5:0]
[7:0]
0x015
[4:0]
0x016
7
14-bit R divider,
Bits[7:0] (LSB)
14-bit R divider,
Bits[13:8] (MSB)
6-bit A counter
13-bit B counter,
Bits[7:0] (LSB)
13-bit B counter,
Bits[12:8] (MSB)
Set CP pin to VCP/2
6
Reset R counter
5
Reset A, B counters
4
Reset all counters
3
B counter
bypass
Description
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires
positive polarity; Bit 7 = 0.
0: positive; higher control voltage produces higher frequency (default).
1: negative; higher control voltage produces lower frequency.
Charge pump current (with CPRSET = 5.1 kΩ).
6
5
4
ICP (mA)
0
0
0
0.6
0
0
1
1.2
0
1
0
1.8
0
1
1
2.4
1
0
0
3.0
1
0
1
3.6
1
1
0
4.2
1
1
1
4.8 (default)
Charge pump operating mode.
3
2
Charge Pump Mode
0
0
High impedance state.
0
1
Force source current (pump up).
1
0
Force sink current (pump down).
1
1
Normal operation (default).
PLL operating mode.
1
0
Mode
0
0
Normal operation.
0
1
Asynchronous power-down (default).
1
0
Normal operation.
1
1
Synchronous power-down.
R divider LSBs—lower eight bits (default = 0x01).
R divider MSBs—upper six bits (default = 0x00).
A counter (part of N divider) (default = 0x00).
B counter (part of N divider)—lower eight bits (default = 0x03).
B counter (part of N divider)—upper five bits (default = 0x00).
Sets the CP pin to one-half of the VCP supply voltage.
0: CP normal operation (default).
1: CP pin set to VCP/2.
Resets R counter (R divider).
0: normal (default).
1: holds the R counter in reset.
Resets A and B counters (part of N divider).
0: normal (default).
1: holds the A and B counters in reset.
Resets R, A, and B counters.
0: normal (default).
1: holds the R, A, and B counters in reset.
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
Rev. C | Page 60 of 80
Data Sheet
Reg.
Addr.
(Hex)
0x016
0x017
Bits
[2:0]
[7:2]
Name
Prescaler P
STATUS pin
control
AD9516-3
Description
Prescaler: DM = dual modulus, and FD = fixed divide.
2
1
0
Mode
Prescaler
0
0
0
FD
Divide-by-1.
0
0
1
FD
Divide-by-2.
0
1
0
DM
Divide-by-2 (2/3 mode).
0
1
1
DM
Divide-by-4 (4/5 mode).
1
0
0
DM
Divide-by-8 (8/9 mode).
1
0
1
DM
Divide-by-16 (16/17 mode).
1
1
0
DM
Divide-by-32 (32/33 mode) (default).
1
1
1
FD
Divide-by-3.
Selects the signal that is connected to the STATUS pin.
Level or
Dynamic
Signal
Signal at STATUS Pin
7
6
5
4
3
2
0
0
0
0
0
0
LVL
Ground (dc) (default).
0
0
0
0
0
1
DYN
N divider output (after the delay).
0
0
0
0
1
0
DYN
R divider output (after the delay).
0
0
0
0
1
1
DYN
A divider output.
0
0
0
1
0
0
DYN
Prescaler output.
0
0
0
1
0
1
DYN
PFD up pulse.
0
0
0
1
1
0
DYN
PFD down pulse.
0
X
X
X
X
X
LVL
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1
0
0
0
0
0
LVL
Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
Status of selected reference (status of differential reference); active
1
0
0
1
0
1
LVL
high.
Status of unselected reference (not available in differential mode);
1
0
0
1
1
0
LVL
active high.
1
0
0
1
1
1
LVL
Status REF1 frequency (active high).
1
0
1
0
0
0
LVL
Status REF2 frequency (active high).
1
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
1
LVL
Status of VCO frequency (active high).
1
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
1
1
0
LVL
Holdover active (active high).
1
0
1
1
1
1
LVL
LD pin comparator output (active high).
1
1
0
0
0
0
LVL
VS (PLL supply).
1
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
1
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
1
0
1
1
1
LVL
Status of REF1 frequency (active low).
1
1
1
0
0
0
LVL
Status of REF2 frequency (active low).
1
1
1
0
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
LVL
LVL
LVL
LVL
LVL
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD) (active low).
Holdover active (active low).
LD pin comparator output (active low).
Rev. C | Page 61 of 80
AD9516-3
Data Sheet
Reg.
Addr.
(Hex)
0x017
Bits
[1:0]
Name
Antibacklash
pulse width
0x018
[6:5]
Lock detect
counter
4
Digital lock detect
window
3
Disable digital
lock detect
[2:1]
VCO cal
divider
[0]
VCO cal now
0x019
[7:6]
R, A, B counters
SYNC pin reset
0x01A
[5:3]
[2:0]
[6]
R path delay
N path delay
Reference
frequency monitor
threshold
Description
1
0
Antibacklash Pulse Width (ns)
0
0
2.9 (default).
0
1
1.3.
1
0
6.0.
1
1
2.9.
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
5
PFD Cycles to Determine Lock
0
0
5 (default).
0
1
16.
1
0
64.
1
1
255.
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
Digital lock detect operation.
0: normal lock detect operation (default).
1: disables lock detect.
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
2
1
VCO Calibration Clock Divider
0
0
2.
0
1
4.
1
0
8.
1
1
16 (default).
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. To initiate
calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0 (if not
zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1, followed by another update bit
(Register 0x232, Bit 0).
7
6
Action
0
0
Does nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
1
Does nothing on SYNC.
R path delay (default = 0x00) (see Table 2).
N path delay (default = 0x00) (see Table 2).
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see Table 16: REF1, REF2, and VCO Frequency Status Monitor parameter).
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
Rev. C | Page 62 of 80
Data Sheet
Reg.
Addr.
(Hex)
0x01A
Bits
[5:0]
Name
LD pin control
0x01B
7
VCO frequency
monitor
6
REF2 (REFIN)
frequency monitor
5
REF1 (REFIN)
frequency monitor
AD9516-3
Description
Selects the signal that is connected to the LD pin.
Level or
Dynamic
Signal
Signal at LD Pin
5
4
3
2
1
0
0
0
0
0
0
0
LVL
Digital lock detect (high = lock, low = unlock) (default).
0
0
0
0
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
1
HIZ
High-Z LD pin.
0
0
0
1
0
0
CUR
Current source lock detect (110 µA when DLD is true).
0
X
X
X
X
X
LVL
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1
0
0
0
0
0
LVL
Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when indifferential mode).
1
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
Status of unselected reference (not available in differential mode); active
1
0
0
1
1
0
LVL
high.
1
0
0
1
1
1
LVL
Status REF1 frequency (active high).
1
0
1
0
0
0
LVL
Status REF2 frequency (active high).
1
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
1
LVL
Status of VCO frequency (active high).
1
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
1
1
0
LVL
Holdover active (active high).
1
0
1
1
1
1
LVL
Not available. Do not use.
1
1
0
0
0
0
LVL
VS (PLL supply).
1
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
Status of unselected reference (not available in differential mode); active
1
1
0
1
1
0
LVL
low.
1
1
0
1
1
1
LVL
Status of REF1 frequency (active low).
1
1
1
0
0
0
LVL
Status of REF2 frequency (active low).
1
1
1
0
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
1
1
0
1
1
LVL
Status of VCO frequency (active low).
1
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
1
0
1
LVL
Digital lock detect (DLD); active low.
1
1
1
1
1
0
LVL
Holdover active (active low).
1
1
1
1
1
1
LVL
Not available. Do not use.
Enables or disables VCO frequency monitor.
0: disables VCO frequency monitor (default).
1: enables VCO frequency monitor.
Enables or disables REF2 frequency monitor.
0: disables REF2 frequency monitor (default).
1: enables REF2 frequency monitor.
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
0: disables REF1 (REFIN) frequency monitor (default).
1: enables REF1 (REFIN) frequency monitor.
Rev. C | Page 63 of 80
AD9516-3
Data Sheet
Reg.
Addr.
(Hex)
0x01B
Bits
[4:0]
Name
REFMON
pin control
0x01C
7
6
Disable
switchover
deglitch
Select REF2
5
Use REF_SEL pin
4
3
2
Reserved
Reserved
REF2 power-on
1
REF1 power-on
0
Differential
reference
Description
Selects the signal that is connected to the REFMON pin.
Level or
Dynamic
Signal
Signal at REFMON Pin
4
3
2
1
0
0
0
0
0
0
LVL
Ground (dc) (default).
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
0
0
0
1
0
DYN
REF2 clock (not available in differential mode).
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
0
0
1
1
1
LVL
Status REF1 frequency (active high).
0
1
0
0
0
LVL
Status REF2 frequency (active high).
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
0
1
0
1
1
LVL
Status of VCO frequency (active high).
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
0
1
1
0
1
LVL
Digital lock detect (DLD); active low.
0
1
1
1
0
LVL
Holdover active (active high).
0
1
1
1
1
LVL
LD pin comparator output (active high).
1
0
0
0
0
LVL
VS (PLL supply).
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
1
1
LVL
Status of REF1 frequency (active low).
1
1
0
0
0
LVL
Status of REF2 frequency (active low).
1
1
0
0
1
LVL
(Status of REF1 frequency) AND (Status of REF2 frequency).
1
1
0
1
0
LVL
(DLD) AND (Status of selected reference) AND (Status of VCO).
1
1
0
1
1
LVL
Status of VCO frequency (active low).
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
0
1
LVL
Digital lock detect (DLD); active low.
1
1
1
1
0
LVL
Holdover active (active low).
1
1
1
1
1
LVL
LD pin comparator output (active low).
Disables or enables the switchover deglitch circuit.
0: enables switchover deglitch circuit (default).
1: disables switchover deglitch circuit.
If Register 0x01C, Bit 5 = 0, select reference for PLL.
0: selects REF1 (default).
1: selects REF2.
Sets method of PLL reference selection.
0: uses Register 0x01C, Bit 6 (default).
1: uses REF_SEL pin.
0: (default).
0: (default).
This bit turns the REF2 power on.
0: REF2 power off (default).
1: REF2 power on.
This bit turns the REF1 power on.
0: REF1 power off (default).
1: REF1 power on.
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic
switchover or REF1 and REF2 to work.
0: single-ended reference mode (default).
1: differential reference mode.
Rev. C | Page 64 of 80
Data Sheet
Reg.
Addr.
(Hex)
0x01D
0x01F
Bits
4
Name
PLL status
register disable
3
LD pin comparator
enable
2
Holdover enable
1
External
holdover control
0
Holdover enable
6
VCO cal finished
5
Holdover active
4
REF2 selected
3
VCO frequency >
threshold
2
REF2 frequency >
threshold
1
REF1 frequency >
threshold
0
Digital lock detect
AD9516-3
Description
Disables the PLL status register readback.
0: PLL status register enable (default).
1: PLL status register disable.
Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When
in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if
the PLL was previously in a locked state (see Figure 53). Otherwise, this function can be used with the REFMON and
STATUS pins to monitor the voltage on this pin.
0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default).
1: enables LD pin comparator.
Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
0: automatic holdover mode—holdover controlled by automatic holdover circuit. (default)
1: external holdover mode—holdover controlled by SYNC pin.
Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
Read-only register. Indicates status of the VCO calibration.
0: VCO calibration not finished.
1: VCO calibration finished.
Read-only register. Indicates if the part is in the holdover state (see Figure 53). This is not the same as holdover enabled.
0: not in holdover.
1: holdover state active.
Read-only register. Indicates which PLL reference is selected as the input to the PLL.
0: REF1 selected (or differential reference if in differential mode).
1: REF2 selected.
Read-only register. Indicates if the VCO frequency is greater than the threshold (see Table 16, REF1, REF2, and VCO
frequency status monitor).
0: VCO frequency is less than the threshold.
1: VCO frequency is greater than the threshold.
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by
Register 0x01A, Bit 6.
0: REF2 frequency is less than threshold frequency.
1: REF2 frequency is greater than threshold frequency.
Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A, Bit 6.
0: REF1 frequency is less than threshold frequency.
1: REF1 frequency is greater than threshold frequency.
Read-only register. Digital lock detect.
0: PLL is not locked.
1: PLL is locked.
Rev. C | Page 65 of 80
AD9516-3
Data Sheet
Table 55. Fine Delay Adjust—OUT6 to OUT9
Reg.
Addr.
(Hex)
0x0A0
Bits
0
Name
OUT6 delay bypass
0x0A1
[5:3]
OUT6 ramp capacitors
[2:0]
OUT6 ramp current
0x0A2
[5:0]
OUT6 delay fraction
0x0A3
0
OUT7 delay bypass
0x0A4
[5:3]
OUT7 ramp capacitors
Description
Bypasses or uses the delay function.
0: uses delay function.
1: bypasses delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the
number of the capacitors and the ramp current sets the delay full scale.
5
4 3 Number of Capacitors
0
0 0 4 (default)
0
0 1 3
0
1 0 3
0
1 1 2
1
0 0 3
1
0 1 2
1
1 0 2
1
1 1 1
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1 0 Current (µA)
0
0 0 200 (default)
0
0 1 400
0
1 0 600
0
1 1 800
1
0 0 1000
1
0 1 1200
1
1 0 1400
1
1 1 1600
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Bypasses or uses the delay function.
0: use delay function.
1: bypass delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the
number of the capacitors and the ramp current sets the delay full scale.
5
4 3 Number of Capacitors
0
0 0 4 (default)
0
0 1 3
0
1 0 3
0
1 1 2
1
0 0 3
1
0 1 2
1
1 0 2
1
1 1 1
Rev. C | Page 66 of 80
Data Sheet
Reg.
Addr.
(Hex)
0x0A4
Bits
[2:0]
Name
OUT7 ramp current
0x0A5
[5:0]
OUT7 delay fraction
0x0A6
0
OUT8 delay bypass
0x0A7
[5:3]
OUT8 ramp capacitors
[2:0]
OUT8 ramp current
[5:0]
OUT8 delay fraction
0x0A8
AD9516-3
Description
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1
0
Current (µA)
0
0
0
200 (default)
0
0
1
400
0
1
0
600
0
1
1
800
1
0
0
1000
1
0
1
1200
1
1
0
1400
1
1
1
1600
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Bypasses or uses the delay function.
0: uses delay function.
1: bypasses delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the
number of capacitors and the ramp current sets the delay full scale.
5
4
3
Number of Capacitors
0
0
0
4 (default)
0
0
1
3
0
1
0
3
0
1
1
2
1
0
0
3
1
0
1
2
1
1
0
2
1
1
1
1
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1
0
Current (µA)
0
0
0
200 (default)
0
0
1
400
0
1
0
600
0
1
1
800
1
0
0
1000
1
0
1
1200
1
1
0
1400
1
1
1
1600
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Rev. C | Page 67 of 80
AD9516-3
Data Sheet
Reg.
Addr.
(Hex)
0x0A9
Bits
0
Name
OUT9 delay bypass
0x0AA
[5:3]
OUT9 ramp capacitors
[2:0]
OUT9 ramp current
[5:0]
OUT9 delay fraction
0x0AB
Description
Bypasses or uses the delay function.
0: uses delay function.
1: bypasses delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the
number of capacitors and the ramp current sets the delay full scale.
5
4
3
Number of Capacitors
0
0
0
4 (default)
0
0
1
3
0
1
0
3
0
1
1
2
1
0
0
3
1
0
1
2
1
1
0
2
1
1
1
1
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1
0
Current Value (µA)
0
0
0
200 (default)
0
0
1
400
0
1
0
600
0
1
1
800
1
0
0
1000
1
0
1
1200
1
1
0
1400
1
1
1
1600
Selects the fraction of the full-scale delay desired (6-bit binary).
A setting of 000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Table 56. LVPECL Outputs
Reg.
Addr.
(Hex)
0x0F0
Bits
4
Name
OUT0 invert
[3:2]
OUT0 LVPECL
differential voltage
[1:0]
OUT0 power-down
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation (default).
0
1
Partial power-down, reference on; use only if there are no external
load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down.
1
1
Total power-down, reference off; use only if there are no external
load resistors.
Rev. C | Page 68 of 80
Output
On
Off
Off
Off
Data Sheet
Reg.
Addr.
(Hex)
0x0F1
0x0F2
0x0F3
Bits
4
Name
OUT1 invert
[3:2]
OUT1 LVPECL
differential voltage
[1:0]
OUT1 power-down
4
OUT2 invert
[3:2]
OUT2 LVPECL
differential voltage
[1:0]
OUT2 power-down
4
OUT3 invert
[3:2]
OUT3 LVPECL
differential voltage
[1:0]
OUT3 power-down
AD9516-3
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation.
0
1
Partial power-down, reference on; use only if there are no external load
resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down (default).
1
1
Total power-down, reference off; use only if there are no external load
resistors.
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation (default).
0
1
Partial power-down, reference on; use only if there are no external load
resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down.
1
1
Total power-down, reference off; use only if there are no external load
resistors.
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation.
0
1
Partial power-down, reference on; use only if there are no external
load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down (default).
1
1
Total power-down, reference off; use only if there are no external
load resistors.
Rev. C | Page 69 of 80
Output
On
Off
Off
Off
Output
On
Off
Off
Off
Output
On
Off
Off
Off
AD9516-3
Reg.
Addr.
(Hex)
0x0F4
0x0F5
Data Sheet
Bits
4
Name
OUT4 invert
[3:2]
OUT4 LVPECL
differential voltage
[1:0]
OUT4 power-down
4
OUT5 invert
[3:2]
OUT5 LVPECL
differential voltage
[1:0]
OUT5 power-down
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation (default).
0
1
Partial power-down, reference on; use only if there are no external load
resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down.
1
1
Total power-down, reference off; use only if there are no external load
resistors.
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation.
0
1
Partial power-down, reference on; use only if there are no external load
resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down (default).
1
1
Total power-down, reference off; use only if there are no external load
resistors.
Rev. C | Page 70 of 80
Output
On
Off
Off
Off
Output
On
Off
Off
Off
Data Sheet
AD9516-3
Table 57. LVDS/CMOS Outputs
Reg.
Addr.
(Hex)
0x140
0x141
Bits
[7:5]
Name
OUT6 output polarity
4
OUT6 CMOS B
3
OUT6 select LVDS/CMOS
[2:1]
OUT6 LVDS output current
0
OUT6 power-down
[7:5]
OUT7 output polarity
4
OUT7 CMOS B
3
OUT7 select LVDS/CMOS
[2:1]
OUT7 LVDS output current
Description
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7
6
5
OUT4A (CMOS)
OUT4B (CMOS)
OUT4 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.
0: turns off the CMOS B output (default).
1: turns on the CMOS B output.
Selects LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Set output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Power-down output (LVDS/CMOS).
0: power on (default).
1: power off.
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7
6
5
OUT5A (CMOS)
OUT5B (CMOS)
OUT5 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.
0: turns off the CMOS B output (default).
1: turns on the CMOS B output.
Select LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Sets output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Rev. C | Page 71 of 80
AD9516-3
Data Sheet
Reg.
Addr.
(Hex)
0x141
Bits
0
Name
OUT7 power-down
0x142
[7:5]
OUT8 output polarity
4
OUT8 CMOS B
3
OUT8 select LVDS/CMOS
[2:1]
OUT8 LVDS output current
0
OUT8 power-down
[7:5]
OUT9 output polarity
4
OUT9 CMOS B
3
OUT9 select LVDS/CMOS
0x143
Description
Power-down output (LVDS/CMOS).
0: power on.
1: power off (default).
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7
6
5
OUT6A (CMOS)
OUT6B (CMOS)
OUT6 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.
0: turn off the CMOS B output (default).
1: turn on the CMOS B output.
Selects LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Sets output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Power-down output (LVDS/CMOS).
0: power on (default).
1: power off.
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7
6
5
OUT7A (CMOS)
OUT7B (CMOS)
OUT7 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turns on/off the CMOS B output. There is no effect in LVDS mode.
0: turn off the CMOS B output (default).
1: turn on the CMOS B output.
Selects LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Rev. C | Page 72 of 80
Data Sheet
Reg.
Addr.
(Hex)
0x143
Bits
[2:1]
Name
OUT9 LVDS output current
0
OUT9 power-down
AD9516-3
Description
Sets output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Power-down output (LVDS/CMOS).
0: power on.
1: power off (default).
Table 58. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
0x190
0x191
0x192
0x193
0x194
Bits
[7:4]
Name
Divider 0 low cycles
[3:0]
Divider 0 high cycles
7
Divider 0 bypass
6
Divider 0 nosync
5
Divider 0 force high
4
Divider 0 start high
[3:0]
1
Divider 0 phase offset
Divider 0 direct to output
0
Divider 0 DCCOFF
[7:4]
Divider 1 low cycles
[3:0]
Divider 1 high cycles
7
Divider 1 bypass
6
Divider 1 nosync
5
Divider 1 force high
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider (default).
1: bypasses divider.
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Rev. C | Page 73 of 80
AD9516-3
Data Sheet
Reg.
Addr.
(Hex)
0x194
Bits
4
Name
Divider 1 start high
0x195
[3:0]
1
Divider 1 phase offset
Divider 1 direct to output
0
Divider 1 DCCOFF
[7:4]
Divider 2 low cycles
[3:0]
Divider 2 high cycles
7
Divider 2 bypass
6
Divider 2 nosync
5
Divider 2 force high
4
Divider 2 start high
[3:0]
1
Divider 2 phase offset
Divider 2 direct to output
0
Divider 2 DCCOFF
0x196
0x197
0x198
Description
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses and powers down the divider; routes input to divider output.
0: uses divider.
1: bypasses divider (default).
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: starts low (default).
1: starts high.
Phase offset (default = 0x0).
Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK.
0: OUT4 and OUT5 are connected to Divider 2 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Table 59. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex)
0x199
Bits
[7:4]
Name
Low Cycles Divider 3.1
[3:0]
High Cycles Divider 3.1
0x19A
[7:4]
Phase Offset Divider 3.2
0x19B
[3:0]
[7:4]
Phase Offset Divider 3.1
Low Cycles Divider 3.2
[3:0]
High Cycles Divider 3.2
Description
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high. A value of
0x0 means that the divider is high for one input clock cycle (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1)of 3.2 divider input during which 3.2 output stays high. A value
of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Rev. C | Page 74 of 80
Data Sheet
Reg.
Addr.
(Hex)
0x19C
Bits
5
Name
Bypass Divider 3.2
4
Bypass Divider 3.1
3
Divider 3 nosync
2
Divider 3 force high
1
Start High Divider 3.2
0
Start High Divider 3.1
0x19D
0
Divider 3 DCCOFF
0x19E
[7:4]
Low Cycles Divider 4.1
[3:0]
High Cycles Divider 4.1
[7:4]
[3:0]
[7:4]
Phase Offset Divider 4.2
Phase Offset Divider 4.1
Low Cycles Divider 4.2
[3:0]
High Cycles Divider 4.2
5
Bypass Divider 4.2
4
Bypass Divider 4.1
3
Divider 4 nosync
2
Divider 4 force high
1
Start High Divider 4.2
0
Start High Divider 4.1
0
Divider 4 DCCOFF
0x19F
0x1A0
0x1A1
0x1A2
AD9516-3
Description
Bypasses (and powers down) 3.2 divider logic, routes clock to 3.2 output.
0: does not bypass (default).
1: bypasses.
Bypasses (and powers down) 3.1 divider logic, routes clock to 3.1 output.
0: does not bypass 3.1 divider logic (default).
1: bypasses 3.1 divider logic.
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Force Divider 3 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
Divider 3.2 starts high/low.
0: starts low (default).
1: starts high.
Divider 3.1 starts high/low.
0: starts low (default).
1: starts high.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 4.1 divider input during which 4.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 4.2 divider input during which 4.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypasses (and powers down) 4.2 divider logic; route clock to 4.2 output.
0: does not bypass 4.2 divider logic (default).
1: bypasses 4.2 divider logic.
Bypasses (and powers down) 4.1 divider logic; route clock to 4.1 output.
0: does not bypass 4.1 divider logic (default).
1: bypasses 4.1 divider logic.
Nosync.
0: obeys chip-level SYNC signal (default).
1: ignores chip-level SYNC signal.
Forces Divider 4 output high. Requires that nosync also be set.
0: forces low (default).
1: forces high.
Divider 4.2 starts high/low.
0: starts low (default).
1: starts high.
Divider 4.1 starts high/low.
0: starts low (default).
1: starts high.
Duty-cycle correction function.
0: enables duty-cycle correction (default).
1: disables duty-cycle correction.
Rev. C | Page 75 of 80
AD9516-3
Data Sheet
Table 60. VCO Divider and CLK Input
Reg.
Addr
(Hex)
0x1E0
Bits
[2:0]
Name
VCO divider
0x1E1
4
Power down clock input section
3
Power down VCO clock interface
2
Power down VCO and CLK
1
Select VCO or CLK
0
Bypass VCO divider
0x1E1
Description
2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
Divide
2.
3.
4 (default).
5.
6.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1 1 0 Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1 1 1 Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
Powers down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
Powers down both VCO and CLK input.
0; normal operation (default).
1: power-down.
Selects either the VCO or the CLK as the input to VCO divider.
0: selects external CLK as input to VCO divider (default).
1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
Bypasses or uses the VCO divider.
0: uses VCO divider (default).
1: bypasses VCO divider; cannot select VCO as input when this is selected.
Table 61. System
Reg.
Addr.
(Hex)
0x230
Bits
2
Name
Power down SYNC
1
Power down distribution reference
0
Soft SYNC
Description
Powers down the SYNC function.
0: normal operation of the SYNC function (default).
1: powers down SYNC circuitry.
Powers down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: powers down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
0: same as SYNC high (default).
1: same as SYNC low.
Table 62. Update All Registers
Reg.
Addr
(Hex)
0x232
Bits
0
Name
Update all registers
Description
This bit must be set to 1 to transfer the contents of the buffer registers into the active
registers. This bit is self-clearing; that is, it does not have to be set back to 0.
1 (self-clearing): updates all active registers to the contents of the buffer registers.
Rev. C | Page 76 of 80
Data Sheet
AD9516-3
APPLICATIONS INFORMATION
Within the AD9516 family, lower VCO frequencies generally
result in slightly lower jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.45 GHz to 2.95 GHz) of the AD9516 family. If the desired
frequency plan can be achieved with a version of the AD9516
that has a lower VCO frequency, choosing the lower frequency
part results in the lowest phase noise and the lowest jitter. However,
choosing a higher VCO frequency may result in more flexibility
in frequency planning.
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current and, thus, allows the designer
to fine-tune the PLL loop bandwidth in either direction.
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. It is a very accurate tool for
determining the optimal loop filter for a given application.
USING THE AD9516 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock.
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 70 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
110
18
1
SNR = 20log 2πf t
A J
100
16
90
tJ =
100
fS
200
f
80
14
S
400
f
70
12
S
1ps
60
2ps
10
10p
s
8
ENOB
The AD9516 has the following four frequency dividers: the
reference (or R) divider, the feedback (or N) divider, the VCO
divider, and the channel divider. When trying to achieve a
particularly difficult frequency divide ratio requiring a large
amount of frequency division, some of the frequency division
can be done by either the VCO divider or the channel divider,
thus allowing a higher phase detector frequency and more
flexibility in choosing the loop bandwidth.
1
SNR(dB) = 20 × log
2πf t
A J
50
40
6
30
10
100
1k
fA (MHz)
06422-044
The AD9516 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9516, keep in mind the following
guidelines.
Considering an ideal ADC of infinite resolution, where the step
size and quantization error can be ignored, the available SNR
can be expressed approximately by
SNR (dB)
FREQUENCY PLANNING USING THE AD9516
Figure 70. SNR and ENOB vs. Analog Input Frequency
See the AN-756 Application Note, Sampled Systems and the Effects
of Clock Phase Noise and Jitter; and the AN-501 Application Note,
Aperture Uncertainty and ADC System Performance, at
www.analog.com.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
may result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can
provide superior clock performance in a noisy environment.)
The AD9516 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
level, termination) should be considered when selecting the best
clocking/converter solution.
Rev. C | Page 77 of 80
AD9516-3
Data Sheet
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9516 provide the lowest jitter
clock signals that are available from the AD9516. The LVPECL
outputs (because they are open emitter) require a dc termination
to bias the output transistors. The simplified equivalent circuit
in Figure 59 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 71) or Y-termination (see Figure 72) is recommended.
In each case, the VS of the receiving buffer should match the
VS_LVPECL. If it does not, ac coupling is recommended (see
Figure 73).
The resistor network is designed to match the transmission line
impedance (50 Ω) and the switching threshold (VS − 1.3 V).
VS_DRV
50Ω
LVPECL
127Ω
127Ω
SINGLE-ENDED
(NOT COUPLED)
50Ω
VS
LVPECL
83Ω
83Ω
LVDS CLOCK DISTRIBUTION
The AD9516 provides four clock outputs (OUT6 to OUT9) that
are selectable as either CMOS or LVDS level outputs. LVDS is a
differential output option that uses a current mode output stage.
The nominal current is 3.5 mA, which yields 350 mV output swing
across a 100 Ω resistor. An output current of 7 mA is also available
in cases where a larger output swing is required. The LVDS
output meets or exceeds all ANSI/TIA/EIA-644 specifications.
Figure 71. DC-Coupled 3.3 V LVPECL, Far-End Thevenin Termination
VS_LVPECL
VS = 3.3V
LVPECL
Z0 = 50Ω
50Ω
50Ω
50Ω
LVPECL
06422-147
Z0 = 50Ω
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below VOL of the LVPECL
driver. In this case, VS_LVPECL on the AD9516 should equal VS
of the receiving buffer. Although the resistor combination shown
in Figure 72 results in a dc bias point of VS_LVPECL − 2 V, the
actual common-mode voltage is VS_LVPECL − 1.3 V because
additional current flows from the AD9516 LVPECL driver through
the pull-down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that
the pull-down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.
06422-145
VS_LVPECL
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 72, where VS_LVPECL = 2.5 V, the 50 Ω
termination resistor that is connected to ground should be
changed to 19 Ω.
A recommended termination circuit for the LVDS outputs is
shown in Figure 74.
Figure 72. DC-Coupled 3.3 V LVPECL, Y-Termination
VS
0.1nF
100Ω
100Ω
DIFFERENTIAL (COUPLED)
LVPECL
200Ω
Figure 73. AC-Coupled LVPECL with Parallel Transmission Line
LVDS
Figure 74. LVDS Output Termination
06422-146
200Ω
100Ω DIFFERENTIAL
100Ω
(COUPLED)
0.1nF TRANSMISSION LINE
06422-047
LVDS
LVPECL
VS
VS
VS_LVPECL
See the AN-586 Application Note, LVDS Data Outputs for HighSpeed Analog-to-Digital Converters for more information on LVDS.
Rev. C | Page 78 of 80
Data Sheet
AD9516-3
The AD9516 provides four clock outputs (OUT6 to OUT9)
that are selectable as either CMOS or LVDS level outputs.
When selected as CMOS, each output becomes a pair of CMOS
outputs, each of which can be individually turned on or off and
set as noninverting or inverting. These outputs are 3.3 V CMOS
compatible.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be used.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver.
The value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are also limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
10Ω
VS
CMOS
CMOS
50Ω
100Ω
CMOS
Figure 76. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9516 offers both LVPECL and
LVDS outputs that are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
60.4Ω
(1.0 INCH)
MICROSTRIP
10Ω
100Ω
06422-076
CMOS
Termination at the far-end of the PCB trace is a second option.
The CMOS outputs of the AD9516 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 76. The farend termination network should match the PCB trace impedance
and provide the desired switching point. The reduced signal
swing may still meet receiver input requirements in some
applications. This can be useful when driving long trace
lengths on less critical nets.
06422-077
CMOS CLOCK DISTRIBUTION
Figure 75. Series Termination of CMOS Output
Rev. C | Page 79 of 80
AD9516-3
Data Sheet
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.30
0.25
0.18
0.60 MAX
0.60
MAX
64 1
49
48
PIN 1
INDICATOR
PIN 1
INDICATOR
8.85
8.75 SQ
8.65
0.50
BSC
0.50
0.40
0.30
33
32
0.25 MIN
7.50 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
16
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
06-12-2012-C
12° MAX
17
BOTTOM VIEW
TOP VIEW
1.00
0.85
0.80
6.35
6.20 SQ
6.05
EXPOSED
PAD
Figure 77. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
CP-64-4
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9516-3BCPZ
AD9516-3BCPZ-REEL7
AD9516-3/PCBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Z = RoHS Compliant Part.
©2007–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06422-0-2/13(C)
Rev. C | Page 80 of 80
Package Option
CP-64-4
CP-64-4
工商网监
湘ICP备2023018690号
