12-Output Clock Generator with
Integrated 1.6 GHz VCO
AD9517-4
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
High performance instrumentation
Broadband infrastructure
ATE
GENERAL DESCRIPTION
The AD9517-4 1 provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz
to 1.80 GHz. Optionally, an external VCO/VCXO of up to
2.4 GHz can be used.
The AD9517-4 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
FUNCTIONAL BLOCK DIAGRAM
CP
REFIN
REF2
LF
STATUS
MONITOR
PLL
REF1
SWITCHOVER
AND MONITOR
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.45 GHz to 1.80 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Auto and manual reference switchover/holdover modes
Autorecover from holdover
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
2 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter 225 fs rms
Channel-to-channel skew paired outputs of 1600 MHz Section; Change to Table 22 ..........27
Changes to Table 24 ........................................................................29
Change to Configuration and Register Settings Section............31
Change to Phase Frequency Detector (PFD) Section ................32
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections .........33
Change to Figure 46; Added Figure 47 .........................................33
Changes to Reference Switchover and VCXO/VCO
Feedback Divider N—P, A, B, R Sections ....................................34
Changes to Table 28 ........................................................................35
Change to Holdover Section ..........................................................37
Changes to VCO Calibration Section ...........................................39
Changes to Clock Distribution Section ........................................40
Change to Clock Frequency Division Section;
Change to Table 34 .......................................................................... 41
Changes to Channel Dividers—LVDS/CMOS Outputs
Section; Change to Table 39 ........................................................... 43
Change to Write Section ................................................................ 50
Change to MSB/LSB First Transfers ............................................. 51
Change to Figure 64 ........................................................................ 52
Added Thermal Performance Section .......................................... 54
Changes to 0x003 Register Address .............................................. 55
Changes to Table 53 ........................................................................ 58
Changes to Table 54 ........................................................................ 59
Changes to Table 55 ........................................................................ 65
Changes to Table 56 ........................................................................ 67
Changes to Table 57 ........................................................................ 69
Changes to Table 58 ........................................................................ 71
Changes to Table 59 ........................................................................ 72
Changes to Table 60 and Table 61 ................................................. 74
Added Frequency Planning Using the AD9517 Section ............ 75
Changes to Figure 70 and Figure 72; Added Figure 71 .............. 76
Changes to LVDS Clock Distribution Section ............................ 76
Added Exposed Paddle Notation to Outline Dimensions ......... 78
Changes to Ordering Guide ........................................................... 78
7/07—Revision 0: Initial Version
Rev. A | Page 3 of 80
AD9517-4
SPECIFICATIONS
Typical (typ) is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted.
Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter
VS
VS_LVPECL
VCP
RSET Pin Resistor
CPRSET Pin Resistor
Min
3.135
2.375
VS
2.7
BYPASS Pin Capacitor
Typ
3.3
Max
3.465
VS
5.25
4.12
5.1
Unit
V
V
V
kΩ
kΩ
220
nF
Test Conditions/Comments
3.3 V ± 5%
Nominally 2.5 V to 3.3 V ± 5%
Nominally 3.3 V to 5.0 V ± 5%
Sets internal biasing currents; connect to ground
Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA);
actual current can be calculated by CP_lsb = 3.06/CPRSET;
connect to ground
Bypass for internal LDO regulator; necessary for LDO stability;
connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter
VCO (ON-CHIP)
Frequency Range
VCO Gain (KVCO)
Tuning Voltage (VT)
Min
1450
0.5
Test Conditions/Comments
1800
MHz
MHz/V
V
See Figure 15
See Figure 10
VCP ≤ VS when using internal VCO; outside of this range,
the CP spurs may increase due to CP up/down mismatch
VCP −
0.5
0
MHz/V
dBc/Hz
dBc/Hz
250
250
1.35
1.30
4.0
4.4
1.60
1.50
4.8
5.3
20
0
1.75
1.60
5.9
6.4
V
V
kΩ
kΩ
250
250
MHz
MHz
V p-p
V
V
μA
pF
0.8
0.8
+100
−100
2
100
45
1.3
2.9
6.0
MHz
mV p-p
2.0
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Antibacklash Pulse Width
Unit
1
−109
−128
Input Sensitivity
Self-Bias Voltage, REFIN
Self-Bias Voltage, REFIN
Input Resistance, REFIN
Input Resistance, REFIN
Dual Single-Ended Mode (REF1, REF2)
Input Frequency (AC-Coupled)
Input Frequency (DC-Coupled)
Input Sensitivity (AC-Coupled)
Input Logic High
Input Logic Low
Input Current
Input Capacitance
Max
50
Frequency Pushing (Open Loop)
Phase Noise @ 100 kHz Offset
Phase Noise @ 1 MHz Offset
REFERENCE INPUTS
Differential Mode (REFIN, REFIN)
Input Frequency
Typ
MHz
MHz
ns
ns
ns
Rev. A | Page 4 of 80
f = 1625 MHz
f = 1625 MHz
Differential mode (can accommodate single-ended input
by ac grounding undriven input)
Frequencies below about 1 MHz should be dc-coupled;
be careful to match VCM (self-bias voltage)
PLL figure of merit increases with increasing slew rate;
see Figure 14
Self-bias voltage of REFIN 1
Self-bias voltage of REFIN1
Self-biased1
Self-biased1
Two single-ended CMOS-compatible inputs
Slew rate > 50 V/μs
Slew rate > 50 V/μs; CMOS levels
Should not exceed VS p-p
Each pin, REFIN/REFIN (REF1/REF2)
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x17[1:0] = 11b
Register 0x017[1:0] = 10b
AD9517-4
Parameter
CHARGE PUMP (CP)
ICP Sink/Source
High Value
Low Value
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. CPV
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL DIVIDER DELAYS
000
001
010
011
100
101
110
111
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge
Pump/Phase Frequency Detector
(In-Band Is Within the LBW of the PLL)
@ 500 kHz PFD Frequency
@ 1 MHz PFD Frequency
@ 10 MHz PFD Frequency
@ 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
Min
Typ
Max
4.8
0.60
2.5
2.7/10
1
2
1.5
2
mA
mA
%
kΩ
nA
%
%
%
300
600
900
600
1000
2400
3000
3000
300
Off
330
440
550
660
770
880
990
Unit
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
1
2
Programmable
With CPRSET = 5.1 kΩ
CPV = VCP/2 V
0.5 < CPV < VCP − 0.5 V
0.5 < CPV < VCP − 0.5 V
CPV = VCP/2 V
A, B counter input frequency (prescaler input frequency
divided by P)
Register 0x019: R, Bits[5:3]; N, Bits[2:0]; see Table 54
ps
ps
ps
ps
ps
ps
ps
The PLL in-band phase noise floor is estimated by measuring
the in-band phase noise at the output of the VCO and
subtracting 20 log(N) (where N is the value of the N divider)
−165
−162
−151
−143
−220
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
3.5
7.5
3.5
ns
ns
ns
Reference slew rate > 0.25 V/ns; FOM +10 log(fPFD) is
an approximation of the PFD/CP in-band phase noise (in the
flat region) inside the PLL loop bandwidth; when running closed
loop, the phase noise, as observed at the VCO output, is
increased by 20 log(N)
Signal available at LD, STATUS, and REFMON pins
when selected by appropriate register settings
Selected by Register 0x017[1:0] and Register 0x018[4]
Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
7
15
11
ns
ns
ns
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
PLL DIGITAL LOCK DETECT WINDOW 2
Required to Lock (Coincidence of Edges)
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
To Unlock After Lock (Hysteresis)2
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6 ns)
Test Conditions/Comments
REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. A | Page 5 of 80
AD9517-4
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Min
Typ
01
01
Input Sensitivity, Differential
1
Unit
2.4
1.6
GHz
GHz
mV p-p
2
V p-p
1.8
1.8
V
V
mV p-p
kΩ
pF
150
Input Level, Differential
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Max
1.3
1.3
3.9
1.57
150
4.7
2
5.7
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed)
Measured at 2.4 GHz; jitter performance is improved
with slew rates > 1 V/ns
Larger voltage swings may turn on the protection
diodes and may degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3
Output Frequency, Maximum
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
LVDS CLOCK OUTPUTS
OUT4, OUT5, OUT6, OUT7
Output Frequency
Differential Output Voltage (VOD)
Min
Typ
Max
Unit
2950
VS − 1.12
VS − 2.03
550
VS − 0.98
VS − 1.77
790
VS − 0.84
VS − 1.49
980
MHz
V
V
mV
247
800
MHz
454
mV
25
mV
1.24
1.375
25
V
mV
14
24
mA
360
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
CMOS CLOCK OUTPUTS
OUT4A, OUT4B, OUT5A, OUT5B,
OUT6A, OUT6B, OUT7A, OUT7B
Output Frequency
Output Voltage High (VOH)
Output Voltage Low (VOL)
1.125
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Differential (OUT, OUT)
Using direct to output; see Figure 25
Differential termination 100 Ω @ 3.5 mA
Differential (OUT, OUT)
The AD9517 outputs toggle at higher frequencies,
but the output amplitude may not meet the VOD
specification
VOH − VOL measurement across a differential pair at
the default amplitude setting with output driver not
toggling; see Figure 26 for variation over frequency
This is the absolute value of the difference
between VOD when the normal output is high vs.
when the complementary output is high
(VOH + VOL)/2 across a differential pair
This is the absolute value of the difference
between VOS when the normal output is high vs.
when the complementary output is high
Output shorted to GND
Single-ended; termination = 10 pF
250
VS − 0.1
0.1
MHz
V
V
Rev. A | Page 6 of 80
See Figure 27
@ 1 mA load
@ 1 mA load
AD9517-4
TIMING CHARACTERISTICS
Table 5.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT
High Frequency Clock Distribution Configuration
Clock Distribution Configuration
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS 1
LVPECL Outputs That Share the Same Divider
LVPECL Outputs on Different Dividers
All LVPECL Outputs Across Multiple Parts
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT
For All Divide Values
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS1
LVDS Outputs That Share the Same Divider
LVDS Outputs on Different Dividers
All LVDS Outputs Across Multiple Parts
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT
For All Divide Values
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS1
CMOS Outputs That Share the Same Divider
All CMOS Outputs on Different Dividers
All CMOS Outputs Across Multiple Parts
DELAY ADJUST 3
Shortest Delay Range 4
Zero Scale
Full Scale
Longest Delay Range4
Zero Scale
Quarter Scale
Full Scale
Delay Variation with Temperature
Short Delay Range5
Zero Scale
Full Scale
Long Delay Range 5
Zero Scale
Full Scale
Min
835
773
1.4
Typ
Max
Unit
70
70
180
180
ps
ps
995
933
0.8
1180
1090
ps
ps
ps/°C
5
13
15
40
220
ps
ps
ps
170
160
350
350
ps
ps
1.8
1.25
2.1
ns
ps/°C
6
25
62
150
430
ps
ps
ps
495
475
1000
985
ps
ps
2.1
2.6
2.6
ns
ps/°C
4
28
66
180
675
ps
ps
ps
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V; level = 810 mV
20% to 80%, measured differentially
80% to 20%, measured differentially
See Figure 42
See Figure 44
Termination = 100 Ω differential; 3.5 mA
20% to 80%, measured differentially 2
20% to 80%, measured differentially2
Delay off on all outputs
Delay off on all outputs
1.6
Termination = open
20% to 80%; CLOAD = 10 pF
80% to 20%; CLOAD = 10 pF
Fine delay off
Fine delay off
50
540
315
880
680
1180
ps
ps
200
1.72
5.7
570
2.31
8.0
950
2.89
10.1
ps
ns
ns
0.23
−0.02
ps/°C
ps/°C
0.3
0.24
ps/°C
ps/°C
1
LVDS and CMOS
Register 0x0A1 (0x0A4) (0x0A7) (0x0AA) [5:0] 101111b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 000000b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 101111b
Register 0x0A1 (0x0A4) (0x0A7) (0x0AA) [5:0] 000000b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 000000b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 001100b
Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 101111b
This is the difference between any two similar delay paths while operating at the same voltage and temperature.
Corresponding CMOS drivers set to A for noninverting and B for inverting.
3
The maximum delay that can be used is a little less than one-half the period of the clock. A longer delay disables the output.
4
Incremental delay; does not include propagation delay.
5
All delays between zero scale and full scale can be estimated by linear interpolation.
2
Rev. A | Page 7 of 80
AD9517-4
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter
CLK-TO-LVPECL ADDITIVE PHASE NOISE
CLK = 1 GHz, OUTPUT = 1 GHz
Divider = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 100 MHz Offset
CLK = 1 GHz, OUTPUT = 200 MHz
Divider = 5
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK-TO-LVDS ADDITIVE PHASE NOISE
CLK = 1.6 GHz, OUTPUT = 800 MHz
Divider = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 100 MHz Offset
CLK = 1.6 GHz, OUTPUT = 400 MHz
Divider = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK-TO-CMOS ADDITIVE PHASE NOISE
CLK = 1 GHz, OUTPUT = 250 MHz
Divider = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
Min
Typ
−109
−118
−130
−139
−144
−146
−147
−149
Max
Unit
Test Conditions/Comments
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−120
−126
−139
−150
−155
−157
−157
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
−103
−110
−120
−127
−133
−138
−147
−149
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−114
−122
−132
−140
−146
−150
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
−110
−120
−127
−136
−144
−147
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 8 of 80
AD9517-4
Parameter
CLK = 1 GHz, OUTPUT = 50 MHz
Divider = 20
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
Min
Typ
Max
−124
−134
−142
−151
−157
−160
−163
Unit
Test Conditions/Comments
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVPECL ABSOLUTE PHASE NOISE
VCO = 1800 MHz; OUTPUT = 1800 MHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
VCO = 1625 MHz; OUTPUT = 1625 MHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
VCO = 1450 MHz; OUTPUT = 1450 MHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
Min
Typ
Max
Unit
−47
−82
−106
−125
−142
−146
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−55
−85
−109
−128
−143
−147
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−61
−90
−113
−131
−144
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 9 of 80
Test Conditions/Comments
Internal VCO; direct to LVPECL output
AD9517-4
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
Min
VCO = 1475 MHz; LVPECL = 491.52 MHz; PLL LBW = 135 kHz
Typ
Max
135
275
145
275
170
305
VCO = 1475 MHz; LVPECL = 122.88 MHz; PLL LBW = 135 kHz
VCO = 1475 MHz; LVPECL = 61.44 MHz; PLL LBW = 135 kHz
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is clean,
so a wider PLL loop bandwidth is used;
reference = 15.36 MHz; R = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
Min
VCO = 1555 MHz; LVPECL = 155.52 MHz; PLL LBW = 500 Hz
VCO = 1475 MHz; LVPECL = 122.88 MHz; PLL LBW = 500 Hz
Typ
Max
500
400
Unit
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 10.0 MHz; R = 20
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
LVPECL = 245.76 MHz; PLL LBW = 125 Hz
LVPECL = 122.88 MHz; PLL LBW = 125 Hz
LVPECL = 61.44 MHz; PLL LBW = 125 Hz
Min
Typ
54
77
109
79
114
163
124
176
259
Rev. A | Page 10 of 80
Max
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup using an external 245.76 MHz VCXO
(Toyocom TCO-2112); reference = 15.36 MHz;
R=1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
AD9517-4
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min
Typ
Max
Unit
CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1
CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4
CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16
40
80
215
fs rms
fs rms
fs rms
CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5
245
fs rms
85
fs rms
113
280
fs rms
fs rms
365
fs rms
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 1.6 GHz; LVDS = 800 MHz; Divider = 2;
VCO Divider Not Used
CLK = 1 GHz; LVDS = 200 MHz; Divider = 5
CLK = 1.6 GHz; LVDS = 100 MHz; Divider = 16
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 1.6 GHz; CMOS = 100 MHz; Divider = 16
Test Conditions/Comments
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method;
DCC not used for even divides
Calculated from SNR of ADC method;
DCC on
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
BW = 12 kHz to 20 MHz
BW = 12 kHz to 20 MHz
Calculated from SNR of ADC method;
DCC not used for even divides
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method;
DCC not used for even divides
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
Min
Typ
CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
LVDS OUTPUT ADDITIVE TIME JITTER
210
CLK = 2.4 GHz; VCO DIV = 2; LVDS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
CMOS OUTPUT ADDITIVE TIME JITTER
285
CLK = 2.4 GHz; VCO DIV = 2; CMOS = 100 MHz;
Divider = 12; Duty-Cycle Correction = Off
Max
350
Rev. A | Page 11 of 80
Unit
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
fs rms
Distribution section only; does not include PLL
and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
AD9517-4
DELAY BLOCK ADDITIVE TIME JITTER
Table 13.
Parameter
DELAY BLOCK ADDITIVE TIME JITTER 1
100 MHz Output
Delay (1600 μA, 1C) Fine Adj. 000000
Delay (1600 μA, 1C) Fine Adj. 101111
Delay (800 μA, 1C) Fine Adj. 000000
Delay (800 μA, 1C) Fine Adj. 101111
Delay (800 μA, 4C) Fine Adj. 000000
Delay (800 μA, 4C) Fine Adj. 101111
Delay (400 μA, 4C) Fine Adj. 000000
Delay (400 μA, 4C) Fine Adj. 101111
Delay (200 μA, 1C) Fine Adj. 000000
Delay (200 μA, 1C) Fine Adj. 101111
Delay (200 μA, 4C) Fine Adj. 000000
Delay (200 μA, 4C) Fine Adj. 101111
1
Min
Typ
Max
0.54
0.60
0.65
0.85
0.79
1.2
1.2
2.0
1.3
2.5
1.9
3.8
Unit
Test Conditions/Comments
Incremental additive jitter
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of squares (RSS) method.
SERIAL CONTROL PORT
Table 14.
Parameter
CS (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup and Hold, tS, tH
CS Minimum Pulse Width High, tPWH
Min
Typ
Max
2.0
0.8
3
110
2
Unit
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
V
V
μA
μA
pF
SCLK has an internal 30 kΩ pull-down resistor
2.0
0.8
110
1
2
2.0
0.8
10
20
2
2.7
0.4
25
16
16
2
1.1
8
2
3
V
V
μA
μA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Rev. A | Page 12 of 80
AD9517-4
PD, SYNC, AND RESET PINS
Table 15.
Parameter
INPUT CHARACTERISTICS
Min
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
RESET TIMING
Pulse Width Low
SYNC TIMING
Pulse Width Low
2.0
Typ
Max
0.8
110
1
2
Unit
Test Conditions/Comments
These pins each have a 30 kΩ internal pull-up
resistor
V
V
μA
μA
pF
50
ns
1.5
High speed
clock cycles
High speed clock is CLK input signal
Max
Unit
Test Conditions/Comments
When selected as a digital output (CMOS);
there are other modes in which these pins
are not CMOS digital outputs; see Table 54,
Register 0x017, Register 0x01A, and
Register 0x01B
0.4
100
V
V
MHz
3
pF
On-chip capacitance; used to calculate RC
time constant for analog lock detect
readback; use a pull-up resistor
1.02
MHz
8
kHz
Frequency above which the monitor
indicates the presence of the reference
Frequency above which the monitor
indicates the presence of the reference
LD, STATUS, AND REFMON PINS
Table 16.
Parameter
OUTPUT CHARACTERISTICS
Min
Output Voltage High (VOH)
Output Voltage Low (VOL)
MAXIMUM TOGGLE RATE
2.7
ANALOG LOCK DETECT
Capacitance
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range
Extended Range (REF1 and REF2 Only)
LD PIN COMPARATOR
Trip Point
Hysteresis
Typ
1.6
260
Rev. A | Page 13 of 80
V
mV
Applies when mux is set to any divider or
counter output, or PFD up/down pulse; also
applies in analog lock detect mode; usually
debug mode only; beware that spurs may
couple to output when any of these pins are
toggling
AD9517-4
POWER DISSIPATION
Table 17.
Parameter
POWER DISSIPATION, CHIP
Power-On Default
Typ
Max
Unit
Test Conditions/Comments
1.0
1.2
W
Full Operation; CMOS Outputs at 229 MHz
1.4
2.0
W
Full Operation; LVDS Outputs at 200 MHz
1.4
2.1
W
PD Power-Down
75
185
mW
PD Power-Down, Maximum Sleep
31
No clock; no programming; default register values;
does not include power dissipated in external resistors
PLL on; internal VCO = 2750 MHz; VCO divider = 2;
all channel dividers on; four LVPECL outputs @ 687.5 MHz;
eight CMOS outputs (10 pF load) @ 229 MHz; all fine delay on,
maximum current; does not include power dissipated in
external resistors
PLL on; internal VCO = 2800 MHz, VCO divider = 2;
all channel dividers on; four LVPECL outputs @ 700 MHz;
four LVDS outputs @ 200 MHz; all fine delay on, maximum
current; does not include power dissipated in external resistors
PD pin pulled low; does not include power dissipated in
terminations
PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
SYNC power-down, Register 0x230[2] = 1b; REF for distribution
power-down, Register 0x230[1] = 1b
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider not used
All references off to differential reference enabled
All references off to REF1 or REF2 enabled; differential
reference not enabled
CLK input selected to VCO selected
PLL off to PLL on, normal operation; no reference enabled
Divider bypassed to divide-by-2 to divide-by-32
No LVPECL output on to one LVPECL output on
Second LVPECL output turned on, same channel
No LVDS output on to one LVDS output on
Second LVDS output turned on, same channel
Static; no CMOS output on to one CMOS output on
Static; second CMOS output, same pair, turned on
Static; first output, second pair, turned on
Delay block off to delay block enabled; maximum current setting
VCP Supply
POWER DELTAS, INDIVIDUAL FUNCTIONS
VCO Divider
REFIN (Differential)
REF1, REF2 (Single-Ended)
VCO
PLL
Channel Divider
LVPECL Channel (Divider Plus Output Driver)
LVPECL Driver
LVDS Channel (Divider Plus Output Driver)
LVDS Driver
CMOS Channel (Divider Plus Output Driver)
CMOS Driver (Second in Pair)
CMOS Driver (First in Second Pair)
Fine Delay Block
Min
4
mW
4.8
mW
30
20
4
mW
mW
mW
70
75
30
160
90
120
50
100
0
30
50
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Rev. A | Page 14 of 80
AD9517-4
TIMING DIAGRAMS
tCLK
CLK
DIFFERENTIAL
80%
tPECL
LVDS
06428-060
tCMOS
tRL
tFL
06428-062
20%
tLVDS
Figure 4. LVDS Timing, Differential
Figure 2. CLK/CLK to Clock Output Timing, DIV = 1
DIFFERENTIAL
SINGLE-ENDED
80%
80%
LVPECL
CMOS
10pF LOAD
20%
tFP
tRC
tFC
Figure 5. CMOS Timing, Single-Ended, 10 pF Load
Figure 3. LVPECL Timing, Differential
Rev. A | Page 15 of 80
06428-063
tRP
06428-061
20%
AD9517-4
ABSOLUTE MAXIMUM RATINGS
Table 18.
Parameter
VS, VS_LVPECL to GND
VCP to GND
REFIN, REFIN to GND
REFIN to REFIN
RSET to GND
CPRSET to GND
CLK, CLK to GND
CLK to CLK
SCLK, SDIO, SDO, CS to GND
OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,
OUT3, OUT3,OUT4, OUT4, OUT5, OUT5,
OUT6, OUT6, OUT7, OUT7 to GND
SYNC to GND
REFMON, STATUS, LD to GND
Junction Temperature 1
Storage Temperature Range
Lead Temperature (10 sec)
1
Rating
−0.3 V to +3.6 V
−0.3 V to +5.8 V
−0.3 V to VS + 0.3 V
−3.3 V to +3.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−1.2 V to +1.2 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 19.
Package Type1
48-Lead LFCSP
1
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
150°C
−65°C to +150°C
300°C
θJA
24.7
Unit
°C/W
Thermal impedance measurements were taken on a 4-layer board in still air
in accordance with EIA/JESD51-2.
ESD CAUTION
See Table 19 for θJA.
Rev. A | Page 16 of 80
AD9517-4
37 VS
38 OUT1
39 OUT1
40 VS_LVPECL
41 OUT0
42 OUT0
44 RSET
45 VS
46 CPRSET
43 VS
36
PIN 1
INDICATOR
2
35
3
34
4
33
32
5
6
AD9517-4
31
7
TOP VIEW
(Not to Scale)
30
8
29
24
23
22
21
20
19
SCLK
CS
SDO
SDIO
RESET
PD
OUT2
OUT2
VS_LVPECL
OUT3
OUT3
VS
18
25
17
26
12
16
27
11
15
28
10
14
9
VS
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
VS
VS
OUT7 (OUT7B)
OUT7 (OUT7A)
OUT6 (OUT6B)
OUT6 (OUT6A)
VS
06428-003
1
13
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
VS
CLK
CLK
47 REFIN (REF2)
48 REFIN (REF1)
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 6. Pin Configuration
Table 20. Pin Function Descriptions
Pin No.
1
Input/
Output
I
Pin Type
3.3 V CMOS
Mnemonic
REFMON
2
O
3.3 V CMOS
LD
3
4
5
6
I
O
O
I
Power
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
VCP
CP
STATUS
REF_SEL
7
I
3.3 V CMOS
SYNC
8
I
Loop filter
LF
9
10, 24, 25,
30, 31, 36,
37, 43, 45
11
O
I
Loop filter
Power
BYPASS
VS
I
CLK
12
I
13
14
I
I
Differential
clock input
Differential
clock input
3.3 V CMOS
3.3 V CMOS
CLK
SCLK
CS
Description
Reference Monitor (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01B.
Lock Detect (Output). This pin has multiple selectable outputs; see Table 54,
Register 0x01A.
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.0 V.
Charge Pump (Output). Connects to external loop filter.
Status (Output). This pin has multiple selectable outputs; see Table 54, Register 0x017.
Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ
pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is also used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
Loop Filter (Input). Connects to VCO control voltage node internally. This pin has
31 pF of internal capacitance to ground, which may influence the loop filter design
for large loop bandwidths.
This pin is for bypassing the LDO to ground with a capacitor.
3.3 V Power Pins.
Along with CLK, this is the self-biased differential input for the clock distribution
section.
Along with CLK, this is the self-biased differential input for the clock distribution
section.
Serial Control Port Data Clock Signal.
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up
resistor.
Rev. A | Page 17 of 80
AD9517-4
Pin No.
15
16
17
18
21, 40
42
41
39
38
19
20
22
23
35
Input/
Output
O
I/O
I
I
I
O
O
O
O
O
O
O
O
O
34
O
33
O
32
O
26
O
27
O
28
O
29
O
44
O
46
O
47
I
48
I
EPAD
Pin Type
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
3.3 V CMOS
Power
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
Current set
resistor
Current set
resistor
Reference
input
Reference
input
GND
Mnemonic
SDO
SDIO
RESET
PD
VS_LVPECL
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4 (OUT4A)
RSET
Description
Serial Control Port Unidirectional Serial Data Out.
Serial Control Port Bidirectional Serial Data In/Out.
Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVPECL Output; One Side of a Differential LVPECL Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
LVDS/CMOS Output; One Side of a Differential LVDS Output
or a Single-Ended CMOS Output.
Resistor connected here sets internal bias currents. Nominal value = 4.12 kΩ.
CPRSET
Resistor connected here sets CP current range. Nominal value = 5.1 kΩ.
REFIN (REF2)
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF2.
Along with REFIN, this is the self-biased differential input for the PLL reference.
Alternatively, this pin is a single-ended input for REF1.
Ground. The external paddle on the bottom of the package must be connected to
ground for proper operation.
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
REFIN (REF1)
GND
Rev. A | Page 18 of 80
AD9517-4
TYPICAL PERFORMANCE CHARACTERISTICS
240
50
2 CHANNELS—4 LVPECL
220
45
40
KVCO (MHz/V)
CURRENT (mA)
200
180
2 CHANNELS—2 LVPECL
160
35
30
140
0
500
1000
1500
2000
2500
3000
FREQUENCY (MHz)
20
1.45
06428-007
100
1.55
1.75
VCO FREQUENCY (GHz)
Figure 7. Current vs. Frequency, Direct to Output, LVPECL Outputs
Figure 10. VCO KVCO vs. Frequency
180
5.0
4.5
2 CHANNELS—4 LVDS
CURRENT FROM CP PIN (mA)
160
CURRENT (mA)
1.65
06428-200
25
1 CHANNEL—1 LVPECL
120
140
2 CHANNELS—2 LVDS
120
100
4.0
3.5
PUMP DOWN
PUMP UP
3.0
2.5
2.0
1.5
1.0
0.5
1 CHANNEL—1 LVDS
200
400
600
800
FREQUENCY (MHz)
0
0
1.0
1.5
2.0
2.5
3.0
VOLTAGE ON CP PIN (V)
Figure 8. Current vs. Frequency—LVDS Outputs
Figure 11. Charge Pump Characteristics @ VCP = 3.3 V
240
5.0
4.5
CURRENT FROM CP PIN (mA)
220
200
2 CHANNELS—8 CMOS
180
2 CHANNELS—2 CMOS
160
140
120
1 CHANNEL—2 CMOS
100
4.0
3.5
PUMP DOWN
PUMP UP
3.0
2.5
2.0
1.5
1.0
0.5
80
0
50
100
150
200
FREQUENCY (MHz)
250
Figure 9. Current vs. Frequency—CMOS Outputs
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VOLTAGE ON CP PIN (V)
Figure 12. Charge Pump Characteristics @ VCP = 5.0 V
Rev. A | Page 19 of 80
5.0
06428-012
1 CHANNEL—1 CMOS
06428-009
CURRENT (mA)
0.5
06428-011
0
06428-008
80
–140
10
–145
–10
RELATIVE POWER (dB)
0
–150
–155
–160
–20
–30
–40
–50
–60
–70
–80
–90
–165
–170
0.1
1
10
100
–110
PFD FREQUENCY (MHz)
CENTER 122.88MHz
5MHz/DIV
SPAN 50MHz
06428-202
–100
06428-013
PFD PHASE NOISE REFERRED TO PFD INPUT
(dBc/Hz)
AD9517-4
Figure 16. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;
LBW = 135 kHz; ICP = 3 mA; FVCO = 1.475 GHz
Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
–210
10
–212
–10
RELATIVE POWER (dB)
PLL FIGURE OF MERIT (dBc/Hz)
0
–214
–216
–218
–220
–20
–30
–40
–50
–60
–70
–80
–90
–222
0
0.5
1.0
1.5
2.0
2.5
SLEW RATE (V/ns)
–110
06428-136
–224
CENTER 122.88MHz
100kHz/DIV
SPAN 1MHz
06428-203
–100
Figure 17. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz;
LBW = 135 kHz; ICP = 3 mA; FVCO = 1.475 GHz
Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN
2.1
10
1.9
–10
RELATIVE POWER (dB)
1.7
1.5
1.3
–20
–30
–40
–50
–60
–70
–80
–90
1.1
0.9
1.45
1.50
1.55
1.60
1.65
1.70
1.75
FREQUENCY (GHz)
1.80
–110
CENTER 122.88MHz
100kHz/DIV
SPAN 1MHz
Figure 18. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz;
LBW = 135 kHz; ICP = 3 mA; FVCO = 1.475 GHz
Figure 15. VCO Tuning Voltage vs. Frequency
Rev. A | Page 20 of 80
06428-204
–100
06428-201
VCO TUNING VOLTAGE (V)
0
AD9517-4
0.4
0.6
DIFFERENTIAL OUTPUT (V)
DIFFERENTIAL OUTPUT (V)
1.0
0.2
–0.2
0.2
0
–0.2
–0.6
5
10
15
20
25
TIME (ns)
–0.4
0
1
06428-017
0
06428-014
–1.0
2
TIME (ns)
Figure 19. LVPECL Output (Differential) @ 100 MHz
Figure 22. LVDS Output (Differential) @ 800 MHz
1.0
OUTPUT (V)
DIFFERENTIAL OUTPUT (V)
2.8
0.6
0.2
–0.2
1.8
0.8
0
1
2
TIME (ns)
06428-015
–0.2
–1.0
0
20
40
80
60
100
TIME (ns)
Figure 20. LVPECL Output (Differential) @ 1600 MHz
06428-018
–0.6
Figure 23. CMOS Output @ 25 MHz
0.4
OUTPUT (V)
0.2
0
1.8
0.8
–0.2
–0.4
0
5
10
15
20
TIME (ns)
25
Figure 21. LVDS Output (Differential) @ 100 MHz
0
2
4
6
8
TIME (ns)
Figure 24. CMOS Output @ 250 MHz
Rev. A | Page 21 of 80
10
12
06428-019
–0.2
06428-016
DIFFERENTIAL OUTPUT (V)
2.8
AD9517-4
1600
–80
1400
PHASE NOISE (dBc/Hz)
DIFFERENTIAL SWING (mV p-p)
–90
1200
1000
–100
–110
–120
–130
0
1
2
3
FREQUENCY (GHz)
–150
10k
06428-020
800
Figure 25. LVPECL Differential Swing vs. Frequency
100k
1M
10M
100M
FREQUENCY (Hz)
06428-205
–140
Figure 28. Internal VCO Phase Noise (Absolute) Direct to LVPECL @1800 MHz
–80
–90
PHASE NOISE (dBc/Hz)
DIFFERENTIAL SWING (mV p-p)
700
600
–100
–110
–120
–130
0
100
200
300
400
500
600
700
800
FREQUENCY (MHz)
–150
10k
06428-021
500
Figure 26. LVDS Differential Swing vs. Frequency
1M
10M
100M
FREQUENCY (Hz)
Figure 29. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 1625 MHz
–80
CL = 2pF
3
–90
CL = 10pF
PHASE NOISE (dBc/Hz)
OUTPUT SWING (V)
10k
06428-206
–140
2
CL = 20pF
1
–100
–110
–120
–130
0
100
200
300
400
500
600
OUTPUT FREQUENCY (MHz)
Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load
–150
10k
100k
1M
FREQUENCY (Hz)
10M
100M
06428-207
0
06428-133
–140
Figure 30. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 1450 MHz
Rev. A | Page 22 of 80
AD9517-4
–120
–110
–125
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–120
–130
–135
–140
–145
–150
–130
–140
–150
100
1k
10k
100k
1M
10M
–160
10
06428-026
100M
FREQUENCY (Hz)
–120
–110
PHASE NOISE (dBc/Hz)
100k
1M
10M
100M
–130
–140
–120
–130
–140
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–150
10
06428-027
100
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
06428-130
PHASE NOISE (dBc/Hz)
–100
–150
Figure 35. Phase Noise (Additive) LVDS @ 800 MHz, Divide-by-2
Figure 32. Phase Noise (Additive) LVPECL @ 200 MHz, Divide-by-5
–120
–110
–130
PHASE NOISE (dBc/Hz)
–100
–120
–130
–140
–150
–160
–140
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
06428-128
PHASE NOISE (dBc/Hz)
10k
Figure 34. Phase Noise (Additive) LVDS @ 200 MHz, Divide-by-1
–110
–150
10
1k
FREQUENCY (Hz)
Figure 31. Phase Noise (Additive) LVPECL @ 245.76 MHz, Divide-by-1
–160
10
100
–170
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 36. Phase Noise (Additive) CMOS @ 50 MHz, Divide-by-20
Figure 33. Phase Noise (Additive) LVPECL @ 1600 MHz, Divide-by-1
Rev. A | Page 23 of 80
06428-131
–160
10
06428-142
–155
AD9517-4
–100
–90
–100
PHASE NOISE (dBc/Hz)
–120
–130
–140
–150
–130
–140
1k
10k
100k
1M
10M
100M
–160
1k
Figure 37. Phase Noise (Additive) CMOS @ 250 MHz, Divide-by-4
–130
PHASE NOISE (dBc/Hz)
–130
–140
1M
FREQUENCY (Hz)
10M
100M
10M
100M
Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO @
1.475 GHz; PFD = 15.36 MHz; LBW = 135 kHz; LVPECL Output = 122.88 MHz
–140
–150
–160
1k
06428-208
–150
100k
1M
Figure 39. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 1.556 GHz;
PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz
–120
10k
100k
FREQUENCY (Hz)
–120
–160
1k
10k
06428-209
100
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
–120
–150
06428-132
–160
10
–110
10k
100k
1M
FREQUENCY (Hz)
10M
100M
06428-140
PHASE NOISE (dBc/Hz)
–110
Figure 40. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @
245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz
Rev. A | Page 24 of 80
AD9517-4
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as being Gaussian (normal)
in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings
varies. In a square wave, the time jitter is a displacement of the
edges from their ideal (regular) times of occurrence. In both
cases, the variations in timing from the ideal are the time jitter.
Because these variations are random in nature, the time jitter is
specified in units of seconds root mean square (rms) or 1 sigma
of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured. The
phase noise of any external oscillators or clock sources is
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise. When there are multiple contributors to phase
noise, the total is the square root of the sum of squares of the
individual contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is
attributable to the device or subsystem being measured. The
time jitter of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
impacts the total system time jitter when used in conjunction with
the various oscillators and clock sources, each of which
contributes its own time jitter to the total. In many cases, the
time jitter of the external oscillators and clock sources dominates
the system time jitter.
Rev. A | Page 25 of 80
AD9517-4
DETAILED BLOCK DIAGRAM
REF_ SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
REF2
R
DIVIDER
PROGRAMMABLE
R DELAY
STATUS
REFIN (REF1)
VCO STATUS
REFIN (REF2)
BYPASS
PLL
REFERENCE
LOCK
DETECT
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4 (OUT4A)
ΔT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT4 (OUT4B)
LVDS/CMOS
OUT5 (OUT5A)
ΔT
OUT5 (OUT5B)
OUT6 (OUT6A)
ΔT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
ΔT
AD9517-4
Figure 41. Detailed Block Diagram
Rev. A | Page 26 of 80
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
06428-002
SCLK
SDIO
SDO
CS
OUT2
LVPECL
AD9517-4
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
Table 21. Default Settings of Some PLL Registers
The AD9517 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 52 and Table 53 through Table 62). Each section or
function must be individually programmed by setting the
appropriate bits in the corresponding control register or registers.
Register
0x010[1:0] = 01b
0x1E0[2:0] = 010b
0x1E1[0] = 0b
0x1E1[1] = 0b
High Frequency Clock Distribution—CLK or External
VCO > 1600 MHz
When using the internal PLL with an external VCO, the PLL
must be turned on.
The AD9517 power-up default configuration has the PLL
powered off and the routing of the input set so that the
CLK/CLK input is connected to the distribution section
through the VCO divider (divide-by-2/ divide-by-3/divide-by-4/
divide-by-5/divide-by-6). This is a distribution-only mode that
allows for an external input up to 2400 MHz (see Table 3). The
maximum frequency that can be applied to the channel dividers
is 1600 MHz; therefore, higher input frequencies must be
divided down before reaching the channel dividers. This input
routing can also be used for lower input frequencies, but the
minimum divide is 2 before the channel dividers.
When the PLL is enabled, this routing also allows the use of the
PLL with an external VCO or VCXO with a frequency of less than
2400 MHz. In this configuration, the internal VCO is not used
and is powered off. The external VCO/VCXO feeds directly into
the prescaler.
The register settings shown in Table 21 are the default values of
these registers at power-up or after a reset operation. If the
contents of the registers are altered by prior programming after
power-up or reset, these registers can also be set intentionally to
these values.
Function
PLL asynchronous power-down (PLL off ).
Set VCO divider = 4.
Use the VCO divider.
CLK selected as the source.
Table 22. Settings When Using an External VCO
Register
0x010[1:0] = 00b
0x010 to 0x01E
0x1E1[1] = 0b
Function
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP,
according to the intended loop configuration.
CLK selected as the source
An external VCO requires an external loop filter that must be
connected between CP and the tuning pin of the VCO. This
loop filter determines the loop bandwidth and stability of the
PLL. Make sure to select the proper PFD polarity for the VCO
being used.
Table 23. Setting the PFD Polarity
Register
0x010[7] = 0b
0x010[7] = 1b
After the appropriate register values are programmed,
Register 0x232 must be set to 0x01 for the values to take effect.
Rev. A | Page 27 of 80
Function
PFD polarity positive (higher control voltage
produces higher frequency).
PFD polarity negative (higher control
voltage produces lower frequency).
AD9517-4
REF_ SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
REF2
R
DIVIDER
PROGRAMMABLE
R DELAY
STATUS
REFIN (REF1)
VCO STATUS
REFIN (REF2)
BYPASS
PLL
REFERENCE
LOCK
DETECT
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4 (OUT4A)
ΔT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT4 (OUT4B)
LVDS/CMOS
OUT5 (OUT5A)
ΔT
OUT5 (OUT5B)
OUT6 (OUT6A)
ΔT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
ΔT
AD9517-4
Figure 42. High Frequency Clock Distribution or External VCO > 1600 MHz
Rev. A | Page 28 of 80
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
06428-029
SCLK
SDIO
SDO
CS
OUT2
LVPECL
AD9517-4
REF_ SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
REF2
R
DIVIDER
PROGRAMMABLE
R DELAY
STATUS
REFIN (REF1)
VCO STATUS
REFIN (REF2)
BYPASS
PLL
REFERENCE
LOCK
DETECT
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
PROGRAMMABLE
N DELAY
A/B
COUNTERS
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4 (OUT4A)
ΔT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT4 (OUT4B)
LVDS/CMOS
OUT5 (OUT5A)
ΔT
OUT5 (OUT5B)
OUT6 (OUT6A)
ΔT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
ΔT
AD9517-4
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
06428-030
SCLK
SDIO
SDO
CS
OUT2
LVPECL
Figure 43. Internal VCO and Clock Distribution
Internal VCO and Clock Distribution
Table 24. Settings When Using Internal VCO
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the channel
dividers does not exceed its specified maximum frequency
(1600 MHz, see Table 3). The internal PLL uses an external loop
filter to set the loop bandwidth. The external loop filter is also
crucial to the loop stability.
Register
0x010[1:0] = 00b
0x010 to 0x1E
0x018[0] = 0,
0x232[0] = 1
When using the internal VCO, it is necessary to calibrate the
VCO (Register 0x018[0]) to ensure optimal performance.
0x1E0[2:0]
For internal VCO and clock distribution applications, the
register settings shown in Table 24 should be used.
0x1E1[0] = 0b
0x1E1[1] = 1b
0x018[0] = 1,
0x232[0] = 1
Rev. A | Page 29 of 80
Function
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP
according to the intended loop configuration.
Reset VCO calibration (this does not have to
be done first time after power-up, but must
be done subsequently).
VCO divider set to divide-by-2, divide-by-3,
divide-by-4, divide-by-5, and divide-by-6.
Use the VCO divider as source for
distribution section.
VCO selected as the source.
Initiate VCO calibration.
AD9517-4
REF_ SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
STATUS
REF2
R
DIVIDER
PROGRAMMABLE
R DELAY
STATUS
REFIN (REF1)
VCO STATUS
REFIN (REF2)
BYPASS
PLL
REFERENCE
LOCK
DETECT
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
HOLD
CHARGE
PUMP
CP
N DIVIDER
LF
VCO
STATUS
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
CLK
1
0
OUT0
DIVIDE BY
1 TO 32
PD
SYNC
OUT0
LVPECL
OUT1
DIGITAL
LOGIC
OUT1
RESET
OUT2
DIVIDE BY
1 TO 32
OUT3
SERIAL
CONTROL
PORT
OUT3
OUT4 (OUT4A)
ΔT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
OUT4 (OUT4B)
LVDS/CMOS
OUT5 (OUT5A)
ΔT
OUT5 (OUT5B)
OUT6 (OUT6A)
ΔT
DIVIDE BY
1 TO 32
DIVIDE BY
1 TO 32
LVDS/CMOS
ΔT
AD9517-4
Figure 44. Clock Distribution or External VCO < 1600 MHz
Rev. A | Page 30 of 80
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
06428-028
SCLK
SDIO
SDO
CS
OUT2
LVPECL
AD9517-4
Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external
VCO/VCXO is 1600 MHz section
only in that the VCO divider (divide-by-2, divide-by-3, divideby-4, divide-by-5, and divide-by-6) is bypassed. This limits the
frequency of the clock source to B not allowed).
P = 32, A = 22, B = 84.
P = 16 is also permitted.
AD9517-4
DIGITAL LOCK DETECT (DLD)
By selecting the proper output through the mux on each pin,
the DLD function can be made available at the LD, STATUS,
and REFMON pins. The DLD circuit indicates a lock when the
time difference of the rising edges at the PFD inputs is less than
a specified value (the lock threshold). The loss of a lock is
indicated when the time difference exceeds a specified value
(the unlock threshold). Note that the unlock threshold is wider
than the lock threshold, which allows some phase error in
excess of the lock window to occur without chattering on the
lock indicator.
The lock detect window timing depends on three settings:
the digital lock detect window bit (Register 0x018[4]), the
antibacklash pulse width setting (Register 0x017[1:0], see Table 2),
and the lock detect counter (Register 0x018[6:5]). A lock is not
indicated until there is a programmable number of consecutive
PFD cycles with a time difference that is less than the lock detect
threshold. The lock detect circuit continues to indicate a lock
until a time difference greater than the unlock threshold occurs
on a single subsequent cycle. For the lock detect to work properly,
the period of the PFD frequency must be greater than the unlock
threshold. The number of consecutive PFD cycles required for
lock is programmable (Register 0x018[6:5]).
detect function is set when it is selected as the output from the
LD pin control (Register 0x01A[5:0]).
The current source lock detect provides a current of 110 μA
when DLD is true, and it shorts to ground when DLD is false.
If a capacitor is connected to the LD pin, it charges at a rate that
is determined by the current source during the DLD true time
but is discharged nearly instantly when DLD is false. By monitoring
the voltage at the LD pin (top of the capacitor), it is possible to
get a logic high level only after the DLD has been true for a
sufficiently long time. Any momentary DLD false resets the
charging. By selecting a properly sized capacitor, it is possible to
delay a lock detect indication until the PLL is stably locked and
the lock detect does not chatter.
The voltage on the capacitor can be sensed by an external
comparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (Register 0x01B[4:0]) or the STATUS pin control
(Register 0x017[7:2]) as an active high signal. It is also available
as an active low signal (REFMON, Register 0x01B[4:0] and
STATUS, Register 0x017[7:2]). The internal LD pin comparator
trip point and hysteresis are listed in Table 16.
AD9517-4
110µA
Analog Lock Detect (ALD)
DLD
The AD9517 provides an ALD function that can be selected for
use at the LD pin. There are two versions of ALD, as follows:
•
The analog lock detect function requires an R-C filter to
provide a logic level indicating lock/unlock.
LD PIN
COMPARATOR
REFMON
OR
STATUS
Figure 50. Current Source Lock Detect
External VCXO/VCO Clock Input (CLK/CLK)
CLK is a differential input that can be used as an input to drive
the AD9517 clock distribution section. This input can receive
up to 2.4 GHz. The pins are internally self-biased, and the input
signal should be ac-coupled via capacitors.
CLOCK INPUT
STAGE
VS = 3.3V
AD9517-4
R2
LD
VS
VOUT
CLK
C
CLK
06428-067
ALD
R1
06428-068
N-channel open-drain lock detect. This signal requires a
pull-up resistor to the positive supply, VS. The output is
normally high with short, low-going pulses. Lock is indicated
by the minimum duty cycle of the low-going pulses.
P-channel open-drain lock detect. This signal requires a
pull-down resistor to GND. The output is normally low
with short, high-going pulses. Lock is indicated by the
minimum duty cycle of the high-going pulses.
C
2.5kΩ
2.5kΩ
5kΩ
Figure 49. Example of Analog Lock Detect Filter
Using an N-Channel Open-Drain Driver
5kΩ
Current Source Digital Lock Detect (DLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This made is possible by using
the current source lock detect function. The current source lock
06428-032
•
VOUT
LD
Figure 51. CLK Equivalent Input Circuit
The CLK/CLK input can be used either as a distribution-only
input (with the PLL off), or as a feedback input for an external
VCO/VCXO using the internal PLL when the internal VCO is
not used. The CLK/CLK input can be used for frequencies up
to 2.4 GHz.
Rev. A | Page 36 of 80
AD9517-4
Holdover
Automatic/Internal Holdover Mode
The AD9517 PLL has a holdover function. Holdover is
implemented by putting the charge pump into a high
impedance state. This is useful when the PLL reference clock is
lost. Holdover mode allows the VCO to maintain a relatively
constant frequency even though there is no reference clock.
Without this function, the charge pump is placed into a
constant pump-up or pump-down state, resulting in a massive
VCO frequency shift. Because the charge pump is placed in a
high impedance state, any leakage that occurs at the charge
pump output or the VCO tuning node causes a drift of the VCO
frequency. This can be mitigated by using a loop filter that
contains a large capacitive component because this drift is
limited by the current leakage induced slew rate (ILEAK/C) of the
VCO control voltage. For most applications, the frequency
accuracy is sufficient for 3 sec to 5 sec.
When enabled, this function automatically puts the charge pump
into a high impedance state when the loop loses lock. The
assumption is that the only reason the loop loses lock is due to
the PLL losing the reference clock; therefore, the holdover function
puts the charge pump into a high impedance state to maintain
the VCO frequency as close as possible to the original frequency
before the reference clock disappears. A flow chart of the internal/
automatic holdover function operation is shown in Figure 52.
PLL ENABLED
DLD == LOW
Both a manual holdover, using the SYNC pin, and an automatic
holdover mode are provided. To use either function, the
holdover function must be enabled (Register 0x01D[0] and
Register 0x01D[2]).
Note that the VCO cannot be calibrated with the holdover
enabled because the holdover resets the N divider during
calibration, which prevents proper calibration. Disable holdover
before issuing a VCO calibration.
LOOP OUT OF LOCK. DIGITAL LOCK
DETECT SIGNAL GOES LOW WHEN THE
LOOP LEAVES LOCK AS DETERMINED
BY THE PHASE DIFFERENCE AT THE
INPUT OF THE PFD.
NO
YES
NO
ANALOG LOCK DETECT PIN INDICATES
LOCK WAS PREVIOUSLY ACHIEVED.
(0x1D[3] = 1: USE LD PIN VOLTAGE
WITH HOLDOVER.
0x1D[3] = 0: IGNORE LD PIN VOLTAGE,
TREAT LD PIN AS ALWAYS HIGH.)
WAS
LD PIN == HIGH
WHEN DLD WENT
LOW?
YES
Manual Holdover Mode
YES
NO
CHARGE PUMP REMAINS HIGH
IMPEDANCE UNTIL THE REFERENCE
HAS RETURNED.
REFERENCE
EDGE AT PFD?
YES
YES
TAKE CHARGE PUMP OUT OF
HIGH IMPEDANCE. PLL CAN
NOW RESETTLE.
RELEASE
CHARGE PUMP
HIGH IMPEDANCE
The B-counter (in the N divider) is reset synchronously with
the charge pump leaving the high impedance state on the
reference path PFD event. This helps align the edges out of the
R and N dividers for faster settling of the PLL. Because the
prescaler is not reset, this feature works best when the B and R
numbers are close because this results in a smaller phase
difference for the loop to settle out.
When using this mode, set the channel dividers to ignore the
SYNC pin (at least after an initial SYNC event). If the dividers
are not set to ignore the SYNC pin, each time SYNC is taken low
to put the part into holdover, the distribution outputs turn off.
CHARGE PUMP IS MADE
HIGH IMPEDANCE.
PLL COUNTERS CONTINUE
OPERATING NORMALLY.
HIGH IMPEDANCE
CHARGE PUMP
YES
NO
DLD == HIGH
WAIT FOR DLD TO GO HIGH. THIS TAKES
5 TO 255 CYCLES (PROGRAMMING OF
THE DLD DELAY COUNTER) WITH THE
REFERENCE AND FEEDBACK CLOCKS
INSIDE THE LOCK WINDOW AT THE PFD.
THIS ENSURES THAT THE HOLDOVER
FUNCTION WAITS FOR THE PLL TO SETTLE
AND LOCK BEFORE THE HOLDOVER
FUNCTION CAN BE RETRIGGERED.
06428-069
A manual holdover mode can be enabled that allows the user to
place the charge pump into a high impedance state when the
SYNC pin is asserted low. This operation is edge sensitive, not
level sensitive. The charge pump enters a high impedance state
immediately. To take the charge pump out of a high impedance
state, take the SYNC pin high. The charge pump then leaves
high impedance state synchronously with the next PFD rising
edge from the reference clock. This prevents extraneous charge
pump events from occurring during the time between SYNC
going high and the next PFD event. This also means that the
charge pump stays in a high impedance state as long as there is
no reference clock present.
Figure 52. Flow Chart of Automatic/Internal Holdover Mode
The holdover function senses the logic level of the LD pin as a
condition to enter holdover. The signal at LD can be from the
DLD, ALD, or current source LD mode. It is possible to disable
the LD comparator (Register 0x01D[3]), which causes the holdover
function to always sense LD as high.
Rev. A | Page 37 of 80
AD9517-4
If DLD is used, it is possible for the DLD signal to chatter some
while the PLL is reacquiring lock. The holdover function may
retrigger, thereby preventing the holdover mode from
terminating. Use of the current source lock detect mode is
recommended to avoid this situation (see the Current Source
Digital Lock Detect section).
For example, to use automatic holdover with the following:
Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
•
•
•
•
As in the external holdover mode, the B counter (in the N
divider) is reset synchronously with the charge pump leaving
the high impedance state on the reference path PFD event. This
helps align the edges out of the R and N dividers for faster
settling of the PLL and to reduce frequency errors during
settling. Because the prescaler is not reset, this feature works
best when the B and R numbers are close because this results in
a smaller phase difference for the loop to settle out.
After leaving holdover, the loop then reacquires lock and the
LD pin must charge (if Register 0x01D[3] = 1) before it can
re-enter holdover (CP high impedance).
The holdover function always responds to the state of the
currently selected reference (Register 0x01C). If the loop loses
lock during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect the internal/automatic holdover
function:
•
•
•
•
•
•
Register 0x018[6:5]. Lock detect counter. This changes how
many consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate lock.
This impacts the time required before the LD pin can begin
to charge as well as the delay from the end of a holdover event
until the holdover function can be re-engaged.
Register 0x018[3]. Disable digital lock detect. This bit must
be set to a 0 to enable the DLD circuit. Internal/automatic
holdover does not operate correctly without the DLD function
enabled.
Register 0x01A[5:0]. Lock detect pin output select. Set this
to 000100b to put it in the current source lock detect mode
if using the LD pin comparator. Load the LD pin with a
capacitor of an appropriate value.
Register 0x01D[3]. Enable LD pin comparator; 1 = enable;
0 = disable. When disabled, the holdover function always
senses the LD pin as high.
Register 0x01D[1]. Enable external holdover control.
Register 0x01D[0] and Register 0x01D[2]. Holdover
function enable. If holdover is disabled, both external
and internal/automatic holdover are disabled.
•
•
•
Automatic reference switchover, prefer REF1
Digital lock detect: five PFD cycles, high range window
Automatic holdover using the LD pin comparator
Set the following registers (in addition to the normal PLL registers):
•
•
•
•
•
•
•
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; lock detect window = high range.
Register 0x018[3] = 0b; DLD normal operation.
Register 0x01A[5:0] = 000100b; current source lock detect
mode.
Register 0x01C[4] = 1b; automatic reference switchover
enabled.
Register 0x01C[3] = 0b; prefer REF1.
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[2]=1b; enable the holdover function.
Register 0x01D[1] = 0b; use internal/automatic holdover
mode.
Register 0x01D[0] = 1b; enable the holdover function.
Frequency Status Monitors
The AD9517 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is shown
in Figure 53.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 16). The reference frequency
monitor thresholds are selected in Register 0x01F.
Rev. A | Page 38 of 80
AD9517-4
REF_SEL
VS
GND
RSET
REFMON
CPRSET VCP
DISTRIBUTION
REFERENCE
REFERENCE
SWITCHOVER
LD
REF1
PLL
REFERENCE
REF2
LOCK
DETECT
STATUS
R
DIVIDER
PROGRAMMABLE
R DELAY
STATUS
REFIN (REF1)
REFIN (REF2)
N DIVIDER
BYPASS
LOW DROPOUT
REGULATOR (LDO)
P, P + 1
PRESCALER
A/B
COUNTERS
LF
PHASE
FREQUENCY
DETECTOR
PROGRAMMABLE
N DELAY
HOLD
CHARGE
PUMP
CP
VCO STATUS
VCO
STATUS
0
DIVIDE BY
2, 3, 4, 5, OR 6
CLK
1
1
06428-070
CLK
0
Figure 53. Reference and VCO Status Monitors
VCO Calibration
The AD9517 on-chip VCO must be calibrated to ensure proper
operation over process and temperature. The VCO calibration
is controlled by a calibration controller running off of a divided
REFIN clock. The calibration requires that the PLL be set up
properly to lock the PLL loop and that the REFIN clock be present.
During the first initialization after a power-up or a reset of the
AD9517, a VCO calibration sequence is initiated by setting
Register 0x018[0] = 1b. This can be done as part of the initial
setup before executing update registers (Register 0x232[0] = 1b).
Subsequent to the initial setup, a VCO calibration sequence is
initiated by resetting Register 0x018[0] = 0b, executing an update
registers operation, setting Register 0x018[0] = 1b, and executing
another update registers operation. The readback bit (Register
0x1F[6]) indicates when a VCO calibration is finished by returning
a logic true (that is, 1b).
The sequence of operations for the VCO calibration is:
•
•
•
•
•
•
•
•
Program the PLL registers to the proper values for the PLL
loop. Note that that automatic holdover mode must be
disabled, and the VCO divider must not be set to “Static.”
Ensure that the input reference signal is present.
For the initial setting of the registers after a power-up or reset,
initiate VCO calibration by setting Register 0x018[0] = 1b.
Subsequently, whenever a calibration is desired, set
Register 0x018[0] = 0b, update registers; and set Register
0x018[0] = 1b, update registers.
A SYNC operation is initiated internally, causing the
outputs to go to a static state determined by normal SYNC
function operation.
VCO calibrates to the desired setting for the requested
VCO frequency.
Internally, the SYNC signal is released, allowing outputs to
continue clocking.
PLL loop is closed.
PLL locks.
A SYNC is executed during the VCO calibration; therefore, the
outputs of the AD9517 are held static during the calibration,
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 54
(Register 0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
fCAL_CLOCK = fREFIN/(R × cal_div)
where:
fREFIN is the frequency of the REFIN signal.
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
Table 29. Example Time to Complete a VCO Calibration
with Different fREFIN Frequencies
fREFIN (MHz)
100
10
10
Rev. A | Page 39 of 80
R Divider
1
10
100
PFD
100 MHz
1 MHz
100 kHz
Time to Calibrate VCO
88 μs
8.8 ms
88 ms
AD9517-4
VCO calibration must be manually initiated. This allows for
flexibility in deciding what order to program registers and when
to initiate a calibration, instead of having it happen every time
certain PLL registers have their values change. For example, this
allows for the VCO frequency to be changed by small amounts
without having an automatic calibration occur each time; this
should be done with caution and only when the user knows the
VCO control voltage is not going to exceed the nominal best
performance limits. For example, a few 100 kHz steps are fine, but
a few MHz might not be. In addition, because the calibration
procedure results in rapid changes in the VCO frequency, the
distribution section is automatically placed in SYNC until the
calibration is finished. Therefore, this temporary loss of outputs
must be expected.
A VCO calibration should be initiated under the following
conditions:
•
•
After changing any of the PLL R, P, B, and A divider
settings, or after a change in the PLL reference clock
frequency. This, in effect, means any time a PLL register
or reference clock is changed such that a different VCO
frequency results.
Whenever system calibration is desired. The VCO is
designed to operate properly over extremes of temperatures
even when it is first calibrated at the opposite extreme.
However, a VCO calibration can be initiated at any time,
if desired.
CLOCK DISTRIBUTION
A clock channel consists of a pair (or double pair, in the case of
CMOS) of outputs that share a common divider. A clock output
consists of the drivers that connect to the output pins. The clock
outputs have either LVPECL or LVDS/CMOS signal levels at
the pins.
The AD9517 has four clock channels: two channels are LVPECL
(four outputs); two channels are LVDS/CMOS (up to four LVDS
outputs or up to eight CMOS outputs).
Each channel has its own programmable divider that divides
the clock frequency applied to its input. The LVPECL channel
dividers can divide by any integer from 2 to 32, or the divider
can be bypassed to achieve a divide by one. Each LVDS/CMOS
channel divider contains two of these divider blocks in a
cascaded configuration. The total division of the channel is the
product of the divide value of the cascaded dividers. This allows
divide values of (1 to 32) × (1 to 32), or up to 1024 (notice that
this is not all values from 1 to 1024 but only the set of numbers
that are the product of the two dividers).
Because the internal VCO frequency is above the maximum
channel divider input frequency (1600 MHz), the VCO divider
must be used after the on-chip VCO. The VCO divider can be
set to divide by 2, 3, 4, 5, or 6. External clock signals connected
to the CLK input also require the VCO divider if the frequency
of the signal is greater than 1600 MHz.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for
N + 1 input clock cycles and low for M + 1 input clock cycles
(where D = N + M + 2). For example, a divide-by-5 can be high
for one divider input cycle and low for four cycles, or a divideby-5 can be high for three divider input cycles and low for two
cycles. Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 31 input clock cycles. The divider
outputs can also be set to start high or to start low.
Internal VCO or External CLK as Clock Source
The clock distribution of the AD9517 has two clock input
sources: an internal VCO or an external clock connected to the
CLK/CLK pins. Either the internal VCO or CLK must be
chosen as the source of the clock signal to distribute. When the
internal VCO is selected as the source, the VCO divider must be
used. When CLK is selected as the source, it is not necessary to
use the VCO divider if the CLK frequency is less than the
maximum channel divider input frequency (1600 MHz);
otherwise, the VCO divider must be used to reduce the
frequency to one acceptable by the channel dividers. Table 30
shows how the VCO, CLK, and VCO divider are selected.
Register 0x1E1[1:0] selects the channel divider source and
determines whether the VCO divider is used. It is not possible
to select the VCO without using the VCO divider.
Table 30. Selecting VCO or CLK as Source for Channel
Divider, and Whether VCO Divider Is Used
Register 0x1E1
1
0
0
0
0
1
1
0
1
1
Channel Divider Source
CLK
CLK
VCO
Not allowed
VCO Divider
Used
Not used
Used
Not allowed
CLK or VCO Direct to LVPECL Outputs
It is possible to connect either the internal VCO or the CLK
(whichever is selected as the input to the VCO divider) directly
to the LVPECL outputs, OUT0 to OUT3. This configuration
can pass frequencies up to the maximum frequency of the VCO
directly to the LVPECL outputs. The LVPECL outputs may not
be able to provide a full voltage swing at the highest frequencies.
Rev. A | Page 40 of 80
AD9517-4
To connect the LVPECL outputs directly to the internal VCO or
CLK, the VCO divider must be selected as the source to the
distribution section, even if no channel uses it.
Either the internal VCO or the CLK can be selected as the
source for the direct-to-output routing.
Table 31. Settings for Routing VCO Divider Input Directly
to LVPECL Outputs
Register Setting
0x1E1[1:0] = 00b
0x1E1[1:0] = 10b
0x192[1] = 1b
0x198[1] = 1b
Selection
CLK is the source; VCO divider selected
VCO is the source; VCO divider selected
Direct to output OUT0, OUT1
Direct to output OUT2, OUT3
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the VCO or CLK to the
output is the product of the VCO divider (2, 3, 4, 5, and 6) and
the division of the channel divider. Table 32 and Table 33
indicate how the frequency division for a channel is set. For the
LVPECL outputs, there is only one divider per channel. For the
LVDS/ CMOS outputs, there are two dividers (X.1, X.2)
cascaded per channel.
Table 32. Frequency Division for Divider 0 and Divider 1
CLK
or VCO
Selected
CLK/VCO
CLK/VCO
CLK/VCO
VCO
Divider
2 to 6
2 to 6
2 to 6
Channel
Divider
1 (bypassed)
1 (bypassed)
2 to 32
Direct to
Output
Yes
No
No
CLK
CLK
Not used
Not used
1 (bypassed)
2 to 32
No
No
Frequency
Division
1
(2 to 6) × (1)
(2 to 6) ×
(2 to 32)
1
2 to 32
Table 33. Frequency Division for Divider 2 and Divider 3
CLK
or VCO
Selected
CLK/VCO
VCO
Divider
2 to 6
CLK/VCO
2 to 6
CLK/VCO
2 to 6
Channel Divider
X.1
X.2
1
1
(bypassed) (bypassed)
2 to 32
1
(bypassed)
2 to 32
2 to 32
CLK
CLK
CLK
Not used
Not used
Not used
1
2 to 32
2 to 32
1
1
2 to 32
Frequency
Division
(2 to 6) ×
(1) × (1)
(2 to 6) ×
(2 to 32) × (1)
(2 to 6) ×
(2 to 32) ×
(2to 32)
1
(2 to 32) × (1)
2 to 32 ×
(2 to 32)
The channel dividers feeding the LVPECL output drivers
contain one 2-to-32 frequency divider. This divider provides for
division by 2 to 32. Division by 1 is accomplished by bypassing
the divider. The dividers also provide for a programmable duty
cycle, with optional duty-cycle correction when the divide ratio
is odd. A phase offset or delay in increments of the input clock
cycle is selectable. The channel dividers operate with a signal at
their inputs up to 1600 MHz. The features and settings of the
dividers are selected by programming the appropriate setup
and control registers (see Table 52 through Table 62).
VCO Divider
The VCO divider provides frequency division between the
internal VCO or the external CLK input and the clock
distribution channel dividers. The VCO divider can be set
to divide by 2, 3, 4, 5, or 6 (see Table 60, Register 0x1E0[2:0]).
Channel Dividers—LVPECL Outputs
Each pair of LVPECL outputs is driven by a channel divider.
There are two channel dividers (0, 1) driving four LVPECL
outputs (OUT0 to OUT3). Table 34 gives the register locations
used for setting the division and other functions of these
dividers. The division is set by the values of M and N. The
divider can be bypassed (equivalent to divide-by-1, divider circuit
is powered down) by setting the bypass bit. The duty-cycle
correction can be enabled or disabled according to the setting of
the DCCOFF bits.
Table 34. Setting DX for Divider 0 and Divider 11
Divider
0
1
1
Low Cycles
M
0x190[7:4]
0x196[7:4]
High Cycles
N
0x190[3:0]
0x196[3:0]
Bypass
0x191[7]
0x197[7]
DCCOFF
0x192[0]
0x198[0]
Note that the value stored in the register = # of cycles minus 1.
Channel Frequency Division (0, 1)
For each channel (where the channel number is x: 0, 1), the
frequency division, DX, is set by the values of M and N
(four bits each, representing Decimal 0 to Decimal 15), where
Number of Low Cycles = M + 1
Number of High Cycles = N + 1
The cycles are cycles of the clock signal currently routed to the
input of the channel dividers (VCO divider out or CLK).
When a divider is bypassed, DX = 1.
Otherwise, DX = (N + 1) + (M + 1) = N + M + 2. This allows
each channel divider to divide by any integer from 2 to 32.
Rev. A | Page 41 of 80
AD9517-4
Duty Cycle and Duty-Cycle Correction (0, 1)
Table 36. Duty Cycle with VCO Divider; Input Duty Cycle Is X%
The duty cycle of the clock signal at the output of a channel is a
result of some or all of the following conditions:
•
•
•
•
What are the M and N values for the channel?
Is the DCC enabled?
Is the VCO divider used?
What is the CLK input duty cycle? (The internal VCO has
a 50% duty cycle.)
VCO
Divider
Even
Odd = 3
Odd = 5
DX
N+M+2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
The DCC function is enabled by default for each channel divider.
However, the DCC function can be disabled individually for
each channel divider by setting the DCCOFF bit for that channel.
Even
Certain M and N values for a channel divider result in a non-50%
duty cycle. A non-50% duty cycle can also result with an even
division, if M ≠ N. The duty-cycle correction function
automatically corrects non-50% duty cycles at the channel
divider output to 50% duty cycle. Duty-cycle correction
requires the following channel divider conditions:
Odd = 3
Even
Odd = 3
Odd
Odd = 5
Even
Odd = 5
Odd
•
•
Odd
An even division must be set as M = N.
An odd division must be set as M = N + 1.
When not bypassed or corrected by the DCC function, the duty
cycle of each channel divider output is the numerical value of
(N + 1)/(N + M + 2), expressed as %.
N+M+2
1
Output Duty Cycle
DCCOFF = 1 DCCOFF = 0
50%
50%
Any
Even
50%
Odd
33.3%
50%
X%
Odd
40%
50%
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
50%; requires M = N
DX
Table 35. Duty Cycle with VCO Divider; Input Duty Cycle Is 50%
Even, Odd
DX
N+M+2
1 (divider
bypassed)
1 (divider
bypassed)
1 (divider
bypassed)
Even
Even, Odd
Odd
VCO
Divider
Even
Odd = 3
Odd = 5
50%; requires M = N + 1
33.3%
(1 + X%)/3
40%
(2 + X%)/5
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
(N + 1)/
(N + M + 2)
50%,
requires M = N
50%,
requires M = N + 1
50%,
requires M = N
(3N + 4 + X%)/(6N + 9),
requires M = N + 1
50%,
requires M = N
(5N + 7 + X%)/(10N +
15), requires M = N + 1
Table 37. Channel Divider Output Duty Cycle When the
VCO Divider Is Not Used
Input
Clock
Duty
Cycle
Any
The duty cycle at the output of the channel divider for various
configurations is shown in Table 35 to Table 37.
Output Duty Cycle
DCCOFF = 1
DCCOFF = 0
50%
50%
Output Duty Cycle
DCCOFF = 1
1 (divider
bypassed)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
(N + 1)/
(M + N + 2)
DCCOFF = 0
Same as input
duty cycle
50%, requires M = N
50%, requires
M=N+1
(N + 1 + X%)/(2 × N + 3),
requires M = N + 1
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Rev. A | Page 42 of 80
AD9517-4
Phase Offset or Coarse Time Delay (0, 1)
Channel Dividers—LVDS/CMOS Outputs
Each channel divider allows for a phase offset, or a coarse time
delay, to be programmed by setting register bits (see Table 38).
These settings determine the number of cycles (successive
rising edges) of the channel divider input frequency by which to
offset, or delay, the rising edge of the output of the divider. This
delay is with respect to a nondelayed output (that is, with a
phase offset of zero). The amount of the delay is set by five bits
loaded into the phase offset (PO) register plus the start high (SH)
bit for each channel divider. When the start high bit is set, the
delay is also affected by the number of low cycles (M)
programmed for the divider.
Channel Divider 2 and Channel Divider 3 each drive a pair of
LVDS outputs, giving four LVDS outputs (OUT4 to OUT7).
Alternatively, each of these LVDS differential outputs can be
configured individually as a pair (A and B) of CMOS singleended outputs, providing for up to eight CMOS outputs. By
default, the B output of each pair is off but can be turned on as
desired.
The SYNC function must be used to make phase offsets effective
(see the Synchronizing the Outputs—SYNC Function section).
Table 38. Setting Phase Offset and Division for Divider 0 and
Divider 1
Divider
0
1
Start
High (SH)
0x191[4]
0x197[4]
Phase
Offset (PO)
0x191[3:0]
0x197[3:0]
Low Cycles
M
0x190[7:4]
0x196[7:4]
High Cycles
N
0x190[3:0]
0x196[3:0]
Let
Δt = delay (in seconds).
Δc = delay (in cycles of clock signal at input to DX).
TX = period of the clock signal at the input of the divider, DX
(in seconds).
Φ = 16 × SH[4] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] + 1 × PO[0]
The channel divide-by is set as N = high cycles and M = low cycles.
Channel Divider 2 and Channel Divider 3 each consist of two
cascaded, 2 to 32, frequency dividers. The channel frequency
division is DX.1 × DX.2 or up to 1024. Divide-by-1 is achieved by
bypassing one or both of these dividers. Both of the dividers
also have DCC enabled by default, but this function can be
disabled, if desired, by setting the DCCOFF bit of the channel.
A coarse phase offset or delay is also programmable (see the
Phase Offset or Coarse Time Delay (Divider 2 and Divider 3)
section). The channel dividers operate up to 1600 MHz. The
features and settings of the dividers are selected by programming
the appropriate setup and control registers (see Table 52 and
Table 53 through Table 62).
Table 39. Setting Division (DX) for Divider 2, Divider 31
Divider
2
2.1
2.2
3
3.1
3.2
1
M
0x199[7:4]
0x19B[7:4]
0x19E[7:4]
0x1A0[7:4]
N
0x199[3:0]
0x19B[3:0]
0x19E[3:0]
0x1A0[3:0]
Bypass
0x19C[4]
0x19C[5]
0x1A1[4]
0x1A1[5]
DCCOFF
0x19D[0]
0x19D[0]
0x1A2[0]
0x1A2[0]
Note that the value stored in the register = # of cycles minus 1.
Case 1
Channel Frequency Division (Divider 2 and Divider 3)
For Φ ≤ 15:
Δt = Φ × TX
Δc = Δt/TX = Φ
The division for each channel divider is set by the bits in the
registers for the individual dividers (X.Y = 2.1, 2.2, 3.1, and 3.2)
Number of Low Cycles = MX.Y + 1
Case 2
Number of High Cycles = NX.Y + 1
For Φ ≥ 16:
Δt = (Φ − 16 + M + 1) × TX
Δc = Δt/TX
When both X.1 and X.2 are bypassed, DX = 1 × 1 = 1.
When only X.2 is bypassed, DX = (NX.1 + MX.1 + 2) × 1.
By giving each divider a different phase offset, output-to-output
delays can be set in increments of the channel divider input
clock cycle. Figure 54 shows the results of setting such a coarse
offset between outputs.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CHANNEL
DIVIDER INPUT
Tx
By cascading the dividers, channel division up to 1024 can be
obtained. However, not all integer value divisions from 1 to
1024 are obtainable; only the values that are the product of the
separate divisions of the two dividers (DX.1 × DX.2) can be realized.
If only one divider is needed when using Divider 2 and Divider 3,
use the first one (X.1) and bypass the second one (X.2). Do not
bypass X.1 and use X.2.
CHANNEL DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
SH = 0
DIVIDER 0 PO = 0
DIVIDER 1
When both X.1 and X.2 are not bypassed, DX = (NX.1 + MX.1 + 2) ×
(NX.2 + MX.2 + 2).
SH = 0
PO = 1
1 × Tx
2 × Tx
06428-071
SH = 0
DIVIDER 2 PO = 2
Figure 54. Effect of Coarse Phase Offset (or Delay)
Rev. A | Page 43 of 80
AD9517-4
Duty Cycle and Duty-Cycle Correction (Divider 2 and
Divider 3)
The same duty cycle and DCC considerations apply to Divider 2
and Divider 3 as to Divider 0 and Divider 1 (see the Duty Cycle
and Duty-Cycle Correction (0, 1) section); however, with these
channel dividers, the number of possible configurations is even
more complex.
Duty-cycle correction on Divider 2 and Divider 3 requires the
following channel divider conditions:
•
•
•
•
An even DX.Y must be set as MX.Y = NX.Y (low cycles = high
cycles).
An odd DX.Y must be set as MX.Y = NX.Y + 1 (the number of
low cycles must be one greater than the number of high
cycles).
If only one divider is bypassed, it must be the second
divider, X.2.
If only one divider has an even divide-by, it must be the
second divider, X.2.
The possibilities for the duty cycle of the output clock from
Divider 2 and Divider 3 are shown in Table 40 through
Table 44.
Table 40. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Off (DCCOFF = 1)
VCO
Divider
Even
Odd = 3
Odd = 5
Even
DX.1
NX.1 + MX.1 + 2
1
1
1
Even, odd
DX.2
NX.2 + MX.2 + 2
1
1
1
1
Odd
Even, odd
1
Even
Even, odd
Even, odd
Odd
Even, odd
Even, odd
Output
Duty Cycle
50%
33.3%
40%
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
Table 42. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Used; Duty Cycle Correction Is On (DCCOFF = 0); VCO
Divider Input Duty Cycle = 50%
VCO
Divider
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Even
Odd
Input Clock
Duty Cycle
50%
X%
50%
DX.1
NX.1 + MX.1 + 2
1
1
Even, odd
DX.2
NX.2 + MX.2 + 2
1
1
1
X%
Even, odd
1
50%
Even, odd
Even, odd
X%
Even, odd
Even, odd
Output
Duty Cycle
50%
X%
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
(NX.1 + 1)/
(NX.1 + MX.1 + 2)
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
(NX.2 + 1)/
(NX.2 + MX.2 + 2)
DX.2
NX.2 + MX.2 + 2
1
1
1
1
1
1
Even (NX.2 = MX.2)
Even (NX.2 = MX.2)
Even (NX.2 = MX.2)
Even (NX.2 = MX.2)
Odd (MX.2 = NX.2 + 1)
Odd (MX.2 = NX.2 + 1)
Output
Duty Cycle
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
Table 43. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Used; Duty Cycle Correction On (DCCOFF = 0); VCO
Divider Input Duty Cycle = X%
VCO
Divider
Even
Odd = 3
Odd = 5
Even
Odd
Even
Odd = 3
Odd = 5
Even
Odd
Table 41. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction Off (DCCOFF = 1)
DX.1
NX.1 + MX.1 + 2
1
1
Even (NX.1 = MX.1)
Even (NX.1 = MX.1)
Odd (MX.1 = NX.1 + 1)
Odd (MX.1 = NX.1 + 1)
Even (NX.1 = MX.1)
Even (NX.1 = MX.1)
Odd (MX.1 = NX.1 + 1)
Odd (MX.1 = NX.1 + 1)
Odd (MX.1 = NX.1 + 1)
Odd (MX.1 = NX.1 + 1)
Even
Odd
Even
Odd = 3
Odd = 5
Rev. A | Page 44 of 80
DX.1
DX.2
NX.1 + MX.1 + 2
1
1
1
Even
(NX.1 = MX.1)
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Even
(NX.1 = MX.1)
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
NX.2 + MX.2 + 2
1
1
1
Output
Duty Cycle
50%
(1 + X%)/3
(2 + X%)/5
1
50%
1
50%
1
50%
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.2 = NX.2 + 1)
1
1
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Odd
(MX.2 = NX.2 + 1)
Odd
(MX.2 = NX.2 + 1)
(3NX.1 + 4 + X%)/
(6NX.1 + 9)
(5NX.1 + 7 + X%)/
(10NX.1 + 15)
50%
50%
50%
50%
50%
(6NX.1NX.2 + 9NX.1 +
9NX.2 + 13 + X%)/
(3(2NX.1 + 3)
(2NX.2 + 3))
(10NX.1NX.2 + 15NX.1 +
15NX.2 + 22 + X%)/
(5(2 NX.1 + 3)
(2 NX.2 + 3))
AD9517-4
Table 44. Divider 2 and Divider 3 Duty Cycle; VCO Divider
Not Used; Duty Cycle Correction On (DCCOFF = 0)
X%
X%
50%
X%
50%
X%
50%
X%
50%
X%
DX.1
DX.2
NX.1 + MX.1 + 2
1
Even
(NX.1 = MX.1)
1
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Even
(NX.1 = MX.1)
Even
(NX.1 = MX.1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
Odd
(MX.1 = NX.1 + 1)
NX.2 + MX.2 + 2
1
1
Output Duty Cycle
50%
50%
1
1
X% (High)
50%
1
50%
1
(NX.1 + 1 + X%)/
(2NX.1 + 3)
50%
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Even
(NX.2 = MX.2)
Odd
(MX.2 = NX.2 + 1)
Odd
(MX.2 = NX.2 + 1)
Case 1
When Φx.1 ≤ 15 and Φx.2 ≤ 15:
Δt = Φx.1 × TX.1 + ΦX.2 × Tx.2
Case 2
When Φx.1 ≤ 15 and Φx.2 ≥ 16:
Δt = ΦX.1 × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2
Case 3
When ΦX.1 ≥ 16 and ΦX.2 ≤ 15:
50%
Δt = (ΦX.1 − 16 + MX.1 + 1) × TX.1 + ΦX.2 × TX.2
Case 4
50%
When ΦX.1 ≥ 16 and ΦX.2 ≥ 16:
50%
Δt =
50%
(ΦX.1 − 16 + MX.1 + 1) × TX.1 + (ΦX.2 − 16 + MX.2 + 1) × TX.2
(2NX.1NX.2 + 3NX.1 +
3NX.2 + 4 + X%)/
((2NX.1 + 3)(2NX.2 + 3))
Fine Delay Adjust (Divider 2 and Divider 3)
Phase Offset or Coarse Time Delay (Divider 2 and Divider 3)
Divider 2 and Divider 3 can be set to have a phase offset or
delay. The phase offset is set by a combination of the bits in the
phase offset and start high registers (see Table 45).
Each AD9517 LVDS/CMOS output (OUT4 to OUT7) includes
an analog delay element that can be programmed to give
variable time delays (Δt) in the clock signal at that output.
DIVIDER
X.1
Table 45. Setting Phase Offset and Division for Divider 2 and
Divider 3
Divider
2 2.1
2.2
3 3.1
3.2
Start
High (SH)
0x19C[0]
0x19C[1]
0x1A1[0]
0x1A1[1]
Phase
Offset (PO)
0x19A[3:0]
0x19A[7:4]
0x19F[3:0]
0x19F[7:4]
Low
Cycles M
0x199[7:4]
0x19B[7:4]
0x19E[7:4]
0x1A0[7:4]
High
Cycles N
0x199[3:0]
0x19B[3:0]
0x19E[3:0]
0x1A0[3:0]
BYPASS
VCO
CLK DIVIDER
CMOS
ΔT
LVDS
FINE DELAY
ADJUST
CMOS
OUTM
OUTM
OUTPUT
DRIVERS
DIVIDER
X.2
BYPASS
CMOS
ΔT
LVDS
FINE DELAY
ADJUST
CMOS
OUTN
OUTN
06428-072
Input
Clock
Duty
Cycle
50%
50%
Let
Δt = delay (in seconds).
Φx.y = 16 × SH[0] + 8 × PO[3] + 4 × PO[2] + 2 × PO[1] +
1 × PO[0].
TX.1 = period of the clock signal at the input to DX.1 (in seconds).
TX.2 = period of the clock signal at the input to DX.2 (in seconds).
Figure 55. Fine Delay (OUT4 to OUT7)
The amount of delay applied to the clock signal is determined
by programming four registers per output (see Table 46).
Table 46. Setting Analog Fine Delays
OUTPUT
(LVDS/CMOS)
OUT4
OUT5
OUT6
OUT7
Rev. A | Page 45 of 80
Ramp
Capacitors
0x0A1[5:3]
0x0A4[5:3]
0x0A7[5:3]
0x0AA[5:3]
Ramp
Current
0x0A1[2:0]
0x0A4[2:0]
0x0A7[2:0]
0x0AA[2:0]
Delay
Fraction
0x0A2[5:0]
0x0A5[5:0]
0x0A8[5:0]
0x0AB[5:0]
Delay
Bypass
0x0A0[0]
0x0A3[0]
0x0A6[0]
0x0A9[0]
AD9517-4
Calculating the Fine Delay
Synchronization of the outputs is executed in several ways:
The following values and equations are used to calculate the
delay of the delay block.
•
•
IRAMP (μA) = 200 × (Ramp Current + 1)
Number of Capacitors = Number of Bits =
0 in Ramp Capacitors + 1
•
Example: 101 = 1 + 1 = 2; 110 = 1 + 1 = 2; 100 = 2 + 1 = 3;
001 = 2 + 1 = 3; 111 = 0 + 1 = 1.
Delay Range (ns) = 200 × ((No. of Caps + 3)/(IRAMP)) × 1.3286
⎛ No.of Caps − 1 ⎞
⎟×6
Offset (ns ) = 0.34 + (1600 − I RAMP )× 10 −4 + ⎜⎜
⎟
I RAMP
⎝
⎠
Delay Full Scale (ns) = Delay Range + Offset
Fine Delay (ns) =
Delay Range × Delay Fraction × (1/63) + Offset
Note that only delay fraction values up to 47 decimal (101111b;
0x2F) are supported.
In no case can the fine delay exceed one-half of the output clock
period. If a delay longer than half of the clock period is attempted,
the output stops clocking.
The delay function adds some jitter greater than that specified
for the nondelayed output. This means that the delay function
should be used primarily for clocking digital chips, such as
FPGA, ASIC, DUC, and DDC. An output with this delay
enabled may not be suitable for clocking data converters. The
jitter is higher for long full scales because the delay block uses a
ramp and trip points to create the variable delay. A slower ramp
time produces more time jitter.
Synchronizing the Outputs—SYNC Function
The AD9517 clock outputs can be synchronized to each other.
Outputs can be individually excluded from synchronization.
Synchronization consists of setting the nonexcluded outputs to
a preset set of static conditions and subsequently releasing these
outputs to continue clocking at the same instant with the preset
conditions applied. This allows for the alignment of the edges of
two or more outputs or for the spacing of edges according to the
coarse phase offset settings for two or more outputs.
•
•
•
The SYNC pin is forced low and then released (manual sync).
By setting and then resetting any one of the following three
bits: the soft SYNC bit (Register 0x230[0]), the soft reset bit
(Register 0x000[2] [mirrored]), and the distribution powerdown bit (Register 0x230[1]).
Synchronization of the outputs can be executed as part of
the chip power-up sequence.
The RESET pin is forced low and then released (chip reset).
The PD pin is forced low, then released (chip power-down).
When a VCO calibration is completed, an internal SYNC
signal is automatically asserted at the beginning and released
upon the completion of a VCO calibration.
The most common way to execute the SYNC function is to use
the SYNC pin to do a manual synchronization of the outputs.
This requires a low-going signal on the SYNC pin, which is held
low and then released when synchronization is desired. The
timing of the SYNC operation is shown in Figure 56 (using
VCO divider) and Figure 57 (VCO divider not used). There is
an uncertainty of up to one cycle of the clock at the input to the
channel divider due to the asynchronous nature of the SYNC
signal with respect to the clock edges inside the AD9517. The
delay from the SYNC rising edge to the beginning of synchronized
output clocking is between 14 and 15 cycles of clock at the
channel divider input, plus either one cycle of the VCO divider
input (see Figure 56), or one cycle of the channel divider input
(see Figure 57), depending on whether the VCO divider is used.
Cycles are counted from the rising edge of the signal.
Another common way to execute the SYNC function is by setting
and resetting the soft SYNC bit at Register 0x230[0] (see Table 53
through Table 62 for details). Both setting and resetting of the
soft SYNC bit require an update all registers (Register 0x232[0] = 1)
operation to take effect.
Rev. A | Page 46 of 80
AD9517-4
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER OUTPUT STATIC
INPUT TO VCO DIVIDER
1
1
INPUT TO CHANNEL DIVIDER
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
06428-073
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
Figure 56. SYNC Timing When VCO Divider Is Used—CLK or VCO Is Input
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER
OUTPUT CLOCKING
CHANNEL DIVIDER OUTPUT STATIC
INPUT TO CLK
IINPUT TO CHANNEL DIVIDER
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SYNC PIN
OUTPUT OF
CHANNEL DIVIDER
06428-074
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
Figure 57. SYNC Timing When VCO Divider Is Not Used—CLK Input Only
A SYNC operation brings all outputs that have not been
excluded (by the nosync bit) to a preset condition before
allowing the outputs to begin clocking in synchronicity. The
preset condition takes into account the settings in each of the
channel’s start high bit and its phase offset. These settings
govern both the static state of each output when the SYNC
operation is happening and the state and relative phase of the
outputs when they begin clocking again upon completion of the
SYNC operation. Between outputs and after synchronization,
this allows for the setting of phase offsets.
The AD9517 outputs are in pairs, sharing a channel divider per
pair (two pairs of pairs, four outputs, in the case of CMOS). The
synchronization conditions apply to both outputs of a pair.
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the nosync bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the nonexcluded
channels.
Clock Outputs
The AD9517 offers three output level choices: LVPECL, LVDS,
and CMOS. OUT0 to OUT3 are LVPECL differential outputs;
and OUT4 to OUT7 are LVDS/CMOS outputs. These outputs
can be configured as either LVDS differential or as pairs of
single-ended CMOS outputs.
Rev. A | Page 47 of 80
AD9517-4
LVPECL Outputs—OUT0 to OUT3
3.5mA
The LVPECL differential voltage (VOD) is selectable from ~400 mV
to ~960 mV (see Register 0x0F0[3:2] to Register 0x0F5[3:2]).
The LVPECL outputs have dedicated pins for power supply
(VS_LVPECL), allowing a separate power supply to be used.
VS_LVPECL can be from 2.5 V to 3.3 V.
OUT
06428-034
The LVPECL output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVPECL output can be powered
down or powered up as needed. Because of the architecture of
the LVPECL output stages, there is the possibility of electrical
overstress and breakdown under certain power-down conditions.
For this reason, the LVPECL outputs have several power-down
modes. This includes a safe power-down mode that continues
to protect the output devices while powered down, although it
consumes somewhat more power than a total power-down. If
the LVPECL output pins are terminated, it is best to select the
safe power-down mode. If the pins are not connected (unused),
it is acceptable to use the total power-down mode.
OUT
3.5mA
Figure 59. LVDS Output Simplified Equivalent Circuit with
3.5 mA Typical Current Source
Each LVDS/CMOS output can be powered-down as needed to
save power. The CMOS output power-down is controlled by the
same bit that controls the LVDS power-down for that output.
This power-down control affects both the CMOS A and CMOS B
outputs. However, when the CMOS A output is powered up, the
CMOS B output can be powered on or off separately.
VS
3.3V
06428-035
OUT
OUT
Figure 60. CMOS Equivalent Output Circuit
OUT
RESET MODES
GND
06428-033
The AD9517 has several ways to force the chip into a reset
condition that restores all registers to their default values and
makes these settings active.
Power-On Reset—Start-Up Conditions When VS Is Applied
Figure 58. LVPECL Output Simplified Equivalent Circuit
LVDS/CMOS Outputs—OUT4 to OUT7
OUT4 to OUT7 can be configured as either an LVDS
differential output or as a pair of CMOS single-ended outputs.
The LVDS outputs allow for selectable output current from
~1.75 mA to ~7 mA.
The LVDS output polarity can be set as noninverting or
inverting, which allows for the adjustment of the relative
polarity of outputs within an application without requiring a
board layout change. Each LVDS output can be powered down
if not needed to save power.
OUT4 to OUT7 can also be CMOS outputs. Each LVDS output
can be configured to be two CMOS outputs. This provides for
up to eight CMOS outputs: OUT4A, OUT4B, OUT5A, OUT5B,
OUT6A, OUT6B, OUT7A, and OUT7B. When an output is
configured as CMOS, CMOS Output A is automatically turned on.
CMOS Output B can be turned on or off independently. The
relative polarity of the CMOS outputs can also be selected for
any combination of inverting and noninverting (see Table 57,
Register 0x140[7:5], Register 0x141[7:5], Register 0x142[7:5],
and Register 0x143[7:5]).
A power-on reset (POR) is issued when the VS power supply is
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the Default Value (Hex) column of Table 52. At
power-on, the AD9517 also executes a SYNC operation, which
brings the outputs into phase alignment according to the default
settings.
Asynchronous Reset via the RESET Pin
An asynchronous hard reset is executed by momentarily pulling
RESET low. A reset restores the chip registers to the default settings.
Soft Reset via Register 0x00[2]
A soft reset is executed by writing Register 0x000[2] and
Register 0x000[5] = 1b. This bit is not self-clearing; it must be
cleared by writing Register 0x000[2] and Register 0x000[5] = 0b to
reset it and complete the soft reset operation. A soft reset restores
the default values to the internal registers. The soft reset bit does
not require an update registers command (Register 0x232) to be
issued.
Rev. A | Page 48 of 80
AD9517-4
In asynchronous power-down mode, the device powers down as
soon as the registers are updated.
POWER-DOWN MODES
Chip Power-Down via PD
The AD9517 can be put into a power-down condition by
pulling the PD pin low. Power-down turns off most of the
functions and currents inside the AD9517. The chip remains in
this power-down state until PD is brought back to logic high.
When the AD9517 wakes it, it returns to the settings programmed
into its registers prior to the power-down, unless the registers
are changed by new programming while the PD pin is held low.
The PD power-down shuts down the currents on the chip,
except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tristated.
Because this is not a complete power-down, it can be called
sleep mode.
When the AD9517 is in a PD power-down, the chip is in the
following state:
•
•
•
•
•
•
•
The PLL is off (asynchronous power-down).
The VCO is off.
The CLK input buffer is off.
All dividers are off.
All LVDS/CMOS outputs are off.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
If the AD9517 clock outputs must be synchronized to each
other, a SYNC is required upon exiting power-down (see the
Synchronizing the Outputs—SYNC Function section). A VCO
calibration is not required when exiting power-down.
PLL Power-Down
The PLL section of the AD9517 can be selectively powered down.
There are three PLL operating modes set by Register 0x010[1:0],
as shown in Table 54.
In synchronous power-down mode, the PLL power-down is
gated by the charge pump to prevent unwanted frequency
jumps. The device goes into power-down on the occurrence of
the next charge pump event after the registers are updated.
Distribution Power-Down
The distribution section can be powered down by writing
Register 0x230[1] = 1b. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
(00b), it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
the LVPECL power-down mode is set to 11b, the LVPECL
output is not protected from reverse bias and may be damaged
under certain termination conditions.
Individual Clock Output Power-Down
Any of the clock distribution outputs can be powered down
individually by writing to the appropriate registers. The register
map details the individual power-down settings for each output
(see Table 52). The LVDS/CMOS outputs can be powered
down, regardless of their output load configuration.
The LVPECL outputs have multiple power-down modes
(see Table 56), which give some flexibility in dealing with the
various output termination conditions. When the mode is set to
10b, the LVPECL output is protected from reverse bias to
2 VBE + 1 V. If the mode is set to 11b, the LVPECL output is
not protected from reverse bias and can be damaged under
certain termination conditions. This setting also affects the
operation when the distribution block is powered down with
Register 0x230[1] = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Other AD9517 circuit blocks (such as CLK, REF1, and REF2)
can be powered down individually. This gives flexibility in
configuring the part for power savings whenever certain chip
functions are not needed.
Rev. A | Page 49 of 80
AD9517-4
SERIAL CONTROL PORT
The AD9517 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9517 serial control port is compatible with most synchronous
transfer formats, including both the Motorola SPI® and Intel®
SSR® protocols. The serial control port allows read/write access
to all registers that configure the AD9517. Single or multiple
byte transfers are supported, as well as MSB first or LSB first
transfer formats. The AD9517 serial control port can be
configured for a single bidirectional I/O pin (SDIO only)
or for two unidirectional I/O pins (SDIO/SDO). By default,
the AD9517 is in bidirectional mode, long instruction (long
instruction is the only instruction mode supported).
SCLK (serial clock) is the serial shift clock. This pin is an input.
SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (serial data input/output) is a dual-purpose pin and acts
as either an input only (unidirectional mode) or as both an
input/output (bidirectional mode). The AD9517 defaults to the
bidirectional I/O mode (Register 0x000[0] = 0).
SDO (serial data out) is used only in the unidirectional I/O mode
(Register 0x000[0] = 1) as a separate output pin for reading
back data.
CS (chip select bar) is an active low control that gates the read
and write cycles. When CS is high, SDO and SDIO are in a high
impedance state. This pin is internally pulled up by a 30 kΩ
resistor to VS.
14
SDO
15
SDIO
16
AD9517-4
SERIAL
CONTROL
PORT
06428-036
13
CS
In the streaming mode (see Table 47), any number of data bytes
can be transferred in a continuous stream. The register address
is automatically incremented or decremented (see the MSB/LSB
First Transfers section). CS must be raised at the end of the last
byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK
During this period, the serial control port state machine enters
a wait state until all data is sent. If the system controller decides
to abort the transfer before all of the data is sent, the state machine
must be reset by either completing the remaining transfers or by
returning the CS low for at least one complete SCLK cycle (but
less than eight SCLK cycles). Raising the CS on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
Figure 61. Serial Control Port
GENERAL OPERATION OF SERIAL CONTROL PORT
A write or a read operation to the AD9517 is initiated by pulling
CS low.
CS stalled high is supported in modes where three or fewer bytes
of data (plus instruction data) are transferred (see Table 47).
In these modes, CS can temporarily return high on any byte
boundary, allowing time for the system controller to process the
next byte. CS can go high on byte boundaries only and can go
high during either part (instruction or data) of the transfer.
There are two parts to a communication cycle with the AD9517.
The first part writes a 16-bit instruction word into the AD9517,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9517 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation, the second part
is the transfer of data into the serial control port buffer of the
AD9517. Data bits are registered on the rising edge of SCLK.
The length of the transfer (1, 2, 3 bytes or streaming mode) is
indicated by two bits (W1:W0) in the instruction byte. When
the transfer is 1, 2, or 3 bytes, but not streaming, CS can be
raised after each sequence of eight bits to stall the bus (except
after the last byte, where it ends the cycle). When the bus is
stalled, the serial transfer resumes when CS is lowered. Raising CS
on a nonbyte boundary resets the serial control port. During a
write, streaming mode does not skip over reserved or blank
registers, and it does not matter what data is written to blank
registers.
Because data is written into a serial control port buffer area, not
directly into the actual control registers of the AD9517, an
additional operation is needed to transfer the serial control port
buffer contents to the actual control registers of the AD9517,
thereby causing them to become active. The update registers
operation consists of setting Register 0x232[0] = 1b (this bit is
self-clearing). Any number of bytes of data can be changed
before executing an update registers. The update registers
simultaneously actuates all register changes that have been
written to the buffer since any previous update.
Rev. A | Page 50 of 80
AD9517-4
Read
If the instruction word is for a read operation, the next N × 8
SCLK cycles clock out the data from the address specified in the
instruction word, where N is 1 to 3 as determined by [W1:W0].
If N = 4, the read operation is in streaming mode, continuing
until CS is raised. Streaming mode does not skip over reserved
or blank registers. The readback data is valid on the falling
edge of SCLK.
The default mode of the AD9517 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible to
set the AD9517 to unidirectional mode via the SDO active bit,
Register 0x000[0] = 1. In unidirectional mode, the readback
data appears on the SDO pin.
A readback request reads the data that is in the serial control
port buffer area, or the data that is in the active registers (see
Figure 62). Readback of the buffer or active registers is controlled
by Register 0x004[0].
The AD9517 supports only the long instruction mode; therefore,
Register 0x000[4:3] must be set to 11b. Long instruction mode is
the default at power-up or reset.
SERIAL
CONTROL
PORT
UPDATE
REGISTERS
WRITE REGISTER 0x232 = 0x01
TO UDATE REGISTERS
06428-037
CS
ACTIVE REGISTERS
SDO
BUFFER REGISTERS
SDIO
Figure 62. Relationship Between Serial Control Port Buffer Registers and
Active Registers of the AD9517
THE INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/W, which indicates
whether the instruction is a read or a write. The next two bits,
[W1:W0], indicate the length of the transfer in bytes. The final
13 bits are the address ([A12:A0]) at which to begin the read or
write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0] (see Table 47).
Table 47. Byte Transfer Count
W1
0
0
1
1
W0
0
1
0
1
Bytes to Transfer
1
2
3
Streaming mode
MSB/LSB FIRST TRANSFERS
The AD9517 instruction word and byte data can be MSB first
or LSB first. Any data written to Register 0x000 must be mirrored;
the upper four bits (Bits[7:4]) must mirror the lower four bits
(Bits[3:0). This makes it irrelevant whether LSB first or MSB
first is in effect. As an example of this mirroring, see the default
setting for this register: 0x18, which mirrors Bit 4 and Bit 3.
This sets the long instruction mode (which is the default and is
the only mode supported).
The default for the AD9517 is MSB first.
When LSB first is set by Register 0x000[1] and Register 0x000[6],
it takes effect immediately because it affects only the operation
of the serial control port and does not require that an update be
executed.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the low
address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the
multibyte transfer cycle.
The AD9517 uses Register Address 0x000 to Register
Address 0x232.
SCLK
The 13 bits found in [A12:A0] select the address within the
register map that is written to or read from during the data
transfer portion of the communications cycle. Only Bits[A9:A0]
are needed to cover the range of the 0x232 registers used by the
AD9517. Bits[A12:A10] must always be 0b. For multibyte
transfers, this address is the starting byte address. In MSB first
mode, subsequent bytes increment the address.
When LSB first is active, the instruction and data bytes must be
written from LSB to MSB. Multibyte data transfers in LSB first
format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple
data bytes. The internal byte address generator of the serial
control port increments for each byte of the multibyte
transfer cycle.
The AD9517 serial control port register address decrements
from the register address just written toward 0x000 for multibyte
I/O operations if the MSB first mode is active (default). If the
LSB first mode is active, the register address of the serial control
port increments from the address just written toward 0x232 for
multibyte I/O operations.
Streaming mode always terminates when it hits Address 0x232.
Note that unused addresses are not skipped during multibyte
I/O operations.
Table 48. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB first
MSB first
Rev. A | Page 51 of 80
Address Direction
Increment
Decrement
Stop Sequence
0x230, 0x231, 0x232, stop
0x001, 0x000, 0x232, stop
AD9517-4
Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
I14
I13
I12
I11
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
LSB
I0
R/W
W1
W0
A12 = 0
A11 = 0
A10 = 0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
SCLK DON'T CARE
SDIO DON'T CARE
R/W W1 W0 A12 A11 A10 A9
A8
A7
A6 A5
A4 A3 A2
A1 A0
16-BIT INSTRUCTION HEADER
D7 D6 D5
D4 D3
D2 D1
D0
D7
D6 D5
REGISTER (N) DATA
D4 D3 D2
D1 D0
DON'T CARE
REGISTER (N – 1) DATA
06428-038
DON'T CARE
Figure 63. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
CS
SCLK
DON’T CARE
SDIO
DON’T CARE
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
SDO DON’T CARE
REGISTER (N) DATA
REGISTER (N – 1) DATA
REGISTER (N – 2) DATA
REGISTER (N – 3) DATA
DON’T
CARE
06428-039
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
16-BIT INSTRUCTION HEADER
Figure 64. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
tDS
tHIGH
tS
tDH
tC
tCLK
tLOW
CS
DON’T CARE
SDIO
DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
A6
A5
D4
D3
D2
D1
D0
DON’T CARE
06428-040
SCLK
Figure 65. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
CS
SCLK
DATA BIT N
06428-041
tDV
SDIO
SDO
DATA BIT N – 1
Figure 66. Timing Diagram for Serial Control Port Register Read
CS
SCLK DON'T CARE
A0 A1 A2 A3
A4
A5 A6 A7
A8
A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4
16-BIT INSTRUCTION HEADER
D5 D6
REGISTER (N) DATA
D7
D0
D1 D2
D6
REGISTER (N + 1) DATA
Figure 67. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
Rev. A | Page 52 of 80
D3 D4 D5
D7
DON'T CARE
06428-042
SDIO DON'T CARE
DON'T CARE
AD9517-4
tS
tC
CS
tCLK
tHIGH
SCLK
tLOW
tDS
SDIO
BIT N
BIT N + 1
Figure 68. Serial Control Port Timing—Write
Table 50. Serial Control Port Timing
Parameter
tDS
tDH
tCLK
tS
tC
tHIGH
tLOW
tDV
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CS falling edge and SCLK rising edge (start of communication cycle)
Setup time between SCLK rising edge and CS rising edge (end of communication cycle)
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
SCLK to valid SDIO and SDO (see Figure 66)
Rev. A | Page 53 of 80
06428-043
tDH
AD9517-4
THERMAL PERFORMANCE
Table 51. Thermal Parameters for the 48-Lead LFCSP
Symbol
θJA
θJMA
θJMA
θJB
ΨJB
ΨJB
ΨJB
θJC
ΨJT
ΨJT
ΨJT
Thermal Characteristic Using a JEDEC JESD51-7 Plus JEDEC JESD51-5 2S2P Test Board
Junction-to-ambient thermal resistance, natural convection per JEDEC JESD51-2 (still air)
Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)
Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air)
Junction-to-board thermal resistance, natural convection per JEDEC JESD51-8 (still air)
Junction-to-board characterization parameter, natural convection per JEDEC JESD51-6 (still air)
and JEDEC JESD51-8
Junction-to-board characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air)
and JEDEC JESD51-8
Junction-to-board characterization parameter, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air)
and JEDEC JESD51-8
Junction-to-case thermal resistance (die-to-heat sink) per MIL-STD-883, Method 1012.1
Junction-to-top-of-package characterization parameter, natural convection per JEDEC JESD51-2 (still air)
Junction-to-top-of-package characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-2 (still air)
Junction-to-top-of-package characterization parameter, 2.0 m/sec airflow per JEDEC JESD51-2 (still air)
The AD9517 is specified for a case temperature (TCASE). To ensure
that TCASE is not exceeded, an airflow source can be used.
Use the following equation to determine the junction
temperature on the application PCB:
Value (°C/W)
24.7
21.6
19.4
12.9
11.9
11.8
11.6
1.3
0.1
0.2
0.3
Values of θJA are provided for package comparison and PCB
design considerations. θJA can be used for a first-order
approximation of TJ by the equation
TJ = TA + (θJA × PD)
TJ = TCASE + (ΨJT × PD)
where TA is the ambient temperature (°C).
where:
TJ is the junction temperature (°C).
TCASE is the case temperature (°C) measured by the user at the
top center of the package.
ΨJT is the value from Table 51.
PD is the power dissipation (see the total power dissipation in
Table 17).
Values of θJC are provided for package comparison and PCB
design considerations when an external heat sink is required.
Values of ΨJB are provided for package comparison and PCB
design considerations.
Rev. A | Page 54 of 80
AD9517-4
CONTROL REGISTERS
CONTROL REGISTER MAP OVERVIEW
Table 52. Control Register Map Overview
Reg.
Addr.
(Hex)
Parameter
Bit 7 (MSB)
Serial Port Configuration
0x000
Serial port
SDO
configuration
active
0x001
0x002
0x003
Part ID
0x004
Read back
control
PLL
0x010
0x011
0x012
0x013
0x014
0x015
0x016
PFD and
charge pump
R counter
A counter
B counter
PLL Control 1
0x017
0x018
PLL Control 2
PLL Control 3
0x019
PLL Control 4
0x01A
PLL Control 5
0x01B
PLL Control 6
0x01C
PLL Control 7
0x01D
PLL Control 8
0x01E
0x01F
PLL Control 9
PLL readback
0x020
to
0x04F
Bit 6
Bit 5
Bit 4
LSB first
Soft reset
Long
Long
instruction
instruction
Blank
Reserved
Part ID (read only)
Blank
PFD
polarity
Bit 3
Charge pump current
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
Soft reset
LSB first
SDO active
0x18
Charge Pump Mode
Read back
active
registers
PLL Power-Down
14-bit R divider, Bits[7:0] (LSB)
14-bit R divider, Bits[13:8] (MSB)
6-bit A counter
13-bit B counter, Bits[7:0] (LSB)
Blank
13-bit B counter, Bits[12:8] (MSB)
Reset R
Reset A and
Reset all
B counter
Prescaler P
Set CP pin
counter
B counters
counters
bypass
to VCP/2
STATUS pin control
Antibacklash pulse width
Reserved
Lock detect counter
Digital lock
Disable
VCO calibration divider
VCO cal now
detect
digital lock
window
detect
R path delay
N path delay
R, A, B counters SYNC
pin reset
LD pin control
Reserved
Reference
frequency
monitor
threshold
REF1 (REFIN)
REFMON pin control
VCO
REF2
frequency
frequency
(REFIN)
monitor
monitor
frequency
monitor
Disable
Select
Use
Automatic
Stay on REF2
REF2
REF1
Differential
switchover REF2
REF_SEL pin reference
power-on
power-on
reference
deglitch
switchover
Holdover
Holdover
External
LD pin
Reserved
PLL status
enable
enable
holdover
comparator
register
control
enable
disable
Reserved
Reserved
VCO cal
Holdover
REF2
VCO
REF2
REF1
Digital
finished
active
selected
frequency >
frequency > frequency >
lock detect
threshold
threshold
threshold
Blank
Blank
Blank
Rev. A | Page 55 of 80
0xD3
0x00
0x7D
0x01
0x00
0x00
0x03
0x00
0x06
0x00
0x06
0x00
0x00
0x00
0x00
0x00
0x00
N/A
AD9517-4
Reg.
Addr.
(Hex)
Parameter
Bit 7 (MSB) Bit 6
Fine Delay Adjust—OUT4 to OUT7
0x0A0 OUT4 delay
bypass
0x0A1 OUT4 delay
Blank
full-scale
0x0A2 OUT4 delay
Blank
fraction
0x0A3
0x0A4
0x0A5
0x0A6
0x0A7
0x0A8
0x0A9
0x0AA
0x0AB
OUT5 delay
bypass
OUT5 delay
full-scale
OUT5 delay
fraction
OUT6 delay
bypass
OUT6 delay
full-scale
OUT6 delay
fraction
OUT7 delay
bypass
OUT7 delay
full-scale
OUT7 delay
fraction
Blank
Bit 3
Bit 2
Bit 1
Blank
Bit 0 (LSB)
OUT4 delay
bypass
OUT4 ramp current
OUT4 ramp capacitors
OUT4 delay fraction
Blank
OUT5 delay fraction
Blank
Blank
Blank
OUT6 delay fraction
Blank
Blank
Blank
OUT7 delay fraction
0x0F1
Blank
0x01
0x00
0x01
0x00
0x00
OUT7 delay
bypass
OUT7 ramp current
OUT7 ramp capacitors
0x00
0x00
OUT6 delay
bypass
OUT6 ramp current
OUT6 ramp capacitors
0x01
0x00
OUT5 delay
bypass
OUT5 ramp current
OUT5 ramp capacitors
Blank
0x01
0x00
0x00
Blank
0x0F2,
0x0F3
0x0F4
OUT2
Blank
0x0F5
OUT3
Blank
OUT0
invert
OUT1
invert
OUT0 LVPECL
differential voltage
OUT1 LVPECL
differential voltage
OUT0 power-down
0x08
OUT1 power-down
0x0A
OUT2 LVPECL
differential voltage
OUT3 LVPECL
differential voltage
OUT2 power-down
0x08
OUT3 power-down
0x0A
Reserved
0x0F6
to
0x13F
LVDS/CMOS Outputs
0x140
OUT4
OUT2
invert
OUT3
invert
Blank
OUT4 CMOS
output polarity
0x141
OUT5
OUT5 CMOS
output polarity
0x142
OUT6
OUT6 CMOS
output polarity
0x143
OUT7
OUT7 CMOS
output polarity
0x144
to
0x18F
Bit 4
Blank
0x0AC
to
0x0EF
LVPECL Outputs
0x0F0
OUT0
OUT1
Bit 5
Default
Value
(Hex)
OUT4 LVDS/
CMOS
output
polarity
OUT5 LVDS/
CMOS
output
polarity
OUT6 LVDS/
CMOS
output
polarity
OUT7 LVDS/
CMOS
output
polarity
OUT4
CMOS B
OUT4 select
LVDS/CMOS
OUT4 LVDS
output current
OUT4
power-down
0x42
OUT5
CMOS B
OUT5 select
LVDS/CMOS
OUT5 LVDS
output current
OUT5
power-down
0x43
OUT6
CMOS B
OUT6 select
LVDS/CMOS
OUT6 LVDS
output current
OUT6
power-down
0x42
OUT7
CMOS B
OUT7 select
LVDS/CMOS
OUT7 LVDS
output current
OUT7
power-down
0x43
Blank
Rev. A | Page 56 of 80
AD9517-4
Reg.
Addr.
(Hex)
Parameter
Bit 7 (MSB)
LVPECL Channel Dividers
0x190
Divider 0
(PECL)
0x191
Divider 0
bypass
0x192
Blank
0x193
to
0x195
0x196
Bit 6
Bit 5
Bit 4
Bit 3
Divider 0 low cycles
Divider 0
nosync
Divider 0
force high
Divider 0
start high
Reserved
Bit 2
Bit 1
Bit 0 (LSB)
Default
Value
(Hex)
Divider 0 high cycles
0x00
Divider 0 phase offset
0x80
Divider 0
direct to
output
Divider 0
DCCOFF
0x00
Reserved
Divider1
(PECL)
0x197
Divider 1 low cycles
Divider 1
bypass
0x198
Divider 1
nosync
Blank
Divider 1
force high
Divider 1
start high
Reserved
Divider 1 high cycles
0x00
Divider 1 phase offset
0x00
Divider 1
direct to
output
Divider 1
DCCOFF
0x00
LVDS/CMOS Channel Dividers
0x199
Divider 2
(LVDS/CMOS)
0x19A
0x19B
Low Cycles Divider 2.1
High Cycles Divider 2.1
0x22
Phase Offset Divider 2.2
Low Cycles Divider 2.2
Phase Offset Divider 2.1
High Cycles Divider 2.2
0x00
0x11
0x19C
Reserved
0x19D
Blank
0x19E
Divider 3
(LVDS/CMOS)
0x19F
0x1A0
0x1A1
Reserved
0x1A2
0x1A3
0x1A4
to
0x1DF
VCO Divider and CLK Input
0x1E0
VCO divider
0x1E1
Input CLKs
Bypass
Divider 2.2
Divider 2
nosync
Reserved
Divider 2
force high
Start High
Divider 2.2
Start High
Divider 2.1
Divider 2
DCCOFF
0x00
0x00
Low Cycles Divider 3.1
High Cycles Divider 3.1
0x22
Phase Offset Divider 3.2
Low Cycles Divider 3.2
Bypass
Divider 3.2
Phase Offset Divider 3.1
High Cycles Divider 3.2
Divider 3
Start High
force high
Divider 3.2
0x00
0x11
0x00
Bypass
Divider 3.1
Blank
Divider 3
nosync
Reserved
Start High
Divider 3.1
Divider 3
DCCOFF
0x00
Reserved
Blank
Blank
Reserved
Power-down
PowerVCO clock
down
interface
clock input
section
Blank
Reserved
0x1E2
to
0x22A
System
0x230
Power-down
and SYNC
0x231
Update All Registers
0x232
Update all
registers
Bypass
Divider 2.1
Reserved
Powerdown VCO
and CLK
Powerdown SYNC
VCO Divider
Select
Bypass VCO
VCO or CLK
divider
Powerdown
distribution
reference
Reserved
Blank
Blank
Rev. A | Page 57 of 80
Soft SYNC
0x02
0x00
0x00
0x00
Update all
registers (selfclearing bit)
0x00
AD9517-4
CONTROL REGISTER MAP DESCRIPTIONS
Table 53 through Table 62 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal
address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, like this: [5:2].
Table 53. Serial Port Configuration and Part ID
Reg.
Addr
(Hex)
0x000
Bits
[7:4]
Name
Mirrored, Bits[3:0]
3
Long instruction
2
Soft reset
1
LSB first
0
SDO active
0x003
[7:0]
Part ID (read only)
0x004
0
Read back active registers
Description
Bits[7:4] should always mirror Bits[3:0] so that it does not matter whether the part
is in MSB or LSB first mode (see Bit 1, Register 0x000). User should set bits as follows:
Bit 7 = Bit 0.
Bit 6 = Bit 1.
Bit 5 = Bit 2.
Bit 4 = Bit 3.
Short/long instruction mode. This part uses long instruction mode only, so this bit should
always be 1.
0: 8-bit instruction (short).
1: 16-bit instruction (long) (default).
Soft reset.
1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared to
0 to complete reset operation.
MSB or LSB data orientation.
0: data-oriented MSB first; addressing decrements (default).
1: data-oriented LSB first; addressing increments.
Selects unidirectional or bidirectional data transfer mode.
0: SDIO pin used for write and read; SDO set high impedance; bidirectional mode (default).
1: SDO used for read, SDIO used for write; unidirectional mode.
Uniquely identifies the dash version (-0 through -4) of the AD9517
AD9517-0: 0x11
AD9517-1: 0x51
AD9517-2: 0x91
AD9517-3: 0x53
AD9517-4: 0xD3
Select register bank used for a readback.
0: read back buffer registers (default).
1: read back active registers.
Rev. A | Page 58 of 80
AD9517-4
Table 54. PLL
Reg.
Addr.
(Hex)
0x010
Bits
7
Name
PFD polarity
[6:4]
CP current
[3:2]
CP mode
[1:0]
PLL powerdown
0x011
[7:0]
0x012
[5:0]
0x013
0x014
[5:0]
[7:0]
0x015
[4:0]
0x016
7
14-bit R divider,
Bits[7:0] (LSB)
14-bit R divider,
Bits[13:8] (MSB)
6-bit A counter
13-bit B counter,
Bits[7:0] (LSB)
13-bit B counter,
Bits[12:8] (MSB)
Set CP pin to VCP/2
6
Reset R counter
5
Reset A, B counters
4
Reset all counters
3
B counter
bypass
Description
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires
positive polarity; Bit 7 = 0.
0: positive; higher control voltage produces higher frequency (default).
1: negative; higher control voltage produces lower frequency.
Charge pump current (with CPRSET = 5.1 kΩ).
6
5
4
ICP (mA)
0
0
0
0.6
0
0
1
1.2
0
1
0
1.8
0
1
1
2.4
1
0
0
3.0
1
0
1
3.6
1
1
0
4.2
1
1
1
4.8 (default)
Charge pump operating mode.
3
2
Charge Pump Mode
0
0
High impedance state.
0
1
Force source current (pump up).
1
0
Force sink current (pump down).
1
1
Normal operation (default).
PLL operating mode.
1
0
Mode
0
0
Normal operation.
0
1
Asynchronous power-down (default).
1
0
Normal operation.
1
1
Synchronous power-down.
R divider LSBs—lower eight bits (default = 0x01).
R divider MSBs—upper six bits (default = 0x00).
A counter (part of N divider) (default = 0x00).
B counter (part of N divider)—lower eight bits (default = 0x03).
B counter (part of N divider)—upper five bits (default = 0x00).
Set the CP pin to one-half of the VCP supply voltage.
0: CP normal operation (default).
1: CP pin set to VCP/2.
Reset R counter (R divider).
0: normal (default).
1: holds the R counter in reset.
Reset A and B counters (part of N divider).
0: normal (default).
1: holds the A and B counters in reset.
Reset R, A, and B counters.
0: normal (default).
1: holds the R, A, and B counters in reset.
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
Rev. A | Page 59 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x016
0x017
Bits
[2:0]
[7:2]
Name
Prescaler P
STATUS pin
control
Description
Prescaler: DM = dual modulus and FD = fixed divide.
2
1
0
Mode
Prescaler
0
0
0
FD
Divide-by-1.
0
0
1
FD
Divide-by-2.
0
1
0
DM
Divide-by-2 (2/3 mode).
0
1
1
DM
Divide-by-4 (4/5 mode).
1
0
0
DM
Divide-by-8 (8/9 mode).
1
0
1
DM
Divide-by-16 (16/17 mode).
1
1
0
DM
Divide-by-32 (32/33 mode) (default).
1
1
1
FD
Divide-by-3.
Select the signal that is connected to the STATUS pin.
Level or
Dynamic
Signal
Signal at STATUS Pin
7
6
5
4
3
2
0
0
0
0
0
0
LVL
Ground (dc) (default).
0
0
0
0
0
1
DYN
N divider output (after the delay).
0
0
0
0
1
0
DYN
R divider output (after the delay).
0
0
0
0
1
1
DYN
A divider output.
0
0
0
1
0
0
DYN
Prescaler output.
0
0
0
1
0
1
DYN
PFD up pulse.
0
0
0
1
1
0
DYN
PFD down pulse.
0
X
X
X
X
X
LVL
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1
0
0
0
0
0
LVL
Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (N/A in differential mode).
1
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active
high.
1
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode);
active high.
1
0
0
1
1
1
LVL
Status REF1 frequency (active high).
1
0
1
0
0
0
LVL
Status REF2 frequency (active high).
1
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
1
LVL
Status of VCO frequency (active high).
1
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
1
1
0
LVL
Holdover active (active high).
1
0
1
1
1
1
LVL
LD pin comparator output (active high).
1
1
0
0
0
0
LVL
VS (PLL supply).
1
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
LVL
LVL
LVL
LVL
LVL
Status of selected reference (status of differential reference); active low.
Status of unselected reference (not available in differential mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
1
1
1
0
1
0
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
(DLD) AND (status of selected reference) AND (status of VCO).
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
LVL
LVL
LVL
LVL
LVL
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD) (active low).
Holdover active (active low).
LD pin comparator output (active low).
Rev. A | Page 60 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x017
Bits
[1:0]
Name
Antibacklash
pulse width
0x018
[6:5]
Lock detect
counter
4
Digital lock detect
window
3
Disable digital
lock detect
[2:1]
VCO cal
divider
[0]
VCO cal now
0x019
[7:6]
R, A, B counters
SYNC pin reset
0x01A
[5:3]
[2:0]
[6]
R path delay
N path delay
Reference
frequency monitor
threshold
Description
1
0
Antibacklash Pulse Width (ns)
0
0
2.9 (default).
0
1
1.3.
1
0
6.0.
1
1
2.9.
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
5
PFD Cycles to Determine Lock
0
0
5 (default).
0
1
16.
1
0
64.
1
1
255.
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window time, the digital
lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
Digital lock detect operation.
0: normal lock detect operation. (default)
1: disable lock detect.
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
2
1
VCO Calibration Clock Divider
0
0
2.
0
1
4.
1
0
8.
1
1
16 (default).
Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. To initiate
calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0 (if not
zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1, followed by another update bit
(Register 0x232, Bit 0).
7
6
Action
0
0
Do nothing on SYNC (default).
0
1
Asynchronous reset.
1
0
Synchronous reset.
1
1
Do nothing on SYNC.
R path delay (see Table 2) (default = 0x00).
N path delay (see Table 2) (default = 0x00).
Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO
frequency monitor’s detection threshold (see Table 16, REF1, REF2, and VCO frequency status monitor).
0: frequency valid if frequency is above the higher frequency threshold (default).
1: frequency valid if frequency is above the lower frequency threshold.
Rev. A | Page 61 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x01A
0x01B
Bits
[5:0]
Name
LD pin control
7
VCO
frequency monitor
6
REF2 (REFIN)
frequency monitor
5
REF1 (REFIN)
frequency monitor
Description
Select the signal that is connected to the LD pin.
Level or
Dynamic
Signal
Signal at LD Pin
5
4
3
2
1
0
0
0
0
0
0
0
LVL
Digital lock detect (high = lock, low = unlock) (default).
0
0
0
0
0
1
DYN
P-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
0
DYN
N-channel, open-drain lock detect (analog lock detect).
0
0
0
0
1
1
HIZ
High-Z LD pin.
0
0
0
1
0
0
CUR
Current source lock detect (110 μA when DLD is true).
0
X
X
X
X
X
LVL
Ground (dc); for all other cases of 0XXXXX not specified above.
The selections that follow are the same as REFMON.
1
0
0
0
0
0
LVL
Ground (dc).
1
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
0
1
0
DYN
REF2 clock (N/A in differential mode).
1
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when indifferential mode).
1
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
1
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active
high.
1
0
0
1
1
1
LVL
Status REF1 frequency (active high).
1
0
1
0
0
0
LVL
Status REF2 frequency (active high).
1
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
1
LVL
Status of VCO frequency (active high).
1
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
1
0
1
LVL
Digital lock detect (DLD); active high.
1
0
1
1
1
0
LVL
Holdover active (active high).
1
0
1
1
1
1
LVL
N/A. Do not use.
1
1
0
0
0
0
LVL
VS (PLL supply).
1
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
1
1
1
0
0
1
1
0
1
1
0
LVL
LVL
1
1
1
1
1
1
0
1
1
1
0
0
1
0
0
1
0
1
LVL
LVL
LVL
Status of selected reference (status of differential reference); active low.
Status of unselected reference (not available in differential mode); active
low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (status of REF2 frequency).
1
1
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
1
1
0
1
1
LVL
1
1
1
1
0
0
LVL
1
1
1
1
0
1
LVL
1
1
1
1
1
0
LVL
1
1
1
1
1
1
LVL
Enable or disable VCO frequency monitor.
0: disable VCO frequency monitor (default).
1: enable VCO frequency monitor.
Enable or disable REF2 frequency monitor.
Status of VCO frequency (active low).
Selected reference (low = REF2, high = REF1).
Digital lock detect (DLD); active low.
Holdover active (active low).
N/A—do not use.
0: disable REF2 frequency monitor (default).
1: enable REF2 frequency monitor.
REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs
(as selected by differential reference mode).
0: disable REF1 (REFIN) frequency monitor (default).
1: enable REF1 (REFIN) frequency monitor.
Rev. A | Page 62 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x01B
0x01C
Bits
[4:0]
7
Name
REFMON
pin control
6
Disable
switchover
deglitch
Select REF2
5
Use REF_SEL pin
4
3
Automatic
reference
switchover
Stay on REF2
2
REF2 power-on
Description
Select the signal that is connected to the REFMON pin.
Level or
Dynamic
Signal
Signal at REFMON Pin
4
3
2
1
0
0
0
0
0
0
LVL
Ground (dc) (default).
0
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
0
0
0
1
0
DYN
REF2 clock (N/A in differential mode).
0
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
0
0
1
0
0
DYN
Unselected reference to PLL (not available in differential mode).
0
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
0
0
1
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
0
0
1
1
1
LVL
Status REF1 frequency (active high).
0
1
0
0
0
LVL
Status REF2 frequency (active high).
0
1
0
0
1
LVL
(Status REF1 frequency) AND (status REF2 frequency).
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
0
1
0
1
1
LVL
Status of VCO frequency (active high).
0
1
1
0
0
LVL
Selected reference (low = REF1, high = REF2).
0
1
1
0
1
LVL
Digital lock detect (DLD); active low.
0
1
1
1
0
LVL
Holdover active (active high).
0
1
1
1
1
LVL
LD pin comparator output (active high).
1
0
0
0
0
LVL
VS (PLL supply).
1
0
0
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
0
1
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
LVL
LVL
LVL
LVL
LVL
Status of selected reference (status of differential reference); active low.
Status of unselected reference (not available in differential mode); active low.
Status of REF1 frequency (active low).
Status of REF2 frequency (active low).
(Status of REF1 frequency) AND (Status of REF2 frequency).
1
1
0
1
0
LVL
(DLD) AND (Status of selected reference) AND (Status of VCO).
1
1
0
1
1
LVL
Status of VCO frequency (active low).
1
1
1
0
0
LVL
Selected reference (low = REF2, high = REF1).
1
1
1
0
1
LVL
Digital lock detect (DLD); active low.
1
1
1
1
0
LVL
Holdover active (active low).
1
1
1
1
1
LVL
LD pin comparator output (active low).
Disable or enable the switchover deglitch circuit.
0: enable switchover deglitch circuit (default).
1: disable switchover deglitch circuit.
If Register 0x01C, Bit 5 = 0, select reference for PLL.
0: select REF1 (default).
1: select REF2.
If Register 0x01C, Bit 4 = 0 (manual), set method of PLL reference selection.
0: use Register 0x01C[6]. (default)
1: use REF_SEL pin.
Automatic or manual reference switchover. Single-ended reference mode must be selected by Register 0x01C, Bit 0 = 0.
0: manual reference switchover (default).
1: automatic reference switchover.
Stay on REF2 after switchover.
0: return to REF1 automatically when REF1 status is good again (default).
1: stay on REF2 after switchover. Do not automatically return to REF1.
When automatic reference switchover is disabled, this bit turns the REF2 power on.
0: REF2 power off (default).
1: REF2 power on.
Rev. A | Page 63 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x01C
0x01D
Bits
1
Name
REF1 power-on
0
Differential
reference
4
PLL status
register disable
3
LD pin comparator
enable
2
Holdover enable
1
External
holdover control
0x01F
0
Holdover enable
6
VCO cal finished
5
Holdover active
4
REF2 selected
3
VCO frequency >
threshold
2
REF2 frequency >
threshold
1
REF1 frequency >
threshold
0
Digital lock detect
Description
When automatic reference switchover is disabled, this bit turns the REF1 power on.
0: REF1 power off (default).
1: REF1 power on.
Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic
switchover or REF1 and REF2 to work.
0: single-ended reference mode (default).
1: differential reference mode.
Disables the PLL status register readback.
0: PLL status register enable (default).
1: PLL status register disable.
Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode. When in the
internal (automatic) holdover mode, this enables the use of the voltage on the LD pin to determine if the PLL was
previously in a locked state (see Figure 52). Otherwise, this can be used with the REFMON and STATUS pins to monitor
the voltage on this pin.
0: disable LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default).
1: enable LD pin comparator.
Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
0: automatic holdover mode—holdover controlled by automatic holdover circuit. (default)
1: external holdover mode—holdover controlled by SYNC pin.
Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration.
0: holdover disabled (default).
1: holdover enabled.
Read-only register: status of the VCO calibration.
0: VCO calibration not finished.
1: VCO calibration finished.
Read-only register: indicates if the part is in the holdover state (see Figure 52). This is not the same as holdover enabled.
0: not in holdover.
1: holdover state active.
Read-only register: Indicates which PLL reference is selected as the input to the PLL.
0: REF1 selected (or differential reference if in differential mode).
1: REF2 selected.
Read-only register: indicates if the VCO frequency is greater than the threshold (see Table 16, REF1, REF2, and VCO
frequency status monitor).
0: VCO frequency is less than the threshold.
1: VCO frequency is greater than the threshold.
Read-only register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by
Register 0x1A, Bit 6.
0: REF2 frequency is less than threshold frequency.
1: REF2 frequency is greater than threshold frequency.
Read-only register: indicates if the frequency of the signal at REF2 is greater than the threshold frequency
set by Register 0x01A, Bit 6.
0: REF1 frequency is less than threshold frequency.
1: REF1 frequency is greater than threshold frequency.
Read-only register: digital lock detect.
0: PLL is not locked.
1: PLL is locked.
Rev. A | Page 64 of 80
AD9517-4
Table 55. Fine Delay Adjust—OUT4 to OUT7
Reg.
Addr.
(Hex)
0x0A0
Bits
0
Name
OUT4 delay bypass
0x0A1
[5:3]
OUT4 ramp capacitors
[2:0]
OUT4 ramp current
0x0A2
[5:0]
OUT4 delay fraction
0x0A3
0
OUT5 delay bypass
0x0A4
[5:3]
OUT5 ramp capacitors
Description
Bypass or use the delay function.
0: use delay function.
1: bypass delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the
number of the capacitors and the ramp current sets the delay full scale.
5
4 3 Number of Capacitors
0
0 0 4 (default)
0
0 1 3
0
1 0 3
0
1 1 2
1
0 0 3
1
0 1 2
1
1 0 2
1
1 1 1
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1 0 Current (μA)
0
0 0 200 (default)
0
0 1 400
0
1 0 600
0
1 1 800
1
0 0 1000
1
0 1 1200
1
1 0 1400
1
1 1 1600
Selects the fraction of the full-scale delay desired (6-bit binary).
000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Bypass or use the delay function.
0: use delay function.
1: bypass delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the
number of the capacitors and the ramp current sets the delay full scale.
5
4 3 Number of Capacitors
0
0 0 4 (default)
0
0 1 3
0
1 0 3
0
1 1 2
1
0 0 3
1
0 1 2
1
1 0 2
1
1 1 1
Rev. A | Page 65 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x0A4
Bits
[2:0]
Name
OUT5 ramp current
0x0A5
[5:0]
OUT5 delay fraction
0x0A6
0
OUT6 delay bypass
0x0A7
[5:3]
OUT6 ramp capacitors
[2:0]
OUT6 ramp current
0x0A8
[5:0]
OUT6 delay fraction
0x0A9
0
OUT7 delay bypass
Description
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1
0
Current (μA)
0
0
0
200 (default)
0
0
1
400
0
1
0
600
0
1
1
800
1
0
0
1000
1
0
1
1200
1
1
0
1400
1
1
1
1600
Selects the fraction of the full-scale delay desired (6-bit binary).
000000 give zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Bypass or use the delay function.
0: use delay function.
1: bypass delay function (default).
Selects the number of ramp capacitors used by the delay function. The combination of the
number of capacitors and the ramp current sets the delay full scale.
5
4
3
Number of Capacitors
0
0
0
4 (default)
0
0
1
3
0
1
0
3
0
1
1
2
1
0
0
3
1
0
1
2
1
1
0
2
1
1
1
1
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1
0
Current (μA)
0
0
0
200 (default)
0
0
1
400
0
1
0
600
0
1
1
800
1
0
0
1000
1
0
1
1200
1
1
0
1400
1
1
1
1600
Selects the fraction of the full-scale delay desired (6-bit binary).
000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Bypass or use the delay function.
0: use delay function.
1: bypass delay function (default).
Rev. A | Page 66 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x0AA
0x0AB
Bits
[5:3]
Name
OUT7 ramp capacitors
[2:0]
OUT7 ramp current
[5:0]
OUT7 delay fraction
Description
Selects the number of ramp capacitors used by the delay function. The combination of the
number of capacitors and the ramp current sets the delay full scale.
5
4
3
Number of Capacitors
0
0
0
4 (default)
0
0
1
3
0
1
0
3
0
1
1
2
1
0
0
3
1
0
1
2
1
1
0
2
1
1
1
1
Ramp current for the delay function. The combination of the number of capacitors and the ramp
current sets the delay full scale.
2
1
0
Current Value (μA)
0
0
0
200 (default)
0
0
1
400
0
1
0
600
0
1
1
800
1
0
0
1000
1
0
1
1200
1
1
0
1400
1
1
1
1600
Selects the fraction of the full-scale delay desired (6-bit binary).
000000 gives zero delay.
Only delay values up to 47 decimals (101111b; 0x2F) are supported (default = 0x00).
Table 56. LVPECL Outputs
Reg.
Addr.
(Hex)
0x0F0
Bits
4
Name
OUT0 invert
[3:2]
OUT0 LVPECL
differential voltage
[1:0]
OUT0 power-down
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation (default).
0
1
Partial power-down, reference on;
use only if there are no external load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down.
1
1
Total power-down, reference off;
use only if there are no external load resistors.
Rev. A | Page 67 of 80
Output
On
Off
Off
Off
AD9517-4
Reg.
Addr.
(Hex)
0x0F1
0x0F4
0x0F5
Bits
4
Name
OUT1 invert
[3:2]
OUT1 LVPECL
differential voltage
[1:0]
OUT1 power-down
4
OUT2 invert
[3:2]
OUT2 LVPECL
differential voltage
[1:0]
OUT2 power-down
4
OUT3 invert
[3:2]
OUT3 LVPECL
differential voltage
[1:0]
OUT3 power-down
Description
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation.
0
1
Partial power-down, reference on; use only if there are no external load
resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down (default).
1
1
Total power-down, reference off; use only if there are no external load
resistors.
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation (default).
0
1
Partial power-down, reference on; use only if there are no external load
resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down.
1
1
Total power-down, reference off; use only if there are no external load
resistors.
Sets the output polarity.
0: noninverting (default).
1: inverting.
Sets the LVPECL output differential voltage (VOD).
3
2
VOD (mV)
0
0
400
0
1
600
1
0
780 (default)
1
1
960
LVPECL power-down modes.
1
0
Mode
0
0
Normal operation.
0
1
Partial power-down, reference on; use only if there are no external
load resistors.
1
0
Partial power-down, reference on, safe LVPECL power-down (default).
1
1
Total power-down, reference off; use only if there are no external
load resistors.
Rev. A | Page 68 of 80
Output
On
Off
Off
Off
Output
On
Off
Off
Off
Output
On
Off
Off
Off
AD9517-4
Table 57. LVDS/CMOS Outputs
Reg.
Addr.
(Hex)
0x140
0x141
Bits
[7:5]
Name
OUT4 output polarity
4
OUT4 CMOS B
3
OUT4 select LVDS/CMOS
[2:1]
OUT4 LVDS output current
0
OUT4 power-down
[7:5]
OUT5 output polarity
4
OUT5 CMOS B
3
OUT5 select LVDS/CMOS
[2:1]
OUT5 LVDS output current
Description
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7
6
5
OUT4A (CMOS)
OUT4B (CMOS)
OUT4 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.
0: turn off the CMOS B output (default).
1: turn on the CMOS B output.
Select LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Set output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Power-down output (LVDS/CMOS).
0: power on (default).
1: power off.
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7
6
5
OUT5A (CMOS)
OUT5B (CMOS)
OUT5 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.
0: turn off the CMOS B output (default).
1: turn on the CMOS B output.
Select LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Set output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Rev. A | Page 69 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x141
Bits
0
Name
OUT5 power-down
0x142
[7:5]
OUT6 output polarity
4
OUT6 CMOS B
3
OUT6 select LVDS/CMOS
[2:1]
OUT6 LVDS output current
0
OUT6 power-down
[7:5]
OUT7 output polarity
4
OUT7 CMOS B
3
OUT7 select LVDS/CMOS
0x143
Description
Power-down output (LVDS/CMOS).
0: power on.
1: power off (default).
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7
6
5
OUT6A (CMOS)
OUT6B (CMOS)
OUT6 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.
0: turn off the CMOS B output (default).
1: turn on the CMOS B output.
Select LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Set output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Power-down output (LVDS/CMOS).
0: power on (default).
1: power off.
In CMOS mode, Bits[7:5] select the output polarity of each CMOS output.
In LVDS mode, only Bit 5 determines LVDS polarity.
7
6
5
OUT7A (CMOS)
OUT7B (CMOS)
OUT7 (LVDS)
0
0
0
Noninverting
Inverting
Noninverting
0
1
0
Noninverting
Noninverting
Noninverting (default)
1
0
0
Inverting
Inverting
Noninverting
1
1
0
Inverting
Noninverting
Noninverting
0
0
1
Inverting
Noninverting
Inverting
0
1
1
Inverting
Inverting
Inverting
1
0
1
Noninverting
Noninverting
Inverting
1
1
1
Noninverting
Inverting
Inverting
In CMOS mode, turn on/off the CMOS B output. There is no effect in LVDS mode.
0: turn off the CMOS B output (default).
1: turn on the CMOS B output.
Select LVDS or CMOS logic levels.
0: LVDS (default).
1: CMOS.
Rev. A | Page 70 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x143
Bits
[2:1]
Name
OUT7 LVDS output current
0
OUT7 power-down
Description
Set output current level in LVDS mode. This has no effect in CMOS mode.
2
1
Current (mA)
Recommended Termination (Ω)
0
0
1.75
100
0
1
3.5
100 (default)
1
0
5.25
50
1
1
7
50
Power-down output (LVDS/CMOS).
0: power on.
1: power off (default).
Table 58. LVPECL Channel Dividers
Reg.
Addr.
(Hex)
0x190
0x191
0x192
0x196
0x197
Bits
[7:4]
Name
Divider 0 low cycles
[3:0]
Divider 0 high cycles
7
Divider 0 bypass
6
Divider 0 nosync
5
Divider 0 force high
4
Divider 0 start high
[3:0]
1
Divider 0 phase offset
Divider 0 direct to output
0
Divider 0 DCCOFF
[7:4]
Divider 1 low cycles
[3:0]
Divider 1 high cycles
7
Divider 1 bypass
6
Divider 1 nosync
5
Divider 1 force high
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays
low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays
high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypass and power-down the divider; route input to divider output.
0: use divider.
1: bypass divider (default).
Nosync.
0: obey chip-level SYNC signal (default).
1: ignore chip-level SYNC signal.
Force divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Selects clock output to start high or start low.
0: start low (default).
1: start high.
Phase offset (default = 0x0).
Connect OUT0 and OUT1 to Divider 0 or directly to VCO or CLK.
0: OUT0 and OUT1 are connected to Divider 0 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enable duty-cycle correction (default).
1: disable duty-cycle correction.
Number of clock cycles of the divider input during which divider output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of the divider input during which divider output stays
high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypass and power-down the divider; route input to divider output.
0: use divider (default).
1: bypass divider.
Nosync.
0: obey chip-level SYNC signal (default).
1: ignore chip-level SYNC signal.
Force divider output to high. This requires that nosync (Bit 6) also be set.
0: divider output forced to low (default).
1: divider output forced to high.
Rev. A | Page 71 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x197
Bits
4
Name
Divider 1 start high
0x198
[3:0]
1
Divider 1 phase offset
Divider 1 direct to output
0
Divider 1 DCCOFF
Description
Selects clock output to start high or start low.
0: start low (default).
1: start high.
Phase offset (default = 0x0).
Connect OUT2 and OUT3 to Divider 2 or directly to VCO or CLK.
0: OUT2 and OUT3 are connected to Divider 1 (default).
1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3.
If Register 0x1E1[1:0] = 01b, there is no effect.
Duty-cycle correction function.
0: enable duty-cycle correction (default).
1: disable duty-cycle correction.
Table 59. LVDS/CMOS Channel Dividers
Reg.
Addr.
(Hex)
0x199
Bits
[7:4]
Name
Low Cycles Divider 2.1
[3:0]
High Cycles Divider 2.1
0x19A
[7:4]
Phase Offset Divider 2.2
0x19B
[3:0]
[7:4]
Phase Offset Divider 2.1
Low Cycles Divider 2.2
[3:0]
High Cycles Divider 2.2
5
Bypass Divider 2.2
4
Bypass Divider 2.1
3
Divider 2 nosync
2
Divider 2 force high
1
Start High Divider 2.2
0
Start High Divider 2.1
0x19D
0
Divider 2 DCCOFF
0x19E
[7:4]
Low Cycles Divider 3.1
[3:0]
High Cycles Divider 3.1
0x19C
Description
Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 2.1 divider input during which 2.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 2.2 divider input during which 2.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1)of 2.2 divider input during which 2.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypass (and power-down) 2.2 divider logic, route clock to 2.2 output.
0: do not bypass (default).
1: bypass.
Bypass (and power-down) 2.1 divider logic, route clock to 2.1 output.
0: do not bypass (default).
1: bypass.
Nosync.
0: obey chip-level SYNC signal (default).
1: ignore chip-level SYNC signal.
Force Divider 2 output high. Requires that nosync also be set.
0: force low (default).
1: force high.
Divider 2.2 start high/low.
0: start low (default).
1: start high.
Divider 2.1 start high/low.
0: start low (default).
1: start high.
Duty-cycle correction function.
0: enable duty-cycle correction (default).
1: disable duty-cycle correction.
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 3.1 divider input during which 3.1 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Rev. A | Page 72 of 80
AD9517-4
Reg.
Addr.
(Hex)
0x19F
0x1A0
0x1A1
0x1A2
Bits
[7:4]
[3:0]
[7:4]
Name
Phase Offset Divider 3.2
Phase Offset Divider 3.1
Low Cycles Divider 3.2
[3:0]
High Cycles Divider 3.2
5
Bypass Divider 3.2
4
Bypass Divider 3.1
3
Divider 3 nosync
2
Divider 3 force high
1
Start High Divider 3.2
0
Start High Divider 3.1
0
Divider 3 DCCOFF
Description
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Refer to LVDS/CMOS channel divider function description (default = 0x0).
Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays low.
A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0).
Number of clock cycles (minus 1) of 3.2 divider input during which 3.2 output stays high.
A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0).
Bypass (and power-down) 3.2 divider logic; route clock to 3.2 output.
0: do not bypass (default).
1: bypass.
Bypass (and power-down) 3.1 divider logic; route clock to 3.1 output.
0: do not bypass (default).
1: bypass.
Nosync.
0: obey chip-level SYNC signal (default).
1: ignore chip-level SYNC signal.
Force Divider 3 output high. Requires that nosync also be set.
0: force low (default).
1: force high.
Divider 3.2 start high/low.
0: start low (default).
1: start high.
Divider 3.1 start high/low.
0: start low (default).
1: start high.
Duty-cycle correction function.
0: enable duty-cycle correction (default).
1: disable duty-cycle correction.
Rev. A | Page 73 of 80
AD9517-4
Table 60. VCO Divider and CLK Input
Reg.
Addr
(Hex)
0x1E0
Bits
[2:0]
Name
VCO divider
0x1E1
4
Power down clock input section
3
Power down VCO clock interface
2
Power down VCO and CLK
1
Select VCO or CLK
0
Bypass VCO divider
0x1E1
Description
2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
Divide
2.
3.
4 (default).
5.
6.
Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1 1 0 Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
1 1 1 Output static. Note that setting the VCO divider static should occur only
after VCO calibration.
Power down the clock input section (including CLK buffer, VCO divider, and CLK tree).
0: normal operation (default).
1: power-down.
Power down the interface block between VCO and clock distribution.
0: normal operation (default).
1: power-down.
Power down both VCO and CLK input.
0; normal operation (default).
1: power-down.
Select either the VCO or the CLK as the input to VCO divider.
0: select external CLK as input to VCO divider (default).
1: select VCO as input to VCO divider; cannot bypass VCO divider when this is selected.
Bypass or use the VCO divider.
0: use VCO divider (default).
1: bypass VCO divider; cannot select VCO as input when this is selected.
Table 61. System
Reg.
Addr.
(Hex)
0x230
Bits
2
Name
Power down SYNC
1
Power down distribution reference
0
Soft SYNC
Description
Power down the SYNC function.
0: normal operation of the SYNC function (default).
1: power down SYNC circuitry.
Power down the reference for distribution section.
0: normal operation of the reference for the distribution section (default).
1: power down the reference for the distribution section.
The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit
is reversed. That is, a high level forces selected channels into a predetermined static
state, and a 1-to-0 transition triggers a SYNC.
0: same as SYNC high (default).
1: same as SYNC low.
Table 62. Update All Registers
Reg.
Addr
(Hex)
0x232
Bits
0
Name
Update all registers
Description
This bit must be set to 1 to transfer the contents of the buffer registers into the active
registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is, it
does not have to be set back to 0.
1 (self-clearing): update all active registers to the contents of the buffer registers.
Rev. A | Page 74 of 80
AD9517-4
APPLICATIONS INFORMATION
The AD9517 has the following four frequency dividers: the
reference (or R) divider, the feedback (or N) divider, the VCO
divider, and the channel divider. When trying to achieve a
particularly difficult frequency divide ratio requiring a large
amount of frequency division, some of the frequency division
can be done by either the VCO divider or the channel divider,
thus allowing a higher phase detector frequency and more
flexibility in choosing the loop bandwidth.
Within the AD9517 family, lower VCO frequencies generally
result in slightly lower jitter. The difference in integrated jitter
(from 12 kHz to 20 MHz offset) for the same output frequency is
usually less than 150 fs over the entire VCO frequency range
(1.45 GHz to 2.95 GHz) of the AD9517 family. If the desired
frequency plan can be achieved with a version of the AD9517
that has a lower VCO frequency, choosing the lower frequency
part results in the lowest phase noise and the lowest jitter.
However, choosing a higher VCO frequency can result in more
flexibility in frequency planning.
⎛ 1
SNR(dB) = 20 × log ⎜
⎜ 2πf t
A J
⎝
⎞
⎟
⎟
⎠
where:
fA is the highest analog frequency being digitized.
tJ is the rms jitter on the sampling clock.
Figure 69 shows the required sampling clock jitter as a function
of the analog frequency and effective number of bits (ENOB).
110
1
SNR = 20log 2πf t
A J
100
18
16
90
tJ =
10
80
200
f
0f
S
14
S
400
f
70
S
12
1ps
60
2ps
10
10p
s
8
ENOB
The AD9517 is a highly flexible PLL. When choosing the PLL
settings and version of the AD9517, keep in mind the following
guidelines.
on the sampling clock. Considering an ideal ADC of infinite
resolution where the step size and quantization error can be
ignored, the available SNR can be expressed approximately by
SNR (dB)
FREQUENCY PLANNING USING THE AD9517
50
40
ADIsimCLK is a powerful PLL modeling tool that can be
downloaded from www.analog.com. It is a very accurate tool for
determining the optimal loop filter for a given application.
USING THE AD9517 OUTPUTS FOR ADC CLOCK
APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of its
sampling clock. An ADC can be thought of as a sampling mixer,
and any noise, distortion, or timing jitter on the clock is combined
with the desired signal at the analog-to-digital output. Clock
integrity requirements scale with the analog input frequency
and resolution, with higher analog input frequency applications
at ≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
30
10
100
fA (MHz)
1k
06428-044
6
Choosing a nominal charge pump current in the middle of the
allowable range as a starting point allows the designer to increase or
decrease the charge pump current, and thus allows the designer
to fine-tune the PLL loop bandwidth in either direction.
Figure 69. SNR and ENOB vs. Analog Input Frequency
See the AN-756 application note and the AN-501 application note
at www.analog.com for more information.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection that can provide
superior clock performance in a noisy environment.) The AD9517
features both LVPECL and LVDS outputs that provide differential clock outputs, which enable clock solutions that maximize
converter SNR performance. The input requirements of the ADC
(differential or single-ended, logic level, termination) should be
considered when selecting the best clocking/converter solution.
Rev. A | Page 75 of 80
AD9517-4
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9517 provide the lowest jitter
clock signals that are available from the AD9517. The LVPECL
outputs (because they are open emitter) require a dc termination
to bias the output transistors. The simplified equivalent circuit in
Figure 58 shows the LVPECL output stage.
In most applications, a LVPECL far-end Thevenin termination
(see Figure 70) or Y-termination (see Figure 71) is recommended.
In each case, the VS of the receiving buffer should match the
VS_LVPECL. If it does not, ac coupling is recommended (see
Figure 72).
VS_DRV
VS_LVPECL
VS
50Ω
LVPECL
127Ω
127Ω
SINGLE-ENDED
(NOT COUPLED)
LVPECL
50Ω
83Ω
06428-145
83Ω
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 71, where VS_LVPECL = 2.5 V, the 50 Ω
termination resistor that is connected to ground should be
changed to 19 Ω.
Thevenin-equivalent termination uses a resistor network to
provide 50 Ω termination to a dc voltage that is below VOL of
the LVPECL driver. In this case, VS_LVPECL on the AD9517
should equal VS of the receiving buffer. Although the resistor
combination shown in Figure 71 results in a dc bias point of
VS_LVPECL − 2 V, the actual common-mode voltage is
VS_LVPECL − 1.3 V because additional current flows from the
AD9517 LVPECL driver through the pull-down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that the
pull-down resistor is 62.5 Ω and the pull-up is 250 Ω.
Figure 70. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
LVDS CLOCK DISTRIBUTION
VS = 3.3V
Z0 = 50Ω
50Ω
The AD9517 provides four clock outputs (OUT4 to OUT7) that
are selectable as either CMOS or LVDS level outputs. LVDS is a
differential output option that uses a current mode output stage.
The nominal current is 3.5 mA, which yields 350 mV output swing
across a 100 Ω resistor. An output current of 7 mA is also available
in cases where a larger output swing is required. The LVDS
output meets or exceeds all ANSI/TIA/EIA-644 specifications.
50Ω
LVPECL
LVPECL
06428-147
50Ω
Z0 = 50Ω
Figure 71. DC-Coupled 3.3 V LVPECL Y-Termination
VS_LVPECL
VS
A recommended termination circuit for the LVDS outputs is
shown in Figure 73.
0.1nF
200Ω
100Ω DIFFERENTIAL
100Ω
(COUPLED)
0.1nF TRANSMISSION LINE
VS
LVPECL
200Ω
06428-146
LVPECL
LVDS
VS
100Ω
100Ω
DIFFERENTIAL (COUPLED)
LVDS
06428-047
VS_LVPECL
Figure 72. AC-Coupled LVPECL with Parallel Transmission Line
Figure 73. LVDS Output Termination
See the AN-586 application note at www.analog.com for more
information on LVDS.
Rev. A | Page 76 of 80
AD9517-4
The AD9517 provides four clock outputs (OUT4 to OUT7)
that are selectable as either CMOS or LVDS level outputs.
When selected as CMOS, each output becomes a pair of CMOS
outputs, each of which can be individually turned on or off and
set as noninverting or inverting. These outputs are 3.3 V CMOS
compatible.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be used.
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9517 do not supply enough current
to provide a full voltage swing with a low impedance resistive,
far-end termination, as shown in Figure 75. The far-end
termination network should match the PCB trace impedance and
provide the desired switching point. The reduced signal swing
may still meet receiver input requirements in some applications.
This can be useful when driving long trace lengths on less
critical nets.
VS
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net.
Series termination at the source is generally required to provide
transmission line matching and/or to reduce current transients
at the driver. The value of the resistor is dependent on the board
design and timing requirements (typically 10 Ω to 100 Ω is used).
CMOS outputs are also limited in terms of the capacitive load
or trace length that they can drive. Typically, trace lengths of less
than 3 inches are recommended to preserve signal rise/fall times
and preserve signal integrity.
CMOS
50Ω
100Ω
CMOS
Figure 75. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9517 offers both LVPECL and
LVDS outputs that are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
60.4Ω
(1.0 INCH)
MICROSTRIP
10Ω
100Ω
06428-076
CMOS
10Ω
CMOS
06428-077
CMOS CLOCK DISTRIBUTION
Figure 74. Series Termination of CMOS Output
Rev. A | Page 77 of 80
AD9517-4
OUTLINE DIMENSIONS
0.30
0.23
0.18
0.60 MAX
7.00
BSC SQ
0.60 MAX
37
36
PIN 1
INDICATOR
6.75
BSC SQ
48
1
0.50
BSC
*5.65
5.50 SQ
5.35
EXPOSED
PAD
(BOTTOM VIEW)
25
24
0.80 MAX
0.65 TYP
12° MAX
0.25 MIN
5.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
12
090209-A
TOP VIEW
1.00
0.85
0.80
13
0.50
0.40
0.30
PIN 1
INDICATOR
*COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
WITH EXCEPTION TO EXPOSED PAD DIMENSION.
Figure 76. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
CP-48-8
Dimensions shown in millimeters
7.00
BSC SQ
0.60 MAX
37
36
PIN 1
INDICATOR
0.50 BSC
5.25
5.10 SQ
4.95
(BOTTOM VIEW)
25
24
13
12
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
SEATING
PLANE
1
EXPOSED
PAD
6.75
BSC SQ
0.50
0.40
0.30
12° MAX
PIN 1
INDICATOR
48
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
080108-A
TOP
VIEW
1.00
0.85
0.80
0.30
0.23
0.18
0.60 MAX
Figure 77. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
CP-48-1
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9517-4ABCPZ 2
AD9517-4ABCPZ-RL72
AD9517-4BCPZ
AD9517-4BCPZ-REEL7
AD9517-4A/PCBZ2
AD9517-4/PCBZ
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
Recommended for use in new designs; reference PCN 09_156.
Rev. A | Page 78 of 80
Package Option
CP-48-8
CP-48-8
CP-48-1
CP-48-1
AD9517-4
NOTES
Rev. A | Page 79 of 80
AD9517-4
NOTES
©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06428-0-1/10(A)
Rev. A | Page 80 of 80
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