AD9518-4BCPZ

6-Output Clock Generator with Integrated 1.6 GHz VCO AD9518-4 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS CP REFIN REF2 CLK LF STATUS MONITOR PLL REF1 SWITCHOVER AND MONITOR Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.45 GHz to 1.80 GHz External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Auto and manual reference switchover/holdover modes Autorecover from holdover Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable 3 pairs of 1.6 GHz LVPECL outputs Each output pair shares a 1-to-32 divider with coarse phase delay Additive output jitter 225 fs rms Channel-to-channel skew paired outputs of 1600 MHz Section; Change to Table 21 ..........22 Changes to Table 23 ........................................................................24 Change to Configuration and Register Settings Section............25 Change to Phase Frequency Detector (PFD) Section ................26 Changes to Charge Pump (CP), On-Chip VCO, PLL External Loop Filter, and PLL Reference Inputs Sections .........27 Change to Figure 31; Added Figure 32 .........................................27 Changes to Reference Switchover and Prescaler Sections .........28 Changes to A and B Counters Section and Table 27 ..................29 Change to Holdover Section ..........................................................31 Changes to VCO Calibration Section ...........................................33 Changes to Clock Distribution Section........................................ 34 Change to Table 32; Change to Channel Frequency Division (0, 1, and 2) Section ........................................................ 35 Change to Write Section ................................................................ 40 Change to Figure 46 ........................................................................ 42 Added Thermal Performance Section; Added Table 41 ............ 44 Changes to 0x003 Register Address .............................................. 45 Changes to Table 43 ........................................................................ 47 Changes to Table 44 ........................................................................ 48 Changes to Table 45 ........................................................................ 55 Changes to Table 46 ........................................................................ 57 Changes to Table 47 ........................................................................ 58 Changes to Table 48 ........................................................................ 59 Added Frequency Planning Using the AD9518 Section ............ 60 Changes to LVDS Clock Distribution Section ............................ 61 Changes to Figure 52 and Figure 54; Added Figure 53 .............. 61 Added Exposed Paddle Notation to Outline Dimensions; Changes to Ordering Guide ........................................................... 62 9/07—Revision 0: Initial Version Rev. A | Page 3 of 64 AD9518-4 SPECIFICATIONS Typical (typ) is given for VS = VS_LVPECL = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation. POWER SUPPLY REQUIREMENTS Table 1. Parameter VS VS_LVPECL VCP RSET Pin Resistor CPRSET Pin Resistor Min 3.135 2.375 VS 2.7 BYPASS Pin Capacitor Typ 3.3 Max 3.465 VS 5.25 4.12 5.1 Unit V V V kΩ kΩ 220 nF Test Conditions/Comments 3.3 V ± 5% Nominally 2.5 V to 3.3 V ± 5% Nominally 3.3 V to 5.0 V ± 5% Sets internal biasing currents; connect to ground Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA); actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground Bypass for internal LDO regulator; necessary for LDO stability; connect to ground PLL CHARACTERISTICS Table 2. Parameter VCO (ON-CHIP) Frequency Range VCO Gain (KVCO) Tuning Voltage (VT) Min 1450 0.5 Test Conditions/Comments 1800 MHz MHz/V V See Figure 11 See Figure 6 VCP ≤ VS when using internal VCO; outside of this range, the CP spurs may increase due to CP up/down mismatch VCP − 0.5 0 MHz/V dBc/Hz dBc/Hz 250 250 MHz mV p-p 1.35 1.30 1.60 1.50 1.75 1.60 V V 4.0 4.4 4.8 5.3 5.9 6.4 kΩ kΩ 250 250 MHz MHz V p-p V V μA pF 20 0 0.8 2.0 0.8 +100 −100 2 PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency Antibacklash Pulse Width Unit 1 −109 −128 Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFIN Input Resistance, REFIN Input Resistance, REFIN Dual Single-Ended Mode (REF1, REF2) Input Frequency (AC-Coupled) Input Frequency (DC-Coupled) Input Sensitivity (AC-Coupled) Input Logic High Input Logic Low Input Current Input Capacitance Max 50 Frequency Pushing (Open-Loop) Phase Noise @ 100 kHz Offset Phase Noise @ 1 MHz Offset REFERENCE INPUTS Differential Mode (REFIN, REFIN) Input Frequency Typ 100 45 1.3 2.9 6.0 MHz MHz ns ns ns Rev. A | Page 4 of 64 f = 1625 MHz f = 1625 MHz Differential mode (can accommodate single-ended input by ac grounding undriven input) Frequencies below about 1 MHz should be dc-coupled; be careful to match VCM (self-bias voltage) PLL figure of merit (FOM) increases with increasingslew rate; see Figure 10 Self-bias voltage of REFIN 1 Self-bias voltage of REFIN1 Self-biased1 Self-biased1 Two single-ended CMOS-compatible inputs Slew rate > 50 V/μs Slew rate > 50 V/μs; CMOS levels Should not exceed VS p-p Each pin, REFIN/REFIN (REF1/REF2) Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash pulse width = 6.0 ns Register 0x017[1:0] = 01b Register 0x017[1:0] = 00b; Register 0x17[1:0] = 11b Register 0x017[1:0] = 10b AD9518-4 Parameter CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. CPV ICP vs. Temperature PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD P = 2 FD P = 3 FD P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM (16/17) P = 32 DM (32/33) Prescaler Output Frequency PLL DIVIDER DELAYS 000 001 010 011 100 101 110 111 NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/Phase Frequency Detector (In-Band Is Within the LBW of the PLL) @ 500 kHz PFD Frequency @ 1 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit (FOM) Min Typ Max 4.8 0.60 2.5 2.7/10 1 2 1.5 2 mA mA % kΩ nA % % % 300 600 900 600 1000 2400 3000 3000 300 Off 330 440 550 660 770 880 990 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz 1 2 Programmable With CPRSET = 5.1 kΩ CPV = VCP /2 V 0.5 < CPV < VCP − 0.5 V 0.5 < CPV < VCP − 0.5 V CPV = VCP /2 V A, B counter input frequency (prescaler input frequency divided by P) See Table 44, Register 0x019: R, Bits[5:3]; N, Bits[2:0] ps ps ps ps ps ps ps The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider) −165 −162 −151 −143 −220 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz 3.5 7.5 3.5 ns ns ns Reference slew rate > 0.25 V/ns; FOM +10 log(fPFD) is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed loop, the phase noise, as observed at the VCO output, is increased by 20 log(N) Signal available at LD, STATUS, and REFMON pins when selected by appropriate register settings Selected by Register 0x017[1:0] and Register 0x018[4] Register 0x017[1:0] = 00b, 01b,11b; Register 0x018[4] = 1b Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b Register 0x017[1:0] = 10b; Register 0x018[4] = 0b 7 15 11 ns ns ns Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b Register 0x017[1:0] = 10b; Register 0x018[4] = 0b PLL DIGITAL LOCK DETECT WINDOW 2 Required to Lock (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns) To Unlock After Lock (Hysteresis)2 Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6 ns) Test Conditions/Comments REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time. Rev. A | Page 5 of 64 AD9518-4 CLOCK INPUTS Table 3. Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min Typ 01 01 Input Sensitivity, Differential 1 Unit 2.4 1.6 GHz GHz mV p-p 2 V p-p 1.8 1.8 V V mV p-p kΩ pF 150 Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Max 1.3 1.3 3.9 1.57 150 4.7 2 5.7 Test Conditions/Comments Differential input High frequency distribution (VCO divider) Distribution only (VCO divider bypassed) Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Larger voltage swings may turn on the protection diodes and may degrade jitter performance Self-biased; enables ac coupling With 200 mV p-p signal applied; dc-coupled CLK ac-coupled; CLK ac-bypassed to RF ground Self-biased Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM. CLOCK OUTPUTS Table 4. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2, OUT3, OUT4, OUT5 Output Frequency, Maximum Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) Min Typ Max Unit Test Conditions/Comments Termination = 50 Ω to VS − 2 V Differential (OUT, OUT) Using direct to output; see Figure 16 2950 VS − 1.12 VS − 2.03 550 VS − 0.98 VS − 1.77 790 VS − 0.84 VS − 1.49 980 MHz V V mV Min Typ Max Unit 70 70 180 180 ps ps Test Conditions/Comments Termination = 50 Ω to VS − 2 V; level = 810 mV 20% to 80%, measured differentially 80% to 20%, measured differentially 835 995 1180 ps See Figure 27 773 933 0.8 1090 ps ps/°C See Figure 29 5 13 15 40 220 ps ps ps TIMING CHARACTERISTICS Table 5. Parameter LVPECL Output Rise Time, tRP Output Fall Time, tFP PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUTPUT High Frequency Clock Distribution Configuration Clock Distribution Configuration Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS1 LVPECL Outputs That Share the Same Divider LVPECL Outputs on Different Dividers All LVPECL Outputs Across Multiple Parts 1 This is the difference between any two similar delay paths while operating at the same voltage and temperature. Rev. A | Page 6 of 64 AD9518-4 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE Min CLK = 1 GHz, OUTPUT = 1 GHz Divider = 1 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset CLK = 1 GHz, OUTPUT = 200 MHz Divider = 5 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset Typ Max −109 −118 −130 −139 −144 −146 −147 −149 Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns −120 −126 −139 −150 −155 −157 −157 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED) Table 7. Parameter LVPECL ABSOLUTE PHASE NOISE VCO = 1800 MHz; OUTPUT = 1800 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 1625 MHz; OUTPUT = 1625 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 1450 MHz; OUTPUT = 1450 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset Min Typ Max Unit −47 −82 −106 −125 −142 −146 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −55 −85 −109 −128 −143 −147 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −61 −90 −113 −131 −144 −148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. A | Page 7 of 64 Test Conditions/Comments Internal VCO; direct to LVPECL output AD9518-4 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min VCO = 1475 MHz; LVPECL = 491.52 MHz; PLL LBW = 135 kHz Typ Max 135 275 145 275 170 305 VCO = 1475 MHz; LVPECL = 122.88 MHz; PLL LBW = 135 kHz VCO = 1475 MHz; LVPECL = 61.44 MHz; PLL LBW = 135 kHz Unit fs rms fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R = 1 Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER Min VCO = 1555 MHz; LVPECL = 155.52 MHz; PLL LBW = 500 Hz VCO = 1475 MHz; LVPECL = 122.88 MHz; PLL LBW = 500 Hz Typ Max 500 400 Unit fs rms fs rms Test Conditions/Comments Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 10.0 MHz; R = 20 Integration BW = 12 kHz to 20 MHz Integration BW = 12 kHz to 20 MHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO) Table 10. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER LVPECL = 245.76 MHz; PLL LBW = 125 Hz LVPECL = 122.88 MHz; PLL LBW = 125 Hz LVPECL = 61.44 MHz; PLL LBW = 125 Hz Min Typ Max 54 77 109 79 114 163 124 176 259 Rev. A | Page 8 of 64 Unit fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R=1 Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz AD9518-4 CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED) Table 11. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK = 622.08 MHz; LVPECL = 622.08 MHz; Divider = 1 CLK = 622.08 MHz; LVPECL = 155.52 MHz; Divider = 4 CLK = 1.6 GHz; LVPECL = 100 MHz; Divider = 16 CLK = 500 MHz; LVPECL = 100 MHz; Divider = 5 Min Typ Max Unit 40 fs rms Test Conditions/Comments Distribution section only; does not include PLL and VCO; uses rising edge of clock signal BW = 12 kHz to 20 MHz 80 fs rms BW = 12 kHz to 20 MHz 215 fs rms 245 fs rms Calculated from SNR of ADC method; DCC not used for even divides Calculated from SNR of ADC method; DCC on CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED) Table 12. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK = 2.4 GHz; VCO DIV = 2; LVPECL = 100 MHz; Divider = 12; Duty-Cycle Correction = Off Min Typ 210 Max Unit fs rms Rev. A | Page 9 of 64 Test Conditions/Comments Distribution section only; does not include PLL and VCO; uses rising edge of clock signal Calculated from SNR of ADC method AD9518-4 SERIAL CONTROL PORT Table 13. Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup and Hold, tS, tH CS Minimum Pulse Width High, tPWH Min Typ Max 2.0 0.8 3 110 2 Unit Test Conditions/Comments CS has an internal 30 kΩ pull-up resistor V V μA μA pF SCLK has an internal 30 kΩ pull-down resistor 2.0 0.8 110 1 2 2.0 0.8 10 20 2 2.7 0.4 25 16 16 2 1.1 8 2 3 V V μA μA pF V V nA nA pF V V MHz ns ns ns ns ns ns ns PD, SYNC, AND RESET PINS Table 14. Parameter INPUT CHARACTERISTICS Min Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low SYNC TIMING Pulse Width Low 2.0 Typ Max 0.8 110 1 2 Unit Test Conditions/Comments These pins each have a 30 kΩ internal pull-up resistor V V μA μA pF 50 ns 1.5 High speed clock cycles Rev. A | Page 10 of 64 High speed clock is CLK input signal AD9518-4 LD, STATUS, AND REFMON PINS Table 15. Parameter OUTPUT CHARACTERISTICS Min Output Voltage High (VOH) Output Voltage Low (VOL) MAXIMUM TOGGLE RATE 2.7 Max Unit 0.4 100 V V MHz 3 pF On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor 1.02 MHz 8 kHz Frequency above which the monitor indicates the presence of the reference Frequency above which the monitor indicates the presence of the reference ANALOG LOCK DETECT Capacitance REF1, REF2, AND VCO FREQUENCY STATUS MONITOR Normal Range Extended Range (REF1 and REF2 Only) LD PIN COMPARATOR Trip Point Hysteresis Typ 1.6 260 Test Conditions/Comments When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 44, Register 0x017, Register 0x01A, and Register 0x01B Applies when mux is set to any divider or counter output, or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs may couple to output when any of these pins are toggling V mV POWER DISSIPATION Table 16. Parameter POWER DISSIPATION, CHIP Power-On Default Typ Max Unit Test Conditions/Comments 0.76 1.0 W Full Operation 1.1 1.7 W PD Power-Down 75 185 mW PD Power-Down, Maximum Sleep 31 No clock; no programming; default register values; does not include power dissipated in external resistors PLL on; internal VCO = 1625 MHz; VCO divider = 2; all channel dividers on; six LVPECL outputs @ 406 MHz; does not include power dissipated in external resistors PD pin pulled low; does not include power dissipated in terminations PD pin pulled low; PLL power-down 0x10 = 01b; SYNC power-down 0x230 = 1b; REF for distribution power-down 0x230 = 1b PLL operating; typical closed-loop configuration Power delta when a function is enabled/disabled VCO divider not used All references off to differential reference enabled All references off to REF1 or REF2 enabled; differential reference not enabled CLK input selected to VCO selected PLL off to PLL on, normal operation; no reference enabled Divider bypassed to divide-by-2 to divide-by-32 No LVPECL output on to one LVPECL output on Second LVPECL output turned on, same channel VCP Supply POWER DELTAS, INDIVIDUAL FUNCTIONS VCO Divider REFIN (Differential) REF1, REF2 (Single-Ended) Min 4 mW 4.8 mW 30 20 4 mW mW mW VCO PLL 70 75 mW mW Channel Divider LVPECL Channel (Divider Plus Output Driver) LVPECL Driver 30 160 90 mW mW mW Rev. A | Page 11 of 64 AD9518-4 TIMING DIAGRAMS DIFFERENTIAL tCLK 80% CLK 20% tRP tFP Figure 3. LVPECL Timing, Differential Figure 2. CLK/CLK to Clock Output Timing, DIV = 1 Rev. A | Page 12 of 64 06433-061 tPECL 06433-060 LVPECL AD9518-4 ABSOLUTE MAXIMUM RATINGS Table 17. Parameter VS, VS_LVPECL to GND VCP to GND REFIN, REFIN to GND REFIN to REFIN RSET to GND CPRSET to GND CLK, CLK to GND CLK to CLK SCLK, SDIO, SDO, CS to GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3,OUT4, OUT4, OUT5, OUT5 to GND SYNC to GND REFMON, STATUS, LD to GND Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec) 1 Rating −0.3 V to +3.6 V −0.3 V to +5.8 V −0.3 V to VS + 0.3 V −3.3 V to +3.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −1.2 V to +1.2 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE Table 18. Package Type1 48-Lead LFCSP 1 −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V 150°C −65°C to +150°C 300°C θJA 24.7 Unit °C/W Thermal impedance measurements were taken on a 4-layer board in still air in accordance with EIA/JESD51-2. ESD CAUTION See Table 18 for θJA. Rev. A | Page 13 of 64 AD9518-4 1 37 VS 38 OUT1 39 OUT1 40 VS_LVPECL 41 OUT0 42 OUT0 44 RSET 45 VS 46 CPRSET 43 VS 36 PIN 1 INDICATOR 2 35 3 34 4 33 5 32 6 AD9518-4 31 7 TOP VIEW (Not to Scale) 30 8 NC VS GND OUT2 OUT2 VS_LVPECL VS_LVPECL 29 OUT3 OUT3 27 GND 26 VS 25 VS 28 9 10 11 06433-003 24 23 22 21 20 19 18 17 16 15 SCLK CS SDO SDIO RESET PD OUT4 OUT4 VS_LVPECL OUT5 OUT5 VS 14 12 13 REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS VS CLK CLK 47 REFIN (REF2) 48 REFIN (REF1) PIN CONFIGURATION AND FUNCTION DESCRIPTIONS NOTES 1. NC = NO CONNECT. 2. THE EXTERNAL PADDLE ON THE BOTTOM OF THE PACKAGE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. Figure 4. Pin Configuration Table 19. Pin Function Descriptions Pin No. 1 Input/ Output I Pin Type 3.3 V CMOS Mnemonic REFMON 2 O 3.3 V CMOS LD 3 4 5 6 I O O I Power 3.3 V CMOS 3.3 V CMOS VCP CP STATUS REF_SEL 7 I 3.3 V CMOS SYNC 8 I Loop filter LF 9 10, 24, 25, 26, 35, 37, 43, 45 11 O I Loop filter Power BYPASS VS Description Reference Monitor (Output). This pin has multiple selectable outputs; see Table 44, Register 0x1B. Lock Detect (Output). This pin has multiple selectable outputs; see Table 44, Register 0x1A. Power Supply for Charge Pump (CP). VS ≤ VCP ≤ 5.0 V. Charge Pump (Output). Connects to external loop filter. Status (Output). This pin has multiple selectable outputs; see Table 44, Register 0x17. Reference Select. Selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor. Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is also used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. Loop Filter (Input). Connects to VCO control voltage node internally. This pin has 31 pF of internal capacitance to ground, which may influence the loop filter design for large loop bandwidths. This pin is for bypassing the LDO to ground with a capacitor. 3.3 V Power Pins. I CLK Along with CLK, this is the self-biased differential input for the clock distribution section. 12 I Differential clock input Differential clock input CLK Along with CLK, this is the self-biased differential input for the clock distribution section. Rev. A | Page 14 of 64 AD9518-4 Pin No. 13 14 Input/ Output I I Pin Type 3.3 V CMOS 3.3 V CMOS Mnemonic SCLK CS O I/O I I O O I 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS LVPECL LVPECL Power SDO SDIO RESET PD OUT4 OUT4 VS_LVPECL Description Serial Control Port Data Clock Signal. Serial Control Port Chip Select, Active Low. This pin has an internal 30 kΩ pull-up resistor. Serial Control Port Unidirectional Serial Data Out. Serial Control Port Bidirectional Serial Data In/Out. Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor. Chip Power Down, Active Low. This pin has an internal 30 kΩ pull-up resistor. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. Extended Voltage 2.5 V to 3.3 V LVPECL Power Pins. O O LVPECL LVPECL GND LVPECL LVPECL LVPECL LVPECL OUT5 OUT5 GND OUT3 OUT3 OUT2 OUT2 NC OUT1 OUT1 OUT0 OUT0 RSET LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. Ground. See the description for EPAD. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. No Connection. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. LVPECL Output; One Side of a Differential LVPECL Output. Resistor connected here sets internal bias currents. Nominal value = 4.12 kΩ. CPRSET Resistor connected here sets the CP current range. Nominal value = 5.1 kΩ. REFIN (REF2) Along with REFIN, this is the (self-biased) differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2. Along with REFIN, this is the (self-biased) differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. Ground. The external paddle on the bottom of the package must be connected to ground for proper operation. 15 16 17 18 19 20 21, 30, 31, 40 22 23 27, 34 28 29 32 33 36 38 39 41 42 44 O O O O O 46 O 47 I 48 I EPAD O O O O LVPECL LVPECL LVPECL LVPECL Current set resistor Current set resistor Reference input Reference input GND REFIN (REF1) GND Rev. A | Page 15 of 64 AD9518-4 TYPICAL PERFORMANCE CHARACTERISTICS 300 5.0 3 CHANNELS—6 LVPECL 280 4.5 220 3 CHANNELS—3 LVPECL 180 160 2 CHANNELS—2 LVPECL 140 3.5 PUMP DOWN 3.0 2.5 2.0 1.5 1.0 1 CHANNEL—1 LVPECL 0 500 1000 1500 2000 2500 0 06433-007 100 3000 FREQUENCY (MHz) 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VOLTAGE ON CP PIN (V) Figure 5. Current vs. Frequency, Direct-to-Output, LVPECL Outputs Figure 8. Charge Pump Characteristics @ VCP = 5.0 V –140 45 40 35 30 20 1.45 1.55 1.65 1.75 VCO FREQUENCY (GHz) –150 –155 –160 –165 –170 0.1 06433-200 25 –145 1 10 100 PFD FREQUENCY (MHz) Figure 6. KVCO vs. VCO Frequency 06433-013 PFD PHASE NOISE REFERRED TO PFD INPUT (dBc/Hz) 50 KVCO (MHz/V) 0.5 06433-012 0.5 120 Figure 9. PFD Phase Noise Referred to PFD Input vs. PFD Frequency –210 5.0 4.5 PLL FIGURE OF MERIT (dBc/Hz) –212 4.0 3.5 PUMP DOWN PUMP UP 3.0 2.5 2.0 1.5 1.0 –214 –216 –218 –220 –222 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 VOLTAGE ON CP PIN (V) 06433-011 CURRENT FROM CP PIN (mA) PUMP UP Figure 7. Charge Pump Characteristics @ VCP = 3.3 V –224 0 0.5 1.0 1.5 2.0 2.5 SLEW RATE (V/ns) Figure 10. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN Rev. A | Page 16 of 64 06433-136 CURRENT (mA) 240 200 4.0 CURRENT FROM CP PIN (mA) 260 AD9518-4 1.0 DIFFERENTIAL OUTPUT (V) VCO TUNING VOLTAGE (V) 1.9 1.7 1.5 1.3 1.1 1.50 1.55 1.60 1.65 1.70 1.75 1.80 FREQUENCY (GHz) 0.2 –0.2 –0.6 –1.0 06433-201 0.9 1.45 0.6 0 5 10 15 20 25 TIME (ns) Figure 11. VCO Tuning Voltage vs. Frequency 06433-014 2.1 Figure 14. LVPECL Output (Differential) @ 100 MHz 10 1.0 0 DIFFERENTIAL OUTPUT (V) RELATIVE POWER (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 0.6 0.2 –0.2 –0.6 CENTER 122.88MHz 5MHz/DIV SPAN 50MHz –1.0 0 1 2 TIME (ns) Figure 12. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz; LBW = 135 kHz; ICP = 3 mA; fVCO = 1.475 GHz 06433-015 –110 06433-202 –100 Figure 15. LVPECL Output (Differential) @ 1600 MHz 10 1600 0 DIFFERENTIAL SWING (mV p-p) RELATIVE POWER (dB) –10 –20 –30 –40 –50 –60 –70 –80 –90 1400 1200 1000 CENTER 122.88MHz 100kHz/DIV SPAN 1MHz 800 0 1 2 FREQUENCY (GHz) Figure 13. Output Spectrum, LVPECL; 122.88 MHz; PFD = 15.36 MHz; LBW = 135 kHz; ICP = 3 mA; fVCO = 1.475 GHz Rev. A | Page 17 of 64 Figure 16. LVPECL Differential Swing vs. Frequency 3 06433-020 –110 06433-203 –100 –80 –120 –90 –125 –100 PHASE NOISE (dBc/Hz) –110 –120 –130 –140 –135 –140 –145 –150 –155 100k 1M 10M 100M FREQUENCY (Hz) –160 10 06433-205 –150 10k –130 Figure 17. Internal VCO Phase Noise (Absolute) Direct to LVPECL @1800 MHz 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) 06433-026 PHASE NOISE (dBc/Hz) AD9518-4 Figure 20. Phase Noise (Additive) LVPECL @ 245.76 MHz, Divide-by-1 –80 –110 –90 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –120 –100 –110 –120 –130 –130 –140 –150 10k 1M 10M 100M FREQUENCY (Hz) –160 10 06433-206 –150 10k 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 18. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 1625 MHz 06433-027 –140 Figure 21. Phase Noise (Additive) LVPECL @ 200 MHz, Divide-by-5 –80 –100 –90 PHASE NOISE (dBc/Hz) PHASE NOISE (dBc/Hz) –110 –100 –110 –120 –130 –120 –130 –140 100k 1M FREQUENCY (Hz) 10M 100M Figure 19. Internal VCO Phase Noise (Absolute) Direct to LVPECL @ 1450 MHz Rev. A | Page 18 of 64 –150 10 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 22. Phase Noise (Additive) LVPECL @ 1600 MHz, Divide-by-1 06433-128 –150 10k 06433-207 –140 –120 –130 –130 –140 –150 –160 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) Figure 23. Phase Noise (Absolute) Clock Generation; Internal VCO @ 1.475 GHz; PFD = 15.36 MHz; LBW = 135 kHz; LVPECL Output = 122.88 MHz PHASE NOISE (dBc/Hz) –120 –130 –140 1M 10M 100M 06433-209 –150 100k 100k 1M 10M 100M Figure 25. Phase Noise (Absolute); External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVPECL Output = 245.76 MHz –110 FREQUENCY (Hz) 10k FREQUENCY (Hz) –100 10k –150 –160 1k –90 –160 1k –140 06433-140 PHASE NOISE (dBc/Hz) –120 06433-208 PHASE NOISE (dBc/Hz) AD9518-4 Figure 24. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 1.556 GHz; PFD = 19.44 MHz; LBW = 12.8 kHz; LVPECL Output = 155.52 MHz Rev. A | Page 19 of 64 AD9518-4 TERMINOLOGY Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in units of seconds root mean square (rms) or 1 sigma of the Gaussian distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in dB) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. Additive Phase Noise It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. A | Page 20 of 64 AD9518-4 DETAILED BLOCK DIAGRAM REF_ SEL VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS R DIVIDER STATUS REFIN (REF1) PLL REFERENCE LOCK DETECT REF2 PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS CPRSET VCP LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 OUT0 DIVIDE BY 1 TO 32 PD SYNC 0 OUT0 LVPECL OUT1 DIGITAL LOGIC OUT1 RESET OUT2 DIVIDE BY 1 TO 32 OUT3 SERIAL CONTROL PORT OUT3 OUT4 DIVIDE BY 1 TO 32 OUT4 LVPECL OUT5 OUT5 AD9518-4 Figure 26. Detailed Block Diagram Rev. A | Page 21 of 64 06433-002 SCLK SDIO SDO CS OUT2 LVPECL AD9518-4 THEORY OF OPERATION OPERATIONAL CONFIGURATIONS Table 20. Default Settings of Some PLL Registers The AD9518 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 42 and Table 43 through Table 49). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. Register 0x010[1:0] = 01b 0x1E0[2:0] = 010b 0x1E1[0] = 0b 0x1E1[1] = 0b High Frequency Clock Distribution—CLK or External VCO > 1600 MHz When using the internal PLL with an external VCO, the PLL must be turned on. The AD9518 power-up default configuration has the PLL powered off and the routing of the input set so that the CLK/CLK input is connected to the distribution section through the VCO divider (divide-by-2/ divide-by-3/divide-by-4/ divide-by-5/divide-by-6). This is a distribution-only mode that allows for an external input up to 2.4 GHz (see Table 3). The maximum frequency that can be applied to the channel dividers is 1600 MHz; therefore, higher input frequencies must be divided down before reaching the channel dividers. This input routing can also be used for lower input frequencies, but the minimum divide is 2 before the channel dividers. When the PLL is enabled, this routing also allows the use of the PLL with an external VCO or VCXO with a frequency of less than 2400 MHz. In this configuration, the internal VCO is not used and is powered off. The external VCO/VCXO feeds directly into the prescaler. The register settings shown in Table 20 are the default values of these registers at power-up or after a reset operation. If the contents of the registers are altered by prior programming after power-up or reset, these registers can also be set intentionally to these values. Function PLL asynchronous power-down (PLL off ). Set VCO divider = 4. Use the VCO divider. CLK selected as the source. Table 21. Settings When Using an External VCO Register 0x010[1:0] = 00b 0x010 to 0x01E 0x1E1[1] = 0b Function PLL normal operation (PLL on). PLL settings. Select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP, according to the intended loop configuration. CLK selected as the source. An external VCO requires an external loop filter that must be connected between CP and the tuning pin of the VCO. This loop filter determines the loop bandwidth and stability of the PLL. Make sure to select the proper PFD polarity for the VCO being used. Table 22. Setting the PFD Polarity Register 0x010[7] = 0b 0x010[7] = 1b After the appropriate register values are programmed, Register 0x232 must be set to 0x01 for the values to take effect. Rev. A | Page 22 of 64 Function PFD polarity positive (higher control voltage produces higher frequency). PFD polarity negative (higher control voltage produces lower frequency). AD9518-4 REF_ SEL VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS R DIVIDER STATUS REFIN (REF1) PLL REFERENCE LOCK DETECT REF2 PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS CPRSET VCP LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 OUT0 DIVIDE BY 1 TO 32 PD SYNC 0 OUT0 LVPECL OUT1 DIGITAL LOGIC OUT1 RESET OUT2 DIVIDE BY 1 TO 32 OUT3 SERIAL CONTROL PORT OUT3 OUT4 DIVIDE BY 1 TO 32 OUT4 LVPECL OUT5 AD9518-4 OUT5 Figure 27. High Frequency Clock Distribution or External VCO >1600 MHz Rev. A | Page 23 of 64 06433-029 SCLK SDIO SDO CS OUT2 LVPECL AD9518-4 Internal VCO and Clock Distribution Table 23. Settings When Using Internal VCO When using the internal VCO and PLL, the VCO divider must be employed to ensure that the frequency presented to the channel dividers does not exceed its specified maximum frequency (1.6 GHz, see Table 3). The internal PLL uses an external loop filter to set the loop bandwidth. The external loop filter is also crucial to the loop stability. Register 0x010[1:0] = 00b 0x010 to 0x01E When using the internal VCO, it is necessary to calibrate the VCO (Register 0x018[0]) to ensure optimal performance. For internal VCO and clock distribution applications, the register settings shown in Table 23 should be used. 0x018[0] = 0b, 0x232[0] = 1b 0x1E0[2:0] 0x1E1[0] = 0b 0x1E1[1] = 1b 0x018[0] = 1b, 0x232[0] = 1b REF_ SEL VS GND RSET REFMON CPRSET VCP DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS R DIVIDER STATUS REFIN (REF1) PLL REFERENCE LOCK DETECT REF2 PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS Function PLL normal operation (PLL on). PLL settings. Select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration. Reset VCO calibration. This process is not required the first time after power-up, but it must be performed subsequently. Set VCO divider to divide-by-2, divide-by-3, divide-by-4, divide-by-5, or divide-by-6. Use the VCO divider as source for the distribution section. Select VCO as the source. Initiate VCO calibration. LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 OUT0 DIVIDE BY 1 TO 32 PD SYNC 0 OUT0 LVPECL OUT1 DIGITAL LOGIC OUT1 RESET OUT2 DIVIDE BY 1 TO 32 OUT3 SERIAL CONTROL PORT OUT3 OUT4 DIVIDE BY 1 TO 32 OUT4 LVPECL OUT5 OUT5 AD9518-4 Figure 28. Internal VCO and Clock Distribution Rev. A | Page 24 of 64 06433-030 SCLK SDIO SDO CS OUT2 LVPECL AD9518-4 REF_ SEL VS GND RSET REFMON DISTRIBUTION REFERENCE REFERENCE SWITCHOVER LD REF1 STATUS R DIVIDER STATUS REFIN (REF1) PLL REFERENCE LOCK DETECT REF2 PROGRAMMABLE R DELAY VCO STATUS REFIN (REF2) BYPASS CPRSET VCP LOW DROPOUT REGULATOR (LDO) P, P + 1 PRESCALER A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP CP N DIVIDER LF VCO STATUS DIVIDE BY 2, 3, 4, 5, OR 6 CLK CLK 1 0 OUT0 DIVIDE BY 1 TO 32 PD SYNC OUT0 LVPECL OUT1 DIGITAL LOGIC OUT1 RESET OUT2 DIVIDE BY 1 TO 32 SCLK SDIO SDO CS OUT2 LVPECL OUT3 SERIAL CONTROL PORT OUT3 OUT4 DIVIDE BY 1 TO 32 OUT4 LVPECL OUT5 OUT5 06433-028 AD9518-4 Figure 29. Clock Distribution or External VCO threshold Blank 0xE3 0x00 0x00 REF2 power-on REF1 power-on Differential reference 0x00 Holdover enable External holdover control Holdover enable 0x00 REF2 frequency > threshold REF1 frequency > threshold Digital lock detect 0x00 N/A AD9518-4 Reg. Addr. (Hex) Parameter LVPECL Outputs 0x0F0 OUT0 Bit 7 (MSB) Bit 6 Bit 5 Blank 0x0F1 OUT1 Blank 0x0F2 OUT2 Blank 0x0F3 OUT3 Blank 0x0F4 OUT4 Blank 0x0F5 OUT5 Blank Divider 1 (PECL) 0x194 Divider 1 bypass 0x197 Divider 1 force high Blank Divider 2 (PECL) Divider 2 bypass 0x199 to 0x1A3 0x1A4 to 0x1DF VCO Divider and CLK Input 0x1E0 VCO divider 0x1E1 Input CLKs Divider 2 force high Bit 0 (LSB) OUT0 power-down 0x08 OUT1 power-down 0x0A OUT2 power-down 0x08 OUT3 power-down 0x0A OUT4 power-down 0x08 OUT5 power-down 0x0A Reserved Blank Divider 0 start high Reserved Divider 1 start high Divider 0 high cycles 0x00 Divider 0 phase offset 0x80 Divider 0 direct to output Divider 1 high cycles Divider 0 DCCOFF Divider 2 start high Reserved Divider 1 direct to output Divider 2 high cycles 0x00 Divider 1 DCCOFF 0x00 0x00 Divider 2 phase offset Divider 2 direct to output 0x00 0xBB Divider 1 phase offset Reserved Divider 2 nosync Blank Bit 1 Blank Divider 2 low cycles 0x198 0x1E2 to 0x22A Divider 1 nosync Bit 2 OUT0 LVPECL differential voltage OUT1 LVPECL differential voltage OUT2 LVPECL differential voltage OUT3 LVPECL differential voltage OUT4 LVPECL differential voltage OUT5 LVPECL differential voltage Divider 1 low cycles 0x195 0x196 Bit 3 OUT0 invert OUT1 invert OUT2 invert OUT3 invert OUT4 invert OUT5 invert 0x0F6 to 0x13F 0x140 to 0x143 0x144 to 0x18F LVPECL Channel Dividers 0x190 Divider 0 Divider 0 low cycles (PECL) 0x191 Divider 0 Divider 0 Divider 0 bypass nosync force high 0x192 Blank 0x193 Bit 4 Default Value (Hex) 0x00 Divider 2 DCCOFF 0x00 Reserved Blank Blank Reserved Reserved Power down Power VCO clock down interface clock input section Blank Rev. A | Page 46 of 64 Power down VCO and CLK VCO Divider Select Bypass VCO VCO or CLK divider 0x02 0x00 AD9518-4 Reg. Addr. (Hex) Parameter System 0x230 Power-down and SYNC Bit 7 (MSB) 0x231 Update All Registers 0x232 Update all registers Bit 6 Bit 5 Bit 4 Bit 3 Reserved Bit 1 Bit 0 (LSB) Default Value (Hex) Power down distribution reference Reserved Soft SYNC 0x00 Bit 2 Power down SYNC Blank Blank 0x00 Update all registers (self-clearing bit) 0x00 CONTROL REGISTER MAP DESCRIPTIONS Table 43 through Table 49 provide a detailed description of each of the control register functions. The registers are listed by hexadecimal address. A range of bits (for example, from Bit 5 through Bit 2) is indicated using a colon and brackets, as follows: [5:2]. Table 43. Serial Port Configuration and Part ID Reg. Addr (Hex) 0x000 Bits [7:4] Name Mirrored, Bits[3:0] 3 Long instruction 2 Soft reset 1 LSB first 0 SDO active 0x003 [7:0] Part ID (read only) 0x004 0 Read back active registers Description Bits[7:4] should always mirror Bits[3:0] so that it does not matter whether the part is in MSB or LSB first mode (see Bit 1, Register 0x000). The user should set the bits as follows: Bit 7 = Bit 0. Bit 6 = Bit 1. Bit 5 = Bit 2. Bit 4 = Bit 3. Short/long instruction mode. This part uses long instruction mode only, so this bit should always be set to 1. 0: 8-bit instruction (short). 1: 16-bit instruction (long) (default). Soft reset. 1: soft reset; restores default values to internal registers. Not self-clearing. Must be cleared to 0 to complete reset operation. MSB or LSB data orientation. 0: data-oriented MSB first; addressing decrements (default). 1: data-oriented LSB first; addressing increments. Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin used for write and read; SDO set to high impedance; bidirectional mode (default). 1: SDO used for read, SDIO used for write; unidirectional mode. Uniquely identifies the dash version (-0 through -4) of the AD9518. AD9518-0: 0x21. AD9518-1: 0x61. AD9518-2: 0xA1. AD9518-3: 0x63. AD9518-4: 0xE3. Selects register bank used for a readback. 0: reads back buffer registers (default). 1: reads back active registers. Rev. A | Page 47 of 64 AD9518-4 Table 44. PLL Reg. Addr. (Hex) 0x010 Bits 7 Name PFD polarity [6:4] CP current [3:2] CP mode [1:0] PLL powerdown 0x011 [7:0] 0x012 [5:0] 0x013 0x014 [5:0] [7:0] 0x015 [4:0] 0x016 7 14-bit R divider, Bits[7:0] (LSB) 14-bit R divider, Bits[13:8] (MSB) 6-bit A counter 13-bit B counter, Bits[7:0] (LSB) 13-bit B counter, Bits[12:8] (MSB) Set CP pin to VCP/2 6 Reset R counter 5 Reset A, B counters 4 Reset all counters 3 B counter bypass Description Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires positive polarity; Bit 7 = 0. 0: positive; higher control voltage produces higher frequency (default). 1: negative; higher control voltage produces lower frequency. Charge pump current (with CPRSET = 5.1 kΩ). 6 5 4 ICP (mA) 0 0 0 0.6. 0 0 1 1.2. 0 1 0 1.8. 0 1 1 2.4. 1 0 0 3.0. 1 0 1 3.6. 1 1 0 4.2. 1 1 1 4.8 (default). Charge pump operating mode. 3 2 Charge Pump Mode 0 0 High impedance state. 0 1 Force source current (pump up). 1 0 Force sink current (pump down). 1 1 Normal operation (default). PLL operating mode. 1 0 Mode 0 0 Normal operation. 0 1 Asynchronous power-down (default). 1 0 Normal operation. 1 1 Synchronous power-down. R divider LSBs—lower eight bits (default = 0x01). R divider MSBs—upper six bits (default = 0x00). A counter (part of N divider) (default = 0x00). B counter (part of N divider)—lower eight bits (default = 0x03). B counter (part of N divider)—upper five bits (default = 0x00). Sets the CP pin to one-half of the VCP supply voltage. 0: CP normal operation (default). 1: CP pin set to VCP/2. Resets R counter (R divider). 0: normal (default). 1: holds the R counter in reset. Resets A and B counters (part of N divider). 0: normal (default). 1: holds the A and B counters in reset. Resets R, A, and B counters. 0: normal (default). 1: holds the R, A, and B counters in reset. B counter bypass. This is valid only when operating the prescaler in FD mode. 0: normal (default). 1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider. Rev. A | Page 48 of 64 AD9518-4 Reg. Addr. (Hex) 0x016 0x017 Bits [2:0] [7:2] Name Prescaler P STATUS pin control Description Prescaler: DM = dual modulus and FD = fixed divide. 2 1 0 Mode Prescaler 0 0 0 FD Divide-by-1. 0 0 1 FD Divide-by-2. 0 1 0 DM Divide-by-2 (2/3 mode). 0 1 1 DM Divide-by-4 (4/5 mode). 1 0 0 DM Divide-by-8 (8/9 mode). 1 0 1 DM Divide-by-16 (16/17 mode). 1 1 0 DM Divide-by-32 (32/33 mode) (default). 1 1 1 FD Divide-by-3. Selects the signal that is connected to the STATUS pin. Level or Dynamic Signal Signal at STATUS Pin 7 6 5 4 3 2 0 0 0 0 0 0 LVL Ground (dc) (default). 0 0 0 0 0 1 DYN N divider output (after the delay). 0 0 0 0 1 0 DYN R divider output (after the delay). 0 0 0 0 1 1 DYN A divider output. 0 0 0 1 0 0 DYN Prescaler output. 0 0 0 1 0 1 DYN PFD up pulse. 0 0 0 1 1 0 DYN PFD down pulse. 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified above. The selections that follow are the same as REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency; active high. 1 0 1 0 0 0 LVL Status REF2 frequency; active high. 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency; active high. 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL Digital lock detect (DLD); active high. 1 0 1 1 1 0 LVL Holdover active; active high. 1 0 1 1 1 1 LVL LD pin comparator output; active high. 1 1 0 0 0 0 LVL VS (PLL supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 1 0 1 0 0 DYN Unselected reference to PLL (not available when in differential mode). 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 LVL LVL LVL LVL LVL Status of selected reference (status of differential reference); active low. Status of unselected reference (not available in differential mode); active low. Status of REF1 frequency; active low. Status of REF2 frequency; active low. 1 1 1 0 1 0 LVL (Status of REF1 frequency) AND (status of REF2 frequency). (DLD) AND (status of selected reference) AND (status of VCO). 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 LVL LVL LVL LVL LVL Status of VCO frequency; active low. Selected reference (low = REF2, high = REF1). Digital lock detect (DLD); active low. Holdover active; active low. LD pin comparator output; active low. Rev. A | Page 49 of 64 AD9518-4 Reg. Addr. (Hex) 0x017 Bits [1:0] Name Antibacklash pulse width 0x018 [6:5] Lock detect counter 4 Digital lock detect window 3 Disable digital lock detect [2:1] VCO cal divider 0 VCO cal now [7:6] R, A, B counters SYNC pin reset [5:3] R path delay R path delay (default = 0x00) (see Table 2). [2:0] N path delay N path delay (default = 0x00) (see Table 2). 0x019 Description 1 0 Antibacklash Pulse Width (ns) 0 0 2.9 (default). 0 1 1.3. 1 0 6.0. 1 1 2.9. Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked condition. 6 5 PFD Cycles to Determine Lock 0 0 5 (default). 0 1 16. 1 0 64. 1 1 255. If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold. 0: high range (default). 1: low range. Digital lock detect operation. 0: normal lock detect operation (default). 1: disables lock detect. VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock. 2 1 VCO Calibration Clock Divider 0 0 2. 0 1 4. 1 0 8. 1 1 16 (default). Bit used to initiate the VCO calibration. This bit must be toggled from 0 to 1 in the active registers. To initiate calibration, use the following three steps: first, ensure that the input reference signal is present; second, set to 0 (if not zero already), followed by an update bit (Register 0x232, Bit 0); and third, program to 1, followed by another update bit (Register 0x232, Bit 0). 7 6 Action 0 0 Does nothing on SYNC (default). 0 1 Asynchronous reset. 1 0 Synchronous reset. 1 1 Does nothing on SYNC. Rev. A | Page 50 of 64 AD9518-4 Reg. Addr. (Hex) 0x01A Bits 6 Name Reference frequency monitor threshold [5:0] LD pin control Description Sets the reference (REF1/REF2) frequency monitor’s detection threshold frequency. This does not affect the VCO frequency monitor’s detection threshold (see Table 15, REF1, REF2, and VCO frequency status monitor). 0: frequency valid if frequency is above the higher frequency threshold (default). 1: frequency valid if frequency is above the lower frequency threshold. Selects the signal that is connected to the LD pin. Level or Dynamic Signal Signal at LD Pin 5 4 3 2 1 0 0 0 0 0 0 0 LVL Digital lock detect (high = lock, low = unlock) (default). 0 0 0 0 0 1 DYN P-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 0 DYN N-channel, open-drain lock detect (analog lock detect). 0 0 0 0 1 1 HIZ High-Z LD pin. 0 0 0 1 0 0 CUR Current source lock detect (110 μA when DLD is true). 0 X X X X X LVL Ground (dc); for all other cases of 0XXXXX not specified above. The selections that follow are the same as REFMON. 1 0 0 0 0 0 LVL Ground (dc). 1 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 1 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 1 0 0 1 1 1 LVL Status REF1 frequency; active high. 1 0 1 0 0 0 LVL Status REF2 frequency; active high. 1 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 1 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 0 1 0 1 1 LVL Status of VCO frequency (active high). 1 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 1 0 1 1 0 1 LVL Digital lock detect (DLD); active high. 1 0 1 1 1 0 LVL Holdover active; active high. 1 0 1 1 1 1 LVL Not available. Do not use. 1 1 0 0 0 0 LVL VS (PLL supply). 1 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 1 0 0 1 1 DYN 1 1 0 1 0 0 DYN 1 1 0 1 0 1 LVL 1 1 0 1 1 0 LVL 1 1 1 1 1 1 0 1 1 1 0 0 1 0 0 1 0 1 LVL LVL LVL Selected reference to PLL (differential reference when in differential mode). Unselected reference to PLL (not available in differential mode). Status of selected reference (status of differential reference); active low. Status of unselected reference (not available in differential mode); active low. Status of REF1 frequency; active low. Status of REF2 frequency; active low. (Status of REF1 frequency) AND (status of REF2 frequency). 1 1 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 LVL LVL LVL LVL LVL Status of VCO frequency; active low. Selected reference (low = REF2, high = REF1). Digital lock detect (DLD); active low. Holdover active; active low. Not available. Do not use. Rev. A | Page 51 of 64 AD9518-4 Reg. Addr. (Hex) 0x01B Bits 7 Name VCO frequency monitor 6 REF2 (REFIN) frequency monitor 5 REF1 (REFIN) frequency monitor [4:0] REFMON pin control Description Enables or disables VCO frequency monitor. 0: disables VCO frequency monitor (default). 1: enables VCO frequency monitor. Enables or disables REF2 frequency monitor. 0: disables REF2 frequency monitor (default). 1: enables REF2 frequency monitor. REF1 (REFIN) frequency monitor enable; this is for both REF1 (single-ended) and REFIN (differential) inputs (as selected by differential reference mode). 0: disables REF1 (REFIN) frequency monitor (default). 1: enables REF1 (REFIN) frequency monitor. Selects the signal that is connected to the REFMON pin. Level or Dynamic Signal 4 3 2 1 0 Signal at REFMON Pin 0 0 0 0 0 LVL Ground (dc) (default). 0 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 0 0 0 1 0 DYN REF2 clock (not available in differential mode). 0 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 0 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 0 0 1 0 1 LVL Status of selected reference (status of differential reference); active high. 0 0 1 1 0 LVL Status of unselected reference (not available in differential mode); active high. 0 0 1 1 1 LVL Status REF1 frequency; active high. 0 1 0 0 0 LVL Status REF2 frequency; active high. 0 1 0 0 1 LVL (Status REF1 frequency) AND (status REF2 frequency). 0 1 0 1 0 LVL (DLD) AND (status of selected reference) AND (status of VCO). 0 1 0 1 1 LVL Status of VCO frequency; active high. 0 1 1 0 0 LVL Selected reference (low = REF1, high = REF2). 0 1 1 0 1 LVL Digital lock detect (DLD); active low. 0 1 1 1 0 LVL Holdover active; active high. 0 1 1 1 1 LVL LD pin comparator output; active high. 1 0 0 0 0 LVL VS (PLL supply). 1 0 0 0 1 DYN REF1 clock (differential reference when in differential mode). 1 0 0 1 0 DYN REF2 clock (not available in differential mode). 1 0 0 1 1 DYN Selected reference to PLL (differential reference when in differential mode). 1 0 1 0 0 DYN Unselected reference to PLL (not available in differential mode). 1 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 LVL LVL LVL LVL LVL Status of selected reference (status of differential reference); active low. Status of unselected reference (not available in differential mode); active low. Status of REF1 frequency; active low. Status of REF2 frequency; active low. (Status of REF1 frequency) AND (Status of REF2 frequency). 1 1 0 1 0 LVL (DLD) AND (Status of selected reference) AND (Status of VCO). 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 0 1 LVL LVL LVL LVL LVL Status of VCO frequency; active low. Selected reference (low = REF2, high = REF1). Digital lock detect (DLD); active low. Holdover active; active low. LD pin comparator output; active low. Rev. A | Page 52 of 64 AD9518-4 Reg. Addr. (Hex) 0x01C 0x01D Bits 7 6 Name Disable switchover deglitch Select REF2 5 Use REF_SEL pin 4 3 Automatic reference switchover Stay on REF2 2 REF2 power-on 1 REF1 power-on 0 Differential reference 4 PLL status register disable 3 LD pin comparator enable 2 Holdover enable 1 0x01F External Description Disables or enables the switchover deglitch circuit. 0: enables switchover deglitch circuit (default). 1: disables switchover deglitch circuit. If Register 0x01C, Bit 5 = 0, select reference for PLL. 0: selects REF1 (default). 1: selects REF2. If Register 0x01C, Bit 4 = 0 (manual), sets method of PLL reference selection. 0: uses Register 0x01C, Bit 6 (default). 1: uses REF_SEL pin. Automatic or manual reference switchover. Single-ended reference mode must be selected by Register 0x01C, Bit 0 = 0. 0: manual reference switchover (default). 1: automatic reference switchover. Stays on REF2 after switchover. 0: returns to REF1 automatically when REF1 status is good again (default). 1: stays on REF2 after switchover. Does not automatically return to REF1. When automatic reference switchover is disabled, this bit turns the REF2 power on. 0: REF2 power off (default). 1: REF2 power on. When automatic reference switchover is disabled, this bit turns the REF1 power on. 0: REF1 power off (default). 1: REF1 power on. Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic switchover or REF1 and REF2 to work. 0: single-ended reference mode (default). 1: differential reference mode. Disables the PLL status register readback. 0: PLL status register enable (default). 1: PLL status register disable. Enables the LD pin voltage comparator. This function is used with the LD pin current source lock detect mode. When in the internal (automatic) holdover mode, this function enables the use of the voltage on the LD pin to determine if the PLL was previously in a locked state (see Figure 37). Otherwise, this function can be used with the REFMON and STATUS pins to monitor the voltage on this pin. 0: disables LD pin comparator; internal/automatic holdover controller treats this pin as true (high) (default). 1: enables LD pin comparator. Along with Bit 0, enables the holdover function. Automatic holdover must be disabled during VCO calibration. 0: holdover disabled (default). 1: holdover enabled. Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.) holdover control 0: automatic holdover mode; holdover controlled by automatic holdover circuit (default). 1: external holdover mode; holdover controlled by SYNC pin. 0 Holdover enable 6 VCO cal finished Along with Bit 2, enables the holdover function. Automatic holdover must be disabled during VCO calibration. 0: holdover disabled (default). 1: holdover enabled. Read-only register. Indicates status of the VCO calibration. 0: VCO calibration not finished. 1: VCO calibration finished. 5 Holdover active 4 REF2 selected 3 VCO frequency > threshold Read-only register. Indicates if the part is in the holdover state (see Figure 37). This is not the same as holdover enabled. 0: not in holdover. 1: holdover state active. Read-only register. Indicates which PLL reference is selected as the input to the PLL. 0: REF1 selected (or differential reference if in differential mode). 1: REF2 selected. Read-only register. Indicates if the VCO frequency is greater than the threshold (see Table 15, REF1, REF2, and VCO frequency status monitor). 0: VCO frequency is less than the threshold. 1: VCO frequency is greater than the threshold. Rev. A | Page 53 of 64 AD9518-4 Reg. Addr. (Hex) 0x01F Bits 2 Name REF2 frequency > threshold 1 REF1 frequency > threshold 0 Digital lock detect Description Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x1A, Bit 6. 0: REF2 frequency is less than threshold frequency. 1: REF2 frequency is greater than threshold frequency. Read-only register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x01A, Bit 6. 0: REF1 frequency is less than threshold frequency. 1: REF1 frequency is greater than threshold frequency. Read-only register. Digital lock detect. 0: PLL is not locked. 1: PLL is locked. Rev. A | Page 54 of 64 AD9518-4 Table 45. LVPECL Outputs Reg. Addr. (Hex) 0x0F0 0x0F1 0x0F2 Bits 4 Name OUT0 invert [3:2] OUT0 LVPECL differential voltage [1:0] OUT0 power-down 4 OUT1 invert [3:2] OUT1 LVPECL differential voltage [1:0] OUT1 power-down 4 OUT2 invert [3:2] OUT2 LVPECL differential voltage [1:0] OUT2 power-down Description Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. LVPECL power-down modes. 1 0 Mode 0 0 Normal operation (default). 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. 1 1 Total power-down, reference off; use only if there are no external load resistors. Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. LVPECL power-down modes. 1 0 Mode 0 0 Normal operation. 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down (default). 1 1 Total power-down, reference off; use only if there are no external load resistors. Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. LVPECL power-down modes. 1 0 Mode 0 0 Normal operation (default). 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. 1 1 Total power-down, reference off; use only if there are no external load resistors. Rev. A | Page 55 of 64 Output On Off Off Off Output On Off Off Off Output On Off Off Off AD9518-4 Reg. Addr. (Hex) 0x0F3 0x0F4 0x0F5 Bits 4 Name OUT3 invert [3:2] OUT3 LVPECL differential voltage [1:0] OUT3 power-down 4 OUT4 invert [3:2] OUT4 LVPECL differential voltage [1:0] OUT4 power-down 4 OUT5 invert [3:2] OUT5 LVPECL differential voltage [1:0] OUT5 power-down Description Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. LVPECL power-down modes. 1 0 Mode 0 0 Normal operation. 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down (default). 1 1 Total power-down, reference off; use only if there are no external load resistors. Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. LVPECL power-down modes. 1 0 Mode 0 0 Normal operation (default). 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down. 1 1 Total power-down, reference off; use only if there are no external load resistors. Sets the output polarity. 0: noninverting (default). 1: inverting. Sets the LVPECL output differential voltage (VOD). 3 2 VOD (mV) 0 0 400. 0 1 600. 1 0 780 (default). 1 1 960. LVPECL power-down modes. 1 0 Mode 0 0 Normal operation. 0 1 Partial power-down, reference on; use only if there are no external load resistors. 1 0 Partial power-down, reference on, safe LVPECL power-down (default). 1 1 Total power-down, reference off; use only if there are no external load resistors. Rev. A | Page 56 of 64 Output On Off Off Off Output On Off Off Off Output On Off Off Off AD9518-4 Table 46. LVPECL Channel Dividers Reg. Addr. (Hex) 0x190 0x191 0x192 0x193 0x194 0x195 Bits [7:4] Name Divider 0 low cycles [3:0] Divider 0 high cycles 7 Divider 0 bypass 6 Divider 0 nosync 5 Divider 0 force high 4 Divider 0 start high [3:0] 1 Divider 0 phase offset Divider 0 direct to output 0 Divider 0 DCCOFF [7:4] Divider 1 low cycles [3:0] Divider 1 high cycles 7 Divider 1 bypass 6 Divider 1 nosync 5 Divider 1 force high 4 Divider 1 start high [3:0] 1 Divider 1 phase offset Divider 1 direct to output 0 Divider 1 DCCOFF Description Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). Bypasses and powers down the divider; routes input to divider output. 0: uses divider. 1: bypasses divider (default). Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. Forces divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. Selects clock output to start high or start low. 0: starts low (default). 1: starts high. Phase offset (default = 0x0). Connects OUT0 and OUT1 to Divider 0 or directly to VCO or CLK. 0: OUT0 and OUT1 are connected to Divider 0 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT0 and OUT1. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT0 and OUT1. If Register 0x1E1[1:0] = 01b, there is no effect. Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0xB). Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0xB). Bypasses and powers down the divider; routes input to divider output. 0: uses divider (default). 1: bypasses divider. Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. Forces divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. Selects clock output to start high or start low. 0: starts low (default). 1: starts high. Phase offset (default = 0x0). Connects OUT2 and OUT3 to Divider 1 or directly to VCO or CLK. 0: OUT2 and OUT3 are connected to Divider 1 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT2 and OUT3. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT2 and OUT3. If Register 0x1E1[1:0] = 01b, there is no effect. Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Rev. A | Page 57 of 64 AD9518-4 Reg. Addr. (Hex) 0x196 0x197 0x198 Bits [7:4] Name Divider 2 low cycles [3:0] Divider 2 high cycles 7 Divider 2 bypass 6 Divider 2 nosync 5 Divider 2 force high 4 Divider 2 start high [3:0] 1 Divider 2 phase offset Divider 2 direct to output 0 Divider 2 DCCOFF Description Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x0 means that the divider is low for one input clock cycle (default = 0x0). Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x0 means that the divider is high for one input clock cycle (default = 0x0). Bypasses and powers down the divider; route input to divider output. 0: uses divider (default). 1: bypasses divider. Nosync. 0: obeys chip-level SYNC signal (default). 1: ignores chip-level SYNC signal. Forces divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. Select clock output to start high or start low. 0: starts low (default). 1: starts high. Phase offset (default = 0x0). Connects OUT4 and OUT5 to Divider 2 or directly to VCO or CLK. 0: OUT4 and OUT5 are connected to Divider 2 (default). 1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT4 and OUT5. If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT4 and OUT5. If Register 0x1E1[1:0] = 01b, there is no effect. Duty-cycle correction function. 0: enables duty-cycle correction (default). 1: disables duty-cycle correction. Table 47. VCO Divider and CLK Input Reg. Addr (Hex) 0x1E0 Bits [2:0] Name VCO divider 0x1E1 4 Power down clock input section 3 Power down VCO clock interface 2 Power down VCO and CLK Description 2 1 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 Divide 2. 3. 4 (default). 5. 6. Output static. Note that setting the VCO divider static should occur only after VCO calibration. 1 1 0 Output static. Note that setting the VCO divider static should occur only after VCO calibration. 1 1 1 Output static. Note that setting the VCO divider static should occur only after VCO calibration. Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). 0: normal operation (default). 1: power-down. Powers down the interface block between VCO and clock distribution. 0: normal operation (default). 1: power-down. Powers down both VCO and CLK input. 0; normal operation (default). 1: power-down. Rev. A | Page 58 of 64 AD9518-4 Reg. Addr (Hex) 0x1E1 Bits 1 Name Select VCO or CLK 0 Bypass VCO divider Description Selects either the VCO or the CLK as the input to VCO divider. 0: selects external CLK as input to VCO divider (default). 1: selects VCO as input to VCO divider; cannot bypass VCO divider when this is selected. Bypasses or uses the VCO divider. 0: uses VCO divider (default). 1: bypasses VCO divider; cannot select VCO as input when this is selected. Table 48. System Reg. Addr. (Hex) 0x230 Bits 2 Name Power down SYNC 1 Power down distribution reference 0 Soft SYNC Description Powers down the SYNC function. 0: normal operation of the SYNC function (default). 1: powers down SYNC circuitry. Powers down the reference for distribution section. 0: normal operation of the reference for the distribution section (default). 1: powers down the reference for the distribution section. The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is reversed. That is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. 0: same as SYNC high (default). 1: same as SYNC low. Table 49. Update All Registers Reg. Addr (Hex) 0x232 Bits 0 Name Update all registers Description This bit must be set to 1 to transfer the contents of the buffer registers into the active registers, which happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0. 1 (self-clearing): updates all active registers to the contents of the buffer registers. Rev. A | Page 59 of 64 AD9518-4 APPLICATIONS INFORMATION The AD9518 has the following four frequency dividers: the reference (or R) divider, the feedback (or N) divider, the VCO divider, and the channel divider. When trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the VCO divider or the channel divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth. Within the AD9518 family, lower VCO frequencies generally result in slightly lower jitter. The difference in integrated jitter (from 12 kHz to 20 MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.45 GHz to 2.95 GHz) of the AD9518 family. If the desired frequency plan can be achieved with a version of the AD9518 that has a lower VCO frequency, choosing the lower frequency part results in the lowest phase noise and the lowest jitter. However, choosing a higher VCO frequency may result in more flexibility in frequency planning. ⎛ 1 SNR(dB) = 20 × log ⎜ ⎜ 2πf t A J ⎝ ⎞ ⎟ ⎟ ⎠ where: fA is the highest analog frequency being digitized. tJ is the rms jitter on the sampling clock. Figure 51 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB). 110 1 SNR = 20log 2πf t A J 100 18 16 90 tJ = 10 80 200 fs 400 fs 70 0fs 14 12 1ps 60 2ps 10 10p s 8 50 40 ENOB The AD9518 is a highly flexible PLL. When choosing the PLL settings and version of the AD9518, keep in mind the following guidelines. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by SNR (dB) FREQUENCY PLANNING USING THE AD9518 30 10 100 fA (MHz) 1k 06433-044 6 Choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current and, thus, allows the designer to fine-tune the PLL loop bandwidth in either direction. Figure 51. SNR and ENOB vs. Analog Input Frequency For more information, see the AN-756 Application Note, Sampled Systems and the Effects of Clock Phase Noise and Jitter; and the AN-501 Application Note, Aperture Uncertainty and ADC System Performance, at www.analog.com. ADIsimCLK is a powerful PLL modeling tool that can be downloaded from www.analog.com. It is very accurate in determining the optimal loop filter for a given application. USING THE AD9518 OUTPUTS FOR ADC CLOCK APPLICATIONS Any high speed ADC is extremely sensitive to the quality of its sampling clock. An ADC can be thought of as a sampling mixer, and any noise, distortion, or timing jitter on the clock is combined with the desired signal at the analog-to-digital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at ≥14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. (Distributing a single-ended clock on a noisy PCB may result in coupled noise on the sample clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment.) The AD9518 features LVPECL outputs that provide differential clock outputs, which enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or single-ended, logic level, termination) should be considered when selecting the best clocking/converter solution. Rev. A | Page 60 of 64 AD9518-4 VS_LVPECL LVPECL CLOCK DISTRIBUTION In most applications, a LVPECL far-end Thevenin termination (see Figure 52) or Y-termination (see Figure 53) is recommended. In both cases, VS of the receiving buffer should match the VS_LVPECL. If not, ac coupling is recommended (see Figure 54). VS_DRV VS_LVPECL LVPECL 127Ω 127Ω SINGLE-ENDED (NOT COUPLED) VS LVPECL 50Ω 83Ω 06433-145 83Ω Figure 52. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination VS_LVPECL VS = 3.3V 50Ω 50Ω 50Ω LVPECL Z0 = 50Ω Figure 53. DC-Coupled 3.3 V LVPECL Y-Termination 06433-147 Z0 = 50Ω LVPECL LVPECL 200Ω 100Ω DIFFERENTIAL 100Ω (COUPLED) 0.1nF TRANSMISSION LINE LVPECL 200Ω 06433-146 The LVPECL outputs of the AD9518 provide the lowest jitter clock signals available from the AD9518. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. The simplified equivalent circuit in Figure 42 shows the LVPECL output stage. 50Ω VS 0.1nF Figure 54. AC-Coupled LVPECL with Parallel Transmission Line LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter-follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue. In the case where VS_LVPECL = 2.5 V, the 50 Ω termination resistor connected to ground in Figure 53 should be changed to 19 Ω. Thevenin-equivalent termination uses a resistor network to provide 50 Ω termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_LVPECL on the AD9518 should equal VS of the receiving buffer. Although the resistor combination shown results in a dc bias point of VS_LVPECL − 2 V, the actual common-mode voltage is VS_LVPECL − 1.3 V because there is additional current flowing from the AD9518 LVPECL driver through the pull-down resistor. The circuit is identical when VS_LVPECL = 2.5 V, except that the pull-down resistor is 62.5 Ω and the pull-up is 250 Ω. Rev. A | Page 61 of 64 AD9518-4 OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 7.00 BSC SQ 0.60 MAX 37 36 PIN 1 INDICATOR 6.75 BSC SQ 48 1 0.50 BSC *5.65 EXPOSED PAD 5.50 SQ 5.35 (BOTTOM VIEW) 25 24 0.80 MAX 0.65 TYP 12° MAX 0.25 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 12 090209-A TOP VIEW 1.00 0.85 0.80 13 0.50 0.40 0.30 PIN 1 INDICATOR *COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION. Figure 55. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-8) Dimensions shown in millimeters 7.00 BSC SQ 0.60 MAX 37 36 PIN 1 INDICATOR 0.50 BSC 1 5.25 5.10 SQ 4.95 (BOTTOM VIEW) 25 24 13 12 0.25 MIN 5.50 REF 0.80 MAX 0.65 TYP SEATING PLANE PIN 1 INDICATOR EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 12° MAX 48 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 080108-A TOP VIEW 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX Figure 56. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9518-4ABCPZ 2 AD9518-4ABCPZ-RL72 AD9518-4BCPZ AD9518-4BCPZ-REEL7 AD9518-4/PCBZ AD9518-4A/PCBZ2 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board Evaluation Board Z = RoHS Compliant Part. Recommended for use in new designs; reference PCN 09_156. Rev. A | Page 62 of 64 Package Option CP-48-8 CP-48-8 CP-48-1 CP-48-1 AD9518-4 NOTES Rev. A | Page 63 of 64 AD9518-4 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06433-0-1/10(A) Rev. A | Page 64 of 64