12 LVDS/24 CMOS Output Clock Generator with Integrated 2 GHz VCO AD9522-3
FEATURES
Low phase noise, phase-locked loop (PLL) On-chip VCO tunes from 1.72 GHz to 2.25 GHz Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVPECL, or LVDS references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capability Auto and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching Glitch-free switchover between references Automatic recovery from holdover Digital or analog lock detect, selectable Optional zero delay operation Twelve 800 MHz LVDS outputs divided into 4 groups Each group of 3 has a 1-to-32 divider with phase delay Additive output jitter as low as 245 fs rms Channel-to-channel skew grouped outputs 1600 MHz .................................................. 31 Phase-Locked Loop (PLL) .................................................... 33 Configuration of the PLL ...................................................... 33 Phase Frequency Detector (PFD) ........................................ 33 Charge Pump (CP)................................................................. 34 On-Chip VCO ........................................................................ 34 PLL External Loop Filter ....................................................... 34 PLL Reference Inputs ............................................................. 34 Reference Switchover ............................................................. 35 Reference Divider R ............................................................... 35 VCO/VCXO Feedback Divider N: P, A, B, R ..................... 35 Digital Lock Detect (DLD) ................................................... 37 Analog Lock Detect (ALD) ................................................... 37 Current Source Digital Lock Detect (CSDLD) .................. 37 External VCXO/VCO Clock Input (CLK/CLK) ................ 38 Holdover .................................................................................. 38 External/Manual Holdover Mode ........................................ 38 Automatic/Internal Holdover Mode.................................... 38 Frequency Status Monitors ................................................... 40 VCO Calibration .................................................................... 41 Zero Delay Operation ................................................................ 42 Internal Zero Delay Mode..................................................... 42 External Zero Delay Mode .................................................... 42 Clock Distribution ..................................................................... 43 Operation Modes ................................................................... 43 Clock Frequency Division..................................................... 44 VCO Divider ........................................................................... 44 Channel Dividers ................................................................... 44 Synchronizing the Outputs—SYNC Function ................... 46 LVDS Output Drivers ............................................................ 47 CMOS Output Drivers .......................................................... 48 Reset Modes ................................................................................ 48 Power-On Reset ...................................................................... 48 Hardware Reset via the RESET Pin ..................................... 48 Soft Reset via the Serial Port ................................................. 48 Soft Reset to Settings in EEPROM when EEPROM Pin = 0 via the Serial Port ......................................................................... 48
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AD9522-3
Power-Down Modes ...................................................................48 Chip Power-Down via PD .....................................................48 PLL Power-Down ....................................................................49 Distribution Power-Down .....................................................49 Individual Clock Output Power-Down................................49 Individual Clock Channel Power-Down .............................49 Serial Control Port ..........................................................................50 SPI/I2C Port Selection ................................................................50 I2C Serial Port Operation ...........................................................50 I C Bus Characteristics ...........................................................50
2
SPI MSB/LSB First Transfers ..................................................... 54 EEPROM Operations ..................................................................... 57 Writing to the EEPROM ............................................................ 57 Reading from the EEPROM ...................................................... 57 Programming the EEPROM Buffer Segment.......................... 58 Register Section Definition Group ....................................... 58 IO_UPDATE (Operational Code 0x80) .............................. 58 End-of-Data (Operational Code 0xFF) ............................... 58 Pseudo-End-of-Data (Operational Code 0xFE) ................. 58 Thermal Performance..................................................................... 60 Register Map .................................................................................... 61 Register Map Descriptions ............................................................. 66 Applications Information ............................................................... 80 Frequency Planning Using the AD9522 .................................. 80 Using the AD9522 Outputs for ADC Clock Applications .... 80 LVDS Clock Distribution........................................................... 80 CMOS Clock Distribution ......................................................... 81 Outline Dimensions ........................................................................ 82 Ordering Guide ........................................................................... 82
Data Transfer Process .............................................................51 Data Transfer Format .............................................................52 I2C Serial Port Timing ............................................................52 SPI Serial Port Operation ...........................................................53 Pin Descriptions ......................................................................53 SPI Mode Operation ...............................................................53 Communication Cycle—Instruction Plus Data ..................53 Write .........................................................................................53 Read ..........................................................................................53 SPI Instruction Word (16 Bits) ..................................................54
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 3 of 84
AD9522-3 SPECIFICATIONS
Typical (typ) is given for VS = 3.3 V ± 5%; VS ≤ VCP ≤ 5.25 V; TA = 25°C; RSET = 4.12 kΩ; CPRSET = 5.1 kΩ, unless otherwise noted. Minimum (min) and maximum (max) values are given over full VS and TA (−40°C to +85°C) variation.
POWER SUPPLY REQUIREMENTS
Table 1.
Parameter VS VCP RSET Pin Resistor CPRSET Pin Resistor BYPASS Pin Capacitor Min 3.135 VS Typ 3.3 4.12 5.1 220 Max 3.465 5.25 Unit V V kΩ kΩ nF Test Conditions/Comments 3.3 V ± 5% This is nominally 3.3 V to 5.0 V ± 5% Sets internal biasing currents; connect to ground Sets internal CP current range, nominally 4.8 mA (CP_lsb = 600 μA); actual current can be calculated by CP_lsb = 3.06/CPRSET; connect to ground Bypass for internal LDO regulator; necessary for LDO stability; connect to ground
PLL CHARACTERISTICS
Table 2.
Parameter VCO (ON-CHIP) Frequency Range VCO Gain (KVCO) Tuning Voltage (VT) Frequency Pushing (Open-Loop) Phase Noise @ 1 kHz Offset Phase Noise @ 100 kHz Offset Phase Noise @ 1 MHz Offset REFERENCE INPUTS Differential Mode (REFIN, REFIN) Input Frequency Input Sensitivity Self-Bias Voltage, REFIN Self-Bias Voltage, REFIN Input Resistance, REFIN Input Resistance, REFIN Dual Single-Ended Mode (REF1, REF2) Input Frequency (AC-Coupled) with DC Offset Off ) Input Frequency (AC-Coupled with DC Offset On) Input Frequency (DC-Coupled) Input Sensitivity (AC-Coupled with DC Offset Off ) Input Sensitivity (AC-Coupled with DC Offset On) Input Logic High, DC Offset Off Input Logic Low, DC Offset Off Input Current Input Capacitance 0 280 1.60 1.50 4.8 5.3 Min 1720 47 0.5 1 −62 −118 −135 VCP − 0.5 Typ Max 2250 Unit MHz MHz/V V MHz/V dBc/Hz dBc/Hz dBc/Hz Test Conditions/Comments See Figure 13 See Figure 8 VCP ≤ VS when using internal VCO
LVDS output; fVCO = 1985 MHz; fOUT = 662MHz LVDS output; fVCO = 1985 MHz; fOUT = 662MHz LVDS output; fVCO = 1985 MHz; fOUT = 662MHz Differential mode (can accommodate single-ended input by ac grounding undriven input) Frequencies below about 1 MHz should be dc-coupled; be careful to match VCM (self-bias voltage) Self-bias voltage of REFIN 1 Self-bias voltage of REFIN1 Self-biased1 Self-biased1 Two single-ended CMOS-compatible inputs Slew rate must be > 50 V/μs Slew rate must be > 50 V/μs, and input amplitude sensitivity specification must be met; see input sensitivity Slew rate > 50 V/μs; CMOS levels VIH should not exceed VS VIH should not exceed VS
250
MHz mV p-p V V kΩ kΩ MHz MHz MHz V p-p V p-p V V μA pF
1.35 1.30 4.0 4.4 10
1.75 1.60 5.9 6.4 250 250
0 0.55 1.5 2.0 −100 2
250 3.28 2.78
0.8 +100
Each pin, REFIN (REF1)/REFIN (REF2)
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AD9522-3
Parameter Crystal Oscillator Crystal Resonator Frequency Range Maximum Crystal Motional Resistance PHASE/FREQUENCY DETECTOR (PFD) PFD Input Frequency Reference Input Clock Doubler Frequency Antibacklash Pulse Width Min 16.62 Typ Max 33.33 30 100 45 50 1.3 2.9 6.0 Unit MHz Ω MHz MHz MHz ns ns ns Antibacklash pulse width = 1.3 ns, 2.9 ns Antibacklash pulse width = 6.0 ns Antibacklash pulse width = 1.3 ns, 2.9 ns 0x017[1:0] = 01b 0x017[1:0] = 00b; 0x017[1:0] = 11b 0x017[1:0] = 10b Programmable With CPRSET = 5.1 kΩ; higher ICP is possible by changing CPRSET With CPRSET = 5.1 kΩ; lower ICP is possible by changing CPRSET Charge pump voltage set to VCP/2 Test Conditions/Comments
0.004
CHARGE PUMP (CP) ICP Sink/Source High Value Low Value Absolute Accuracy CPRSET Range ICP High Impedance Mode Leakage Sink-and-Source Current Matching ICP vs. VCP ICP vs. Temperature PRESCALER (PART OF N DIVIDER) Prescaler Input Frequency P = 1 FD P = 2 FD P = 3 FD P = 2 DM (2/3) P = 4 DM (4/5) P = 8 DM (8/9) P = 16 DM (16/17) P = 32 DM (32/33) Prescaler Output Frequency PLL N DIVIDER DELAY 000 001 010 011 100 101 110 111 PLL R DIVIDER DELAY 000 001 010 011 100 101 110 111
4.8 0.60 2.5 2.7 1 1 1.5 2 10
mA mA % kΩ nA % % %
0.5 V < VCP < VCP − 0.5 V; VCP is the voltage on the CP (charge pump) pin; VCP is the voltage on the VCP power supply pin 0.5 V < VCP < VCP − 0.5 V VCP = VCP/2 V
300 600 900 600 1000 2400 3000 3000 300
MHz MHz MHz MHz MHz MHz MHz MHz MHz
A, B counter input frequency (prescaler input frequency divided by P) Register 0x019[2:0]; see Table 52
Off 385 504 623 743 866 989 1112 Off 365 486 608 730 852 976 1101
ps ps ps ps ps ps ps Register 0x019[5:3]; see Table 52 ps ps ps ps ps ps ps
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AD9522-3
Parameter PHASE OFFSET IN ZERO DELAY Phase Offset (REF-to-LVDS Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-LVDS Clock Output Pins) in Internal Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode Phase Offset (REF-to-CLK Input Pins) in External Zero Delay Mode NOISE CHARACTERISTICS In-Band Phase Noise of the Charge Pump/ Phase Frequency Detector (In-Band Means Within the LBW of the PLL) @ 500 kHz PFD Frequency @ 1 MHz PFD Frequency @ 10 MHz PFD Frequency @ 50 MHz PFD Frequency PLL Figure of Merit (FOM) Min 1890 900 318 −329 Typ 2348 1217 677 +33 Max 3026 1695 1085 +360 Unit ps ps ps ps Test Conditions/Comments REF refers to REFIN (REF1)/REFIN (REF2) When N delay and R delay are bypassed When N delay = Setting 111 and R delay is bypassed When N delay and R delay are bypassed When N delay = Setting 011 and R delay is bypassed
The PLL in-band phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the value of the N divider) −165 −162 −152 −144 −222 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
PLL DIGITAL LOCK DETECT WINDOW 2
Lock Threshold (Coincidence of Edges) Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6.0 ns) Unlock Threshold (Hysteresis)2 Low Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 1.3 ns, 2.9 ns) High Range (ABP 6.0 ns)
1 2
3.5 7.5 3.5
ns ns ns
7 15 11
ns ns ns
Reference slew rate > 0.5 V/ns; FOM + 10 log(fPFD) is an approximation of the PFD/CP in-band phase noise (in the flat region) inside the PLL loop bandwidth; when running closed-loop, the phase noise, as observed at the VCO output, is increased by 20 log(N); PLL figure of merit decreases with decreasing slew rate; see Figure 12 Signal available at the LD, STATUS, and REFMON pins when selected by appropriate register settings; lock detect window settings can be varied by changing the CPRSET resistor Selected by 0x017[1:0] and 0x018[4] (this is the threshold to go from unlock to lock) 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b 0x017[1:0] = 10b; 0x018[4] = 0b Selected by 0x017[1:0] and 0x018[4] (this is the threshold to go from lock to unlock) 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 1b 0x017[1:0] = 00b, 01b, 11b; 0x018[4] = 0b 0x017[1:0] = 10b; 0x018[4] = 0b
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition. For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
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AD9522-3
CLOCK INPUTS
Table 3.
Parameter CLOCK INPUTS (CLK, CLK) Input Frequency Min 01 01 150 2 1.3 1.3 3.9 1.57 150 4.7 2 1.8 1.8 5.7 Typ Max 2.4 1.6 Unit GHz GHz mV p-p V p-p V V mV p-p kΩ pF Test Conditions/Comments Differential input High frequency distribution (VCO divider) Distribution only (VCO divider bypassed); this is the frequency range supported by the channel divider Measured at 2.4 GHz; jitter performance is improved with slew rates > 1 V/ns Larger voltage swings can turn on the protection diodes and can degrade jitter performance Self-biased; enables ac coupling With 200 mV p-p signal applied; dc-coupled CLK ac-coupled; CLK ac-bypassed to RF ground Self-biased
Input Sensitivity, Differential Input Level, Differential Input Common-Mode Voltage, VCM Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance
1
Below about 1 MHz, the input should be dc-coupled. Care should be taken to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter LVDS CLOCK OUTPUTS OUT0, OUT1, OUT2, OUT3, OUT4, OUT5, OUT6, OUT7, OUT8, OUT9, OUT10, OUT11 Output Frequency, Maximum Min Typ Max Unit Test Conditions/Comments Termination = 100 Ω across differential pair Differential (OUT, OUT) The AD9522 outputs toggle at higher frequencies, but the output amplitude may not meet the VOD specification See Figure 21
800
MHz
Output Differential Voltage, VOD Delta VOD Output Offset Voltage, VOS Delta VOS Short-Circuit Current, ISA, ISB CMOS CLOCK OUTPUTS OUT0A, OUT0B, OUT1A, OUT1B, OUT2A, OUT2B, OUT3A, OUT3B, OUT4A, OUT4B, OUT5A, OUT5B, OUT6A, OUT6B, OUT7A, OUT7B, OUT8A, OUT8B, OUT9A, OUT9B, OUT10A, OUT10B, OUT11A, OUT11B Output Frequency Output Voltage High, VOH Output Voltage Low, VOL Output Voltage High, VOH Output Voltage Low, VOL
247 1.125
360 1.25 14
454 25 1.375 25 24
mV mV V mV mA
Output shorted to GND Single-ended; termination = 10 pF
250 VS − 0.1 0.1 2.7 0.5
MHz V V V V
See Figure 22 @ 1 mA load @ 1 mA load @ 10 mA load @ 10 mA load
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AD9522-3
TIMING CHARACTERISTICS
Table 5.
Parameter LVDS OUTPUT RISE/FALL TIMES Output Rise Time, tRP Output Fall Time, tFP PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUTPUT For All Divide Values Variation with Temperature OUTPUT SKEW, LVDS OUTPUTS 1 LVDS Outputs That Share the Same Divider LVDS Outputs on Different Dividers All LVDS Outputs Across Multiple Parts CMOS OUTPUT RISE/FALL TIMES Output Rise Time, tRC Output Fall Time, tFC PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUTPUT For All Divide Values Variation with Temperature OUTPUT SKEW, CMOS OUTPUTS1 CMOS Outputs That Share the Same Divider All CMOS Outputs on Different Dividers All CMOS Outputs Across Multiple Parts OUTPUT SKEW, LVDS-TO-CMOS OUTPUT1 Outputs That Share the Same Divider Outputs That Are on Different Dividers
1
Min
Typ 150 150
Max 350 350 2812 2740
Unit ps ps ps ps ps/°C ps ps ps ps ps ps ps/°C ps ps ps ps ps
Test Conditions/Comments Termination = 100 Ω across differential pair 20% to 80%, measured differentially 80% to 20%, measured differentially High frequency clock distribution configuration Clock distribution configuration Termination = 100 Ω across differential pair
1866 1808
2313 2245 1 7 19
60 162 432 835 800 2950
625 625 1913 2400 2 10 27
Termination = open 20% to 80%; CLOAD = 10 pF 80% to 20%; CLOAD = 10 pF Clock distribution configuration
55 230 500 +495 +495
−31 −193
+152 +160
All settings identical; different logic type LVDS to CMOS on the same part LVDS to CMOS on the same part
The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
Timing Diagrams
tCLK
CLK
tLVDS
SINGLE-ENDED 80% CMOS 10pF LOAD 20%
07224-060
tCMOS
tRC
tFC
Figure 2. CLK/CLK to Clock Output Timing, DIV = 1
DIFFERENTIAL 80% LVDS 20%
07224-061
Figure 4. CMOS Timing, Single-Ended, 10 pF Load
tRP
tFP
Figure 3. LVDS Timing, Differential
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07224-063
AD9522-3
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter CLK-TO-LVDS ADDITIVE PHASE NOISE CLK = 1.6 GHz, Output = 800 MHz Divider = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset CLK = 1 GHz, Output = 200 MHz Divider = 5 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK-TO-CMOS ADDITIVE PHASE NOISE CLK = 1 GHz, Output = 500 MHz Divider = 2 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset CLK = 1 GHz, Output = 50 MHz Divider = 20 @ 10 Hz Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset >10 MHz Offset Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns
−100 −110 −117 −126 −134 −137 −147 −148
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns
−111 −123 −132 −141 −146 −150 −156
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Distribution section only; does not include PLL and VCO Input slew rate > 1 V/ns
−102 −114 −122 −129 −135 −140 −150
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns
−125 −136 −144 −152 −157 −160 −164
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
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AD9522-3
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter LVDS ABSOLUTE PHASE NOISE VCO = 2250 MHz; Output = 750 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 1985 MHz; Output = 662 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset VCO = 1720 MHz; Output = 573 MHz @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 40 MHz Offset Min Typ Max Unit Test Conditions/Comments Internal VCO; VCO divider = 3; LVDS output and for loop bandwidths < 1 kHz
−58 −90 −116 −133 −147 −150 −62 −94 −118 −135 −148 −151 −70 −99 −123 −138 −149 −151
dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter LVDS OUTPUT ABSOLUTE TIME JITTER Min Typ Max Unit Test Conditions/Comments Application example based on a typical setup where the reference source is clean, so a wider PLL loop bandwidth is used; reference = 15.36 MHz; R DIV = 1 Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz
VCO = 1966 MHz; LVDS = 245.76 MHz; PLL LBW = 55 kHz VCO = 1720 MHz; LVDS = 122.88 MHz; PLL LBW = 55 kHz VCO = 1720 MHz; LVDS = 61.44 MHz; PLL LBW = 55 kHz
141 312 136 285 187 340
fs rms fs rms fs rms fs rms fs rms fs rms
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter LVDS OUTPUT ABSOLUTE TIME JITTER Min Typ Max Unit Test Conditions/Comments Application example based on a typical setup where the reference source is jittery, so a narrower PLL loop bandwidth is used; reference = 19.44 MHz; R DIV = 162 Integration BW = 12 kHz to 20 MHz Integration BW = 12 kHz to 20 MHz
VCO = 1866 MHz; LVDS = 155.52 MHz; PLL LBW = 1.8 kHz VCO = 1720 MHz; LVDS = 122.88 MHz; PLL LBW = 1.8 kHz
440 362
fs rms fs rms
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AD9522-3
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter LVDS OUTPUT ABSOLUTE TIME JITTER Min Typ Max Unit Test Conditions/Comments Application example based on a typical setup using an external 245.76 MHz VCXO (Toyocom TCO-2112); reference = 15.36 MHz; R DIV = 1 Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz Integration BW = 200 kHz to 5 MHz Integration BW = 200 kHz to 10 MHz Integration BW = 12 kHz to 20 MHz
LVDS = 245.76 MHz; PLL LBW = 125 Hz
LVDS = 122.88 MHz; PLL LBW = 125 Hz
LVDS = 61.44 MHz; PLL LBW = 125 Hz
87 108 146 120 151 207 157 210 295
fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms fs rms
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter LVDS OUTPUT ADDITIVE TIME JITTER CLK = 622.08 MHz Any LVDS Output = 622.08 MHz Divide Ratio = 1 CLK = 622.08 MHz Any LVDS Output = 155.52 MHz Divide Ratio = 4 CLK = 100 MHz Any LVDS Output = 100 MHz Divide Ratio = 1 CLK = 500 MHz Any LVDS Output = 100 MHz Divide Ratio = 5 CMOS OUTPUT ADDITIVE TIME JITTER CLK = 200 MHz Any CMOS Output Pair = 100 MHz Divide Ratio = 2 Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO; measured at rising edge of clock signal Integration bandwidth = 12 kHz to 20 MHz
69
fs rms
116
fs rms
Integration bandwidth = 12 kHz to 20 MHz
263
fs rms
Calculated from SNR of ADC method Broadband jitter Calculated from SNR of ADC method Broadband jitter Distribution section only; does not include PLL and VCO Calculated from SNR of ADC method Broadband jitter
242
fs rms
289
fs rms
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AD9522-3
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter LVDS OUTPUT ADDITIVE TIME JITTER CLK = 500 MHz; VCO DIV = 5; LVDS = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = On CMOS OUTPUT ADDITIVE TIME JITTER CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = Off CLK = 200 MHz; VCO DIV = 1; CMOS = 100 MHz; Bypass Channel Divider; Duty-Cycle Correction = Off Min Typ Max Unit Test Conditions/Comments Distribution section only; does not include PLL and VCO; uses rising edge of clock signal Calculated from SNR of ADC method (broadband jitter) Distribution section only; does not include PLL and VCO; uses rising edge of clock signal Calculated from SNR of ADC method (broadband jitter) Calculated from SNR of ADC method (broadband jitter)
248
fs rms
290 288
fs rms fs rms
SERIAL CONTROL PORT—SPI MODE
Table 13.
Parameter CS (INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SCLK (INPUT) IN SPI MODE Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tHIGH Pulse Width Low, tLOW SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CS to SCLK Setup and Hold, tS, tC CS Minimum Pulse Width High, tPWH 2.0 0.8 110 1 2 2.0 0.8 1 1 2 2.7 0.4 25 16 16 4 0 11 2 3 Min 2.0 0.8 3 −110 2 Typ Max Unit V V μA μA pF SCLK has an internal 30 kΩ pull-down resistor in SPI mode, but not in I2C mode V V μA μA pF V V μA μA pF V V MHz ns ns ns ns ns ns ns Test Conditions/Comments CS has an internal 30 kΩ pull-up resistor
The minus sign indicates that current is flowing out of the AD9522, which is due to the internal pull-up resistor
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AD9522-3
SERIAL CONTROL PORT—I²C MODE
Table 14.
Parameter SDA, SCL (WHEN INPUTTING DATA) Input Logic 1 Voltage Input Logic 0 Voltage Input Current with an Input Voltage Between 0.1 × VS and 0.9 × VS Hysteresis of Schmitt Trigger Inputs Pulse Width of Spikes That Must Be Suppressed by the Input Filter, tSPIKE SDA (WHEN OUTPUTTING DATA) Output Logic 0 Voltage at 3 mA Sink Current Output Fall Time from VIHMIN to VILMAX with a Bus Capacitance from 10 pF to 400 pF TIMING Min 0.7 × VS −10 0.015 × VS 50 0.3 × VS +10 Typ Max Unit V V μA V ns Test Conditions/Comments
20 + 0.1 Cb
0.4 250
V ns
Cb = capacitance of one bus line in pF Note that all I2C timing values refer to VIHMIN (0.3 × VS) and VILMAX levels (0.7 × VS)
Clock Rate (SCL, fI2C) Bus Free Time Between a Stop and Start Condition, tIDLE Setup Time for a Repeated Start Condition, tSET; STR Hold Time (Repeated) Start Condition (After This Period, the First Clock Pulse Is Generated), tHLD; STR Setup Time for Stop Condition, tSET; STP Low Period of the SCL Clock, tLOW High Period of the SCL Clock, tHIGH SCL, SDA Rise Time, tRISE SCL, SDA Fall Time, tFALL Data Setup Time, tSET; DAT
400 1.3 0.6 0.6 0.6 1.3 0.6 20 + 0.1 Cb 20 + 0.1 Cb 120
kHz μs μs μs μs μs μs ns ns ns
300 300
Data Hold Time, tHLD; DAT
140
880
ns
This is a minor deviation from the original I²C specification of 100 ns minimum This is a minor deviation from the original I²C specification of 0 ns minimum 1
Capacitive Load for Each Bus Line, Cb
1
400
pF
According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL falling edge.
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AD9522-3
PD, SYNC, AND RESET PINS
Table 15.
Parameter INPUT CHARACTERISTICS Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low RESET Inactive to Start of Register Programming SYNC TIMING Pulse Width Low Min 2.0 0.8 1 −110 2 50 100 1.3 Typ Max Unit V V μA μA pF ns ns ns High speed clock is CLK input signal Test Conditions/Comments Each of these pins has a 30 kΩ internal pull-up resistor
The minus sign indicates that current is flowing out of the AD9522, which is due to the internal pull-up resistor
SERIAL PORT SETUP PINS: SP1, SP0
Table 16.
Parameter SP1, SP0 Logic Level 0 Logic Level ½ Logic Level 1 Min Typ Max 0.25 × VS 0.65 × VS Unit V V V Test Conditions/Comments These pins do not have internal pull-up/pull-down resistors VS is the voltage on the VS pin User can float these pins to obtain Logic Level ½; if floating this pin, user should connect a capacitor to ground
0.4 × VS 0.8 × VS
LD, STATUS, AND REFMON PINS
Table 17.
Parameter OUTPUT CHARACTERISTICS Min Typ Max Unit Test Conditions/Comments When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 52, 0x017, 0x01A, and 0x01B
Output Voltage High, VOH Output Voltage Low, VOL MAXIMUM TOGGLE RATE
2.7 0.4 100
V V MHz
Applies when mux is set to any divider or counter output, or PFD up/down pulse; also applies in analog lock detect mode; usually debug mode only; beware that spurs can couple to output when any of these pins are toggling On-chip capacitance; used to calculate RC time constant for analog lock detect readback; use a pull-up resistor Frequency above which the monitor indicates the presence of the reference Frequency above which the monitor indicates the presence of the reference
ANALOG LOCK DETECT Capacitance REF1, REF2, AND VCO FREQUENCY STATUS MONITOR Normal Range Extended Range LD PIN COMPARATOR Trip Point Hysteresis
3
pF
1.02 8
MHz kHz
1.6 260
V mV
Rev. 0 | Page 14 of 84
AD9522-3
POWER DISSIPATION
Table 18.
Parameter POWER DISSIPATION, CHIP Min Typ Max Unit Test Conditions/Comments Does not include power dissipated in external resistors; all LVDS outputs terminated with 100 Ω across differential pair; all CMOS outputs have 10 pF capacitive loading No clock; no programming; default register values fREF = 25 MHz; fOUT = 250 MHz; VCO = 2000 MHz; VCO divider = 2; one LVDS output and output divider enabled; zero delay off; ICP = 4.8 mA fREF = 25 MHz; fOUT = 62.5 MHz; VCO = 2000 MHz; VCO divider = 2; one CMOS output and output divider enabled; zero delay off; ICP = 4.8 mA fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2; one LVDS output and output divider enabled; zero delay off fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider bypassed; one LVDS output and output divider enabled; zero delay off PLL on; internal VCO = 2000 MHz; VCO divider = 2; all channel dividers on; 12 LVDS outputs @ 125 MHz; zero delay on PD pin pulled low; does not include power dissipated in termination resistors PD pin pulled low; PLL power-down, 0x010[1:0] = 01b; powerdown SYNC, 0x230[2] = 1b; power-down distribution reference, 0x230[1] = 1b PLL operating; typical closed-loop configuration Power delta when a function is enabled/disabled VCO divider not used Delta between reference input off and differential reference input mode Delta between reference inputs off and one singled-ended reference enabled; double this number if both REF1 and REF2 are powered up Internal VCO disabled; CLK input selected PLL off to PLL on, normal operation; no reference enabled No LVDS output on to one LVDS output on; channel divider set to 1 Second LVDS output turned on, same channel No CMOS output on to one CMOS output on; channel divider set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading Additional CMOS outputs within the same channel turned on Delta between divider bypassed (divide-by-1) and divide-by-2 to divide-by-32
Power-On Default PLL Locked; One LVDS Output Enabled
0.88 0.54
1.0 0.63
W W
PLL Locked; One CMOS Output Enabled
0.55
0.66
W
Distribution Only Mode; VCO Divider On; One LVDS Output Enabled Distribution Only Mode; VCO Divider Off; One LVDS Output Enabled Maximum Power, Full Operation PD Power-Down PD Power-Down, Maximum Sleep
0.36 0.33 1.1 35 27
0.43 0.4 1.3 50 43
W W W mW mW
VCP Supply POWER DELTAS, INDIVIDUAL FUNCTIONS VCO Divider On/Off REFIN (Differential) Off REF1, REF2 (Single-Ended) On/Off
8 33 25 16
2.3 43 31 22
mW mW mW mW
VCO On/Off PLL Dividers and Phase Detector On/Off LVDS Channel LVDS Driver CMOS Channel CMOS Driver On/Off Channel Divider Enabled Zero Delay Block On/Off
60 54 118 11 120 16 33 30
95 67 146 15 154 30 40 35
mW mW mW mW mW mW mW mW
Rev. 0 | Page 15 of 84
AD9522-3 ABSOLUTE MAXIMUM RATINGS
Table 19.
Parameter or Pin VS VCP, CP REFIN, REFIN RSET, LF, BYPASS CPRSET CLK, CLK CLK SCLK/SCL, SDIO/SDA, SDO, CS OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9, OUT10, OUT10, OUT11, OUT11 SYNC, RESET, PD REFMON, STATUS, LD SP0, SP1, EEPROM Junction Temperature 1 Storage Temperature Range Lead Temperature (10 sec)
1
With Respect to GND GND GND GND GND GND CLK GND GND
Rating −0.3 V to +3.6 V −0.3 V to +5.8 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −1.2 V to +1.2 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL RESISTANCE
Thermal impedance measurements were taken on a JEDEC JESD51-5 2S2P test board in still air in accordance with JEDEC JESD51-2. See the Thermal Performance section for more details. Table 20.
Package Type 64-Lead LFCSP (CP-64-4) θJA 22 Unit °C/W
GND GND GND
−0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V 150°C −65°C to +150°C 300°C
ESD CAUTION
See Table 20 for θJA.
Rev. 0 | Page 16 of 84
AD9522-3 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
REFIN (REF1) REFIN (REF2) CPRSET VS VS GND RSET VS OUT0 (OUT0A) OUT0 (OUT0B) VS OUT1 (OUT1A) OUT1 (OUT1B) OUT2 (OUT2A) OUT2 (OUT2B) VS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VS REFMON LD VCP CP STATUS REF_SEL SYNC LF BYPASS VS VS CLK CLK CS SCLK/SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
AD9522
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
OUT3 (OUT3A) OUT3 (OUT3B) VS OUT4 (OUT4A) OUT4 (OUT4B) OUT5 (OUT5A) OUT5 (OUT5B) VS VS OUT8 (OUT8B) OUT8 (OUT8A) OUT7 (OUT7B) OUT7 (OUT7A) VS OUT6 (OUT6B) OUT6 (OUT6A)
SDIO/SDA SDO GND SP1 SP0 EEPROM RESET PD OUT9 (OUT9A) OUT9 (OUT9B) VS OUT10 (OUT10A) OUT10 (OUT10B) OUT11 (OUT11A) OUT11 (OUT11B) VS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES 1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
Figure 5. Pin Configuration
Table 21. Pin Function Descriptions
Pin No. 1, 11, 12, 27, 32, 35, 40, 41, 46, 49, 54, 57, 60, 61 2 3 4 5 6 7 8 Input/ Output I Pin Type Power Mnemonic VS Description 3.3 V Power Pins.
O O I O O I I
3.3 V CMOS 3.3 V CMOS Power Loop filter 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS
REFMON LD VCP CP STATUS REF_SEL SYNC
9 10 13 14
I O I I
Loop filter Loop filter Differential clock input Differential clock input
LF BYPASS CLK CLK
Reference Monitor (Output). This pin has multiple selectable outputs. Lock Detect (Output). This pin has multiple selectable outputs. Power Supply for Charge Pump (CP); VS < VCP < 5.0 V. VCP must still be connected to 3.3 V if the PLL is not used. Charge Pump (Output). This pin connects to an external loop filter. This pin can be left unconnected if the PLL is not used. Programmable Status Output. Reference Select. It selects REF1 (low) or REF2 (high). This pin has an internal 30 kΩ pull-down resistor. Manual Synchronizations and Manual Holdover. This pin initiates a manual synchronization and is used for manual holdover. Active low. This pin has an internal 30 kΩ pull-up resistor. Loop Filter (Input). It connects internally to the VCO control voltage node. This pin is for bypassing the LDO to ground with a 220 nF capacitor. This pin can be left unconnected if the PLL is not used. Along with CLK, this pin is the differential input for the clock distribution section. Along with CLK, this pin is the differential input for the clock distribution section. If a single-ended input is connected to the CLK pin, connect a 0.1 μF bypass capacitor from this pin to ground.
Rev. 0 | Page 17 of 84
07224-003
AD9522-3
Pin No. 15 16 17 18 19, 59 20 21 22 Input/ Output I I I/O O I I I I Pin Type 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS GND Three-level logic Three-level logic 3.3 V CMOS Mnemonic CS SCLK/SCL SDIO/SDA SDO GND SP1 SP0 EEPROM Description Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor. Serial Control Port Clock Signal. This pin has an internal 30 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode. Serial Control Port Bidirectional Serial Data In/Out. Serial Control Port Unidirectional Serial Data Out. Ground Pins. Select SPI or I²C as the serial interface port and select the I²C slave address in I²C mode. Three-level logic. This pin is internally biased for the open logic level. Select SPI or I²C as the serial interface port and select the I²C slave address in I²C mode. Three-level logic. This pin is internally biased for the open logic level. Setting this pin high selects the register values stored in the internal EEPROM to be loaded at reset and/or power-up. Setting this pin low causes the AD9522 to load the hard-coded default register values at power-up/reset. This pin has an internal 30 kΩ pull-down resistor. Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor. Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output.
23 24 25 26 28 29 30 31 33 34 36 37 38 39 42 43 44 45
I I O O O O O O O O O O O O O O O O
3.3 V CMOS 3.3 V CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS
RESET PD OUT9 (OUT9A) OUT9 (OUT9B) OUT10 (OUT10A) OUT10 (OUT10B) OUT11 (OUT11A) OUT11 (OUT11B) OUT6 (OUT6A) OUT6 (OUT6B) OUT7 (OUT7A) OUT7 (OUT7B) OUT8 (OUT8A) OUT8 (OUT8B) OUT5 (OUT5B) OUT5 (OUT5A) OUT4 (OUT4B) OUT4 (OUT4A)
Rev. 0 | Page 18 of 84
AD9522-3
Pin No. 47 48 50 51 52 53 55 56 58 62 63 64 EPAD Input/ Output O O O O O O O O O O I I Pin Type LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS LVDS or CMOS Current set resistor Current set resistor Reference input Reference input GND Mnemonic OUT3 (OUT3B) OUT3 (OUT3A) OUT2 (OUT2B) OUT2 (OUT2A) OUT1 (OUT1B) OUT1 (OUT1A) OUT0 (OUT0B) OUT0 (OUT0A) RSET CPRSET REFIN (REF2) REFIN (REF1) GND Description Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Output. This pin can be configured as one side of a differential LVDS output or as a single-ended CMOS output. Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin to GND. Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND. This resistor can be omitted if the PLL is not used. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF2. Along with REFIN, this is the differential input for the PLL reference. Alternatively, this pin is a single-ended input for REF1. The exposed die pad must be connected to GND.
Rev. 0 | Page 19 of 84
AD9522-3 TYPICAL PERFORMANCE CHARACTERISTICS
275 3 CHANNELS—6 LVDS 250 225
CURRENT (mA)
CURRENT FROM CP PIN (mA)
5
4
PUMP DOWN PUMP UP
200 175 150 125 100 75 0 200 400
3 CHANNELS—3 LVDS
3
2 CHANNELS—2 LVDS
2
1
1 CHANNEL—1 LVDS 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V)
07224-108
600
800
1000
FREQUENCY (MHz)
Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), Channel and VCO Divider Bypassed, LVDS Outputs Terminated 100 Ω Across Differential Pair
240 2 CHANNELS—8 CMOS 220 200
CURRENT (mA) CURRENT FROM CP PIN (mA)
4 5
Figure 9. Charge Pump Characteristics @ VCP = 3.3 V
PUMP DOWN 3
PUMP UP
180 160 140 120 100 80 0 50 100 150 200 250 FREQUENCY (MHz) 1 CHANNEL—2 CMOS 2 CHANNELS—2 CMOS
2
1
1 CHANNEL—1 CMOS
07224-109
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VOLTAGE ON CP PIN (V)
Figure 7. Total Current vs. Frequency, CLK-to-Output (PLL Off), Channel and VCO Divider Bypassed, CMOS Outputs with 10 pF Load
70 65 60 55
KVCO (MHz/V)
PFD PHASE NOISE REFERRED TO PFD INPUT (dBc/Hz)
Figure 10. Charge Pump Characteristics @ VCP = 5.0 V
–140
–145
–150
50 45 40 35 30
07224-010
–155
–160
–165
1.8
1.9
2.0
2.1
2.2
2.3
1
10
100
VCO FREQUENCY (GHz)
PFD FREQUENCY (MHz)
Figure 8. KVCO vs. VCO Frequency
Figure 11. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
Rev. 0 | Page 20 of 84
07224-013
25 1.7
–170 0.1
07224-112
0
07224-111
AD9522-3
–208 –210
PLL FIGURE OF MERIT (dBc/Hz)
0 –10 –20
–212 –30
POWER (dBm)
–214 –216 –218 DIFFERENTIAL INPUT –220
–40 –50 –60 –70 –80
–222 SINGLE-ENDED INPUT
07224-114
–90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 122.58 122.78 122.98 123.18 123.38
07224-117 07224-014 07224-118
–224 INPUT SLEW RATE (V/ns)
–100 122.38
FREQUENCY (MHz)
Figure 12. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN
1.9
Figure 15. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; fVCO = 1720 MHz
3.5 VS_DRV = 3.3V 3.0
1.7
VCO TUNING VOLTAGE (V)
VS_DRV = 3.135V VS_DRV = 2.5V VS_DRV = 2.35V
2.5 1.5
VOH (V)
2.0 1.5 1.0
1.3
1.1 0.5 0.9 1.7 0 10k
1.8
1.9
2.0
2.1
2.2
2.3
07224-115
1k RESISTIVE LOAD (Ω)
100
FREQUENCY (GHz)
Figure 13. VCO Tuning Voltage vs. Frequency
0 –10 –20
DIFFERENTIAL OUTPUT (V)
Figure 16. CMOS Output VOH (Static) vs. RLOAD (to Ground)
0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TIME (ns)
–30
POWER (dBm)
–40 –50 –60 –70 –80 –90 –100 105 110 115 120 125 130 135 140 145
07224-116
–110 100
FREQUENCY (MHz)
Figure 14. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz; LBW = 127 kHz; ICP = 3.0 mA; fVCO = 1720 MHz
Figure 17. LVDS Output (Differential) @ 100 MHz Output Terminated 100 Ω Across Differential Pair
Rev. 0 | Page 21 of 84
AD9522-3
0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 0.5 1.0 1.5 TIME (ns) 2.0 2.5 3.0
DIFFERENTIAL SWING (mV p-p) 1600 1400 1200 1000 800 DEFAULT 3.5mA SETTING 600 400 200 0 0 200 400 600 800 1000 FREQUENCY (GHz)
7mA SETTING
DIFFERENTIAL SWING (V p-p)
07224-015
Figure 18. LVDS Differential Voltage Swing @ 800 MHz Output Terminated 100 Ω Across Differential Pair
3.2 2.8 2.4
AMPLITUDE (V)
Figure 21. LVDS Differential Voltage Swing vs. Frequency Output Terminated 100 Ω Across Differential Pair
4.0 3.5 3.0 2pF
AMPLITUDE (V)
2.0 1.6 1.2 0.8 0.4 0 0 10 20 30 40 50 TIME (ns) 60 70 80 90 100
2.5 2.0 1.5 1.0 0.5 10pF 20pF
07224-018
0
100
200
300
400
500
600
700
FREQUENCY (MHz)
Figure 19. CMOS Output with 10 pF Load @ 25 MHz
Figure 22. CMOS Output Swing vs. Frequency and Capacitive Load
–50 –60 –70
3.2 2.8
2pF LOAD
PHASE NOISE (dBc/Hz)
2.4 AMPLITUDE (V) 2.0 1.6 1.2 0.8 0.4 0 0 1 2 3 4 5 TIME (ns) 6
10pF LOAD
–80 –90 –100 –110 –120 –130 –140 –150
07224-019
7
8
9
10
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 20. CMOS Output with 2 pF and 10 pF Load @ 250 MHz
Figure 23. Internal VCO Phase Noise (Absolute), LVDS Output @ 573 MHz
Rev. 0 | Page 22 of 84
07224-023
–160 1k
07224-124
0
07224-123
AD9522-3
–50 –60 –70 –110 –100
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
07224-024
–80 –90 –100 –110 –120 –130 –140 –150 10k 100k 1M 10M 100M
–120
–130
–140
–150
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. Internal VCO Phase Noise (Absolute), LVDS Output @ 662 MHz
–50 –60 –70 –110 –100
Figure 27. Additive (Residual) Phase Noise, CLK-to-LVDS @ 200 MHz, Divide-by-5
PHASE NOISE (dBc/Hz)
–90 –100 –110 –120 –130 –140 –150
07224-025
PHASE NOISE (dBc/Hz)
–80
–120
–130
–140
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 25. Internal VCO Phase Noise (Absolute), LVDS Output @ 750 MHz
–100 –110
Figure 28. Additive (Residual) Phase Noise, CLK-to-LVDS @ 800 MHz, Divide-by-1
–110
–120
PHASE NOISE (dBc/Hz)
–120
PHASE NOISE (dBc/Hz)
–130
–130
–140
–140
–150
–150
–160
07224-128
100
1k
10k
100k
1M
10M
100M
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 26. Additive (Residual) Phase Noise, CLK-to-LVDS @ 245.76 MHz, Divide-by-1
Figure 29. Additive (Residual) Phase Noise, CLK-to-CMOS @ 50 MHz, Divide-by-20
Rev. 0 | Page 23 of 84
07224-131
–160 10
–170 10
07224-130
–160 1k
–150 10
07224-129
–160 1k
–160 10
AD9522-3
–100 –80 INTEGRATED RMS JITTER (12kHz TO 20MHz): 146fs –110 –90 –100 –110 –120 –130 –140 –150 –160 1k
PHASE NOISE (dBc/Hz)
–120
–130
–140
–150
07224-132
100
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 30. Additive (Residual) Phase Noise, CLK-to-CMOS @ 250 MHz, Divide-by-4
–100
Figure 33. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112) @ 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVDS Output = 245.76 MHz
R2 390Ω C2 62pF C1 240nF R1 820Ω C3 33pF BYPASS
07224-234
CP
–110
LF
PHASE NOISE (dBc/Hz)
–120
–130
BYPASS CAPACITOR FOR LDO
C12 220nF
–140
Figure 34. PLL Loop Filter Used for Clock Generation Plot (See Figure 31)
R2 3kΩ C2 1.5nF
10k 100k 1M 10M 100M
07224-033
–150
CP
–160 1k
C1 4.7µF R1 2.1kΩ
LF C3 2.2nF BYPASS
07224-235
FREQUENCY (Hz)
Figure 31. Phase Noise (Absolute) Clock Generation; Internal VCO @ 1720 MHz; PFD = 15.36 MHz; LBW = 40 kHz; LVDS Output = 122.88 MHz
–80 –90 –100 –110 –120 –130 –140 –150 –160 1k
INTEGRATED RMS JITTER (12kHz TO 20MHz): 440fs INTEGRATED RMS JITTER (20kHz TO 80MHz): 347fs (EXTRAPOLATED)
BYPASS CAPACITOR FOR LDO
C12 220nF
Figure 35. PLL Loop Filter Used for Clock Cleanup Plot (See Figure 32)
PHASE NOISE (dBc/Hz)
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 32. Phase Noise (Absolute) Clock Cleanup; Internal VCO @ 1866 MHz; PFD = 120 kHz; LBW = 1.92 kHz; LVDS Output = 155.52 MHz
Rev. 0 | Page 24 of 84
07224-034
07224-135
–160 10
PHASE NOISE (dBc/Hz)
AD9522-3 TERMINOLOGY
Phase Jitter and Phase Noise An ideal sine wave can be thought of as having a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as Gaussian (normal) in distribution. This phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values whose units are dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. It is meaningful to integrate the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase noise has a detrimental effect on the performance of ADCs, DACs, and RF mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the signal-to-noise ratio (SNR) and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter.
Rev. 0 | Page 25 of 84
AD9522-3 DETAILED BLOCK DIAGRAM
REF_SEL VS GND RSET DISTRIBUTION REFERENCE LD REFMON CPRSET VCP REFERENCE SWITCHOVER REF1
PROGRAMMABLE R DELAY
CLOCK DOUBLER
LOCK DETECT
OPTIONAL REFIN
REF2
STATUS BUF
R DIVIDER
STATUS
PLL REFERENCE
HOLD
REFIN AMP LOW DROPOUT REGULATOR (LDO) STATUS P, P + 1 PRESCALER LF A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP
BYPASS
N DIVIDER ZERO DELAY BLOCK DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK 1 0 DIVIDE BY 1 TO 32 DIGITAL LOGIC EEPROM OUT1 OUT1 OUT0 OUT0 STATUS
PD SYNC RESET EEPROM
OUT2 OUT2
OUT3 SP1 SP0 SERIAL PORT DECODE DIVIDE BY 1 TO 32 SPI INTERFACE SCLK/SCL SDIO/SDA SDO CS I2C INTERFACE OUT3
OUT4 OUT4
OUT5 OUT5
OUT6 OUT6
DIVIDE BY 1 TO 32
OUT7 OUT7
OUT8 OUT8
OUT9 OUT9
DIVIDE BY 1 TO 32
OUT10 OUT10
AD9522
OUT11
07224-028
OUT11
Figure 36.
Rev. 0 | Page 26 of 84
LVDS/LVCMOS OUTPUT
AD9522-3 THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
The AD9522 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 48 to Table 59). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. When the desired configuration is programmed, the user can store these values in the on-board EEPROM to allow the part to power up in the desired configuration without user intervention. Table 22. Settings When Using Internal VCO
Register 0x010[1:0] = 00b 0x010 to 0x01E Description PLL normal operation (PLL on) PLL settings; select and enable a reference input; set R, N (P, A, B), PFD polarity, and ICP according to the intended loop configuration VCO selected as the source Enable reference inputs Set VCO divider Use the VCO divider as the source for the distribution section Reset VCO calibration and issue IO_UPDATE (not necessary for the first time after power-up but must be done subsequently) Initiate VCO calibration, issue IO_UPDATE
Mode 0: Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must be employed to ensure that the frequency presented to the channel dividers does not exceed its specified maximum frequency (see Table 3). The internal PLL uses an external loop filter to set the loop bandwidth. The external loop filter is also crucial to the loop stability. When using the internal VCO, it is necessary to calibrate the VCO (0x018[0]) to ensure optimal performance. For internal VCO and clock distribution applications, the register settings shown in Table 22 should be used.
0x1E1[1] = 1b 0x01C[2:0] 0x1E0[2:0] 0x1E1[0] = 0b 0x018[0] = 0b 0x232[0] = 1b 0x018[0] = 1b 0x232[0] = 1b
Rev. 0 | Page 27 of 84
AD9522-3
REF_SEL VS GND RSET DISTRIBUTION REFERENCE LD REFMON CPRSET VCP
REFERENCE SWITCHOVER REF1 REF2
OPTIONAL REFIN
STATUS BUF
PLL REFERENCE
R DIVIDER
STATUS
PROGRAMMABLE R DELAY
CLOCK DOUBLER
LOCK DETECT
HOLD
REFIN AMP LOW DROPOUT REGULATOR (LDO) STATUS P, P + 1 PRESCALER LF A/B COUNTERS PROGRAMMABLE N DELAY PHASE FREQUENCY DETECTOR CHARGE PUMP CP
BYPASS
N DIVIDER ZERO DELAY BLOCK DIVIDE BY 1, 2, 3, 4, 5, OR 6 CLK CLK 1 0 DIVIDE BY 1 TO 32 DIGITAL LOGIC EEPROM OUT0 OUT0 STATUS
PD SYNC RESET EEPROM
OUT1 OUT1
OUT2 OUT2
OUT3 SP1 SP0 SERIAL PORT DECODE DIVIDE BY 1 TO 32 SPI INTERFACE SCLK/SCL SDIO/SDA SDO CS I2C INTERFACE OUT3
OUT4 OUT4
OUT5 OUT5
OUT6 OUT6
DIVIDE BY 1 TO 32
OUT7 OUT7
OUT8 OUT8
OUT9 OUT9
DIVIDE BY 1 TO 32
OUT10 OUT10
AD9522
OUT11 OUT11
07224-030
Figure 37. Internal VCO and Clock Distribution (Mode 0)
Rev. 0 | Page 28 of 84
LVDS/CMOS OUTPUT
AD9522-3
Mode 1: Clock Distribution or External VCO < 1600 MHz
When the external clock source to be distributed or the external VCO/VCXO is threshold (read-only) 01F [1] Description Readback register. Indicates if the frequency of the signal at REF2 is greater than the threshold frequency set by Register 0x01A[6]. [2] = 0; REF2 frequency is less than the threshold frequency. [2] = 1; REF2 frequency is greater than the threshold frequency. REF1 frequency Readback register. Indicates if the frequency of the signal at REF1 is greater than the threshold frequency > threshold set by Register 0x01A[6]. (read-only) [1] = 0; REF1 frequency is less than the threshold frequency. [1] = 1; REF1 frequency is greater than the threshold frequency. Readback register. Digital lock detect. Digital lock detect [0] = 0; PLL is not locked. (read-only) [0] = 1; PLL is locked.
01F
[0]
Table 53. Output Driver Control
Reg. Addr (Hex) Bit(s) Name 0F0 [7] OUT0 format
0F0
[6:5]
OUT0 CMOS configuration
0F0
[4:3]
OUT0 polarity
0F0
[2:1]
OUT0 LVDS differential voltage
0F0
[0]
OUT0 LVDS power-down OUT1 control OUT2 control OUT3 control OUT4 control OUT5 control
0F1 0F2 0F3 0F4 0F5
[7:0] [7:0] [7:0] [7:0] [7:0]
Description Selects the output type for OUT0. [7] = 0; LVDS (default). [7] = 1; CMOS. Sets the CMOS output configuration for OUT0 when 0x0F0[7] = 1. [6:5] OUT0A OUT0B 00 Tristate Tristate 01 On Tristate 10 Tristate On 11 (default) On On Sets the output polarity for OUT0. [7] [4] [3] Output Type OUT0A OUT0B 0 (default) X 0 LVDS Noninverting Inverting 0 X 1 LVDS Inverting Noninverting 1 0 (default) 0 (default) CMOS Noninverting Noninverting 1 0 1 CMOS Inverting Inverting 1 1 0 CMOS Noninverting Inverting 1 1 1 CMOS Inverting Noninverting Sets the LVDS output differential voltage (VOD). [2] [1] IOD (mA) 0 0 1.75 (VOD = 175 mV for 100 Ω termination across differential pair) 0 (default) 1 (default) 3.5 (VOD = 350 mV for 100 Ω termination across differential pair) 1 0 5.25 (VOD = 525 mV for 100 Ω termination across differential pair) 1 1 7.0 (VOD = 700 mV for 100 Ω termination across differential pair) LVDS power-down. [0] = 0; normal operation (default). [0] = 1; power-down. Output driver is in a high impedance state. This register controls OUT1, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT2, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT3, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT4, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT5, and the bit assignments for this register are identical to Register 0x0F0.
Rev. 0 | Page 74 of 84
AD9522-3
Reg. Addr (Hex) 0F6 0F7 0F8 0F9 0FA 0FB 0FC Bit(s) [7:0] [7:0] [7:0] [7:0] [7:0] [7:0] [7] Name OUT6 control OUT7 control OUT8 control OUT9 control OUT10 control OUT11 control CSDLD En OUT7 Description This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0. This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0. OUT7 is enabled only if CSDLD is high. [7] CSDLD Signal OUT7 Enable Status 0 0 Not affected by CSDLD signal (default). 1 0 Asynchronous power-down. 1 1 Asynchronously enable OUT7 if not powered down by other settings. To use this feature, the user must use current source digital lock detect, and set the enable LD pin comparator bit (0x01D[3]). OUT6 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT5 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT4 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT3 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT2 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT1 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT0 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. OUT11 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
0FC 0FC 0FC 0FC 0FC 0FC 0FC 0FD 0FD 0FD 0FD
[6] [5] [4] [3] [2] [1] [0] [3] [2] [1] [0]
CSDLD En OUT6 CSDLD En OUT5 CSDLD En OUT4 CSDLD En OUT3 CSDLD En OUT2 CSDLD En OUT1 CSDLD En OUT0 CSDLD En OUT11 OUT10 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. CSDLD En OUT10 CSDLD En OUT9 OUT9 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7]. CSDLD En OUT8 OUT8 is enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Table 54. LVDS Channel Dividers
Reg. Addr (Hex) Bit(s) Name 190 [7:4] Divider 0 low cycles 190 191 [3:0] [7] Divider 0 high cycles Divider 0 bypass
191
[6]
Divider 0 ignore SYNC
191
[5]
Divider 0 force high
191
[4]
Divider 0 start high
191
[3:0]
Divider 0 phase offset
Description Number of clock cycles (minus 1) of the divider input during which divider output stays low. A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7). Number of clock cycles (minus 1) of the divider input during which divider output stays high. A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7). Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. Phase offset (default: 0x0).
Rev. 0 | Page 75 of 84
AD9522-3
Reg. Addr (Hex) Bit(s) Name 192 [2] Channel 0 power-down Description Channel 0 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT0/OUT0, OUT1/OUT1, and OUT2/OUT2 are put into the high impedance power-down mode by setting this bit.) Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x3 means the divider is low for four input clock cycles (default: 0x3). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x3 means the divider is high for four input clock cycles (default: 0x3). Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. Phase offset (default: 0x0). Channel 1 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT3/OUT3, OUT4/OUT4, and OUT5/OUT5 are put into the high impedance power-down mode by setting this bit.) Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x1 means the divider is low for two input clock cycles (default: 0x1). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x1 means the divider is high for two input clock cycles (default: 0x1). Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. Phase offset(default: 0x0).
192
[0]
Disable Divider 0 DCC
193 193 194
[7:4] [3:0] [7]
Divider 1 low cycles Divider 1 high cycles Divider 1 bypass
194
[6]
Divider 1 ignore SYNC
194
[5]
Divider 1 force high
194
[4]
Divider 1 start high
194 195
[3:0] [2]
Divider 1 phase offset Channel 1 power-down
195
[0]
Disable Divider 1 DCC
196 196 197
[7:4] [3:0] [7]
Divider 2 low cycles Divider 2 high cycles Divider 2 bypass
197
[6]
Divider 2 ignore SYNC
197
[5]
Divider 2 force high
197
[4]
Divider 2 start high
197
[3:0]
Divider 2 phase offset
Rev. 0 | Page 76 of 84
AD9522-3
Reg. Addr (Hex) Bit(s) Name 198 [2] Channel 2 power-down Description Channel 2 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT6/OUT6, OUT7/OUT7, and OUT8/OUT8 are put into the high impedance power-down mode by setting this bit.) Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction. Number of clock cycles (minus 1) of the divider input during which the divider output stays low. A value of 0x0 means the divider is low for one input clock cycle (default: 0x0). Number of clock cycles (minus 1) of the divider input during which the divider output stays high. A value of 0x0 means the divider is high for one input clock cycle (default: 0x0). Bypasses and powers down the divider; routes input to divider output. [7] = 0; use divider (default). [7] = 1; bypass divider. Ignore SYNC. [6] = 0; obey chip-level SYNC signal (default). [6] = 1; ignore chip-level SYNC signal. Forces divider output to high. This requires that ignore SYNC also be set. [5] = 0; divider output forced to low (default). [5] = 1; divider output forced to high. Selects clock output to start high or start low. [4] = 0; start low (default). [4] = 1; start high. Phase offset (default: 0x0). Channel 3 powers down. [2] = 0; normal operation (default). [2] = 1; powered down. (OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 are put into the high impedance power-down mode by setting this bit.) Duty-cycle correction function. [0] = 0; enable duty-cycle correction (default). [0] = 1; disable duty-cycle correction.
198
[0]
Disable Divider 2 DCC
199 199 19A
[7:4] [3:0] [7]
Divider 3 low cycles Divider 3 high cycles Divider 3 bypass
19A
[6]
Divider 3 ignore SYNC
19A
[5]
Divider 3 force high
19A
[4]
Divider 3 start high
19A 19B
[3:0] [2]
Divider 3 phase offset Channel 3 power-down
19B
[0]
Disable Divider 3 DCC
Table 55. VCO Divider and CLK Input
Reg. Addr (Hex) Bit(s) Name 1E0 [2:0] VCO divider
1E1
[4]
Description [2] [1] [0] Divide 0 0 0 2 (default) 0 0 1 3 0 1 0 4 0 1 1 5 1 0 0 6 1 0 1 Output static 1 1 0 1 (bypass) 1 1 1 Output static Power-down clock input section Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree). [4] = 0; normal operation (default). [4] = 1; power down.
Rev. 0 | Page 77 of 84
AD9522-3
Reg. Addr (Hex) Bit(s) Name Description 1E1 [3] Power-down VCO clock interface Powers down the interface block between VCO and clock distribution. [3] = 0; normal operation (default). [3] = 1; power down. 1E1 [2] Power-down VCO and CLK Powers down both the CLK input and VCO. [2] = 0; normal operation (default). [2] = 1; power down. 1E1 [1] Select VCO or CLK Selects either the VCO or the CLK as the input to VCO divider. [1] = 0; select external CLK as input to VCO divider (default). [1] = 1; select VCO as input to VCO divider; cannot bypass VCO divider when this is selected. This bit must be set to use the PLL with the internal VCO. 1E1 [0] Bypass VCO divider Bypasses or uses the VCO divider. [0] = 0; use VCO divider (default). [0] = 1; bypass VCO divider; cannot select VCO as input when this is selected.
Table 56. System
Reg. Addr (Hex) Bit(s) Name 230 [3] Disable power-on SYNC
230
[2]
Power-down SYNC
230
[1]
Power-down distribution reference
230
[0]
Soft SYNC
Description Power-on SYNC mode. Used to disable the antiruntpulse circuitry. [3] = 0; enable the antiruntpulse circuitry (default). [3] = 1; disable the antiruntpulse circuitry. Powers down the SYNC function. [2] = 0; normal operation of the SYNC function (default). [2] = 1; power-down SYNC circuitry. Powers down the reference for the distribution section. [1] = 0; normal operation of the reference for the distribution section (default). [1] = 1; powers down the reference for the distribution section. The soft SYNC bit works the same as the SYNC pin, except that the polarity of the bit is reversed; that is, a high level forces selected channels into a predetermined static state, and a 1-to-0 transition triggers a SYNC. [0] = 0; same as SYNC high. [0] = 1; same as SYNC low.
Table 57. Update All Registers
Reg. Addr (Hex) Bit(s) Name 232 [0] IO_UPDATE
Description This bit must be set to 1 to transfer the contents of the buffer registers into the active registers. This happens on the next SCLK rising edge. This bit is self-clearing; that is, it does not have to be set back to 0. [0] = 1 (self-clearing); update all active registers to the contents of the buffer registers.
Rev. 0 | Page 78 of 84
AD9522-3
Table 58. EEPROM Buffer Segment
Reg. Addr (Hex) Bit(s) Name A00 to [7:0] EEPROM Buffer A16 Segment Register 1 to EEPROM Buffer Segment Register 23
Description The EEPROM buffer segment section stores the starting address and number of bytes that are to be stored and read back to and from the EEPROM. Because the AD9522 register space is noncontiguous, the EEPROM controller needs to know the starting address and number of bytes in the AD9522 register space to store and retrieve from the EEPROM. In addition, there are special instructions for the EEPROM controller, operational codes (that is, IO_UPDATE and end-of-data) that are also stored in the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment registers is designed such that all registers are transferred to/from the EEPROM, and an IO_UPDATE is issued after transfer. See the Programming the EEPROM Buffer Segment section for more information.
Table 59. EEPROM Control
Reg. Addr (Hex) Bit(s) Name Description B00 [0] STATUS_EEPROM This read-only register indicates the status of the data transferred between the EEPROM and the buffer (read-only) register bank during the writing and reading of the EEPROM. This signal is also available at the STATUS pin when 0x01D[7] is set. [0] = 0; data transfer is done. [0] = 1; data transfer is not done. B01 [0] This read-only register indicates an error during the data transferred between the EEPROM and the buffer. EEPROM data error [0] = 0; no error. Data is correct. (read-only) [0] = 1; incorrect data detected. B02 [1] Soft_EEPROM When the EEPROM pin is tied low, setting Soft_EEPROM resets the AD9522 using the settings saved in EEPROM. [1] = 1; soft reset with EEPROM settings (self-clearing). This bit self clears on the next serial port clock cycle after the completion of writing to this register. B02 [0] Enable EEPROM Enables the user to write to the EEPROM. write [0] = 0; EEPROM write protection is enabled. User cannot write to EEPROM (default). [0] = 1; EEPROM write protection is disabled. User can write to EEPROM. B03 [0] REG2EEPROM Transfers data from the buffer register to the EEPROM (self-clearing). [0] = 1; setting this bit initiates the data transfer from the buffer register to the EEPROM (writing process); it is reset by the I²C master after the data transfer is done.
Rev. 0 | Page 79 of 84
AD9522-3 APPLICATIONS INFORMATION
FREQUENCY PLANNING USING THE AD9522
The AD9522 is a highly flexible PLL. When choosing the PLL settings and version of the AD9522, the following guidelines should be kept in mind. The AD9522 has four frequency dividers: the reference (or R) divider, the feedback (or N) divider, the VCO divider, and the channel divider. When trying to achieve a particularly difficult frequency divide ratio requiring a large amount of frequency division, some of the frequency division can be done by either the VCO divider or the channel divider, thus allowing a higher phase detector frequency and more flexibility in choosing the loop bandwidth. Within the AD9522 family, lower VCO frequencies generally result in slightly better jitter. The difference in integrated jitter (from 12 kHz to 20 MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.4 GHz to 2.95 GHz) of the AD9522 family. If the desired frequency plan can be achieved with a version of the AD9522 that has a lower VCO frequency, choosing the lower frequency part results in the best phase noise and the lowest jitter. However, choosing a higher VCO frequency can result in more flexibility in frequency planning. Choosing a nominal charge pump current in the middle of the allowable range as a starting point allows the designer to increase or decrease the charge pump current, and thus allows the designer to fine-tune the PLL loop bandwidth in either direction. ADIsimCLK is a powerful PLL modeling tool that can be downloaded from www.analog.com and is a very accurate tool for determining the optimal loop filter for a given application.
Figure 70 shows the required sampling clock jitter as a function of the analog frequency and effective number of bits (ENOB).
110 100 90 80 1 SNR = 20log 2πf t AJ 18 16
70 60 50 40 30 10
200 fs tJ = 400 fs tJ = 1ps tJ = 2ps
SNR (dB)
tJ = 100 fs tJ =
14 12 10 8
tJ = 10p
s
6
07224-044
100
1k
fA (MHz)
Figure 70. SNR and ENOB vs. Analog Input Frequency
See the AN-756 Application Note and the AN-501 Application Note at www.analog.com. Many high performance ADCs feature differential clock inputs to simplify the task of providing the required low jitter clock on a noisy PCB. Distributing a single-ended clock on a noisy PCB can result in coupled noise on the sampling clock. Differential distribution has inherent common-mode rejection that can provide superior clock performance in a noisy environment. The differential LVDS outputs of the AD9522 enable clock solutions that maximize converter SNR performance. The input requirements of the ADC (differential or singleended, logic level termination) should be considered when selecting the best clocking/converter solution. In some cases, the LVPECL outputs of the AD9520 may be desirable for clocking a converter instead of the LVDS outputs of the AD9522.
USING THE AD9522 OUTPUTS FOR ADC CLOCK APPLICATIONS
Any high speed ADC is extremely sensitive to the quality of the sampling clock of the AD9522. An ADC can be thought of as a sampling mixer, and any noise, distortion, or time jitter on the clock is combined with the desired signal at the analog-todigital output. Clock integrity requirements scale with the analog input frequency and resolution, with higher analog input frequency applications at ≥14-bit resolution being the most stringent. The theoretical SNR of an ADC is limited by the ADC resolution and the jitter on the sampling clock. Considering an ideal ADC of infinite resolution where the step size and quantization error can be ignored, the available SNR can be expressed approximately by
LVDS CLOCK DISTRIBUTION
The AD9522 provides clock outputs that are selectable as either CMOS or LVDS level outputs. LVDS is a differential output option that uses a current mode output stage. The nominal current is 3.5 mA, which yields 350 mV output swing across a 100 Ω resistor. An output current of 7 mA is also available in cases where a larger output swing is required. The LVDS output meets or exceeds all ANSI/TIA/EIA-644 specifications.
⎛1 SNR(dB) = 20log ⎜ ⎜ 2πf t AJ ⎝
⎞ ⎟ ⎟ ⎠
where: fA is the highest analog frequency being digitized. tJ is the rms jitter on the sampling clock.
Rev. 0 | Page 80 of 84
ENOB
AD9522-3
A recommended termination circuit for the LVDS outputs is shown in Figure 71. If ac coupling is necessary, place decoupling capacitors either before or after the 100 Ω termination resistor.
VS VS
LVDS
100Ω DIFFERENTIAL (COUPLES) 100Ω
LVDS
07224-047
The value of the resistor is dependent on the board design and timing requirements (typically 10 Ω to 100 Ω is used). CMOS outputs are also limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 3 inches are recommended to preserve signal rise/fall times and signal integrity.
07224-076
CMOS
10Ω
60.4Ω (1.0 INCH) CMOS MICROSTRIP
Figure 71. LVDS Output Termination
Figure 72. Series Termination of CMOS Output
See the AN-586 Application Note at www.analog.com for more information on LVDS.
CMOS CLOCK DISTRIBUTION
The output drivers of the AD9522 can be configured as CMOS drivers. When selected as a CMOS driver, each output becomes a pair of CMOS outputs, each of which can be individually turned on or off and set as inverting or noninverting. These outputs are 3.3 V CMOS compatible. When single-ended CMOS clocking is used, some of the following guidelines apply. Point-to-point connections should be designed such that each driver has only one receiver, if possible. Connecting outputs in this manner allows for simple termination schemes and minimizes ringing due to possible mismatched impedances on the output trace. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver.
Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9522 do not supply enough current to provide a full voltage swing with a low impedance resistive, farend termination, as shown in Figure 73. The far-end termination network should match the PCB trace impedance and provide the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets.
VS 10Ω 50Ω 100Ω CMOS 100Ω
07224-077
CMOS
Figure 73. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9522 offers LVDS outputs that are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters.
Rev. 0 | Page 81 of 84
AD9522-3 OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
48 49 64 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 8.75 BSC SQ 0.50 BSC EXPOSED PAD
(BOTTOM VIEW)
6.35 6.20 SQ 6.05
0.50 0.40 0.30 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
33 32
16 17
7.50 REF
0.25 MIN
1.00 0.85 0.80
SEATING PLANE
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 74. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 9 mm × 9 mm Body, Very Thin Quad CP-64-4 Dimensions shown in millimeters
ORDERING GUIDE
Model AD9522-3BCPZ 1 AD9522-3BCPZ-REEL71 AD9522-3/PCBZ1
1
Temperature Range −40°C to +85°C −40°C to +85°C
Package Description 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board
Z = RoHS Compliant Part.
Rev. 0 | Page 82 of 84
091707-C
Package Option CP-64-4 CP-64-4
AD9522-3 NOTES
Rev. 0 | Page 83 of 84
AD9522-3 NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07224-0-10/08(0)
Rev. 0 | Page 84 of 84
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