FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Low jitter, low phase noise clock distribution
Clock generation and translation for SONET, 10Ge, 10G FC,
and other 10 Gbps protocols
Forward error correction (G.710)
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
ATE and high performance instrumentation
Broadband infrastructures
GENERAL DESCRIPTION
The AD9522-41 provides a multioutput clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.4 GHz to
1.8 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz
can also be used.
1
CP
OPTIONAL
REF1
REFIN
REFIN
CLK
REF2
LF
STATUS
MONITOR
PLL
Low phase noise, phase-locked loop (PLL)
On-chip voltage controlled oscillator (VCO) tunes from
1.4 GHz to 1.8 GHz
Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz
1 differential or 2 single-ended reference inputs
Accepts CMOS, LVPECL, or LVDS references to 250 MHz
Accepts 16.62 MHz to 33.3 MHz crystal for reference input
Optional reference clock doubler
Reference monitoring capability
Revertive automatic and manual reference switchover/
holdover modes
Glitch-free switchover between references
Automatic recovery from holdover
Digital or analog lock detect, selectable
Optional zero delay operation
Twelve 800 MHz LVDS outputs divided into 4 groups
Each group of 3 has a 1-to-32 divider with phase delay
Additive output jitter as low as 242 fs rms
Channel-to-channel skew grouped outputs 50 V/µs
1.75
1.60
5.9
6.4
V
V
kΩ
kΩ
250
MHz
250
MHz
0
0.55
250
3.28
MHz
V p-p
Slew rate must be > 50 V/µs, and input amplitude
sensitivity specification must be met; see input sensitivity
Slew rate > 50 V/µs; CMOS levels
VIH must not exceed VS
1.5
2.78
V p-p
VIH must not exceed VS
0.8
+100
V
V
µA
pF
Each pin, REFIN (REF1)/REFIN (REF2)
10
2.0
−100
2
Rev. A | Page 5 of 84
AD9522-4
Parameter
Pulse Width High/Low
Data Sheet
Max
Unit
ns
33.33
30
MHz
Ω
100
45
50
1.3
2.9
6.0
MHz
MHz
MHz
ns
ns
ns
CHARGE PUMP (CP)
ICP Sink/Source
High Value
4.8
mA
Low Value
0.60
mA
Crystal Oscillator
Crystal Resonator Frequency Range
Maximum Crystal Motional Resistance
PHASE/FREQUENCY DETECTOR (PFD)
PFD Input Frequency
Reference Input Clock Doubler Frequency
Antibacklash Pulse Width
Absolute Accuracy
CPRSET Range
ICP High Impedance Mode Leakage
Sink-and-Source Current Matching
ICP vs. VCP
ICP vs. Temperature
PRESCALER (PART OF N DIVIDER)
Prescaler Input Frequency
P = 1 FD
P = 2 FD
P = 3 FD
P = 2 DM (2/3)
P = 4 DM (4/5)
P = 8 DM (8/9)
P = 16 DM (16/17)
P = 32 DM (32/33)
Prescaler Output Frequency
PLL N DIVIDER DELAY
000
001
010
011
100
101
110
111
Min
1.8
Typ
16.62
0.004
2.5
1
1
%
kΩ
nA
%
1.5
2
%
%
2.7
10
300
600
900
200
1000
2400
3000
3000
300
Off
385
504
623
743
866
989
1112
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
Rev. A | Page 6 of 84
Test Conditions/Comments
Amount of time a square wave is high/low determines the
allowable input duty cycle
Antibacklash pulse width = 1.3 ns, 2.9 ns
Antibacklash pulse width = 6.0 ns
Antibacklash pulse width = 1.3 ns, 2.9 ns
Register 0x017[1:0] = 01b
Register 0x017[1:0] = 00b; Register 0x017[1:0] = 11b
Register 0x017[1:0] = 10b
Programmable
With CPRSET = 5.1 kΩ; higher ICP is possible by
changing CPRSET
With CPRSET = 5.1 kΩ; lower ICP is possible by
changing CPRSET
Charge pump voltage set to VCP/2
0.5 V < VCP < VCP − 0.5 V; VCP is the voltage on the CP (charge
pump) pin; VCP is the voltage on the VCP power supply pin
0.5 V < VCP < VCP − 0.5 V
VCP = VCP/2 V
A, B counter input frequency (prescaler input frequency
divided by P)
Register 0x019[2:0]; see Table 53
Data Sheet
Parameter
PLL R DIVIDER DELAY
000
001
010
011
100
101
110
111
PHASE OFFSET IN ZERO DELAY
Phase Offset (REF-to-LVDS Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-LVDS Clock Output
Pins) in Internal Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
Phase Offset (REF-to-CLK Input Pins) in
External Zero Delay Mode
NOISE CHARACTERISTICS
In-Band Phase Noise of the Charge Pump/
Phase Frequency Detector (In-Band
Means Within the LBW of the PLL)
At 500 kHz PFD Frequency
At 1 MHz PFD Frequency
At 10 MHz PFD Frequency
At 50 MHz PFD Frequency
PLL Figure of Merit (FOM)
AD9522-4
Min
Typ
Max
Off
365
486
608
730
852
976
1101
Unit
ps
ps
ps
ps
ps
ps
ps
1890
2348
3026
ps
REF refers to REFIN (REF1)/REFIN (REF2)
When N delay and R delay are bypassed
900
1217
1695
ps
When N delay = Setting 111 and R delay is bypassed
318
677
1085
ps
When N delay and R delay are bypassed
−329
+33
+360
ps
When N delay = Setting 011 and R delay is bypassed
The PLL in-band phase noise floor is estimated by
measuring the in-band phase noise at the output of
the VCO and subtracting 20 log(N) (where N is the value
of the N divider)
−165
−162
−152
−144
−222
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
Unlock Threshold (Hysteresis)2
3.5
7.5
3.5
ns
ns
ns
Low Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 1.3 ns, 2.9 ns)
High Range (ABP 6.0 ns)
7
15
11
ns
ns
ns
PLL DIGITAL LOCK DETECT WINDOW 2
Lock Threshold (Coincidence of Edges)
1
2
Test Conditions/Comments
Register 0x019[5:3]; see Table 53
Reference slew rate > 0.5 V/ns; FOM + 10 log (fPFD) is an
approximation of the PFD/CP in-band phase noise (in
the flat region) inside the PLL loop bandwidth; when
running closed-loop, the phase noise, as observed at
the VCO output, is increased by 20 log(N); PLL figure of
merit decreases with decreasing slew rate; see Figure 12
Signal available at the LD, STATUS, and REFMON pins
when selected by appropriate register settings; lock
detect window settings can be varied by changing the
CPRSET resistor
Selected by Register 0x017[1:0] and Register 0x018[4]
(this is the threshold to go from unlock to lock)
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
Selected by Register 0x017[1:0] and Register 0x018[4]
(this is the threshold to go from lock to unlock)
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 1b
Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[4] = 0b
Register 0x017[1:0] = 10b; Register 0x018[4] = 0b
The REFIN and REFIN self-bias points are offset slightly to avoid chatter on an open input condition.
For reliable operation of the digital lock detect, the period of the PFD frequency must be greater than the unlock-after-lock time.
Rev. A | Page 7 of 84
AD9522-4
Data Sheet
CLOCK INPUTS
Table 3.
Parameter
CLOCK INPUTS (CLK, CLK)
Input Frequency
Min
Typ
01
01
Input Sensitivity, Differential
1
Unit
2.4
2
GHz
GHz
150
Input Level, Differential
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Max
1.3
1.3
3.9
1.57
150
4.7
2
mV p-p
2
V p-p
1.8
1.8
V
V
mV p-p
kΩ
pF
5.7
Test Conditions/Comments
Differential input
High frequency distribution (VCO divider)
Distribution only (VCO divider bypassed); this is the
frequency range supported by the channel divider, see the
Channel Divider Maximum Frequency section
Measured at 2.4 GHz; jitter performance is improved with
slew rates > 1 V/ns
Larger voltage swings can turn on the protection diodes
and can degrade jitter performance
Self-biased; enables ac coupling
With 200 mV p-p signal applied; dc-coupled
CLK ac-coupled; CLK ac-bypassed to RF ground
Self-biased
Below about 1 MHz, the input must be dc-coupled. Take care to match VCM.
CLOCK OUTPUTS
Table 4.
Parameter
LVDS CLOCK OUTPUTS
OUT0, OUT1, OUT2, OUT3, OUT4, OUT5,
OUT6, OUT7, OUT8, OUT9, OUT10, OUT11
Output Frequency
Output Differential Voltage, VOD
Min
247
Typ
Max
Unit
Test Conditions/Comments
Termination = 100 Ω across differential pair
Differential (OUT, OUT)
800
MHz
454
mV
25
mV
1.25
1.375
25
V
mV
14
10 MHz Offset
CLK-TO-CMOS ADDITIVE PHASE NOISE
CLK = 1 GHz, Output = 500 MHz
Divider = 2
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
CLK = 1 GHz, Output = 50 MHz
Divider = 20
At 10 Hz Offset
At 100 Hz Offset
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
>10 MHz Offset
Min
Typ
−100
−110
−117
−126
−134
−137
−147
−148
Max
Unit
Test Conditions/Comments
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−111
−123
−132
−141
−146
−150
−156
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
−102
−114
−122
−129
−135
−140
−150
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Input slew rate > 1 V/ns
−125
−136
−144
−152
−157
−160
−164
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. A | Page 10 of 84
Data Sheet
AD9522-4
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVDS ABSOLUTE PHASE NOISE
VCO = 1.8 GHz; Output = 600 MHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
VCO = 1.6 GHz; Output = 533 MHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
VCO = 1.4 GHz; Output = 467 MHz
At 1 kHz Offset
At 10 kHz Offset
At 100 kHz Offset
At 1 MHz Offset
At 10 MHz Offset
At 40 MHz Offset
Min
Typ
Max
Unit
−64
−93
−116
−135
−148
−151
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−66
−96
−120
−137
−149
−151
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−71
−101
−124
−140
−150
−152
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Test Conditions/Comments
Internal VCO; VCO divider = 3; LVDS output and
for loop bandwidths < 1 kHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
Min
VCO = 1475 MHz; LVDS = 245.76 MHz; PLL LBW = 55 kHz
Typ
Max
127
285
145
299
194
351
VCO = 1475 MHz; LVDS = 122.88 MHz; PLL LBW = 55 kHz
VCO = 1475 MHz; LVDS = 61.44 MHz; PLL LBW = 55 kHz
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
clean, so a wider PLL loop bandwidth is
used; reference = 15.36 MHz; R DIV = 1
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
VCO = 1400 MHz; LVDS = 155.52 MHz; PLL LBW = 1.8 kHz
VCO = 1475 MHz; LVDS = 122.88 MHz; PLL LBW = 1.8 kHz
Min
Typ
Max
372
418
Rev. A | Page 11 of 84
Unit
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 19.44 MHz; R DIV = 162
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 12 kHz to 20 MHz
AD9522-4
Data Sheet
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
Min
Typ
LVDS = 245.76 MHz; PLL LBW = 125 Hz
Max
87
108
146
120
151
207
157
210
295
LVDS = 122.88 MHz; PLL LBW = 125 Hz
LVDS = 61.44 MHz; PLL LBW = 125 Hz
Unit
Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R DIV = 1
Integration bandwidth = 200 kHz to 5 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 200 kHz to 5 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 200 kHz to 5 MHz
Integration bandwidth = 200 kHz to 10 MHz
Integration bandwidth = 12 kHz to 20 MHz
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVDS OUTPUT ADDITIVE TIME JITTER
CLK = 622.08 MHz
Any LVDS Output = 622.08 MHz
Divide Ratio = 1
CLK = 622.08 MHz
Any LVDS Output = 155.52 MHz
Divide Ratio = 4
CLK = 100 MHz
Any LVDS Output = 100 MHz
Divide Ratio = 1
CLK = 500 MHz
Any LVDS Output = 100 MHz
Divide Ratio = 5
CMOS OUTPUT ADDITIVE TIME JITTER
CLK = 200 MHz
Any CMOS Output Pair = 100 MHz
Divide Ratio = 2
Min
Typ
Max
Unit
69
fs rms
Test Conditions/Comments
Distribution section only; does not include PLL and
VCO; measured at rising edge of clock signal
Integration bandwidth = 12 kHz to 20 MHz
116
fs rms
Integration bandwidth = 12 kHz to 20 MHz
263
fs rms
Calculated from SNR of ADC method
Broadband jitter
242
fs rms
Calculated from SNR of ADC method
Broadband jitter
289
fs rms
Distribution section only; does not include PLL and VCO
Calculated from SNR of ADC method
Broadband jitter
Rev. A | Page 12 of 84
Data Sheet
AD9522-4
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVDS OUTPUT ADDITIVE TIME JITTER
Min
Typ
Max
Unit
CLK = 500 MHz; VCO DIV = 5; LVDS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = On
CMOS OUTPUT ADDITIVE TIME JITTER
248
fs rms
CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = Off
CLK = 200 MHz; VCO DIV = 1; CMOS = 100 MHz;
Bypass Channel Divider; Duty-Cycle Correction = Off
290
fs rms
288
fs rms
Test Conditions/Comments
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
(broadband jitter)
Distribution section only; does not include
PLL and VCO; uses rising edge of clock signal
Calculated from SNR of ADC method
(broadband jitter)
Calculated from SNR of ADC method
(broadband jitter)
SERIAL CONTROL PORT—SPI MODE
Table 13.
Parameter
CS (INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Min
Max
Unit
0.8
3
−110
V
V
µA
µA
2
pF
2.0
Input Capacitance
SCLK (INPUT) IN SPI MODE
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup and Hold, tS, tC
CS Minimum Pulse Width High, tPWH
Typ
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
The minus sign indicates that current is flowing out of
the AD9522, which is due to the internal pull-up resistor
SCLK has an internal 30 kΩ pull-down resistor in SPI
mode, but not in I2C mode
2.0
0.8
110
1
2
2.0
0.8
1
1
2
2.7
0.4
25
16
16
4
0
11
2
3
V
V
µA
µA
pF
V
V
µA
µA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Rev. A | Page 13 of 84
At 1 mA current; maximum recommended current: 5 mA
At 1 mA current
AD9522-4
Data Sheet
SERIAL CONTROL PORT—I²C MODE
Table 14.
Parameter
SDA, SCL (WHEN INPUTTING DATA)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current with an Input Voltage Between
0.1 × VS and 0.9 × VS
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be Suppressed by
the Input Filter, tSPIKE
SDA (WHEN OUTPUTTING DATA)
Output Logic 0 Voltage at 3 mA Sink Current
Output Fall Time from VIHMIN to VILMAX with a Bus
Capacitance from 10 pF to 400 pF
TIMING
Min
Typ
Unit
0.3 × VS
+10
V
V
µA
50
V
ns
0.4
250
V
ns
0.7 × VS
−10
0.015 × VS
20 + 0.1 Cb
Test Conditions/Comments
Cb = capacitance of one bus line in pF
Note that all I2C timing values refer
to VIHMIN (0.3 × VS) and VILMAX levels
(0.7 × VS)
Clock Rate (SCL, fI2C)
Bus Free Time Between a Stop and Start Condition, tIDLE
Setup Time for a Repeated Start Condition, tSET; STR
Hold Time (Repeated) Start Condition (After This Period,
the First Clock Pulse Is Generated), tHLD; STR
Setup Time for Stop Condition, tSET; STP
Low Period of the SCL Clock, tLOW
High Period of the SCL Clock, tHIGH
SCL, SDA Rise Time, tRISE
SCL, SDA Fall Time, tFALL
Data Setup Time, tSET; DAT
1.3
0.6
0.6
400
kHz
µs
µs
µs
0.6
1.3
0.6
20 + 0.1 Cb
20 + 0.1 Cb
120
µs
µs
µs
ns
ns
ns
Data Hold Time, tHLD; DAT
140
Capacitive Load for Each Bus Line, Cb
1
Max
300
300
880
ns
400
pF
Cb = capacitance of one bus line in pF
Cb = capacitance of one bus line in pF
This is a minor deviation from the
original I²C specification of 100 ns
minimum
This is a minor deviation from the
original I²C specification of 0 ns
minimum 1
According to the original I2C specification, an I2C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
falling edge.
Rev. A | Page 14 of 84
Data Sheet
AD9522-4
PD, SYNC, AND RESET PINS
Table 15.
Parameter
INPUT CHARACTERISTICS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Min
Typ
Max
Unit
0.8
1
−110
V
V
µA
µA
2
pF
2.0
Capacitance
RESET TIMING
Pulse Width Low
RESET Inactive to Start of Register Programming
50
100
ns
ns
SYNC TIMING
Pulse Width Low
1.3
ns
Test Conditions/Comments
Each of these pins has an 30 kΩ internal pull-up resistor
The minus sign indicates that current is flowing out of
the AD9522, which is due to the internal pull-up resistor
High speed clock is CLK input signal
SERIAL PORT SETUP PINS: SP1, SP0
Table 16.
Parameter
SP1, SP0
Logic Level 0
Logic Level ½
Logic Level 1
Min
0.4 × VS
Typ
Max
Unit
0.25 × VS
0.65 × VS
V
V
0.8 × VS
Test Conditions/Comments
These pins do not have internal pull-up/pull-down resistors
VS is the voltage on the VS pin
User can float these pins to obtain Logic Level ½; if floating this pin, connect a
capacitor to ground
V
LD, STATUS, AND REFMON PINS
Table 17.
Parameter
OUTPUT CHARACTERISTICS
Min
Output Voltage High, VOH
Output Voltage Low, VOL
MAXIMUM TOGGLE RATE
2.7
Max
Unit
0.4
100
V
V
MHz
3
pF
On-chip capacitance; used to calculate RC time constant
for analog lock detect read back; use a pull-up resistor
1.02
MHz
8
kHz
Frequency above which the monitor indicates the
presence of the reference
Frequency above which the monitor indicates the
presence of the reference
ANALOG LOCK DETECT
Capacitance
REF1, REF2, AND VCO FREQUENCY STATUS MONITOR
Normal Range
Extended Range
LD PIN COMPARATOR
Trip Point
Hysteresis
Typ
1.6
260
V
mV
Rev. A | Page 15 of 84
Test Conditions/Comments
When selected as a digital output (CMOS); there are other
modes in which these pins are not CMOS digital outputs; see
Table 53, Register 0x017, Register 0x01A, and Register 0x01B
At 1 mA current; maximum recommended current: 5 mA
At 1 mA current
Applies when mux is set to any divider or counter output,
or PFD up/down pulse; also applies in analog lock detect
mode; usually debug mode only; note that spurs can
couple to output when any of these pins are toggling
AD9522-4
Data Sheet
POWER DISSIPATION
Table 18.
Parameter
POWER DISSIPATION, CHIP
Typ
Max
Unit
Power-On Default
PLL Locked; One LVDS Output Enabled
0.88
0.54
1.0
0.63
W
W
PLL Locked; One CMOS Output Enabled
0.55
0.66
W
Distribution Only Mode; VCO Divider On;
One LVDS Output Enabled
Distribution Only Mode; VCO Divider Off;
One LVDS Output Enabled
Maximum Power, Full Operation
0.36
0.43
W
0.33
0.4
W
1.1
1.3
W
PD Power-Down
35
50
mW
PD Power-Down, Maximum Sleep
27
43
mW
2.3
8
mW
33
25
43
31
mW
mW
REF1, REF2 (Single-Ended) On/Off
16
22
mW
VCO On/Off
PLL Dividers and Phase Detector On/Off
LVDS Channel
LVDS Driver
CMOS Channel
60
54
118
11
120
95
67
146
15
154
mW
mW
mW
mW
mW
CMOS Driver On/Off
Channel Divider Enabled
16
33
30
40
mW
mW
Zero Delay Block On/Off
30
35
mW
VCP Supply
POWER DELTAS, INDIVIDUAL FUNCTIONS
VCO Divider On/Off
REFIN (Differential) Off
Min
Test Conditions/Comments
Does not include power dissipated in external resistors; all LVDS
outputs terminated with 100 Ω across differential pair; all CMOS
outputs have 10 pF capacitive loading
No clock; no programming; default register values
fREF = 25 MHz; fOUT = 250 MHz; VCO = 1500 MHz; VCO divider = 2;
one LVDS output and output divider enabled; zero delay off;
ICP = 4.8 mA
fREF = 25 MHz; fOUT = 62.5 MHz; VCO = 1500 MHz; VCO divider = 2;
one CMOS output and output divider enabled; zero delay off;
ICP = 4.8 mA
fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider = 2; one LVDS output
and output divider enabled; zero delay off
fCLK = 2.4 GHz; fOUT = 200 MHz; VCO divider bypassed; one LVDS
output and output divider enabled; zero delay off
PLL on; internal VCO = 1500 MHz; VCO divider = 2; all channel
dividers on; 12 LVDS outputs at 125 MHz; zero delay on
PD pin pulled low; does not include power dissipated in
termination resistors
PD pin pulled low; PLL power-down, Register 0x010[1:0] = 01b;
power-down SYNC, Register 0x230[2] = 1b; power-down
distribution reference, Register 0x230[1] = 1b
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider not used
Delta between reference input off and differential reference
input mode
Delta between reference inputs off and one single-ended
reference enabled; double this number if both REF1 and REF2
are powered up
Internal VCO disabled; CLK input selected
PLL off to PLL on, normal operation; no reference enabled
No LVDS output on to one LVDS output on; channel divider set to 1
Second LVDS output turned on, same channel
No CMOS output on to one CMOS output on; channel divider
set to 1; fOUT = 62.5 MHz and 10 pF of capacitive loading
Additional CMOS outputs within the same channel turned on
Delta between divider bypassed (divide-by-1) and divide-by-2 to
divide-by-32
Rev. A | Page 16 of 84
Data Sheet
AD9522-4
ABSOLUTE MAXIMUM RATINGS
Table 19.
Parameter or Pin
VS
VCP, CP
REFIN, REFIN
RSET, LF, BYPASS
CPRSET
CLK, CLK
CLK
SCLK/SCL, SDIO/SDA, SDO, CS
OUT0, OUT0, OUT1, OUT1,
OUT2, OUT2, OUT3, OUT3,
OUT4, OUT4, OUT5, OUT5,
OUT6, OUT6, OUT7, OUT7,
OUT8, OUT8, OUT9, OUT9,
OUT10, OUT10, OUT11, OUT11
SYNC, RESET, PD
REFMON, STATUS, LD
SP0, SP1, EEPROM
Junction Temperature 1
Storage Temperature Range
Lead Temperature (10 sec)
1
With
Respect to
GND
GND
GND
GND
GND
GND
CLK
GND
GND
Rating
−0.3 V to +3.6 V
−0.3 V to +5.8 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−1.2 V to +1.2 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal impedance measurements were taken on a JEDEC
JESD51-5 2S2P test board in still air in accordance with JEDEC
JESD51-2. See the Thermal Performance section for more details.
Table 20.
Package Type
64-Lead LFCSP (CP-64-4)
GND
GND
GND
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
−0.3 V to VS + 0.3 V
125°C
−65°C to +150°C
300°C
ESD CAUTION
See the Specifications section for operating temperature range (TA).
Rev. A | Page 17 of 84
θJA
22
Unit
°C/W
AD9522-4
Data Sheet
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
REFIN (REF1)
REFIN (REF2)
CPRSET
VS
VS
GND
RSET
VS
OUT0 (OUT0A)
OUT0 (OUT0B)
VS
OUT1 (OUT1A)
OUT1 (OUT1B)
OUT2 (OUT2A)
OUT2 (OUT2B)
VS
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
AD9522
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT3 (OUT3A)
OUT3 (OUT3B)
VS
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
VS
VS
OUT8 (OUT8B)
OUT8 (OUT8A)
OUT7 (OUT7B)
OUT7 (OUT7A)
VS
OUT6 (OUT6B)
OUT6 (OUT6A)
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.
07225-003
SDIO/SDA
SDO
GND
SP1
SP0
EEPROM
RESET
PD
OUT9 (OUT9A)
OUT9 (OUT9B)
VS
OUT10 (OUT10A)
OUT10 (OUT10B)
OUT11 (OUT11A)
OUT11 (OUT11B)
VS
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VS
REFMON
LD
VCP
CP
STATUS
REF_SEL
SYNC
LF
BYPASS
VS
VS
CLK
CLK
CS
SCLK/SCL
Figure 5. Pin Configuration
Table 21. Pin Function Descriptions
Input/
Output
I
Pin
Type
Power
Mnemonic
VS
Description
3.3 V Power Pins.
O
O
I
3.3 V CMOS
3.3 V CMOS
Power
REFMON
LD
VCP
5
O
Loop filter
CP
6
7
O
I
3.3 V CMOS
3.3 V CMOS
STATUS
REF_SEL
8
I
3.3 V CMOS
SYNC
9
10
I
O
Loop filter
Loop filter
LF
BYPASS
13
I
CLK
14
I
Differential
clock input
Differential
clock input
Reference Monitor (Output). This pin has multiple selectable outputs.
Lock Detect (Output). This pin has multiple selectable outputs.
Power Supply for Charge Pump (CP); VS ≤ VCP ≤ 5.25 V. VCP must still be
connected to 3.3 V if the PLL is not used.
Charge Pump (Output). This pin connects to an external loop filter. This pin can
be left unconnected if the PLL is not used.
Programmable Status Output.
Reference Select. It selects REF1 (low) or REF2 (high). This pin has an internal
30 kΩ pull-down resistor.
Manual Synchronizations and Manual Holdover. This pin initiates a manual
synchronization and is used for manual holdover. Active low. This pin has an
internal 30 kΩ pull-up resistor.
Loop Filter (Input). It connects internally to the VCO control voltage node.
This pin is for bypassing the LDO to ground with a 220 nF capacitor.
This pin can be left unconnected if the PLL is not used.
Along with CLK, this pin is the differential input for the clock distribution section.
Pin No.
1, 11, 12, 27,
32, 35, 40,
41, 46, 49,
54, 57, 60, 61
2
3
4
CLK
Along with CLK, this pin is the differential input for the clock distribution section.
If a single-ended input is connected to the CLK pin, connect a 0.1 µF bypass
capacitor from this pin to ground.
Rev. A | Page 18 of 84
Data Sheet
AD9522-4
Pin No.
15
Input/
Output
I
Pin
Type
3.3 V CMOS
Mnemonic
CS
16
I
3.3 V CMOS
SCLK/SCL
17
18
19, 59
20
I/O
O
I
I
SDIO/SDA
SDO
GND
SP1
21
I
22
I
3.3 V CMOS
3.3 V CMOS
GND
Three-level
logic
Three-level
logic
3.3 V CMOS
23
24
25
I
I
O
RESET
PD
OUT9 (OUT9A)
26
O
28
O
29
O
30
O
31
O
33
O
34
O
36
O
37
O
38
O
39
O
42
O
43
O
44
O
45
O
3.3 V CMOS
3.3 V CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
SP0
EEPROM
OUT9 (OUT9B)
OUT10 (OUT10A)
OUT10 (OUT10B)
OUT11 (OUT11A)
OUT11 (OUT11B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
OUT8 (OUT8A)
OUT8 (OUT8B)
OUT5 (OUT5B)
OUT5 (OUT5A)
OUT4 (OUT4B)
OUT4 (OUT4A)
Description
Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ
pull-up resistor.
Serial Control Port Clock Signal. This pin has an internal 30 kΩ pull-down resistor
in SPI mode but is high impedance in I²C mode.
Serial Control Port Bidirectional Serial Data In/Out.
Serial Control Port Unidirectional Serial Data Out.
Ground Pins.
Select SPI or I²C as the serial interface port and select the I²C slave address in I²C
mode. Three-level logic. This pin is internally biased for the open logic level.
Select SPI or I²C as the serial interface port and select the I²C slave address in I²C
mode. Three-level logic. This pin is internally biased for the open logic level.
Setting this pin high selects the register values stored in the internal EEPROM to
be loaded at reset and/or power-up. Setting this pin low causes the AD9522 to
load the hard-coded default register values at power-up/reset. This pin has an
internal 30 kΩ pull-down resistor. Note that to guarantee the proper loading of
EEPROM during startup, a high-low-high pulse on the RESET pin occurs after the
power supply stabilizes.
Chip Reset, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Chip Power-Down, Active Low. This pin has an internal 30 kΩ pull-up resistor.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Rev. A | Page 19 of 84
AD9522-4
Pin No.
47
Input/
Output
O
48
O
50
O
51
O
52
O
53
O
55
O
56
O
58
O
62
O
63
I
64
I
EPAD
Data Sheet
Pin
Type
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
LVDS or
CMOS
Current set
resistor
Current set
resistor
Reference
input
Reference
input
GND
Mnemonic
OUT3 (OUT3B)
OUT3 (OUT3A)
OUT2 (OUT2B)
OUT2 (OUT2A)
OUT1 (OUT1B)
OUT1 (OUT1A)
OUT0 (OUT0B)
OUT0 (OUT0A)
RSET
CPRSET
REFIN (REF2)
REFIN (REF1)
GND
Description
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Output. This pin can be configured as one side of a differential LVDS output
or as a single-ended CMOS output.
Clock Distribution Current Set Resistor. Connect a 4.12 kΩ resistor from this pin
to GND.
Charge Pump Current Set Resistor. Connect a 5.1 kΩ resistor from this pin to GND.
This resistor can be omitted if the PLL is not used.
Along with REFIN, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF2.
Along with REFIN, this is the differential input for the PLL reference. Alternatively,
this pin is a single-ended input for REF1.
The exposed die pad must be connected to GND.
Rev. A | Page 20 of 84
Data Sheet
AD9522-4
TYPICAL PERFORMANCE CHARACTERISTICS
275
5
3 CHANNELS—6 LVDS
CURRENT FROM CP PIN (mA)
250
3 CHANNELS—3 LVDS
200
175
2 CHANNELS—2 LVDS
150
125
PUMP DOWN
2
1
1000
800
0
0
2.0
1.5
3.0
2.5
3.5
5.0
Figure 9. Charge Pump Characteristics at VCP = 3.3 V
5
240
CURRENT FROM CP PIN (mA)
2 CHANNELS—8 CMOS
220
200
180
2 CHANNELS—2 CMOS
160
140
1 CHANNEL—2 CMOS
120
100
4
PUMP DOWN
PUMP UP
3
2
1
1 CHANNEL—1 CMOS
0
50
100
150
200
FREQUENCY (MHz)
250
0
07225-109
CURRENT (mA)
1.0
VOLTAGE ON CP PIN (V)
Figure 6. Total Current vs. Frequency, CLK-to-Output (PLL Off), Channel and
VCO Divider Bypassed, LVDS Outputs Terminated 100 Ω Across Differential Pair
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
Figure 10. Charge Pump Characteristics at VCP = 5.0 V
–140
PFD PHASE NOISE REFERRED TO PFD INPUT
(dBc/Hz)
50
45
40
35
30
1.55
1.65
VCO FREQUENCY (GHz)
Figure 8. KVCO vs. VCO Frequency
1.75
–145
–150
–155
–160
–165
–170
0.1
07225-010
25
20
1.45
0
VOLTAGE ON CP PIN (V)
Figure 7. Total Current vs. Frequency, CLK-to-Output (PLL Off), Channel and
VCO Divider Bypassed, CMOS Outputs with 10 pF Load
KVCO (MHz/V)
0.5
07225-111
600
07225-112
400
200
07225-108
0
FREQUENCY (MHz)
80
PUMP UP
3
1 CHANNEL—1 LVDS
100
75
4
1
10
100
PFD FREQUENCY (MHz)
Figure 11. PFD Phase Noise Referred to PFD Input vs. PFD Frequency
Rev. A | Page 21 of 84
07225-013
CURRENT (mA)
225
AD9522-4
Data Sheet
–208
3.5
VS_DRV = 3.3V
3.0
–212
VS_DRV = 2.5V
2.5
–216
–218
DIFFERENTIAL INPUT
2.0
1.5
0.2
0.6
0.4
1.0
0.8
1.4
1.2
INPUT SLEW RATE (V/ns)
0
10k
Figure 12. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/REFIN
Figure 15. CMOS Output VOH (Static) vs. RLOAD (to Ground)
0
0.4
–10
0.3
DIFFERENTIAL OUTPUT (V)
–20
–30
–40
–50
–60
–70
–80
–90
0.2
0.1
0
–0.1
–0.2
110
115
120
125
130
135
140
145
FREQUENCY (MHz)
–0.4
07225-116
105
0
3
4
5
6
7
8
9
10 11 12 13 14 15
Figure 16. LVDS Output (Differential) at 100 MHz
Output Terminated 100 Ω Across Differential Pair
0
0.4
–10
0.3
DIFFERENTIAL SWING (V p-p)
–20
–30
–40
–50
–60
–70
–80
0.2
0.1
0
–0.1
–0.2
–0.3
–90
122.58
122.78
122.98
123.18
123.38
FREQUENCY (MHz)
07225-117
POWER (dBm)
2
TIME (ns)
Figure 13. PFD/CP Spurs; 122.88 MHz; PFD = 15.36 MHz;
LBW = 127 kHz; ICP = 3.0 mA; fVCO = 1475 MHz
–100
122.38
1
07225-014
–0.3
–100
–110
100
100
1k
RESISTIVE LOAD (Ω)
–0.4
0
0.5
1.0
1.5
2.0
2.5
TIME (ns)
Figure 17. LVDS Differential Voltage Swing at 800 MHz
Output Terminated 100 Ω Across Differential Pair
Figure 14. Output Spectrum, LVDS; 122.88 MHz; PFD = 15.36 MHz;
LBW = 127 kHz; ICP = 3.0 mA; fVCO = 1475 MHz
Rev. A | Page 22 of 84
3.0
07225-015
0
07225-118
0.5
SINGLE-ENDED INPUT
07225-114
–224
VS_DRV = 2.35V
1.0
–220
–222
POWER (dBm)
VS_DRV = 3.135V
–214
VOH (V)
PLL FIGURE OF MERIT (dBc/Hz)
–210
Data Sheet
AD9522-4
4.0
3.2
3.5
2.8
3.0
1.6
1.2
2.5
2.0
0.8
1.0
0.4
0.5
0
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
10pF
1.5
20pF
0
0
100
200
300
400
500
600
700
FREQUENCY (MHz)
07225-124
AMPLITUDE (V)
2pF
2.0
07225-018
AMPLITUDE (V)
2.4
Figure 21. CMOS Output Swing vs. Frequency and Capacitive Load
Figure 18. CMOS Output with 10 pF Load at 25 MHz
–50
2pF LOAD
3.2
–60
2.8
–70
AMPLITUDE (V)
2.4
PHASE NOISE (dBc/Hz)
10pF
LOAD
2.0
1.6
1.2
0.8
–80
–90
–100
–110
–120
–130
–140
0.4
1
2
3
4
5
6
7
8
9
10
TIME (ns)
–160
1k
07225-019
0
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 22. Internal VCO Phase Noise (Absolute), LVDS Output at 467 MHz
Figure 19. CMOS Output with 2 pF and 10 pF Load at 250 MHz
–50
1600
–60
1400
7mA SETTING
–70
PHASE NOISE (dBc/Hz)
1200
1000
800
DEFAULT 3.5mA SETTING
600
400
–80
–90
–100
–110
–120
–130
–140
200
0
200
400
600
800
FREQUENCY (GHz)
Figure 20. LVDS Differential Voltage Swing vs. Frequency
Output Terminated 100 Ω Across Differential Pair
1000
–160
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
07225-024
–150
0
07225-123
DIFFERENTIAL SWING (mV p-p)
10k
07225-023
–150
0
Figure 23. Internal VCO Phase Noise (Absolute), LVDS Output at 533 MHz
Rev. A | Page 23 of 84
AD9522-4
Data Sheet
–50
–100
–60
–110
–80
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–70
–90
–100
–110
–120
–130
–120
–130
–140
–140
1M
10M
100M
FREQUENCY (Hz)
–150
10
–110
–120
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–110
–140
–150
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
10M
100M
100M
100M
–140
–150
–170
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 28. Additive (Residual) Phase Noise,
CLK-to-CMOS at 50 MHz, Divide-by-20
–100
–110
–110
PHASE NOISE (dBc/Hz)
–100
–120
–130
–140
–120
–130
–140
–150
–150
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
100M
07225-129
PHASE NOISE (dBc/Hz)
1M
–130
Figure 25. Additive (Residual) Phase Noise,
CLK-to-LVDS at 245.76 MHz, Divide-by-1
–160
10
100k
–160
07225-128
–160
10
10k
Figure 27. Additive (Residual) Phase Noise,
CLK-to-LVDS at 800 MHz, Divide-by-1
–100
–130
1k
FREQUENCY (Hz)
Figure 24. Internal VCO Phase Noise (Absolute), LVDS Output at 600 MHz
–120
100
07225-130
100k
07225-131
10k
07225-025
–160
1k
07225-132
–150
–160
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 29. Additive (Residual) Phase Noise,
CLK-to-CMOS at 250 MHz, Divide-by-4
Figure 26. Additive (Residual) Phase Noise,
CLK-to-LVDS at 200 MHz, Divide-by-5
Rev. A | Page 24 of 84
Data Sheet
AD9522-4
–100
–80
PHASE NOISE (dBc/Hz)
–120
–130
–140
–150
100k
1M
10M
100M
PHASE NOISE (dBc/Hz)
–130
–140
–110
–120
–130
–140
100k
1M
10M
100M
07225-034
–150
FREQUENCY (Hz)
100k
1M
10M
100M
Figure 32. Phase Noise (Absolute), External VCXO (Toyocom TCO-2112)
at 245.76 MHz; PFD = 15.36 MHz; LBW = 250 Hz; LVDS Output = 245.76 MHz
INTEGRATED RMS JITTER (12kHz TO 20MHz): 372fs
INTEGRATED RMS JITTER (20kHz TO 80MHz): 318fs (EXTRAPOLATED)
10k
10k
FREQUENCY (Hz)
–100
–160
1k
–120
–160
1k
07225-033
10k
Figure 30. Phase Noise (Absolute) Clock Generation; Internal VCO at
1475 MHz; PFD = 15.36 MHz; LBW = 40 kHz; LVDS Output = 122.88 MHz
–90
–110
–150
FREQUENCY (Hz)
–80
–100
07225-135
PHASE NOISE (dBc/Hz)
–110
–160
1k
INTEGRATED RMS JITTER (12kHz TO 20MHz): 146fs
–90
Figure 31. Phase Noise (Absolute) Clock Cleanup; Internal VCO at 1400 MHz;
PFD = 120 kHz; LBW = 1.84 kHz; LVDS Output = 155.52 MHz
Rev. A | Page 25 of 84
AD9522-4
Data Sheet
TEST CIRCUITS
C1
62pF
C2
240nF
R1
820Ω
LF
R2
3kΩ
CP
C3
33pF
C1
1.5nF
C2
4.7µF
R1
2.1kΩ
C3
2.2nF
BYPASS
C12
220nF
BYPASS
BYPASS
CAPACITOR
FOR LDO
07225-234
BYPASS
CAPACITOR
FOR LDO
LF
Figure 33. PLL Loop Filter Used for Clock Generation Plot (See Figure 30)
C12
220nF
07225-235
R2
390Ω
CP
Figure 34. PLL Loop Filter Used for Clock Cleanup Plot (See Figure 31)
Rev. A | Page 26 of 84
Data Sheet
AD9522-4
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount
of variation from ideal phase progression over time. This
phenomenon is called phase jitter. Although many causes can
contribute to phase jitter, one major cause is random noise,
which is characterized statistically as Gaussian (normal) in
distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in decibels) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on the performance of ADCs,
DACs, and RF mixers. It lowers the achievable dynamic range of
the converters and mixers, although they are affected in somewhat
different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When observing
a sine wave, the time of successive zero crossings varies. In a square
wave, the time jitter is a displacement of the edges from their
ideal (regular) times of occurrence. In both cases, the variations in
timing from the ideal are the time jitter. Because these variations
are random in nature, the time jitter is specified in seconds root
mean square (rms) or 1 sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the signal-to-noise ratio (SNR) and dynamic
range of the converter. A sampling clock with the lowest possible
jitter provides the highest performance from a given converter.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is
attributable to the device or subsystem being measured.
The phase noise of any external oscillators or clock sources is
subtracted. This makes it possible to predict the degree to which
the device impacts the total system phase noise when used in
conjunction with the various oscillators and clock sources, each
of which contributes its own phase noise to the total. In many
cases, the phase noise of one element dominates the system
phase noise. When there are multiple contributors to phase
noise, the total is the square root of the sum of squares of the
individual contributors.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attributable to
the device or subsystem being measured. The time jitter of any
external oscillators or clock sources is subtracted. This makes it
possible to predict the degree to which the device impacts the
total system time jitter when used in conjunction with the various
oscillators and clock sources, each of which contributes its own
time jitter to the total. In many cases, the time jitter of the external
oscillators and clock sources dominates the system time jitter.
Rev. A | Page 27 of 84
AD9522-4
Data Sheet
DETAILED BLOCK DIAGRAM
VS
GND
RSET
DISTRIBUTION
REFERENCE
STATUS
REF2
STATUS
R
DIVIDER
CLOCK
DOUBLER
REF1
BUF
LD
LOCK
DETECT
PLL
REFERENCE
REFERENCE
SWITCHOVER
OPTIONAL
REFIN
CPRSET VCP
REFMON
PROGRAMMABLE
R DELAY
REF_SEL
HOLD
REFIN
AMP
BYPASS
LOW DROPOUT
REGULATOR (LDO)
STATUS
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
N DIVIDER
LF
ZERO DELAY BLOCK
STATUS
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLK
OUT0
CLK
1
PD
SYNC
DIGITAL
LOGIC
EEPROM
OUT0
0
DIVIDE BY
1 TO 32
RESET
OUT1
OUT1
OUT2
OUT2
EEPROM
OUT3
DIVIDE BY
1 TO 32
SPI
INTERFACE
I2C
INTERFACE
OUT4
OUT4
OUT5
SCLK/SCL
SDIO/SDA
SDO
CS
OUT5
OUT6
OUT6
DIVIDE BY
1 TO 32
LVDS/LVCMOS OUTPUT
SP0
OUT3
SERIAL
PORT
DECODE
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
DIVIDE BY
1 TO 32
AD9522
OUT10
OUT10
OUT11
OUT11
Figure 35.
Rev. A | Page 28 of 84
07225-028
SP1
Data Sheet
AD9522-4
THEORY OF OPERATION
OPERATIONAL CONFIGURATIONS
Table 22. Settings When Using Internal VCO
The AD9522 can be configured in several ways. These
configurations must be set up by loading the control registers
(see Table 49 to Table 60). Each section or function must be
individually programmed by setting the appropriate bits in the
corresponding control register or registers. After the desired
configuration is programmed, the user can store these values in
the on-board EEPROM to allow the part to power up in the
desired configuration without user intervention.
Register
0x010[1:0] = 00b
0x010 to 0x01E
Mode 0: Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure in most cases that the input frequency to the
channel dividers does not exceed its specified maximum
frequency (see Table 3). The exceptions to this are VCO direct
mode and cases where the VCO frequency is ≤2000 MHz. The
channel divider maximum input frequency is 2000 MHz
provided that the user does not choose a divide-by-17 or a
divide-by-3. If divide-by-3 or divide-by-17 is desired, the
maximum channel divider input frequency is 1600 MHz.
0x1E1[1] = 1b
0x01C[2:0]
0x1E0[2:0]
0x1E1[0] = 0b
0x018[0] = 0b
0x232[0] = 1b
0x018[0] = 1b
0x232[0] = 1b
The internal PLL uses an external loop filter to set the loop
bandwidth. The external loop filter is also crucial to the loop
stability. The internal PLL uses an external loop filter to set the
loop bandwidth. The external loop filter is also crucial to the
loop stability.
When using the internal VCO, it is necessary to calibrate the
VCO (Register 0x018[0] = 1b) to ensure optimal performance.
For internal VCO and clock distribution applications, use the
register settings shown in Table 22.
Rev. A | Page 29 of 84
Description
PLL normal operation (PLL on)
PLL settings; select and enable a reference
input; set R, N (P, A, B), PFD polarity, and ICP
according to the intended loop configuration
VCO selected as the source
Enable reference inputs
Set VCO divider
Use the VCO divider as the source for
the distribution section
Reset VCO calibration and issue IO_UPDATE
(not necessary for the first time after power-up,
but must be done subsequently)
Initiate VCO calibration, issue IO_UPDATE
AD9522-4
Data Sheet
VS
GND
RSET
REFMON
DISTRIBUTION
REFERENCE
STATUS
REF2
STATUS
R
DIVIDER
CLOCK
DOUBLER
REF1
BUF
LD
LOCK
DETECT
PLL
REFERENCE
REFERENCE
SWITCHOVER
OPTIONAL
REFIN
CPRSET VCP
PROGRAMMABLE
R DELAY
REF_SEL
HOLD
REFIN
AMP
BYPASS
LOW DROPOUT
REGULATOR (LDO)
STATUS
P, P + 1
PRESCALER
A/B
COUNTERS
PROGRAMMABLE
N DELAY
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CP
N DIVIDER
LF
ZERO DELAY BLOCK
STATUS
DIVIDE BY 1,
2, 3, 4, 5, OR 6
CLK
OUT0
CLK
1
PD
SYNC
DIGITAL
LOGIC
EEPROM
OUT0
0
DIVIDE BY
1 TO 32
RESET
OUT1
OUT1
OUT2
OUT2
EEPROM
OUT3
SP0
OUT3
SERIAL
PORT
DECODE
DIVIDE BY
1 TO 32
SPI
INTERFACE
I2C
INTERFACE
OUT4
OUT4
OUT5
SCLK/SCL
SDIO/SDA
SDO
CS
OUT5
OUT6
OUT6
DIVIDE BY
1 TO 32
LVDS/CMOS OUTPUT
SP1
OUT7
OUT7
OUT8
OUT8
OUT9
OUT9
DIVIDE BY
1 TO 32
AD9522
OUT10
OUT10
OUT11
07225-030
OUT11
Figure 36. Internal VCO and Clock Distribution (Mode 0)
Rev. A | Page 30 of 84
Data Sheet
AD9522-4
Mode 1: Clock Distribution or External VCO
