10-Bit, 105 MSPS/125 MSPS/150 MSPS,
1.8 V Dual Analog-to-Digital Converter
AD9600
FEATURES
I/Q demodulation systems
Smart antenna systems
Digital predistortion
General-purpose software radios
Broadband data applications
Data acquisition
Nondestructive testing
SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS
SFDR = 81 dBc to 70 MHz at 150 MSPS
Low power: 825 mW at 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply
Integer 1 to 8 input clock divider
Intermediate frequency (IF) sampling frequencies up to 450 MHz
Internal analog-to-digital converter (ADC) voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input: 1 V p-p to 2 V p-p range
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
APPLICATIONS
7.
Point-to-point radio receivers (GPSK, QAM)
Diversity radio systems
Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.
Fast overrange detect and signal monitor with serial output.
Signal monitor block with dedicated serial output mode.
Proprietary differential input maintains excellent SNR
performance for input frequencies up to 450 MHz.
The AD9600 operates from a single 1.8 V supply and
features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or gray coding), enabling the
clock DCS, power-down mode, and voltage reference mode.
The AD9600 is pin compatible with the AD9627-11, AD9627,
and AD9640, allowing a simple migration from 10 bits to
11 bits, 12 bits, or 14 bits.
FUNCTIONAL BLOCK DIAGRAM
FD[0:3]A
SDIO/ SCLK/
DCS DFS CSB
FD BITS/THRESHOLD
DETECT
SPI
AD9600
PROGRAMMING DATA
VIN + A
SHA
ADC
VIN – A
– +
SENSE
CML
DUTY CYCLE
STABLIZER
DCO
GENERATION
VIN – B
SHA
ADC
SERIAL MONITOR
DATA
VIN + B
MULTICHIP
SYNC
AGND SYNC
SERIAL MONITOR
INTERFACE
FD BITS/THRESHOLD
DETECT
FD[0:3]B
D0A
CLK–
SIGNAL
MONITOR
REFERENCE
SELECT
D9A
CLK+
DIVIDE 1
TO 8
SMI
SMI
SMI
SDFS SCLK/ SDO/
PDWN OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
CMOS/LVDS
OUTPUT BUFFER
VREF
DRVDD
DCOA
DCOB
D9B
D0B
DRGND
06909-001
DVDD
CMOS/LVDS
OUTPUT BUFFER
AVDD
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved.
AD9600
TABLE OF CONTENTS
Features .............................................................................................. 1
Peak Detector Mode................................................................... 33
Applications ....................................................................................... 1
RMS/MS Magnitude Mode ....................................................... 33
Product Highlights ........................................................................... 1
Threshold Crossing Mode ......................................................... 34
Functional Block Diagram .............................................................. 1
Additional Control Bits ............................................................. 34
Revision History ............................................................................... 3
DC Correction ............................................................................ 35
General Description ......................................................................... 4
Signal Monitor SPORT Output ................................................ 35
Specifications..................................................................................... 5
Built-In Self-Test (BIST) and Output Test .................................. 36
DC Specifications ......................................................................... 5
Built-In Self-Test (BIST) ............................................................ 36
AC Specifications.......................................................................... 6
Output Test Modes ..................................................................... 36
Digital Specifications ................................................................... 7
Channel/Chip Synchronization .................................................... 37
Switching Specifications .............................................................. 9
Serial Port Interface (SPI) .............................................................. 38
Timing Characteristics .............................................................. 10
Configuration Using the SPI ..................................................... 38
Timing Diagrams........................................................................ 10
Hardware Interface..................................................................... 38
Absolute Maximum Ratings.......................................................... 12
Configuration Without the SPI ................................................ 39
Thermal Characteristics ............................................................ 12
SPI Accessible Features .............................................................. 39
ESD Caution ................................................................................ 12
Memory Map .................................................................................. 40
Pin Configuration and Function Descriptions ........................... 13
Reading the Memory Map Table .............................................. 40
Equivalent Circuits ......................................................................... 17
Memory Map .............................................................................. 41
Typical Performance Characteristics ........................................... 18
Memory Map Register Description ......................................... 44
Theory of Operation ...................................................................... 23
Applications Information .............................................................. 47
ADC Architecture ...................................................................... 23
Design Guidelines ...................................................................... 47
Analog Input Considerations.................................................... 23
Evaluation Board ............................................................................ 48
Voltage Reference ....................................................................... 25
Power Supplies ............................................................................ 48
Clock Input Considerations ...................................................... 26
Input Signals................................................................................ 48
Power Dissipation and Standby Mode ..................................... 28
Output Signals ............................................................................ 48
Digital Outputs ........................................................................... 28
Default Operation and Jumper Selection Settings ................. 49
Timing .......................................................................................... 29
Alternative Clock Configurations ............................................ 49
ADC Overrange and Gain Control .............................................. 30
Alternative Analog Input Drive Configuration...................... 50
Fast Detect Overview ................................................................. 30
Schematics ................................................................................... 51
ADC Fast Magnitude ................................................................. 30
Evaluation Board Layouts ......................................................... 61
ADC Overrange (OR) ................................................................ 31
Bill of Materials ........................................................................... 69
Gain Switching ............................................................................ 31
Outline Dimensions ....................................................................... 71
Signal Monitor ................................................................................ 33
Ordering Guide .......................................................................... 72
Rev. B | Page 2 of 72
AD9600
REVISION HISTORY
Added new models to Specifications Section ................................ 5
Changes to Table 7 ..........................................................................12
Updated Outline Dimensions ........................................................71
Changes to Ordering Guide ...........................................................72
Changes to Configuration Using the SPI Section ....................... 37
Changes to Table 22 ........................................................................ 40
Changes to Signal Monitor Period (Register 0x113 to
Register 0x115) Section .................................................................. 45
Added Exposed Pad Notation to Outline Dimensions .............. 70
6/09—Rev. 0 to Rev. A
11/07—Revision 0: Initial Version
12/09—Rev. A to Rev. B
Changes to Specifications Section................................................... 4
Changes to Figure 3.........................................................................10
Changes to Figure 11, Figure 12, and Figure 14 ..........................16
Changes to Table 12 ........................................................................28
Rev. B | Page 3 of 72
AD9600
GENERAL DESCRIPTION
The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS
ADC. It is designed to support communications applications
where low cost, small size, and versatility are desired.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold
analog input amplifiers supporting a variety of user-selectable
input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the
converters to maintain excellent performance.
The AD9600 has several functions that simplify the automated
gain control (AGC) function in a communications receiver. For
example, the fast detect feature allows fast overrange detection
by outputting four bits of input level information with very
short latency.
In addition, the programmable threshold detector allows monitoring the amplitude of the incoming signal with short latency,
using the four fast detect bits of the ADC. If the input signal level
exceeds the programmable threshold, the fine upper threshold
indicator goes high. Because this threshold is set from the four
MSBs, the user can quickly adjust the system gain to avoid an
overrange condition.
Another AGC-related function of the AD9600 is the signal
monitor. This block allows the user to monitor the composite
magnitude of the incoming signal, which aids in setting the gain
to optimize the dynamic range of the overall system.
The ADC output data can be routed directly to the two external
10-bit output ports. These outputs can be set from 1.8 V to 3.3 V
CMOS or 1.8 V LVDS. In addition, flexible power-down options
allow significant power savings.
Rev. B | Page 4 of 72
AD9600
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTICS
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance 2
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS Mode)
Supply Current
IAVDD1
IDVDD1
IAVDD and IDVDD1, 3
IDRVDD (3.3 V CMOS)
IDRVDD (1.8 V CMOS)
IDRVDD (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input1
DRVDD = 1.8 V
DRVDD = 3.3 V
Standby Power 3
Power-Down Power
Temp
Full
AD9600ABCPZ-105/
AD9600BCPZ-105
Min
Typ
Max
10
AD9600ABCPZ-125/
AD9600BCPZ-125
Min
Typ
Max
10
AD9600ABCPZ-150/
AD9600BCPZ-150
Min
Typ
Max
10
Unit
Bits
Full
Full
Full
Full
25°C
Full
25°C
Guaranteed
±0.3
±0.7
−3.6
−2.2
−1.0
±0.2
±0.1
±0.3
±0.1
Guaranteed
±0.3
±0.7
−4.0
−2.5
−1.3
±0.2
±0.1
±0.3
±0.1
Guaranteed
±0.3
±0.7
−4.3
−3.0
−1.6
±0.2
±0.1
±0.4
±0.1
% FSR
% FSR
LSB
LSB
LSB
LSB
Full
Full
±0.3
±0.2
Full
Full
±15
±95
Full
Full
±5
7
25°C
0.1
0.1
0.1
LSB rms
Full
Full
Full
2
8
6
2
8
6
2
8
6
V p-p
pF
kΩ
Full
Full
1.7
1.7
±0.7
±0.8
±0.3
±0.3
Full
Full
310
34
Full
Full
35
15
42
Full
600
Full
Full
Full
Full
645
740
68
2.5
±0.2
±0.2
±15
±95
±16
1.8
3.3
±0.7
±0.8
1.9
3.6
±5
7
1.7
1.7
1.8
3.3
±15
±95
±16
1.9
3.6
385
42
365
1.7
1.7
1.8
3.3
455
750
6
813
900
77
2.5
1
±5
7
% FSR
% FSR
ppm/°C
ppm/°C
±16
1.9
3.6
419
50
36
18
44
650
±0.7
±0.8
mV
mV
V
V
mA
mA
495
42
22
46
800
825
6
892
990
77
2.5
mA
mA
mA
890
mW
6
mW
mW
mW
mW
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure.
3
Standby power is measured with a dc input and the CLK+ and CLK− pins inactive )set to AVDD or AGND.
2
Rev. B | Page 5 of 72
AD9600
AC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 29.1 MHz, 32.1 MHz (−7 dBFS )
fIN = 169.1 MHz, 172.1 MHz (−7 dBFS )
CROSSTALK 2
ANALOG INPUT BANDWIDTH
1
2
Temp
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
AD9600ABCPZ-105/
AD9600BCPZ-105
AD9600ABCPZ-125/
AD9600BCPZ-125
AD9600ABCPZ-150/
AD9600BCPZ-150
Min
Min
Min
Typ
Max
60.7
60.6
Typ
Max
60.6
60.6
60.3
Typ
Max
60.6
60.6
60.3
dB
dB
dB
dB
dB
60.3
60.6
60.5
60.6
60.5
60.5
60.4
60.6
60.5
60.5
60.5
60.5
60.5
Unit
60.5
60.4
60.5
60.4
60.4
60.3
dB
dB
dB
dB
dB
25°C
25°C
25°C
25°C
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
9.9
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
−87.0
−85.0
−86.5
−85.0
−88.5
−84.0
−84.0
−83.0
−84.0
−83.0
−83.5
−77
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
85.5
85.0
85.5
85.0
85.5
84.0
60.2
60.2
60.1
−72.0
72.0
−72.0
72.0
−72.0
dBc
dBc
dBc
dBc
dBc
72.0
83.0
81.0
84.0
81.0
83.5
77
25°C
25°C
Full
25°C
25°C
−92
−88
−92
-88
−92
−88
−86
−86
−86
−86
−86
−86
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
84
82
95
650
84
82
95
650
84
82
95
650
dBc
dBc
dB
MHz
−81
−81
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel.
Rev. B | Page 6 of 72
−80
AD9600
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB) 1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS) 2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
Temperature
Min
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
1.2
0.2
6
GND − 0.3
AVDD + 1.6
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
4
8
10
12
Full
Full
Full
Full
Full
Full
Full
Full
Max
CMOS
1.2
GND − 0.3
1.2
0
−10
−10
8
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
Rev. B | Page 7 of 72
Typ
AVDD + 1.6
3.6
0.8
+10
+10
4
10
12
V
V p-p
V
V
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
3.6
0.6
+10
132
V
V
μA
μA
kΩ
pF
3.6
0.6
−135
+10
V
V
μA
μA
kΩ
pF
3.6
0.6
+10
128
V
V
μA
μA
kΩ
pF
26
2
26
2
26
5
Unit
AD9600
Parameter
LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 μA)
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage (IOH = 50 μA)
High Level Output Voltage (IOH = 0.5 mA)
Low Level Output Voltage (IOL = 1.6 mA)
Low Level Output Voltage (IOL = 50 μA)
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
1
2
Temperature
Min
Full
Full
Full
Full
Full
Full
1.22
0
−90
−10
Full
Full
Full
Full
3.29
3.25
Full
Full
Full
Full
1.79
1.75
Full
Full
Full
Full
250
1.15
150
1.15
Pull up.
Pull down.
Rev. B | Page 8 of 72
Typ
Max
Unit
3.6
0.6
−134
+10
V
V
μA
μA
kΩ
pF
26
5
350
1.25
200
1.25
0.2
0.05
V
V
V
V
0.2
0.05
V
V
V
V
450
1.35
280
1.35
mV
V
mV
V
AD9600
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS
enabled, unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled
DCS Disabled
CLK Period (tCLK)
CLK Pulse Width High
Divide-by-1 Mode,
DCS Enabled
Divide-by-1 Mode,
DCS Disabled
Divide-by-2 Mode,
DCS Enabled
Divide-by-3 Through Divideby-8 Modes, DCS Enabled
DATA OUTPUT PARAMETERS
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD) 1
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)1
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)1
DCO Propagation Delay (tDCO)
CMOS Mode Pipeline Delay
(Latency)
LVDS Mode Pipeline Delay
(Latency) Channel A/Channel B
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time 2
OUT-OF-RANGE RECOVERY TIME
1
2
Temp
AD9600ABCPZ-105/
AD9600BCPZ-105
Min
Typ
Max
Full
AD9600ABCPZ-125/
AD9600BCPZ-125
Min
Typ
Max
625
AD9600ABCPZ-150/
AD9600BCPZ-150
Min
Typ
Max
625
105
105
20
10
8
4.75
6.65
2.4
4.75
5.23
3.6
Unit
625
MHz
150
150
MSPS
MSPS
ns
Full
Full
Full
20
10
9.5
125
125
20
10
6.66
Full
2.85
4
5.6
2.0
3.33
4.66
ns
Full
4.28
4
4.4
3.0
3.33
3.66
ns
Full
1.6
1.6
1.6
ns
Full
0.8
0.8
0.8
ns
Full
Full
Full
Full
2.2
3.8
4.5
5.0
5.25
4.25
6.4
6.8
2.2
3.8
4.5
5.0
4.5
3.5
6.4
6.8
2.2
3.8
4.5
5.0
3.83
2.83
6.4
6.8
ns
ns
ns
ns
Full
Full
Full
Full
2.4
4.0
5.2
5.6
5.25
4.25
6.9
7.3
2.4
4.0
5.2
5.6
4.5
3.5
6.9
7.3
2.4
4.0
5.2
5.6
3.83
2.83
6.9
7.3
ns
ns
ns
ns
Full
Full
Full
3.0
5.2
3.7
6.4
12
4.4
7.6
3.0
5.0
3.8
6.2
12
4.5
7.4
3.0
4.8
3.8
5.9
12
4.5
7.3
ns
ns
Cycles
Full
12/12.5
12/12.5
12/12.5
Cycles
Full
Full
Full
Full
1.0
0.1
350
2
1.0
0.1
350
3
1.0
0.1
350
3
ns
ps rms
μs
Cycles
Output propagation delay is measured from the CLK+ and CLK− pins 50% transition to the output data pins 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors.
Rev. B | Page 9 of 72
AD9600
TIMING CHARACTERISTICS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Conditions
Min
Setup time between SYNC and the rising edge of CLK+
Hold time between SYNC and the rising edge of CLK+
SPORT TIMING REQUIREMENTS
tCSSCLK
tSSCLKSDO
tSSCLKSDFS
Delay from the rising edge of CLK+ to the rising edge of SMI SCLK
Delay from the rising edge of SMI SCLK to SMI SDO
Delay from the rising edge of SMI SCLK to SMI SDFS
10
ns
3.2
−0.4
−0.4
4.5
0
0
N+3
N
N+4
N+8
N+5
N+6
N+7
tCLK
CLK+
CLK–
CH A/CH B DATA
N – 13
N – 12
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
CH A/CH B FAST
DETECT
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
tH
tDCO
tCLK
DCOA/DCOB
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing
Rev. B | Page 10 of 72
06909-012
tPD
tS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
N+2
tA
Unit
2
2
40
2
2
10
10
10
TIMING DIAGRAMS
N+1
Max
0.24
0.40
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output
relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an input
relative to the SCLK rising edge
tDIS_SDIO
Typ
6.2
0.4
0.4
ns
ns
ns
AD9600
N+2
N+1
N+3
N
N+4
N+8
tA
N+5
N+6
N+7
tCLK
CLK+
CLK–
tPD
CH A/CH B DATA
A
B
A
N – 12
N – 13
CH A/CH B FAST
DETECT
A
B
B
A
N–7
B
N–6
A
B
N – 11
A
B
N–5
A
B
N – 10
A
B
N–4
A
B
A
N–9
A
B
N–8
B
A
N–3
B
N–2
tDCO
A
B
N–7
A
B
N–1
A
B
A
N–6
A
B
B
N–5
A
N
B
N+1
A
N–4
A
N+2
tCLK
06909-089
DCO+
DCO–
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
CLK+
tHSYNC
06909-072
tSSYNC
SYNC
Figure 4. SYNC Input Timing Requirements
CLK+
CLK–
tCSSCLK
SMI SCLK/PDWN
tSSCLKSDFS
tSSCLKSDO
SMI SDO/OEB
DATA
Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode)
Rev. B | Page 11 of 72
DATA
06909-082
SMI SDFS
AD9600
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
ELECTRICAL
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
VIN + A/VIN + B, VIN − A/VIN − B to
AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB
SMI SCLK/PDWN
SMI SDFS
Output Data Pins to DRGND1
Fast Detect Output Pins to DRGND2
Data Clock Output Pins to DRGND3
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
THERMAL CHARACTERISTICS
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 7. Thermal Resistance
Airflow
Velocity
Package Type
(m/s)
64-Lead, 9 mm × 9 mm 0
LFCSP (CP-64-3,
1.0
CP-64-6)
2.0
θJC1, 3
0.6
θJB1, 4
6.0
15.8
1
Per JEDEC 51-7 standard and JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
3
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal (such as metal traces through holes, ground,
and power planes) that is in direct contact with the package
leads reduces the θJA.
ESD CAUTION
−40°C to +85°C
θJA1, 2
18.8
16.5
150°C
−65°C to +150°C
1
The output data pins are D0A/D0B to D9A/D9B for the CMOS configuration
and D0+/D0− to D9+/D9− for the LVDS configuration.
2
The fast detect output pins are FD0A/FD0B to FD3A/FD3B for the CMOS
configuration and FD0+/FD0− to FD3+/FD3−.
3
The data clock output pins are DCOA and DCOB for the CMOS configuration
and DCO+ and DCO− for the LVDS configuration.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 12 of 72
Unit
°C/W
°C/W
°C/W
AD9600
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
D1B
D0B (LSB)
DNC
DNC
DNC
DNC
DVDD
FD3B
FD2B
FD1B
FD0B
SYNC
CSB
CLK–
CLK+
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9600
PARALLEL CMOS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN + B
VIN – B
RBIAS
CML
SENSE
VREF
VIN – A
VIN + A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
06909-002
D1A
D2A
D3A
DRGND
DRVDD
D4A
D5A
DVDD
D6A
D7A
D8A
(MSB) D9A
FD0A
FD1A
FD2A
FD3A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
D2B
D3B
D4B
D5B
D6B
D7B
D8B
(MSB) D9B
DCOB
DCOA
DNC
DNC
DNC
DNC
(LSB) D0A
Figure 6. Parallel CMOS Mode Pin Configuration (Top View)
Table 8. Parallel CMOS Mode Pin Function Descriptions
Pin No.
ADC Power Supplies
20, 64
1, 21
24, 57
36, 45, 46
0
ADC Inputs
37
38
44
43
39
40
42
41
49
50
Mnemonic
Type
Description
DRGND
DRVDD
DVDD
AVDD
AGND
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
VIN + A
VIN − A
VIN + B
VIN − B
VREF
SENSE
RBIAS
CML
CLK+
Input
Input
Input
Input
I/O
Input
Input
Output
Input
CLK−
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select (see Table 11 for details).
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Master Clock True. The ADC clock can be driven using a single-ended
CMOS (see Figure 60 and Figure 61 for the recommended connection).
ADC Master Clock Complement. The ADC clock can be driven using a singleended CMOS (see Figure 60 and Figure 61 for the recommended connection).
Rev. B | Page 13 of 72
AD9600
Pin No.
ADC Fast Detect Outputs
29
30
31
32
53
54
55
56
Digital Inputs
52
Digital Outputs
16 to 19, 22, 23,
25 to 28
62, 63, 2 to 9
11
10
SPI Control
48
47
51
Signal Monitor Port
33
35
34
Do Not Connect
12 to 15, 58 to 61
Mnemonic
Type
Description
FD0A
FD1A
FD2A
FD3A
FD0B
FD1B
FD2B
FD3B
Output
Output
Output
Output
Output
Output
Output
Output
Channel A Fast Detect Indicator (see Table 14 for details).
Channel A Fast Detect Indicator (see Table 14 for details).
Channel A Fast Detect Indicator (see Table 14 for details).
Channel A Fast Detect Indicator (see Table 14 for details).
Channel B Fast Detect Indicator (see Table 14 for details).
Channel B Fast Detect Indicator (see Table 14 for details).
Channel B Fast Detect Indicator (see Table 14 for details).
Channel B Fast Detect Indicator (see Table 14 for details).
SYNC
Input
Digital Synchronization Pin (Slave Mode Only).
D0A to D9A
Output
Channel A CMOS Output Data.
D0B to D9B
DCOA
DCOB
Output
Output
Output
Channel B CMOS Output Data.
Channel A Data Clock Output.
Channel B Data Clock Output.
SCLK/DFS
SDIO/DCS
CSB
Input
I/O
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data Input and Output/Duty Cycle Stabilizer in External Pin Mode.
SPI Chip Select (Active Low).
SMI SDO/OEB
I/O
SMI SDFS
SMI SCLK/PDWN
Output
I/O
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in
External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
DNC
N/A
Do Not Connect.
Rev. B | Page 14 of 72
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
DNC
DNC
FD3+
FD3–
FD2+
FD2–
DVDD
FD1+
FD1–
FD0+
FD0–
SYNC
CSB
CLK–
CLK+
AD9600
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9600
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN + B
VIN – B
RBIAS
CML
SENSE
VREF
VIN – A
VIN + A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
06909-003
D3+
D4–
D4+
DRGND
DRVDD
D5–
D5+
DVDD
D6–
D6+
D7–
D7+
D8–
D8+
D9–
(MSB) D9+
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
DNC
DNC
DNC
DNC
DNC
DNC
(LSB) D0–
D0+
DCO–
DCO+
D1–
D1+
D2–
D2+
D3–
Figure 7. Interleaved Parallel LVDS Mode Pin Configuration (Top View)
Table 9. Interleaved Parallel LVDS Mode Pin Function Descriptions
Pin No.
ADC Power Supplies
20, 64
1, 21
24, 57
36, 45, 46
0
ADC Inputs
37
38
44
43
39
40
42
41
49
50
Mnemonic
Type
Description
DRGND
DRVDD
DVDD
AVDD
AGND
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
VIN + A
VIN − A
VIN + B
VIN − B
VREF
SENSE
RBIAS
CML
CLK+
Input
Input
Input
Input
I/O
Input
Input
Output
Input
CLK−
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select (see Table 11 for details).
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Master Clock True. The ADC clock can be driven using a single-ended CMOS
(see Figure 60 and Figure 61 for the recommended connection).
ADC Master Clock Complement. The ADC clock can be driven using a single-ended
CMOS (see Figure 60 and Figure 61 for the recommended connection).
Rev. B | Page 15 of 72
AD9600
Pin No.
ADC Fast Detect Outputs
54
53
Mnemonic
Type
Description
FD0+
FD0−
Output
Output
56
55
FD1+
FD1−
Output
Output
59
58
FD2+
FD2−
Output
Output
61
60
FD3+
FD3−
Output
Output
Channel A/Channel B LVDS Fast Detect Indicator 0 True (see Table 14 for full details).
Channel A/Channel B LVDS Fast Detect Indicator 0 Complement (see Table 14
for details).
Channel A/Channel B LVDS Fast Detect Indicator 1 True (see Table 14 for details).
Channel A/Channel B LVDS Fast Detect Indicator 1 Complement (see Table 14
for details).
Channel A/Channel B LVDS Fast Detect Indicator 2 True (see Table 14 for details).
Channel A/Channel B LVDS Fast Detect Indicator 2 Complement (see Table 14
for details).
Channel A/Channel B LVDS Fast Detect Indicator 3 True (see Table 14 for details).
Channel A/Channel B LVDS Fast Detect Indicator 3 Complement (see Table 14
for details).
SYNC
Input
Digital Synchronization Pin (Slave Mode Only).
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
D8+
D8−
D9+
D9−
DCO+
DCO−
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0 True.
Channel A/Channel B LVDS Output Data 0 Complement.
Channel A/Channel B LVDS Output Data 1 True.
Channel A/Channel B LVDS Output Data 1 Complement.
Channel A/Channel B LVDS Output Data 2 True.
Channel A/Channel B LVDS Output Data 2 Complement.
Channel A/Channel B LVDS Output Data 3 True.
Channel A/Channel B LVDS Output Data 3 Complement.
Channel A/Channel B LVDS Output Data 4 True.
Channel A/Channel B LVDS Output Data 4 Complement.
Channel A/Channel B LVDS Output Data 5 True.
Channel A/Channel B LVDS Output Data 5 Complement.
Channel A/Channel B LVDS Output Data 6 True.
Channel A/Channel B LVDS Output Data 6 Complement.
Channel A/Channel B LVDS Output Data 7 True.
Channel A/Channel B LVDS Output Data 7 Complement.
Channel A/Channel B LVDS Output Data 8 True.
Channel A/Channel B LVDS Output Data 8 Complement.
Channel A/Channel B LVDS Output Data 9 True.
Channel A/Channel B LVDS Output Data 9 Complement.
Channel A/Channel B LVDS Data Clock Output True.
Channel A/Channel B LVDS Data Clock Output Complement.
SCLK/DFS
SDIO/DCS
CSB
Input
I/O
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data Input and Output/Duty Cycle Stabilizer in External Pin Mode.
SPI Chip Select (Active Low).
SMI SDO/OEB
I/O
SMI SDFS
SMI SCLK/PDWN
Output
I/O
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in
External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
DNC
N/A
Do Not Connect.
Digital Inputs
52
Digital Outputs
9
8
13
12
15
14
17
16
19
18
23
22
26
25
28
27
30
29
32
31
11
10
SPI Control
48
47
51
Signal Monitor Port
33
35
34
Do Not Connect
2 to 7, 62, 63
Rev. B | Page 16 of 72
AD9600
EQUIVALENT CIRCUITS
DVDD
1kΩ
SCLK/DFS
26kΩ
06909-004
06909-008
VIN
Figure 12. Equivalent SCLK/DFS Input Circuit
Figure 8. Analog Input Circuit
AVDD
1kΩ
SENSE
1.2V
10kΩ
10kΩ
CLK+
06909-005
06909-009
CLK–
Figure 13. Equivalent SENSE Circuit
Figure 9. Equivalent Clock Input Circuit
DRVDD
DVDD
26kΩ
DVDD
1kΩ
06909-081
06909-010
CSB
DRGND
Figure 14. Equivalent CSB Input Circuit
Figure 10. Digital Output
DRVDD
DVDD
26kΩ
DVDD
1kΩ
SDIO/DCS
AVDD
06909-007
6kΩ
Figure 11. Equivalent SDIO/DCS Input Circuit
06909-011
VREF
DRVDD
Figure 15. Equivalent VREF Circuit
Rev. B | Page 17 of 72
AD9600
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1 V internal reference, 2 V p-p differential input,
VIN = −1.0 dBFS, 64k sample, and TA = 25°C, unless otherwise noted.
0
0
150MSPS
2.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.9 BITS
SFDR = 85.5dBc
–20
AMPLITUDE (dBFS)
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
20
30
40
50
60
70
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
Figure 19. AD9600-150 Single-Tone FFT with fIN = 140 MHz
0
0
150MSPS
30.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.9 BITS
SFDR = 84.0dBc
–40
–60
THIRD HARMONIC
SECOND
HARMONIC
–80
150MSPS
220MHz @ –1dBFS
SNR = 60.4dB (61.4dBFS)
ENOB = 9.7 BITS
SFDR = 77.0dBc
–20
AMPLITUDE (dBFS)
–20
–100
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–100
10
20
30
40
50
60
70
FREQUENCY (MHz)
–120
06909-030
0
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
06909-120
AMPLITUDE (dBFS)
THIRD HARMONIC
–80
–120
Figure 16. AD9600-150 Single-Tone FFT with fIN = 2.3 MHz
Figure 20. AD9600-150 Single-Tone FFT with fIN = 220 MHz
Figure 17. AD9600-150 Single-Tone FFT with fIN = 30.3 MHz
0
0
150MSPS
70MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 84.0dBc
–40
–60
SECOND HARMONIC
150MSPS
337MHz @ –1dBFS
SNR = 60.2dB (61.2dBFS)
ENOB = 9.7 BITS
SFDR = 74.0dBc
–20
AMPLITUDE (dBFS)
–20
THIRD HARMONIC
–80
–40
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–100
–100
–120
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
06909-118
AMPLITUDE (dBFS)
SECOND HARMONIC
06909-119
10
06909-029
0
FREQUENCY (MHz)
–120
–60
–100
–100
–120
–40
–120
0
10
20
30
40
50
FREQUENCY (MHz)
60
70
Figure 21. AD9600-150 Single-Tone FFT with fIN = 337 MHz
Figure 18. AD9600-150 Single-Tone FFT with fIN = 70 MHz
Rev. B | Page 18 of 72
06909-121
AMPLITUDE (dBFS)
–20
150MSPS
140MHz @ –1dBFS
SNR = 60.5dB (61.5dBFS)
ENOB = 9.8 BITS
SFDR = 83.5dBc
AD9600
0
0
150MSPS
440MHz @ –1dBFS
SNR = 60.0dB (61.0dBFS)
ENOB = 9.6 BITS
SFDR = 70.0dBc
–20
AMPLITUDE (dBFS)
–40
SECOND HARMONIC
–60
THIRD HARMONIC
–80
THIRD HARMONIC
SECOND HARMONIC
–80
10
20
30
40
50
FREQUENCY (MHz)
60
70
–120
0
Figure 22. AD9600-150 Single-Tone FFT with fIN = 440 MHz
10
20
30
40
FREQUENCY (MHz)
50
60
06909-125
0
06909-122
–120
Figure 25. AD9600-125 Single-Tone FFT with fIN = 70.1 MHz
0
0
125MSPS
2.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 86.5dBc
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
125MSPS
140.1MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 84.0dBc
–20
AMPLITUDE (dBFS)
–20
–40
–60
SECOND HARMONIC
THIRD HARMONIC
–80
–100
–100
0
10
20
30
40
FREQUENCY (MHz)
50
60
–120
06909-123
–120
0
Figure 23. AD9600-125 Single-Tone FFT with fIN = 2.3 MHz
10
20
30
40
FREQUENCY (MHz)
50
60
06909-126
AMPLITUDE (dBFS)
–60
–100
–100
Figure 26. AD9600-125 Single-Tone FFT with fIN = 140.1 MHz
0
0
125MSPS
30.3MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 85.0dBc
125MSPS
220.1MHz @ –1dBFS
SNR = 60.5dB (61.5dBFS)
ENOB = 9.7 BITS
SFDR = 81.0dBc
–20
AMPLITUDE (dBFS)
–20
–40
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–40
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–100
–100
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
06909-124
AMPLITUDE (dBFS)
–40
Figure 24. AD9600-125 Single-Tone FFT with fIN = 30.3 MHz
–120
0
10
20
30
40
FREQUENCY (MHz)
50
60
Figure 27. AD9600-125 Single-Tone FFT with fIN = 220.1 MHz
Rev. B | Page 19 of 72
06909-127
AMPLITUDE (dBFS)
–20
125MSPS
70.1MHz @ –1dBFS
SNR = 60.6dB (61.6dBFS)
ENOB = 9.8 BITS
SFDR = 85.0dBc
AD9600
95
120
90
SFDR +25°C
SFDR (dBFS)
SNR (dBFS)
SFDR –40°C
85
80
SNR/SFDR (dBc)
SNR/SFDR (dBc AND dBm)
100
60
85dB REFERENCE LINE
40
80
75
SFDR +85°C
70
SNR +25°C
SNR +85°C
SNR –40°C
65
SFDR (dBc)
20
60
–40
–30
–20
–10
0
AMPLITUDE (dBm)
55
Figure 28. AD9600-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 2.4 MHz
0
50
100
150
200
250
350
400
–2.5
0.5
SFDR (dBFS)
80
GAIN
–3.0
GAIN ERROR (%FSR)
SNR (dBFS)
60
85dB REFERENCE LINE
40
450
Figure 31. AD9600-150 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with12 V p-p Full Scale
100
SNR/SFDR (dBc AND dBm)
300
INPUT FREQUENCY (MHz)
0.4
OFFSET
–3.5
0.3
–4.0
0.2
–4.5
0.1
SNR (dBc)
20
OFFSET ERROR (%FSR)
–50
06909-031
0
–60
06909-034
SNR (dBc)
–50
–40
–30
–20
–10
0
AMPLITUDE (dBm)
–5.0
–40
06909-032
0
–60
0
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 29. AD9600-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 98.12 MHz
06909-132
SFDR (dBc)
Figure 32. AD9600-150 Gain and Offset vs. Temperature
95
0
90
–20
SFDR/IMD3 (dBc AND dBFS)
SFDR +85°C
SNR/SFDR (dBc)
85
SFDR +25°C
80
SFDR –40°C
75
70
SNR +25°C
SNR +85°C
SNR –40°C
65
SFDR (dBc)
–40
–60
IMD3 (dBc)
SFDR (dBFS)
–80
–100
60
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
350
400
450
–120
–60
Figure 30. AD9600-150 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 2 V p-p Full Scale
–48
–36
–24
INPUT AMPLITUDE (dBFS)
–12
06909-133
0
06909-033
55
IMD3 (dBFS)
Figure 33. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 150 MSPS
Rev. B | Page 20 of 72
AD9600
0
0
150MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
SFDR = 83.1dBc (90.1dBFS)
SFDR (dBc)
–20
AMPLITUDE (dBFS)
–40
IMD3 (dBc)
–60
SFDR (dBFS)
–80
–60
–80
IMD3 (dBFS)
–100
–100
–36
–24
INPUT AMPLITUDE (dBFS)
–12
–120
Figure 34. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS
0
20
30
40
50
INPUT FREQUENCY (MHz)
60
70
Figure 37. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Frequency (fIN) with
fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS
0
0
NPR = 54.3dBc
NOTCH @ 18.5MHz
NOTCH WIDTH = 3MHz
–20
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–40
–60
–80
–100
15.36
30.72
46.08
61.44
FREQUENCY (MHz)
–120
0
10
20
30
40
50
60
06909-138
0
06909-135
–120
70
FREQUENCY (MHz)
Figure 35. AD9600-125 Two 64k WCDMA Carriers with
fIN = 170 MHz, fS = 125 MSPS
Figure 38. AD9600-150 Noise Power Ratio (NPR)
100
0
150MSPS
29.1MHz @ –7dBFS
32.1MHz @ –7dBFS
SFDR = 86.1dBc (93.1dBFS)
–20
SFDR—SIDE B
90
–40
SNR/SFDR (dBc)
AMPLITUDE (dBFS)
10
06909-137
–48
06909-134
–120
–60
AMPLITUDE (dBFS)
–40
–60
–80
80
SFDR—SIDE A
70
SNR—SIDE A
SNR—SIDE B
60
–100
0
10
20
30
40
50
INPUT FREQUENCY (MHz)
60
70
50
06909-136
–120
Figure 36. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Frequency (fIN) with
fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 150 MSPS
0
25
50
75
ENCODE (MSPS)
100
125
150
06909-035
SFDR/IMD3 (dBc AND dBFS)
–20
Figure 39. AD9600-150 Single-Tone SNR/SFDR vs. Clock Frequency (fS ) with
fIN1 = 2.3 MHz
Rev. B | Page 21 of 72
AD9600
12
100
0.10 LSB rms
95
SFDR DCS ON
90
8
SNR/SFDR (dBc)
NUMBER OF HITS (1M)
10
6
4
85
80
SFDR DCS OFF
75
SNR DCS ON
70
2
65
N–2
N–1
N
N+1
N+2
N+3
OUTPUT CODE
06909-140
N–3
60
20
40
60
80
DUTY CYCLE (%)
Figure 40. AD9600 Grounded Input Histogram
06909-143
SNR DCS OFF
0
Figure 43. AD9600-150 SNR/SFDR vs. Duty Cycle with fIN1 = 10.3 MHz
95
0.10
90
SNR/SFDR (dBc)
INL ERROR (LSB)
SFDR
85
0.05
0
80
75
70
65
–0.05
SNR
0
128
256
384
512
640
768
896
1024
OUTPUT CODE
55
0.2
06909-036
–0.10
Figure 41. AD9600 INL with fIN1 = 10.3 MHz
0.025
0
–0.025
–0.050
–0.075
256
384
512
640
768
OUTPUT CODE
896
1024
06909-037
DNL ERROR (LSB)
0.050
128
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Figure 44. AD9600-150 SNR/SFDR vs. Input Common-Mode Voltage (VCM) with
fIN1 = 30 MHz
0.075
0
0.4
INPUT COMMON-MODE VOLTAGE (V)
0.100
–0.100
0.3
06909-144
60
Figure 42. AD9600 DNL with fIN1 = 10.3 MHz
Rev. B | Page 22 of 72
AD9600
THEORY OF OPERATION
The AD9600 dual ADC design can be used for diversity
reception of signals, where the ADCs are operating identically
on the same carrier but from two separate antennae. The ADCs
can also be operated with independent analog inputs. The user
can sample any fS/2 frequency segment from dc to 200 MHz
using appropriate low-pass or band-pass filtering at the ADC
inputs with little loss in ADC performance. Although operation
of up to 450 MHz analog input is permitted, ADC distortion
increases at frequencies toward the higher end of this range.
In nondiversity applications, the AD9600 can be used as a
baseband receiver where one ADC is used for I input data and
the other used for Q input data.
Synchronization capability is provided to allow synchronized
timing among multiple channels or multiple devices.
Programming and control of the AD9600 is accomplished using
a 3-bit SPI-compatible serial interface.
of a clock cycle. A small resistor in series with each input can
help reduce the peak transient current required from the output
stage of the driving source. A shunt capacitor can be placed
across the inputs to provide dynamic charging currents. This
passive network creates a low-pass filter at the ADC’s input;
therefore, the precise values are dependent on the application.
In undersampling (IF sampling) applications, any shunt capacitors
should be reduced. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth. See
the AN-742 Application Note, Frequency Domain Response of
Switched-Capacitor ADCs; the AN-827 Application Note, A
Resonant Approach to Interfacing Amplifiers to Switched-Capacitor
ADCs; and the Analog Dialogue article “Transformer-Coupled
Front-End for Wideband A/D Converters” (Volume 39, April 2005)
for more information. In general, the precise values are dependent
on the application.
S
ADC ARCHITECTURE
CH
The AD9600 architecture consists of a dual front-end sampleand-hold amplifier (SHA) followed by a pipelined switchedcapacitor ADC. The quantized outputs from each stage are
combined into a final 10-bit result in the digital correction
logic. The pipelined architecture permits the first stage to
operate on a new input sample while the remaining stages
operate on preceding samples. Sampling occurs on the rising
edge of the clock.
Each stage of the pipeline excluding the last consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(a multiplying digital-to-analog converter (MDAC)). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the
pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage simply
consists of a flash ADC.
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output-staging block aligns the data, corrects errors, and
passes the data to the output buffers. The output buffers are
powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9600 is a differential switchedcapacitor SHA that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternatively switches the SHA between
sample mode and hold mode (see Figure 45). When the SHA is
switched into sample mode, the signal source must be capable
of charging the sample capacitors and settling within one-half
S
CS
VIN+
CPIN, PAR
S
H
CS
VIN–
CH
S
06909-013
CPIN, PAR
Figure 45. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched.
An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core.
The span of the ADC core is set by the buffer to 2 × VREF.
Input Common Mode
The analog inputs of the AD9600 are not internally dc-biased.
Therefore, in ac-coupled applications, the user must provide this
bias externally. Setting the device so that VCM = 0.55 × AVDD is
recommended for optimum performance, but the device can
function over a wider range with reasonable performance (see
Figure 44). An on-board common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage (typically
0.55 × AVDD). The CML pin must be decoupled to ground by a
0.1 μF capacitor as described in the Applications Information
section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9600
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, and ADA4938-2 differential drivers
provide excellent performance and a flexible interface to the
Rev. B | Page 23 of 72
AD9600
An alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone is to use the AD8352
differential driver. An example is shown in Figure 50. See the
AD8352 data sheet for more information.
ADC. The output common-mode voltage of the AD8138 is
easily set with the CML pin of the AD9600 (see Figure 46), and
the driver can be configured in a Sallen-Key filter topology to
band limit the input signal.
AVDD
VIN+
R
499Ω
AD9600
C
AD8138
R
523Ω
VIN–
CML
499Ω
Table 10. Example RC Network
Figure 46. Differential Input Configuration Using the AD8138
Frequency Range (MHz)
0 to 70
70 to 200
200 to 300
>300
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 47. The CML
voltage can be connected to the center tap of the transformer’s
secondary winding to bias the analog input.
49.9Ω
A single-ended input can provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input commonmode swing. If the source impedances on each input are matched,
there should be little effect on SNR performance. Figure 48
details a typical single-ended input configuration.
VIN+
AD9600
C
R
AVDD
10µF
VIN–
1kΩ
CML
R
06909-015
0.1µF
2V p-p
49.9Ω
0.1µF
AVDD
Figure 47. Differential Transformer-Coupled Configuration
0.1µF
10µF
0.1µF
ADC
AD9600
C
1kΩ
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9600. For applications where
SNR is a key parameter, differential double-balun coupling is
the recommended input configuration. An example is shown
in Figure 49.
VIN+
1kΩ
R
VIN–
1kΩ
Figure 48. Single-Ended Input Configuration
0.1µF
R
VIN+
2V p-p
25Ω
PA
S
S
P
AD9600
C
25Ω
0.1µF
0.1µF
R
CML
VIN–
06909-228
2V p-p
Figure 49. Differential Double-Balun Input Configuration
VCC
0.1µF
0Ω
ANALOG INPUT
16
0.1µF
8, 13
1
11
0.1µF
RD
RG
3
200Ω
AD8352
10
4
5
ANALOG INPUT
0.1µF
0Ω
R
VIN+
2
CD
C Differential (pF)
15
5
5
Open
Single-Ended Input Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz. Excessive signal power can cause core
saturation, which leads to distortion.
R
R Series (Ω, Each)
33
33
15
15
C
0.1µF
200Ω
R
AD9600
VIN–
CML
14
0.1µF
0.1µF
Figure 50. Differential Input Configuration Using the AD8352
Rev. B | Page 24 of 72
06909-270
0.1µF
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and source impedance and may
need to be reduced or removed. Table 10 lists the recommended
values to set the RC network. However, the actual values are
dependent on the input signal; therefore, Table 10 should only
be used as a starting guide.
499Ω
06909-018
49.9Ω
06909-014
1V p-p
AD9600
VOLTAGE REFERENCE
VIN + A/VIN + B
VIN – A/VIN – B
A stable and accurate voltage reference is built into the AD9600.
The input range can be adjusted by varying the reference voltage
applied to the AD9600, using either the internal reference or an
externally applied reference voltage. The input span of the ADC
tracks reference voltage changes linearly. The various reference
modes are summarized in this section. The Reference
Decoupling section describes the best PCB layout practices
for the reference.
ADC
CORE
VREF
1µF
0.1µF
R2
SELECT
LOGIC
SENSE
R1
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
VIN + A/VIN + B
VIN – A/VIN – B
Figure 52. Programmable Reference Configuration
If the internal reference of the AD9600 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 53 depicts
how the internal reference voltage is affected by loading.
0
VREF = 0.5V
ADC
CORE
–0.25
VREF = 1.0V
–0.50
–0.75
–1.00
–1.25
0
0.5
1.0
1.5
2.0
LOAD CURRENT (mA)
VREF
1µF
Figure 53. VREF Accuracy vs. Load
0.1µF
SELECT
LOGIC
SENSE
AD9600
06909-019
0.5V
Figure 51. Internal Reference Configuration
Table 11. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
SENSE Voltage
AVDD
VREF
0.2 V to VREF
Resulting VREF (V)
N/A
0.5
Internal Fixed Reference
AGND to 0.2 V
1.0
R2 ⎞ (see Figure 52)
0 . 5 × ⎛⎜ 1 +
⎟
R1 ⎠
⎝
Rev. B | Page 25 of 72
Resulting Differential Span (V p-p)
2 × external reference
1.0
2 × VREF
2.0
06909-280
R2 ⎞
VREF = 0.5 × ⎛⎜1 +
⎟
⎝ R1 ⎠
0.5V
AD9600
REFERENCE VOLTAGE ERROR (%)
A comparator within the AD9600 detects the potential at the
SENSE pin and configures the reference into four possible modes,
which are summarized in Table 11. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 51), setting VREF to 1.0 V. Connecting the
SENSE pin to VREF switches the reference amplifier output to
the SENSE pin, completing the loop and providing a 0.5 V
reference output. If a resistor divider is connected external to
the chip as shown in Figure 52, the switch again selects the
SENSE pin. This puts the reference amplifier in a noninverting
mode with the VREF output defined as
06909-020
Internal Reference Connection
AD9600
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or to improve the thermal drift
characteristics. Figure 54 shows the typical drift characteristics
of the internal reference in 1.0 V mode.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9600 while
preserving the fast rise and fall times of the signal that are
critical to low jitter performance.
2.0
1.5
1.0
0
Mini-Circuits®
ADT1-1WT, 1:1Z
0.1µF
XFMR
–0.5
0.1µF
–1.0
CLK+
CLK+
ADC
AD9600
100Ω
50Ω
0.1µF
–1.5
CLK–
–2.0
SCHOTTKY
DIODES:
HSMS2822
–2.5
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
06909-299
0.1µF
06909-024
REFERENCE VOLTAGE ERROR (mV)
2.5
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from 10 MHz
to 200 MHz. The back-to-back Schottky diodes across the
secondary transformer or balun limit clock excursions into the
AD9600 to approximately 0.8 V p-p differential.
Figure 56. Transformer-Coupled Differential Clock (up to 200 MHz)
Figure 54. Typical VREF Drift
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9600 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
1nF
0.1µF
CLK+
CLK+
ADC
AD9600
50Ω
0.1µF
1nF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 57. Balun-Coupled Differential Clock (up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 58. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515 family of clock drivers offers excellent
jitter performance.
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
AVDD
0.1µF
0.1µF
CLK+
CLK+
1.2V
0.1µF
CLK–
100Ω
0.1µF
CLK–
ADC
AD9600
50kΩ
240Ω
06909-025
CLK–
50kΩ
2pF
06909-023
2pF
PECL
DRIVER
240Ω
Figure 58. Differential PECL Sample Clock (up to 150 MSPS)
Figure 55. Equivalent Clock Input Circuit
Clock Input Options
The AD9600 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, the jitter of the clock
source is of the most concern, as described in the Jitter
Considerations section.
Figure 56 and Figure 57 show preferred methods for clocking the
AD9600 (at clock rates of up to 625 MHz). A low jitter clock source
is converted from a single-ended signal to a differential signal
using either an RF balun or an RF transformer.
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins as shown in Figure 59. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offer excellent jitter performance.
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
0.1µF
0.1µF
CLK+
CLK+
0.1µF
CLK–
LVDS
DRIVER
100Ω
0.1µF
ADC
AD9600
CLK–
50kΩ
50kΩ
Figure 59. Differential LVDS Sample Clock (up to 150 MSPS)
Rev. B | Page 26 of 72
06909-026
CLK+
06909-057
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
AD9600
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 60). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages of up to 3.6 V and therefore offers
several selections for the drive logic voltage.
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
VCC
1kΩ
CLK+
50Ω
OPTIONAL
100Ω
CMOS
DRIVER
0.1µF
1kΩ
CLK+
ADC
AD9600
Jitter Considerations
CLK–
39kΩ
06909-027
0.1µF
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated as
SNR = −20 log (2πf IN × t J )
Figure 60. Single-Ended 1.8 V CMOS Sample Clock (up to 150 MSPS)
AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter. IF undersampling
applications are particularly sensitive to jitter (see Figure 62).
VCC
1kΩ
50Ω
1kΩ
CMOS
DRIVER
OPTIONAL
100Ω
CLK+
0.1µF
0.1µF
ADC
AD9600
CLK–
65
06909-028
0.1µF
CLK+
0.05ps
60
Figure 61. Single-Ended 3.3 V CMOS Sample Clock (up to 150 MSPS)
0.20ps
Input Clock Divider
The AD9600 contains an input clock divider with the ability to
divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
The AD9600 clock divider can be synchronized by using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized either on every SYNC signal
or on only the first SYNC signal after the register is written. A
valid SYNC causes the clock divider to reset to its initial state.
This synchronization feature allows aligning the clock dividers of
multiple devices to guarantee simultaneous input sampling.
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a ±5% tolerance
is required on the clock duty cycle to maintain dynamic
performance characteristics. The AD9600 contains a duty cycle
stabilizer (DCS) that retimes the nonsampling (or falling) edge,
providing an internal clock signal with a nominal 50% duty
cycle. This allows the user to provide a wide range of clock
input duty cycles without affecting the performance of the
AD9600. When the SDIO/DCS pin functions as DCS, noise and
distortion performance are nearly flat for a wide range of duty
cycles, as shown in Figure 43.
SNR (dBc)
MEASURED
0.5ps
55
1.0ps
1.50ps
50
2.00ps
45
2.50ps
3.00ps
1
10
100
1000
INPUT FREQUENCY (MHz)
06909-162
0.1µF
Jitter in the rising edge of the input is an important concern, and it
is not reduced by the internal stabilization circuit. The duty cycle
control loop does not function for clock rates less than 20 MHz
nominally. The loop has a time constant associated with it that
needs to be considered if the clock rate may change dynamically.
This requires a wait time of 1.5 μs to 5 μs after a dynamic clock
frequency increase or decrease before the DCS loop is relocked
to the input signal. During this time, the loop is not locked, the
DCS loop is bypassed, and the internal device timing is dependent
on the duty cycle of the input clock signal. In such applications,
it may be appropriate to disable the duty clock stabilizer. In all
other applications, enabling the DCS circuit is recommended to
maximize ac performance.
Figure 62. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9600.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or another method), it
should be retimed by the original clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs.
Rev. B | Page 27 of 72
AD9600
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load presented
to the output drivers can minimize digital power consumption.
The data in Figure 63 was taken with the same operating
conditions as the Typical Performance Characteristics, with a
5 pF load on each output driver.
0.5
IAVDD
TOTAL POWER
0.2
0.50
0.25
0.1
IDRVDD
IDVDD
0
0
25
50
75
100
SUPPLY CURRENT (A)
0.3
0.75
125
0
150
ENCODE (MSPS)
Figure 63. AD9600-150 Power and Current vs. Sample Rate
0.5
1.00
0.4
0.3
0.75
TOTAL POWER
0.2
0.50
0.25
0
0
25
50
75
100
0
125
ENCODE (MSPS)
Figure 64. AD9600-125 Power and Current vs. Sample Rate
IDRVDD
IDVDD
0
0
0
25
50
ENCODE (MSPS)
75
100
Figure 65. AD9600-105 Power and Current vs. Sample Rate
By asserting the PDWN mode (either through the SPI port or
by asserting the PDWN pin high), the AD9600 is placed into
power-down mode. In this state, the ADC typically dissipates
2.5 mW. During power-down, the output drivers are placed in a
high impedance state. Asserting the PDWN pin low returns the
AD9600 to its normal operating mode. Note that PDWN is
referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
When using the SPI port interface, the user can place the ADC
into power-down or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map
Register Description section for more details.
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies and may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
0.1
IDRVDD
IDVDD
0.1
0.25
The AD9600 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic.
06909-039
TOTAL POWER (W)
IAVDD
0.2
DIGITAL OUTPUTS
SUPPLY CURRENT (A)
1.25
TOTAL POWER
0.50
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and must be recharged when returning to
normal operation. As a result, the wake-up time is related to the
time spent in power-down mode: shorter power-down cycles
result in proportionally shorter wake-up times.
06909-038
TOTAL POWER (W)
0.4
0.3
SUPPLY CURRENT (A)
where N is the number of output bits (22 in the case of AD9600
with the fast detect output pins disabled).
TOTAL POWER (W)
I DRVDD = V DRVDD × C LOAD × f CLK × N
1.00
IAVDD
0.75
06909-999
As shown in Figure 63, the power dissipated by the AD9600 is
proportional to its sample rate. In CMOS output mode, the
digital power dissipation is determined primarily by the
strength of the digital drivers and the load on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
1.25
0.4
1.00
POWER DISSIPATION AND STANDBY MODE
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when
operating in the external pin mode (see Table 12). As detailed in
the Memory Map Register Description section, the data format
can be selected for offset binary, twos complement, or gray code
when using the SPI control.
Rev. B | Page 28 of 72
AD9600
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
TIMING
Voltage at Pin
AGND
AVDD
The AD9600 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
SCLK/DFS
Offset binary (default)
Twos complement
SDIO/DCS
DCS disabled
DCS enabled (default)
Digital Output Enable Function (OEB)
The AD9600 has a flexible three-state ability for the digital
output pins. The three-state mode can be enabled by using the
SMI SDO/OEB pin or the SPI interface. If the SMI SDO/OEB pin
is low, the output data drivers are enabled. If the SMI SDO/OEB pin
is high, the output data drivers are placed into a high impedance
state. This output enable function is not intended for rapid access
to the data bus. Note that OEB is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply voltage.
When the device uses the SPI interface, each channel’s data and
fast detect output pins can be independently three-stated by
using the output enable bar bit in Register 0x14.
The length of the output data lines and the loads placed on them
should be minimized to reduce transients within the AD9600.
These transients can degrade the dynamic performance of the
converter. The lowest typical conversion rate of the AD9600 is
typically 10 MSPS. At clock rates below 10 MSPS, dynamic
performance may degrade.
Data Clock Output (DCO)
The AD9600 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO, unless the polarity
has been changed via the SPI. See the timing diagrams shown
in Figure 2 and Figure 3 for more information.
Table 13. Output Data Format
Input (V)
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
(VIN+ ) − (VIN− )
Condition (V)
< −VREF − 0.5 LSB
= –VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
Binary Output Mode
00 0000 0000
00 0000 0000
10 0000 0000
11 1111 1111
11 1111 1111
Rev. B | Page 29 of 72
Twos Complement Mode
10 0000 0000
10 0000 0000
00 0000 0000
01 1111 1111
01 1111 1111
Overrange
1
0
0
0
1
AD9600
ADC OVERRANGE AND GAIN CONTROL
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness.
Therefore, it is helpful to have a programmable threshold below
full scale that allows time to reduce the gain before the clip
actually occurs. In addition, because input signals can have
significant slew rates, latency of this function is of major concern.
Highly pipelined converters can have significant latency. A good
compromise is to use the output bits from the first stage of the
ADC for this function. Latency for these output bits is very low,
and overall resolution is not highly significant. Peak input signals
are typically between full scale and 6 dB to 10 dB below full
scale. A 3-bit or 4-bit output provides adequate range and
resolution for this function.
Via the SPI port, the user can provide a threshold above which
an overrange output would be active. As long as the signal is below
that threshold, the output should remain low. The fast detect
output pins can also be programmed via the SPI port so that one of
the pins functions as a traditional overrange pin for customers
who currently use this feature. In this mode, all 12 bits of the
converter are examined in the traditional manner, and the output is
high for the condition normally defined as overflow. In either
mode, the magnitude of the data is considered in the calculation
of the condition (but the sign of the data is not considered). The
threshold detection responds identically to positive and negative
signals outside the desired magnitude range.
FAST DETECT OVERVIEW
The AD9600 contains circuitry to facilitate fast overrange detection, allowing very flexible external gain control implementations.
Each ADC has four fast detect output pins that are used to output
information about the current state of the ADC input level. The
function of these pins is programmable via the fast detect mode
select bits and the fast detect enable bit in Register 0x104, allowing
range information to be output from several points in the internal
datapath. These pins can also be set up to indicate the presence of
overrange or underrange conditions, according to programmable
threshold levels. Table 14 shows the six configurations available
for the fast detect pins.
Table 14. Fast Detect Mode Select Bits Settings
Fast Detect
Mode Select Bits
(Register 0x104 [3:1])
000
001
010
011
100
101
Information Presented on
Fast Detect (FD) Pins of Each ADC1, 2
FD [3]
FD [2]
FD [1]
FD [0]
ADC fast magnitude (see Table 15)
OR
ADC fast magnitude
(see Table 16)
ADC fast magnitude
OR
F_LT
(see Table 17)
ADC fast magnitude
C_UT
F_LT
(see Table 17)
OR
C_UT
F_UT
F_LT
OR
F_UT
IG
DG
1
The fast detect pins are FD0A/FD0B to FD9A/FD9B for the CMOS mode
configuration and FD0+/FD0− to FD9+/FD9− for the LVDS mode
configuration.
2
See the ADC Overrange (OR) and Gain Switching sections for more
information about OR, C_UT, F_UT, F_LT, IG, and DG.
ADC FAST MAGNITUDE
When the fast detect output pins are configured to output the ADC
fast magnitude (that is, when the fast detect mode select bits are
set to 0b000), the information presented is the ADC level from an
early converter stage with only a two-clock-cycle latency (when
in CMOS output mode). Using the fast detect output pins in
this configuration provides the earliest possible level indication
information. Because this information is provided early in the
datapath, there is a significant uncertainty in the level indicated.
The nominal levels, along with the uncertainty indicated by the
ADC fast magnitude, are shown in Table 15.
Table 15. ADC Fast Magnitude Nominal Levels with
Fast Detect Mode Select Bits = 000
ADC Fast Magnitude on
FD [3:0] Pins
0000
0001
0010
0011
0100
0101
0110
0111
1000
Rev. B | Page 30 of 72
Nominal Input
Magnitude
Below FS (dB)
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