AD9625BBPZRL-2.6

12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter AD9625 Data Sheet FUNCTIONAL BLOCK DIAGRAM AVDD AGND REFERENCE DRVDD DRGND DIGITAL INTERFACE AND CONTROL VCM VIN+ VIN– ADC CORE DDC fS/8 OR fS/16 SERDOUT[0]± SERDOUT[1]± SERDOUT[2]± SERDOUT[3]± SERDOUT[4]± SERDOUT[5]± SERDOUT[6]± SERDOUT[7]± RBIAS_EXT CONTROL REGISTERS SYSREF± CLK± CLOCK MANAGEMENT AD9625 CMOS DIGITAL INPUT/OUTPUT SDIO SCLK CSB CMOS DIGITAL INPUT/ OUTPUT LVDS DIGITAL INPUT/ OUTPUT FD RSTB IRQ SYNCINB± DIVCLK± 11814-001 12-bit 2.5 GSPS ADC, no missing codes SFDR = 79 dBc, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS SFDR = 77 dBc, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS SNR = 57.6 dBFS, AIN up to 1 GHz at −1 dBFS, 2.5 GSPS SNR = 57 dBFS, AIN up to 1.8 GHz at −1 dBFS, 2.5 GSPS Noise spectral density = −149.5 dBFS/Hz at 2.5 GSPS Differential analog input: 1.2 V p-p Differential clock input 3.2 GHz analog input bandwidth, full power High speed 6- or 8-lane JESD204B serial output at 2.6 GSPS Subclass 1: 6.5 Gbps at 2.6 GSPS Two independent decimate by 8 or decimate by 16 filters with 10-bit NCOs Supply voltages: 1.3 V, 2.5 V Serial port control Flexible digital output modes Built-in selectable digital test patterns Timestamp feature Conversion error rate < 10−15 JESD204B INTERFACE FEATURES Figure 1. APPLICATIONS Spectrum analyzers Military communications Radar High performance digital storage oscilloscopes Active jamming/antijamming Electronic surveillance and countermeasures GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9625 is a 12-bit monolithic sampling analog-to-digital converter (ADC) that operates at conversion rates of up to 2.6 giga samples per second (GSPS). This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for spectrum analyzers, data acquisition systems, and a wide assortment of military electronics applications, such as radar and electronic countermeasures. 1. 2. 3. High performance: exceptional SFDR in high sample rate applications, direct RF sampling, and on-chip reference. Flexible digital data output formats based on the JESD204B specification. Control path SPI interface port that supports various product features and functions, such as data formatting, gain, and offset calibration values. The analog input, clock, and SYSREF± signals are differential inputs. The JESD204B-based high speed serialized output is configurable in a variety of one-, two-, four-, six-, or eight-lane configurations. The product is specified over the industrial temperature range of −40°C to +85°C, measured at the case. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9625 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Numerically Controlled Oscillator .......................................... 33  Applications ....................................................................................... 1  High Bandwidth Decimator ..................................................... 33  Functional Block Diagram .............................................................. 1  Low Bandwidth Decimator ....................................................... 36  General Description ......................................................................... 1  Digital Outputs ............................................................................... 37  Product Highlights ........................................................................... 1  Introduction to the JESD204B Interface ................................. 37  Revision History ............................................................................... 3  Functional Overview ................................................................. 37  Specifications..................................................................................... 4  JESD204B Link Establishment ................................................. 39  DC Specifications ......................................................................... 4  Physical Layer Output................................................................ 43  AC Specifications.......................................................................... 5  Scrambler ..................................................................................... 43  Digital Specifications ................................................................... 6  Tail Bits ........................................................................................ 43  Switching Specifications .............................................................. 7  DDC Modes (Single and Dual) ................................................ 43  Timing Specifications .................................................................. 7  CheckSum ................................................................................... 44  Absolute Maximum Ratings............................................................ 9  8-Bit/10-Bit Encoder Control ................................................... 44  Thermal Characteristics .............................................................. 9  Initial Lane Alignment Sequence (ILAS) ................................ 44  ESD Caution .................................................................................. 9  Lane Synchronization ................................................................ 45  Pin Configuration and Function Descriptions ........................... 10  JESD204B Application Layers .................................................. 48  Typical Performance Characteristics ........................................... 16  Frame Alignment Character Insertion .................................... 51  AD9625-2.0 ................................................................................. 17  Thermal Considerations............................................................ 51  AD9625-2.5 ................................................................................. 20  Power Supply Considerations ................................................... 51  AD9625-2.6 ................................................................................. 24  Serial Port Interface (SPI) .............................................................. 52  Equivalent Test Circuits ................................................................. 27  Configuration Using the SPI ..................................................... 52  Theory of Operation ...................................................................... 28  Hardware Interface..................................................................... 52  ADC Architecture ...................................................................... 28  Memory Map .................................................................................. 53  Fast Detect ................................................................................... 28  Reading the Memory Map Register ......................................... 53  Gain Threshold Operation ........................................................ 28  Memory Map Registers ............................................................. 53  Test Modes ................................................................................... 29  Applications Information .............................................................. 71  Analog Input Considerations ........................................................ 30  Design Guidelines ...................................................................... 71  Differential Input Configurations ............................................ 30  Power and Ground Recommendations ................................... 71  Using the ADA4961 ................................................................... 30  Clock Stability Considerations ................................................. 71  DC Coupling ............................................................................... 32  SPI Port ........................................................................................ 71  Clock Input Considerations ...................................................... 32  Outline Dimensions ....................................................................... 72  Digital Downconverters (DDC) ................................................... 33  Ordering Guide .......................................................................... 72  Frequency Synthesizer and Mixer ............................................ 33  Rev. C | Page 2 of 72 Data Sheet AD9625 REVISION HISTORY 9/2016—Rev. B to Rev. C Changes to ADC Output Control Bits on JESD204B Samples Section ..............................................................................................45 Changes to Table 94 ........................................................................67 Changes to Table 110 and Table 111 .............................................69 Changes to Table 113 and Table 114 .............................................70 Changes to the Clock Stability Considerations Section .............71 Changes to Ordering Guide ...........................................................72 5/2015—Rev. A to Rev. B Added AD9625-2.6 ....................................................... Throughout Change to Figure 1 ............................................................................ 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 5 Change to Figure 5 ..........................................................................10 Added Endnote 1, Table 8 ..............................................................11 Added Endnote 2, Table 9 ..............................................................13 Added AD9625-2.6 Section ...........................................................24 Changes to Figure 61 and Figure 63 .............................................27 Changes to Table 11 ........................................................................30 Added Using the ADA4961 Section .............................................30 Added Figure 77; Renumbered Sequentially, Figure 78, Figure 79, and Figure 80 .................................................................31 Changes to Table 12 ........................................................................34 Changes to Low Bandwidth Decimator Section and Table 13.....36 Changes to Table 28 ........................................................................54 Changes to Table 107 ......................................................................69 Changes to Ordering Guide ...........................................................72 9/2014—Rev. 0 to Rev. A Added AD9625-2.5 ....................................................... Throughout Changes to Features and General Description Sections .............. 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 5 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Figure 3 and Figure 4.................................................... 8 Changes to Table 6 ............................................................................ 9 Changes to Pin K4; Figure 5, Table 8, and Table 9 ......................10 Added Typical Performance Characteristics Summary and Changes to Typical Performance Characteristics .......................16 Changes to Figure 45, Figure 49, and Figure 50; Added Figure 51 to Figure 54 ..................................................................... 23 Changes to Gain Threshold Operation Section .......................... 24 Changes to Analog Input Considerations Section...................... 26 Changes to Digital Downconverters (DDC) Section ................. 28 Added Figure 68 .............................................................................. 32 Changes to Data Streaming Section; Added Link Setup Parameters Section.......................................................................... 33 Changes to Digital Outputs, Timing, and Controls Section and Table 15 ............................................................................................. 34 Changes to Table 16 and Table 17 ................................................. 35 Added Table 18 ................................................................................ 36 Added Multichip Synchronization Using SYSREF± Timestamp, Six Lane Output Mode, and SYSREF± Setup and Hold IRQ Sections ............................................................................................. 39 Added IRQ Guardband Delays (SYSREF± Setup and Hold) Section .............................................................................................. 40 Added Using Rising/Falling Edges of CLK to Latch SYSREF± Section .............................................................................................. 41 Changes to Configuration Using the SPI Section ....................... 46 Changes to Transfer Register Map Section, Table 26, and Table 27 ............................................................................................. 47 Changes to Table 28, Table 29, and Table 30 ............................... 48 Changes to Table 33 and Table 34 ................................................. 49 Changes to Table 53 ........................................................................ 52 Changes to Table 54 ........................................................................ 52 Changes to Table 58 ........................................................................ 54 Changes to Table 71 ........................................................................ 56 Changes to Table 79 and Table 80 ................................................. 57 Changes to Table 81, Table 82, Table 83, Table 84, Table 85, and Table 86 ............................................................................................. 58 Changes to Table 89 ........................................................................ 59 Changes to Table 92 and Table 93 ................................................. 60 Changes to Table 94, Table 97, and Table 98 ............................... 61 Changes to Table 101 and Table 106 ............................................. 62 Added Table 107 and Table 108..................................................... 63 Added Table 115 and Table 116..................................................... 64 Added Applications Information Section .................................... 65 Changes to Ordering Guide ........................................................... 66 5/2014—Revision 0: Initial Version Rev. C | Page 3 of 72 AD9625 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD1 = DVDD1 = DRVDD1 = 1.3 V, AVDD2 = DVDD2 = DRVDD2 = 2.5 V, specified maximum sampling rate, 1.2 V internal reference, AIN = −1.0 dBFS, default SPI settings, dc-coupled output data, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) ANALOG INPUTS Differential Input Voltage Range Resistance Capacitance Internal Common-Mode Voltage (VCM) Analog Full-Power Bandwidth2 Input Referred Noise POWER SUPPLIES AVDD1 AVDD2 DRVDD1 DRVDD2 DVDD1 DVDD2 DVDDIO SPI_VDDIO IAVDD1 IAVDD2 IDRVDD1 IDRVDD2 IDVDD1 IDVDD2 IDVDDIO ISPI_VDDIO Power Dissipation Power-Down Dissipation 1 2 Test Conditions/ Comments Internal VREF = 1.2 V Internal termination Eight lane mode Temperature1 AD9625-2.0 Min Typ Max 12 Full Full Full Full −7 −8 −0.7 Full −3.6 ±0.9 492 1.1 100 1.5 525 Full 25°C 25°C Full 25°C 25°C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Guaranteed ±0.5 +6.4 +8 ±0.3 +0.7 +3.6 563 Min 12 1.3 2.5 1.3 2.5 1.3 2.5 2.5 2.5 1120 383 456 9 410