11-Bit, 105 MSPS/150 MSPS, 1.8 V
Dual Analog-to-Digital Converter
AD9627-11
FUNCTIONAL BLOCK DIAGRAM
B
SO
APPLICATIONS
O
Communications
Diversity radio systems
Multimode digital receivers (3G)
GSM, EDGE, WCDMA, CDMA2000,
WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Broadband data applications
SDIO/ SCLK/
DCS DFS CSB
FD(0:3)A
FD BITS/THRESHOLD
DETECT
DRVDD
SPI
PROGRAMMING DATA
VIN+A
SHA
ADC
VIN–A
TE
SIGNAL
MONITOR
SENSE
CML
DIVIDE
1 TO 8
REF
SELECT
VIN–B
SHA
ADC
VIN+B
SIGNAL MONITOR
DATA
AD9627-11
MULTICHIP
SYNC
AGND
SYNC
FD BITS/THRESHOLD
DETECT
FD(0:3)B
CLK–
DCO
GENERATION
DUTY CYCLE
STABILIZER
RBIAS
D0A
CLK+
CMOS
OUTPUT BUFFER
VREF
D10A
DCOA
DCOB
D10B
D0B
SIGNAL MONITOR
INTERFACE
SMI
SMI
SMI DRGND
SDFS SCLK/ SDO/
PDWN OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
07054-001
AVDD DVDD
LE
SNR = 65.8 dBc (66.8 dBFS) to 70 MHz @ 105 MSPS
SFDR = 85 dBc to 70 MHz @ 105 MSPS
Low power: 600 mW @ 105 MSPS
SNR = 65.7 dBc (66.7 dBFS) to 70 MHz @ 150 MSPS
SFDR = 84 dBc to 70 MHz @ 150 MSPS
Low power: 820 mW @ 150 MSPS
1.8 V analog supply operation
1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS
output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 450 MHz
Internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
Integrated receive features
Fast detect/threshold bits
Composite signal monitor
CMOS
OUTPUT BUFFER
FEATURES
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
Integrated dual, 11-bit, 105 MSPS/150 MSPS ADC.
Fast overrange detect and signal monitor with serial output.
Signal monitor block with dedicated serial output mode.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 450 MHz.
Operation from a single 1.8 V supply and a separate digital
output driver supply to accommodate 1.8 V to 3.3 V logic
families.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
Pin compatibility with the AD9640, AD9627, and AD9600
for a simple migration from 11 bits to 14 bits, 12 bits, or
10 bits.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.
AD9627-11
TABLE OF CONTENTS
RMS/MS Magnitude Mode ....................................................... 33
Applications ....................................................................................... 1
Threshold Crossing Mode ......................................................... 34
Functional Block Diagram .............................................................. 1
Additional Control Bits ............................................................. 34
Product Highlights ........................................................................... 1
DC Correction ............................................................................ 34
Revision History ............................................................................... 3
Signal Monitor SPORT Output ................................................ 35
General Description ......................................................................... 4
Built-In Self-Test (BIST) and Output Test .................................. 36
Specifications..................................................................................... 5
Built-In Self-Test (BIST) ............................................................ 36
ADC DC Specifications—AD9627-11-105/AD9627-11-150. 5
Output Test Modes ..................................................................... 36
ADC AC Specifications—AD9627-11-105/AD9627-11-150 . 6
Channel/Chip Synchronization .................................................... 37
Digital Specifications ................................................................... 7
Serial Port Interface (SPI) .............................................................. 38
Switching Specifications—AD9627-11-105/AD9627-11-150 9
Configuration Using the SPI ..................................................... 38
Timing Specifications ................................................................ 10
Hardware Interface..................................................................... 38
Absolute Maximum Ratings.......................................................... 12
Configuration Without the SPI ................................................ 39
Thermal Characteristics ............................................................ 12
SPI Accessible Features .............................................................. 39
LE
TE
Features .............................................................................................. 1
Memory Map .................................................................................. 40
Pin Configurations and Function Descriptions ......................... 13
Reading the Memory Map Register Table............................... 40
Equivalent Circuits ......................................................................... 17
Memory Map Register Table ..................................................... 41
Typical Performance Characteristics ........................................... 18
Memory Map Register Descriptions ........................................ 44
Theory of Operation ...................................................................... 23
Applications Information .............................................................. 47
B
SO
ESD Caution ................................................................................ 12
Design Guidelines ...................................................................... 47
Analog Input Considerations.................................................... 23
Evaluation Board ............................................................................ 48
Voltage Reference ....................................................................... 25
Power Supplies ............................................................................ 48
Clock Input Considerations ...................................................... 26
Input Signals................................................................................ 48
Power Dissipation and Standby Mode ..................................... 28
Output Signals ............................................................................ 48
Digital Outputs ........................................................................... 28
Default Operation and Jumper Selection Settings ................. 49
Timing .......................................................................................... 29
Alternative Clock Configurations ............................................ 49
ADC Overrange and Gain Control .............................................. 30
Alternative Analog Input Drive Configuration...................... 50
Fast Detect Overview ................................................................. 30
Schematics ................................................................................... 51
ADC Fast Magnitude ................................................................. 30
Evaluation Board Layouts ......................................................... 61
ADC Overrange (OR) ................................................................ 31
Bill of Materials ........................................................................... 69
Gain Switching ............................................................................ 31
Outline Dimensions ....................................................................... 71
Signal Monitor ................................................................................ 33
Ordering Guide .......................................................................... 71
O
ADC Architecture ...................................................................... 23
Peak Detector Mode ................................................................... 33
Rev. B | Page 2 of 72
AD9627-11
REVISION HISTORY
O
B
SO
10/07—Revision 0: Initial Version
LE
9/09—Rev. 0 to Rev. A
Changes to Table 4 ............................................................................ 9
Changes to Figure 3.........................................................................11
Changes to Figure 11, Figure 12, and Figure 14 ..........................17
Changes to Table 12 ........................................................................29
Changes to Configuration Using the SPI Section .......................38
Change to Table 22 ..........................................................................43
Change to Signal Monitor Period (Register 0x113
to Register 0x115) Section..............................................................46
Updated Outline Dimensions ........................................................71
TE
5/10—Rev. A to Rev. B
Deleted CP-64-3 Package .................................................. Universal
Added CP-64-6 Package .................................................... Universal
Changed AD9627BCPZ11-150 to AD9627-11-150 and
AD9627BCPZ11-105 to AD9627-11-105 Throughout................ 5
Changes to Figure 6.........................................................................13
Changes to Figure 7.........................................................................15
Updated Outline Dimensions ........................................................71
Changes to Ordering Guide ...........................................................71
Rev. B | Page 3 of 72
AD9627-11
GENERAL DESCRIPTION
The AD9627-11 is a dual, 11-bit, 105 MSPS/150 MSPS analog-todigital converter (ADC). The AD9627-11 is designed to support
communications applications where low cost, small size, and
versatility are desired.
the programmable threshold, the coarse upper threshold indicator
goes high. Because this threshold indicator has very low latency,
the user can quickly turn down the system gain to avoid an overrange condition.
The dual ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth differential sample-and-hold analog
input amplifiers supporting a variety of user-selectable input
ranges. An integrated voltage reference eases design considerations.
A duty cycle stabilizer is provided to compensate for variations
in the ADC clock duty cycle, allowing the converters to maintain
excellent performance.
The second AGC-related function is the signal monitor. This block
allows the user to monitor the composite magnitude of the
incoming signal, which aids in setting the gain to optimize the
dynamic range of the overall system.
Flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-bit
SPI-compatible serial interface.
The AD9627-11 is available in a 64-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C.
O
B
SO
LE
In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits
of the ADC with very low latency. If the input signal level exceeds
TE
The AD9627-11 has several functions that simplify the automatic
gain control (AGC) function in the system receiver. The fast detect
feature allows fast overrange detection by outputting four bits of
input level information with very short latency.
The ADC output data can be routed directly to the two external
11-bit output ports. These outputs can be set from 1.8 V to 3.3 V
CMOS or 1.8 V LVDS.
Rev. B | Page 4 of 72
AD9627-11
SPECIFICATIONS
ADC DC SPECIFICATIONS—AD9627-11-105/AD9627-11-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 1.
25°C
25°C
Full
Full
Full
25°C
−3.6
AD9627-11-105
Typ
Max
Guaranteed
±0.3
±0.7
−2.2
−1.0
±0.3
±0.1
±0.5
±0.2
±0.3
±0.2
O
Min
11
−4.3
±0.7
±0.75
±15
±95
±5
7
B
SO
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance2
VREF INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD, DVDD
DRVDD (CMOS Mode)
DRVDD (LVDS Mode)
Supply Current
IAVDD1, 3
IDVDD1, 3
IDRVDD1 (3.3 V CMOS)
IDRVDD1 (1.8 V CMOS)
IDRVDD1 (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Sine Wave Input1 (DRVDD = 1.8 V)
Sine Wave Input1 (DRVDD = 3.3 V)
Standby Power4
Power-Down Power
Full
Full
Full
Full
25°C
Full
25°C
Min
11
AD9627-11-150
Typ
Max
±16
Unit
Bits
Guaranteed
±0.2
±0.6
−3.0
−1.7
±0.4
±0.1
±0.7
±0.3
% FSR
% FSR
LSB
LSB
LSB
LSB
±0.2
±0.2
% FSR
% FSR
TE
Integral Nonlinearity (INL)1
Temperature
Full
LE
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
±0.7
±0.7
±15
±95
±5
7
ppm/°C
ppm/°C
±16
mV
mV
25°C
0.15
0.15
LSB rms
Full
Full
Full
2
8
6
2
8
6
V p-p
pF
kΩ
Full
Full
Full
1.7
1.7
1.7
1.8
3.3
1.8
Full
Full
Full
Full
Full
310
34
34
16
44
Full
Full
Full
Full
Full
600
645
730
68
2.5
1
1.9
3.6
1.9
365
650
6
1.7
1.7
1.7
1.8
3.3
1.8
419
50
42
29
46
820
895
1000
77
2.5
1.9
3.6
1.9
495
890
6
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure.
3
The maximum limit applies to the combination of IAVDD and IDVDD currents.
4
Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
2
Rev. B | Page 5 of 72
V
V
V
mA
mA
mA
mA
mA
mW
mW
mW
mW
mW
AD9627-11
ADC AC SPECIFICATIONS—AD9627-11-105/AD9627-11-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect output pins disabled, and signal monitor disabled, unless otherwise noted.
Table 2.
25°C
25°C
Full
25°C
25°C
fIN = 140 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.3 MHz
fIN = 70 MHz
O
fIN = 140 MHz
fIN = 220 MHz
WORST OTHER HARMONIC OR SPUR
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 29.1 MHz, 32.1 MHz (−7 dBFS )
fIN = 169.1 MHz, 172.1 MHz (−7 dBFS )
CROSSTALK2
ANALOG INPUT BANDWIDTH
1
2
AD9627-11-105
Typ
Max
Min
AD9627-11-150
Typ
Max
65.9
65.8
65.8
65.7
65.3
65.5
65.2
65.9
65.7
65.7
65.6
64.9
65.4
65.1
dB
dB
dB
dB
dB
64.4
65.5
65.1
Unit
dB
dB
dB
dB
dB
65.0
65.6
65.2
25°C
25°C
25°C
25°C
10.8
10.8
10.8
10.7
10.8
10.8
10.7
10.7
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
−87
−85
−86.5
−84
−84
−83
−83.5
−77
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
87
85
86.5
84
B
SO
fIN = 140 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.3 MHz
fIN = 70 MHz
fIN = 140 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.3 MHz
fIN = 70 MHz
25°C
25°C
Full
25°C
25°C
Min
TE
fIN = 140 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.3 MHz
fIN = 70 MHz
Temperature
LE
Parameter1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.3 MHz
fIN = 70 MHz
−73
73
−72
dBc
dBc
dBc
dBc
dBc
72
84
83
83.5
77
25°C
25°C
Full
25°C
25°C
−92
−88
−92
−88
−86
−86
−86
−86
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
85
82
−95
650
85
82
−95
650
dBc
dBc
dB
MHz
−82
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1 dBFS on one channel and with no input on the alternate channel.
Rev. B | Page 6 of 72
−80
AD9627-11
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 3.
Min
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
1.2
0.2
6
GND − 0.3
AVDD + 1.6
1.1
AVDD
1.2
3.6
0
0.8
−10
+10
−10
+10
4
8
10
12
Full
Full
Full
Full
Full
Full
Full
Full
B
SO
O
Typ
Max
TE
Temperature
LE
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK/DFS)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 3.3 V)
Low Level Input Current
GND − 0.3
1.2
0
−10
−10
8
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
Full
Full
Full
Full
1.22
0
−90
−10
Rev. B | Page 7 of 72
CMOS
1.2
AVDD + 1.6
3.6
0.8
+10
+10
4
10
12
Unit
V
V p-p
V
V
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
3.6
0.6
+10
132
V
V
μA
μA
kΩ
pF
3.6
0.6
−135
+10
V
V
μA
μA
kΩ
pF
3.6
0.6
+10
128
V
V
μA
μA
kΩ
pF
3.6
0.6
−134
+10
V
V
μA
μA
26
2
26
2
26
5
AD9627-11
Full
Full
3.29
3.25
Pull up.
Pull down.
Typ
26
5
Full
Full
Full
Full
Full
Full
0.2
0.05
TE
Full
Full
Rev. B | Page 8 of 72
Max
1.79
1.75
250
1.15
150
1.15
Unit
kΩ
pF
V
V
Full
Full
B
SO
2
Min
O
1
Temperature
Full
Full
LE
Parameter
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 3.3 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = 50 μA
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 μA
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD), ANSI Mode
Output Offset Voltage (VOS), ANSI Mode
Differential Output Voltage (VOD), Reduced Swing Mode
Output Offset Voltage (VOS), Reduced Swing Mode
350
1.25
200
1.25
V
V
V
V
0.2
0.05
V
V
450
1.35
280
1.35
mV
V
mV
V
AD9627-11
SWITCHING SPECIFICATIONS—AD9627-11-105/AD9627-11-150
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and
DCS enabled, unless otherwise noted.
Table 4.
Temperature
Min
AD9627-11-105
Typ
Max
Full
Full
Full
Full
Full
2.85
4.28
1.6
0.8
Full
Full
Full
Full
O
1
2
3
Full
Full
Full
Full
Full
Full
Full
AD9627-11-150
Typ
Max
105
105
4.75
4.75
6.65
5.23
MHz
150
150
MSPS
MSPS
ns
3.33
3.33
4.66
3.66
ns
ns
ns
ns
20
10
6.66
2.0
3.0
1.6
0.8
Unit
625
TE
20
10
9.5
LE
Full
Full
Full
Full
Full
Full
Full
Min
625
2.2
3.8
4.5
5.0
5.25
4.25
6.4
6.8
2.2
3.8
4.5
5.0
3.83
2.83
6.4
6.8
ns
ns
ns
ns
2.4
4.0
5.2
5.6
5.15
4.35
6.9
7.3
2.4
4.0
5.2
5.6
3.73
2.93
6.9
7.3
ns
ns
ns
ns
3.0
5.2
3.7
6.4
12
12/12.5
4.4
7.6
3.0
4.8
3.8
5.9
12
12/12.5
4.5
7.3
ns
ns
Cycles
Cycles
B
SO
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate
DCS Enabled1
DCS Disabled1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode, DCS Enabled
Divide-by-3 Mode Through Divide-by8 Mode, DCS Enabled
DATA OUTPUT PARAMETERS (DATA, FD)
CMOS Mode—DRVDD = 3.3 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
CMOS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
LVDS Mode—DRVDD = 1.8 V
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency)
Channel A/Channel B
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY TIME
1.0
0.1
350
2
Conversion rate is the clock rate after the divider.
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors.
Rev. B | Page 9 of 72
1.0
0.1
350
3
ns
ps rms
μs
Cycles
AD9627-11
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Test Conditions/Comments
Min
Typ
SYNC to rising edge of CLK setup time
SYNC to rising edge of CLK hold time
Unit
ns
ns
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
Delay from rising edge of CLK+ to rising edge of SMI SCLK
Delay from rising edge of SMI SCLK to SMI SDO
Delay from rising edge of SMI SCLK to SMI SDFS
3.2
−0.4
−0.4
TE
SPORT TIMING REQUIREMENTS
tCSSCLK
tSSCLKSDO
tSSCLKSDFS
0.24
0.40
LE
tDIS_SDIO
Max
B
SO
Timing Diagrams
4.5
0
0
N+2
N+1
N+3
N
N+4
tA
N+8
N+5
N+6
N+7
tCLK
CLK+
CLK–
N – 13
N – 12
N – 11
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
CH A/CH B FAST
DETECT
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
O
CH A/CH B DATA
tS
tH
tDCO
tCLK
DCOA/DCOB
Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
Rev. B | Page 10 of 72
07054-002
tPD
6.2
0.4
0.4
ns
ns
ns
AD9627-11
N+1
N+2
N+3
N
N+4
N+8
tA
N+5
N+6
N+7
tCLK
CLK+
CLK–
tPD
A
CH A/CH B FAST
DETECT
A
B
N – 13
B
N–7
A
B
N – 12
A
B
N–6
A
B
N – 11
A
B
N–5
A
B
N – 10
A
B
N–4
A
B
N–9
A
B
A
B
N–8
A
B
A
B
A
N–7
A
B
B
A
N–6
A
B
B
N–5
A
B
A
N–4
A
TE
CH A/CH B DATA
N–3
N–2
tDCO
N
N+1
N+2
tCLK
07054-003
DCO+
N–1
DCO–
LE
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 001 Through Fast Detect Mode Select Bits = 100)
tSSYNC
B
SO
SYNC
tHSYNC
07054-004
CLK+
Figure 4. SYNC Input Timing Requirements
CLK+
CLK–
tCSSCLK
SMI SCLK
tSSCLKSDO
O
tSSCLKSDFS
SMI SDO
DATA
Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode)
Rev. B | Page 11 of 72
DATA
07054-005
SMI SDFS
AD9627-11
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Rating
Table 7. Thermal Resistance
Package Type
64-Lead LFCSP
9 mm × 9 mm
(CP-64-6)
1
Airflow
Velocity
(m/s)
0
1.0
2.0
−0.3 V to DRVDD + 0.3 V
θJA1, 2
18.8
16.5
15.8
θJC1, 3
0.6
θJB1, 4
6.0
Unit
°C/W
°C/W
°C/W
Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown, airflow improves heat dissipation, which
reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θJA.
LE
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the customer
board increases the reliability of the solder joints and maximizes
the thermal capability of the package.
ESD CAUTION
−0.3 V to DRVDD + 0.3 V
B
SO
Parameter
ELECTRICAL
AVDD, DVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
CML to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to DRGND
SDIO/DCS to DRGND
SMI SDO/OEB
SMI SCLK/PDWN
SMI SDFS
D0A/D0B through D10A/D10B to
DRGND
FD0A/FD0B through FD3A/FD3B to
DRGND
DCOA/DCOB to DRGND
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
TE
Table 6.
−40°C to +85°C
150°C
−65°C to +150°C
O
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 12 of 72
AD9627-11
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
D2B
D1B
D0B (LSB)
DNC
DNC
DNC
DVDD
FD3B
FD2B
FD1B
FD0B
SYNC
CSB
CLK–
CLK+
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9627-11
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
TE
PARALLEL CMOS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
07054-006
LE
D2A
D3A
D4A
DRGND
DRVDD
D5A
D6A
DVDD
D7A
D8A
D9A
D10A (MSB)
FD0A
FD1A
FD2A
FD3A
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
D3B
D4B
D5B
D6B
D7B
D8B
D9B
D10B (MSB)
DCOB
DCOA
DNC
DNC
DNC
D0A (LSB)
D1A
Figure 6. LFCSP Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Type
Description
O
B
SO
Pin No.
Mnemonic
ADC Power Supplies
20, 64
DRGND
1, 21
DRVDD
24, 57
DVDD
36, 45, 46
AVDD
0
AGND
12 to 14, 58 to 60 DNC
ADC Analog
37
VIN+A
38
VIN−A
44
VIN+B
43
VIN−B
39
VREF
40
SENSE
42
RBIAS
41
CML
49
CLK+
50
CLK−
ADC Fast Detect Outputs
29
FD0A
30
FD1A
31
FD2A
32
FD3A
53
FD0B
54
FD1B
55
FD2B
56
FD3B
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Do Not Connect.
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Output
Output
Output
Output
Output
Output
Output
Output
Channel A Fast Detect Indicator. See Table 14 for details.
Channel A Fast Detect Indicator. See Table 14 for details.
Channel A Fast Detect Indicator. See Table 14 for details.
Channel A Fast Detect Indicator. See Table 14 for details.
Channel B Fast Detect Indicator. See Table 14 for details.
Channel B Fast Detect Indicator. See Table 14 for details.
Channel B Fast Detect Indicator. See Table 14 for details.
Channel B Fast Detect Indicator. See Table 14 for details.
Rev. B | Page 13 of 72
AD9627-11
Description
Input
Digital Synchronization Pin. Slave mode only.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel A CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel B CMOS Output Data.
Channel A Data Clock Output.
Channel B Data Clock Output.
Input
Input/Output
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
Input/Output
Output
Input/Output
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
LE
TE
Type
O
B
SO
Pin No.
Mnemonic
Digital Input
52
SYNC
Digital Outputs
15
D0A (LSB)
16
D1A
17
D2A
18
D3A
19
D4A
22
D5A
23
D6A
25
D7A
26
D8A
27
D9A
28
D10A (MSB)
61
D0B (LSB)
62
D1B
63
D2B
2
D3B
3
D4B
4
D5B
5
D6B
6
D7B
7
D8B
8
D9B
9
D10B (MSB)
11
DCOA
10
DCOB
SPI Control
48
SCLK/DFS
47
SDIO/DCS
51
CSB
Signal Monitor Port
33
SMI SDO/OEB
35
SMI SDFS
34
SMI SCLK/PDWN
Rev. B | Page 14 of 72
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
DRGND
DNC
DNC
FD3+
FD3–
FD2+
FD2–
DVDD
FD1+
FD1–
FD0+
FD0–
SYNC
CSB
CLK–
CLK+
AD9627-11
PIN 1
INDICATOR
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
AD9627-11
PARALLEL LVDS
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN+B
VIN–B
RBIAS
CML
SENSE
VREF
VIN–A
VIN+A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
TE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LE
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.
07054-007
D4+
D5–
D5+
DRGND
DRVDD
D6–
D6+
DVDD
D7–
D7+
D8–
D8+
D9–
D9+
D10– (MSB)
D10+ (MSB)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DRVDD
DNC
DNC
DNC
DNC
D0– (LSB)
D0+ (LSB)
D1–
D1+
DCO–
DCO+
D2–
D2+
D3–
D3+
D4–
Figure 7. LFCSP Interleaved Parallel LVDS Pin Configuration (Top View)
Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Type
Description
Ground
Supply
Supply
Supply
Ground
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Digital Power Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
Do Not Connect.
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Voltage Reference Mode Select. See Table 11 for details.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 14 for details.
Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 14 for details.
Input
Digital Synchronization Pin. Slave mode only.
O
B
SO
Pin No.
Mnemonic
ADC Power Supplies
20, 64
DRGND
1, 21
DRVDD
24, 57
DVDD
36, 45, 46 AVDD
0
AGND
2, 3, 4, 5, DNC
62, 63
ADC Analog
37
VIN+A
38
VIN−A
44
VIN+B
43
VIN−B
39
VREF
40
SENSE
42
RBIAS
41
CML
49
CLK+
50
CLK−
ADC Fast Detect Outputs
54
FD0+
53
FD0−
56
FD1+
55
FD1−
59
FD2+
58
FD2−
61
FD3+
60
FD3−
Digital Input
52
SYNC
Rev. B | Page 15 of 72
AD9627-11
Description
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0—True.
Channel A/Channel B LVDS Output Data 0—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3 —True.
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
LE
TE
Type
B
SO
Pin No.
Mnemonic
Digital Outputs
7
D0+ (LSB)
6
D0− (LSB)
9
D1+
8
D1−
13
D2+
12
D2−
15
D3+
14
D3−
17
D4+
16
D4−
19
D5+
18
D5−
23
D6+
22
D6−
26
D7+
25
D7−
28
D8+
27
D8−
30
D9+
29
D9−
32
D10+ (MSB)
31
D10− (MSB)
11
DCO+
10
DCO−
SPI Control
48
SCLK/DFS
47
SDIO/DCS
51
CSB
Signal Monitor Port
33
SMI SDO/OEB
35
SMI SDFS
34
SMI SCLK/PDWN
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
SPI Chip Select (Active Low).
Input/Output
Output
Input/Output
Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode.
Signal Monitor Serial Data Frame Sync.
Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode.
O
Input
Input/Output
Input
Rev. B | Page 16 of 72
AD9627-11
EQUIVALENT CIRCUITS
DVDD
VIN
1kΩ
SCLK/DFS
07054-012
07054-008
26kΩ
Figure 8. Equivalent Analog Input Circuit
Figure 12. Equivalent SCLK/DFS Input Circuit
TE
AVDD
1kΩ
1.2V
10kΩ
CLK+
Figure 9. Equivalent Clock Input Circuit
Figure 13. Equivalent SENSE Circuit
CSB
DVDD
26kΩ
DVDD
1kΩ
07054-010
B
SO
DRVDD
LE
07054-009
CLK–
07054-014
10kΩ
07054-013
SENSE
DRGND
Figure 10. Digital Output
Figure 14. Equivalent CSB Input Circuit
O
DRVDD
AVDD
DVDD
26kΩ
DVDD
VREF
1kΩ
SDIO/DCS
6kΩ
07054-011
07054-015
DRVDD
Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit
Figure 15. Equivalent VREF Circuit
Rev. B | Page 17 of 72
AD9627-11
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1.0 V internal reference, 2 V p-p differential
input, VIN = −1.0 dBFS; and 64k sample, TA = 25°C, unless otherwise noted.
0
0
150MSPS
2.3MHz @ –1dBFS
SNR = 65.8dB (66.8dBFS)
ENOB = 10.8 BITS
SFDR = 86.5dBc
–20
–40
–60
SECOND
HARMONIC
THIRD
HARMONIC
–80
–80
THIRD
HARMONIC
SECOND
HARMONIC
–100
0
10
20
30
40
50
60
–120
07054-016
–120
70
FREQUENCY (MHz)
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 19. AD9627-11-150 Single-Tone FFT with fIN = 140 MHz
LE
Figure 16. AD9627-11-150 Single-Tone FFT with fIN = 2.3 MHz
0
150MSPS
30.3MHz @ –1dBFS
SNR = 65.7dB (66.7dBFS)
ENOB = 10.8 BITS
SFDR = 85.7dBc
THIRD
HARMONIC
–80
–100
–120
0
10
20
30
40
50
SECOND
HARMONIC
60
70
FREQUENCY (MHz)
O
THIRD
HARMONIC
–80
20
30
40
50
60
70
Figure 20. AD9627-11-150 Single-Tone FFT with fIN = 220 MHz
0
AMPLITUDE (dBFS)
–60
10
FREQUENCY (MHz)
150MSPS
337MHz @ –1dBFS
SNR = 64.6dB (65.4dBFS)
ENOB = 10.6 BITS
SFDR = 76.0dBc
–20
–40
THIRD
HARMONIC
SECOND
HARMONIC
–80
0
150MSPS
70MHz @ –1dBFS
SNR = 65.7dB (66.7dBFS)
ENOB = 10.8 BITS
SFDR = 84.0dBc
–20
–60
–120
Figure 17. AD9627-11-150 Single-Tone FFT with fIN = 30.3 MHz
0
–40
–100
07054-017
–60
B
SO
–40
–20
AMPLITUDE (dBFS)
–20
150MSPS
220MHz @ –1dBFS
SNR = 65.2dB (66.2dBFS)
ENOB = 10.7 BITS
SFDR = 79.0dBc
07054-020
0
–40
–60
THIRD
HARMONIC
SECOND
HARMONIC
–80
SECOND
HARMONIC
–100
–120
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
07054-018
–100
Figure 18. AD9627-11-150 Single-Tone FFT with fIN = 70 MHz
–120
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 21. AD9627-11-150 Single-Tone FFT with fIN = 337 MHz
Rev. B | Page 18 of 72
07054-021
AMPLITUDE (dBFS)
–60
07054-019
–100
AMPLITUDE (dBFS)
–40
TE
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
150MSPS
140MHz @ –1dBFS
SNR = 65.5dB (66.5dBFS)
ENOB = 10.7 BITS
SFDR = 84.1dBc
AD9627-11
0
0
150MSPS
440MHz @ –1dBFS
SNR = 63.8dB (64.5dBFS)
ENOB = 10.2 BITS
SFDR = 71.0dBc
–20
AMPLITUDE (dBFS)
–40
SECOND
HARMONIC
–60
THIRD
HARMONIC
–80
–80
10
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 22. AD9627-11-150 Single-Tone FFT with fIN = 440 MHz
–120
0
10
20
30
40
50
FREQUENCY (MHz)
07054-025
0
Figure 25. AD9627-11-105 Single-Tone FFT with fIN = 72 MHz
0
105MSPS
2.3MHz @ –1dBFS
SNR = 65.9dB (66.9dBFS)
ENOB = 10.8 BITS
SFDR = 89.0dBc
AMPLITUDE (dBFS)
–40
–60
SECOND
HARMONIC
–100
–120
0
B
SO
THIRD
HARMONIC
10
20
30
40
50
FREQUENCY (MHz)
–60
THIRD
HARMONIC
–80
SECOND
HARMONIC
10
20
30
40
50
FREQUENCY (MHz)
Figure 26. AD9627-11-105 Single-Tone FFT with fIN = 141 MHz
0
105MSPS
337MHz @ –1dBFS
SNR = 64.5dB (65.5dBFS)
ENOB = 10.6 BITS
SFDR = 79.0dBc
–20
AMPLITUDE (dBFS)
O
–40
THIRD
HARMONIC
–80
0
105MSPS
30.3MHz @ –1dBFS
SNR = 65.8dB (66.8dBFS)
ENOB = 10.8 BITS
SFDR = 86dBc
–20
–60
–120
Figure 23. AD9627-11-105 Single-Tone FFT with fIN = 2.3 MHz
0
–40
–100
07054-023
–80
–20
LE
–20
105MSPS
141MHz @ –1dBFS
SNR = 65.6dB (66.6dBFS)
ENOB = 10.8 BITS
SFDR = 83dBc
07054-026
0
AMPLITUDE (dBFS)
SECOND
HARMONIC
THIRD
HARMONIC
TE
–120
–40
–60
THIRD
HARMONIC
SECOND
HARMONIC
–80
SECOND
HARMONIC
–100
–100
–120
0
10
20
30
40
50
FREQUENCY (MHz)
07054-024
AMPLITUDE (dBFS)
–60
–100
07054-022
–100
–40
Figure 24. AD9627-11-105 Single-Tone FFT with fIN = 30.3 MHz
–120
0
10
20
30
40
50
FREQUENCY (MHz)
Figure 27. AD9627-11-105 Single-Tone FFT with fIN = 337 MHz
Rev. B | Page 19 of 72
07054-027
AMPLITUDE (dBFS)
–20
105MSPS
72MHz @ –1dBFS
SNR = 65.8dB (66.8dBFS)
ENOB = 10.8 BITS
SFDR = 85dBc
AD9627-11
120
95
SFDR = +85°C
90
85
SFDR (dBFS)
80
SNR (dBFS)
40
SFDR = –40°C
75
70
65
85dB REFERENCE LINE
20
SNR = +25°C
SNR = +85°C
SNR = –40°C
60
SNR (dBc)
–70
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
55
0
250
300
350
400
40
SFDR (dBc)
450
0.5
–2.5
0.4
LE
GAIN ERROR (%FSR)
SNR (dBFS)
–3.0
0.3
GAIN
–3.5
0.2
OFFSET
85dB REFERENCE LINE
B
SO
SNR/SFDR (dBc AND dBFS)
200
–2.0
SFDR (dBFS)
20
150
Figure 31. AD9627-11-150 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) and Temperature with 1 V p-p Full Scale
100
60
100
INPUT FREQUENCY (MHz)
Figure 28. AD9627-11-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 2.4 MHz
80
50
TE
–80
07054-028
0
–90
07054-031
SFDR (dBc)
80
–4.0
OFFSET ERROR (%FSR)
60
SFDR = +25°C
SNR/SFDR (dBc)
SNR/SFDR (dBc AND dBFS)
100
0.1
–60
–50
–40
–30
–20
–10
0
INPUT AMPLITUDE (dBFS)
–4.5
–40
90
SFDR = –40°C
75
70
65
100
150
200
250
SFDR (dBc)
IMD3 (dBc)
–40
–60
SFDR (dBFS)
–80
IMD3 (dBFS)
300
350
400
450
INPUT FREQUENCY (MHz)
Figure 30. AD9627-11-150 Single-Tone SNR/SFDR vs.
Input Frequency (fIN) and Temperature with 2 V p-p Full Scale
–120
–90
07054-030
50
80
–100
55
0
60
–20
SNR = +25°C
SNR = +85°C
SNR = –40°C
60
40
0
SFDR/IMD3 (dBc AND dBFS)
O
SNR/SFDR (dBc)
SFDR = +25°C
80
20
Figure 32. AD9627-11-150 Gain and Offset vs. Temperature
SFDR = +85°C
85
0
TEMPERATURE (°C)
Figure 29. AD9627-11-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 98.12 MHz
95
0
–20
07054-032
–70
–78
–66
–54
–42
–30
INPUT AMPLITUDE (dBFS)
–18
–6
07054-033
–80
07054-029
SNR (dBc)
0
–90
Figure 33. AD9627-11-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 150 MSPS
Rev. B | Page 20 of 72
AD9627-11
0
0
–20
SFDR (dBc)
AMPLITUDE (dBFS)
SFDR/IMD3 (dBc AND dBFS)
–20
150MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
SFDR = 83.8dBc (90.8dBFS)
–40
IMD3 (dBc)
–60
SFDR (dBFS)
–80
–100
–40
–60
–80
–100
–66
–54
–42
–30
–18
–6
INPUT AMPLITUDE (dBFS)
Figure 34. AD9627-11-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS
0
0
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 37. AD9627-11-150 Two-Tone FFT with fIN1 = 169.1 MHz and
fIN2 = 172.1 MHz
NPR = 58.4dBc
NOTCH @ 18.5MHz
NOTCH WIDTH = 3MHz
AMPLITUDE (dBFS)
LE
–20
0
15.36
30.72
46.08
61.44
FREQUENCY (MHz)
–80
–100
–120
07054-035
–120
B
SO
–80
–60
0
–60
–80
20
30
40
50
60
70
FREQUENCY (MHz)
Figure 36. AD9627-11-150 Two-Tone FFT with fIN1 = 29.1 MHz
and fIN2 = 32.1 MHz
70
SFDR - SIDE A
80
SNR - SIDE B
70
SNR - SIDE A
50
07054-036
10
60
90
60
0
50
SFDR - SIDE B
–100
–120
40
100
SNR/SFDR (dBc)
O
–40
30
Figure 38. AD9627-11 Noise Power Ratio (NPR)
150MSPS
29.1MHz @ –7dBFS
32.1MHz @ –7dBFS
SFDR = 86.1dBc (93.1dBFS)
–20
20
FREQUENCY (MHz)
Figure 35. AD9627-11-150, Two 64k WCDMA Carriers
with fIN = 170 MHz, fS = 122.88 MSPS
0
10
07054-038
–60
–40
0
25
50
75
100
SAMPLE RATE (MSPS)
125
150
07054-039
–40
–100
AMPLITUDE (dBFS)
10
0
–20
AMPLITUDE (dBFS)
–120
07054-037
–78
TE
–120
–90
07054-034
IMD3 (dBFS)
Figure 39. AD9627-11-150 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 2.3 MHz
Rev. B | Page 21 of 72
AD9627-11
12
100
0.15 LSB rms
95
90
8
SNR/SFDR (dBc)
NUMBER OF HITS (1M)
10
6
4
SFDR DCS ON
85
80
SFDR DCS OFF
75
SNR DCS ON
70
2
65
N–1
N
N+1
N+2
N+3
OUTPUT CODE
40
60
DUTY CYCLE (%)
Figure 40. AD9627-11 Grounded Input Histogram
Figure 43. AD9627-11 SNR/SFDR vs. Duty Cycle with fIN = 10.3 MHz
0.2
95
SFDR
90
SNR/SFDR (dBc)
LE
85
0
80
75
70
0
256
512
768
1024
1280
1536
1792
2048
OUTPUT CODE
Figure 41. AD9627-11 INL with fIN = 10.3 MHz
0.15
0.10
O
0.05
0
–0.05
–0.15
0
256
512
768
1024
1280
1536
1792
OUTPUT CODE
2048
07054-042
–0.10
Figure 42. AD9627-11 DNL with fIN = 10.3 MHz
Rev. B | Page 22 of 72
SNR
65
60
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
INPUT COMMON-MODE VOLTAGE (V)
Figure 44. AD9627-11 SNR/SFDR vs. Input Common Mode (VCM)
with fIN = 30 MHz
07054-044
–0.2
B
SO
–0.1
07054-041
INL ERROR (LSB)
0.1
DNL ERROR (LSB)
80
TE
N–2
07054-040
N–3
60
20
07054-043
SNR DCS OFF
0
AD9627-11
THEORY OF OPERATION
Synchronization capability is provided to allow synchronized
timing between multiple channels or multiple devices.
Programming and control of the AD9627-11 are accomplished
using a 3-bit SPI-compatible serial interface.
B
SO
The AD9627-11 architecture consists of a dual front-end sampleand-hold amplifier (SHA), followed by a pipelined, switchedcapacitor ADC. The quantized outputs from each stage are
combined into a final 11-bit result in the digital correction logic.
The pipelined architecture permits the first stage to operate on
a new input sample and the remaining stages to operate on the
preceding samples. Sampling occurs on the rising edge of the clock.
O
The input stage of each channel contains a differential SHA that
can be ac- or dc-coupled in differential or single-ended modes.
The output staging block aligns the data, corrects errors, and passes
the data to the output buffers. The output buffers are powered from
a separate supply, allowing adjustment of the output voltage swing.
During power-down, the output buffers go into a high impedance
state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9627-11 is a differential switchedcapacitor SHA that has been designed for optimum performance
while processing a differential input signal.
The clock signal alternatively switches the SHA between sample
mode and hold mode (see Figure 45). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
CH
CS
VIN+
CPIN, PAR
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The residue amplifier magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage
simply consists of a flash ADC.
S
S
LE
ADC ARCHITECTURE
In intermediate frequency (IF) undersampling applications,
any shunt capacitors should be reduced. In combination with
the driving source impedance, the shunt capacitors limit the
input bandwidth. See Application Note AN-742, Frequency
Domain Response of Switched-Capacitor ADCs; Application
Note AN-827, A Resonant Approach to Interfacing Amplifiers
to Switched-Capacitor ADCs; and the Analog Dialogue article,
“Transformer-Coupled Front-End for Wideband A/D Converters,”
for more information on this subject.
S
H
CS
VIN–
CPIN, PAR
CH
S
07054-045
In nondiversity applications, the AD9627-11 can be used as a baseband or direct downconversion receiver, where one ADC is
used for I input data and the other is used for Q input data.
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
TE
The AD9627-11 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the
same carrier but from two separate antennae. The ADCs can also
be operated with independent analog inputs. The user can sample
any fS/2 frequency segment from dc to 200 MHz, using appropriate
low-pass or band-pass filtering at the ADC inputs with little loss
in ADC performance. Operation to 450 MHz analog input is
permitted but occurs at the expense of increased ADC noise and
distortion.
Figure 45. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched.
An internal differential reference buffer creates positive and
negative reference voltages that define the input span of the ADC
core. The span of the ADC core is set by this buffer to 2 ×
VREF.
Input Common Mode
The analog inputs of the AD9627-11 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.55 × AVDD
is recommended for optimum performance, but the device
functions over a wider range with reasonable performance
(see Figure 44). An on-board common-mode voltage reference
is included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Applications
Information section.
Differential Input Configurations
Optimum performance is achieved while driving the AD9627-11
in a differential input configuration. For baseband applications,
the AD8138, ADA4937-2, and ADA4938-2 differential drivers
provide excellent performance and a flexible interface to the ADC.
Rev. B | Page 23 of 72
AD9627-11
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use the AD8352 differential driver.
An example is shown in Figure 50. See the AD8352 data sheet
for more information.
The output common-mode voltage of the AD8138 is easily set
with the CML pin of the AD9627-11 (see Figure 46), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
499Ω
R
49.9Ω
VIN+
In any configuration, the value of Shunt Capacitor C is dependent
on the input frequency and source impedance and may need to
be reduced or removed. Table 10 displays recommended values to
set the RC network. However, these values are dependent on the
input signal and should be used only as a starting guide.
AVDD
499Ω
R
CML
VIN–
07054-046
523Ω
AD9627-11
C
AD8138
0.1µF
499Ω
Table 10. Example RC Network
Figure 46. Differential Input Configuration Using the AD8138
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 47. To bias the
analog input, the CML voltage can be connected to the center
tap of the secondary winding of the transformer.
VIN+
49.9Ω
C
Single-Ended Input Configuration
AD9627-11
R
A single-ended input can provide adequate performance in cost
sensitive applications. In this configuration, SFDR and distortion
performance degrade due to the large input common-mode swing.
If the source impedances on each input are matched, there should
be little effect on SNR performance. Figure 48 shows a typical
single-ended input configuration.
CML
07054-047
LE
VIN–
0.1µF
Figure 47. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
B
SO
0.1µF
AVDD
10µF
1kΩ
R
49.9Ω
1V p-p
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9627-11. For applications
where SNR is a key parameter, differential double balun coupling
is the recommended input configuration (see Figure 49).
0.1µF
0.1µF
AD9627-11
C
1kΩ
10µF
VIN+
1kΩ
AVDD
R
VIN–
1kΩ
Figure 48. Single-Ended Input Configuration
0.1µF
R
VIN+
2V p-p
25Ω
S
P
25Ω
0.1µF
AD9627-11
C
0.1µF
R
CML
VIN–
07054-049
S
O
PA
Figure 49. Differential Double Balun Input Configuration
VCC
0Ω
16
0.1µF
8, 13
1
11
0.1µF
CD
RD
RG
3
200Ω
AD8352
10
4
5
ANALOG INPUT
0.1µF
0Ω
R
VIN+
2
C
0.1µF
200Ω
R
AD9627-11
VIN–
CML
14
0.1µF
0.1µF
Figure 50. Differential Input Configuration Using the AD8352
Rev. B | Page 24 of 72
07054-050
0.1µF
ANALOG INPUT
C Differential (pF)
15
5
5
Open
TE
R
2V p-p
R Series
(Ω Each)
33
33
15
15
Frequency Range (MHz)
0 to 70
70 to 200
200 to 300
>300
07054-048
1V p-p
AD9627-11
A stable and accurate voltage reference is built into the
AD9627-11. The input range can be adjusted by varying the
reference voltage applied to the AD9627-11, using either the
internal reference or an externally applied reference voltage.
The input span of the ADC tracks reference voltage changes
linearly. The various reference modes are summarized in the
sections that follow. The Reference Decoupling section describes
the best practices PCB layout of the reference.
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
VIN+A/VIN+B
VIN–A/VIN–B
ADC
CORE
VREF
Internal Reference Connection
1.0µF
VIN–A/VIN–B
ADC
CORE
VREF
0.1µF
TE
R1
Figure 52. Programmable Reference Configuration
If the internal reference of the AD9627-11 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 53 shows
how the internal reference voltage is affected by loading.
0
SELECT
LOGIC
SENSE
07054-051
0.5V
AD9627-11
0.5V
AD9627-11
B
SO
1.0µF
SELECT
LOGIC
SENSE
REFERENCE VOLTAGE ERROR (%)
VIN+A/VIN+B
R2
LE
A comparator within the AD9627-11 detects the potential at the
SENSE pin and configures the reference into four possible
modes, which are summarized in Table 11. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 51), setting VREF to 1.0 V. Connecting
the SENSE pin to VREF switches the reference amplifier output
to the SENSE pin, completing the loop and providing a 0.5 V
reference output.
0.1µF
07054-052
VOLTAGE REFERENCE
VREF = 0.5V
–0.25
VREF = 1.0V
–0.50
–0.75
–1.00
–1.25
0
0.5
1.0
1.5
2.0
LOAD CURRENT (mA)
Figure 53. VREF Accuracy vs. Load
O
If a resistor divider is connected external to the chip, as shown
in Figure 52, the switch again sets to the SENSE pin. This puts
the reference amplifier in a noninverting mode with the VREF
output defined as follows:
R2
VREF 0.5 1
R1
Table 11. Reference Configuration Summary
Selected Mode
External Reference
SENSE Voltage
AVDD
Resulting VREF (V)
N/A
Resulting Differential Span (V p-p)
2 × external reference
Internal Fixed Reference
VREF
0.5
1.0
Programmable Reference
0.2 V to VREF
Internal Fixed Reference
AGND to 0.2 V
R2
0 .5 1
(see Figure 52)
R1
1.0
Rev. B | Page 25 of 72
2 × VREF
2.0
07054-053
Figure 51. Internal Reference Configuration
AD9627-11
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 54 shows the typical drift characteristics of the
internal reference in 1.0 V mode.
2.5
1.5
1.0
0.5
The RF balun configuration is recommended for clock
frequencies between 125 MHz and 625 MHz, and the RF
transformer is recommended for clock frequencies from 10 MHz
to 200 MHz. The back-to-back Schottky diodes across the
transformer/balun secondary limit clock excursions into the
AD9627-11 to approximately 0.8 V p-p differential.
This helps prevent the large voltage swings of the clock from
feeding through to other portions of the AD9627-11 while
preserving the fast rise and fall times of the signal that are critical
to a low jitter performance.
–1.0
–1.5
–2.0
0.1µF
0
20
40
60
80
TEMPERATURE (°C)
0.1µF
AVDD
CLK+
CLK–
1nF
0.1µF
CLOCK
INPUT
CLK+
ADC
AD9627-11
50Ω
0.1µF
1nF
CLK–
SCHOTTKY
DIODES:
HSMS2822
Figure 57. Balun-Coupled Differential Clock (Up to 625 MHz)
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins, as shown in Figure 58. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent
jitter performance.
CLK–
0.1µF
0.1µF
CLOCK
INPUT
2pF
07054-055
O
1.2V
ADC
AD9627-11
Figure 56. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9627-11 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
(see Figure 55) and require no external bias.
CLK+
SCHOTTKY
DIODES:
HSMS2822
0.1µF
B
SO
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 15). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.0 V.
2pF
100Ω
50Ω
LE
Figure 54. Typical VREF Drift
CLOCK
INPUT
Figure 55. Equivalent Clock Input Circuit
0.1µF
CLOCK
INPUT
100Ω
0.1µF
ADC
AD9627-11
CLK–
50kΩ
Clock Input Options
The AD9627-11 has a very flexible clock input structure. Clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
CLK+
AD951x
PECL DRIVER
50kΩ
240Ω
240Ω
Figure 58. Differential PECL Sample Clock (Up to 625 MHz)
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 59. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock
drivers offer excellent jitter performance.
Rev. B | Page 26 of 72
07054-058
–20
07054-054
–2.5
–40
Mini-Circuits®
ADT1–1WT, 1:1Z
0.1µF
XFMR
07054-056
–0.5
07054-057
0
TE
REFERENCE VOLTAGE ERROR (mV)
2.0
Figure 56 and Figure 57 show two preferred methods for clocking
the AD9627-11 (at clock rates up to 625 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
AD9627-11
Clock Duty Cycle
0.1µF
CLK+
AD951x
LVDS DRIVER
100Ω
0.1µF
CLOCK
INPUT
ADC
AD9627-11
07054-059
CLK–
50kΩ
50kΩ
Figure 59. Differential LVDS Sample Clock (Up to 625 MHz)
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor in parallel with a 39 kΩ resistor (see Figure 60).
CLK+ can be driven directly from a CMOS gate. Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is designed
to withstand input voltages of up to 3.6 V, making the selection
of the drive logic voltage very flexible.
CLOCK
INPUT
1kΩ
OPTIONAL
0.1µF
100Ω
AD951x
CMOS DRIVER
CLK+
ADC
AD9627-11
1kΩ
50Ω1
150Ω
39kΩ
RESISTOR IS OPTIONAL.
07054-060
CLK–
0.1µF
B
SO
Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS)
VCC
50Ω 1
1kΩ
AD951x
CMOS DRIVER
1kΩ
0.1µF
CLK+
ADC
AD9627-11
CLK–
150Ω RESISTOR IS OPTIONAL.
07054-061
0.1µF
CLOCK
INPUT
OPTIONAL 0.1µF
100Ω
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
less than 20 MHz nominally. The loop has a time constant
associated with it that must be considered where the clock rate
can change dynamically. A wait time of 1.5 μs to 5 μs is required
after a dynamic clock frequency increase or decrease before the
DCS loop is relocked to the input signal. During the time period
that the loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In such applications, it may be appropriate to disable the
duty cycle stabilizer. In all other applications, enabling the DCS
circuit is recommended to maximize ac performance.
LE
VCC
0.1µF
The AD9627-11 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling (falling) edge, providing an internal clock signal
with a nominal 50% duty cycle. This allows the user to provide
a wide range of clock input duty cycles without affecting the
performance of the AD9627-11. Noise and distortion performance
are nearly flat for a wide range of duty cycles with the DCS on,
as shown in Figure 43.
Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS)
Input Clock Divider
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low
frequency SNR (SNRLF) at a given input frequency (fINPUT) due
to jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( SNRLF /10) ]
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 62.
70
The AD9627-11 clock divider can be synchronized using the
external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the
clock divider to be resynchronized on every SYNC signal or only
on the first SYNC signal after the register is written. A valid
SYNC causes the clock divider to reset to its initial state. This
synchronization feature allows multiple parts to have their clock
dividers aligned to guarantee simultaneous input sampling.
0.05ps
65
MEASURED
SNR (dBc)
O
The AD9627-11 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8. If a
divide ratio other than 1 is selected, the duty cycle stabilizer is
automatically enabled.
0.20ps
60
0.5ps
55
1.0ps
1.50ps
50
2.00ps
45
2.50ps
3.00ps
1
10
100
INPUT FREQUENCY (MHz)
Figure 62. SNR vs. Input Frequency and Jitter
Rev. B | Page 27 of 72
1000
07054-062
0.1µF
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
TE
0.1µF
CLOCK
INPUT
AD9627-11
1.00
0.3
TOTAL POWER
0.50
0.2
0.1
0.25
IDRVDD
0
0
0
25
50
75
100
SAMPLE RATE (MSPS)
TE
As shown in Figure 63 and Figure 64, the power dissipated by
the AD9627-11 is proportional to its sample rate. In CMOS
output mode, the digital power dissipation is determined
primarily by the strength of the digital drivers and the load on
each output bit.
Figure 64. AD9627-11-105 Power and Current vs. Sample Rate
By asserting PDWN (either through the SPI port or by asserting
the PDWN pin high), the AD9627-11 is placed in power-down
mode. In this state, the ADC typically dissipates 2.5 mW. During
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD9627-11 to
its normal operating mode. Note that PDWN is referenced to
the digital output driver supply (DRVDD) and should not exceed
that supply voltage.
The maximum DRVDD current (IDRVDD) can be calculated as
LE
where N is the number of output bits (24, in the case of the
AD9627-11, with the fast detect output pins disabled).
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
B
SO
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency of fCLK/2. In practice, the DRVDD current
is established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 63 was
taken using the same operating conditions as those used for the
Typical Performance Characteristics, with a 5 pF load on each
output driver.
1.25
0.5
0.3
TOTAL POWER
0.2
0.50
IDRVDD
50
75
100
125
0
150
SAMPLE RATE (MSPS)
Figure 63. AD9627-11-150 Power and Current vs. Sample Rate
07054-063
0
25
In CMOS output mode, the output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause current glitches on
the supplies that may affect converter performance.
0.1
IDVDD
0
The AD9627-11 output drivers can be configured to interface
with 1.8 V to 3.3 V CMOS logic families by matching DRVDD
to the digital supply of the interfaced logic. The AD9627-11 can
also be configured for LVDS outputs using a DRVDD supply
voltage of 1.8 V.
SUPPLY CURRENT (A)
O
0.4
0.75
0.25
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section for more details.
DIGITAL OUTPUTS
IAVDD
1.00
07054-064
IDVDD
POWER DISSIPATION AND STANDBY MODE
TOTAL POWER (W)
IAVDD
SUPPLY CURRENT (A)
Refer to Application Note AN-501 and Application Note AN-756
(see www.analog.com) for more information about jitter performance as it relates to ADCs.
IDRVDD = VDRVDD × CLOAD × fCLK × N
0.4
0.75
TOTAL POWER (W)
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9627-11. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating
the clock signal with digital noise. Low jitter, crystal-controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or some other
method), it should be retimed by the original clock at the last step.
Applications requiring the ADC to drive large capacitive loads
or large fanouts may require external buffers or latches.
Rev. B | Page 28 of 72
AD9627-11
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when operating
in the external pin mode (see Table 12).
When using the SPI interface, the data and fast detect outputs
of each channel can be independently three-stated by using the
output enable bar bit in Register 0x14.
As detailed in Application Note AN-877, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI control.
TIMING
Table 12. SCLK/DFS Mode Selection (External Pin Mode)
The AD9627-11 provides latched data with a pipeline delay of
12 clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
Voltage at Pin
AGND
AVDD
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9627-11.
These transients can degrade converter dynamic performance.
SDIO/DCS
DCS disabled
DCS enabled (default)
Digital Output Enable Function (OEB)
Table 13. Output Data Format
Offset Binary Output Mode
000 0000 0000
000 0000 0000
100 0000 0000
111 1111 1111
111 1111 1111
B
SO
Condition (V)
< −VREF − 0.5 LSB
= −VREF
=0
= +VREF − 1.0 LSB
> +VREF − 0.5 LSB
The AD9627-11 provides two data clock output (DCO) signals
intended for capturing the data in an external register. The data
outputs are valid on the rising edge of DCO, unless the DCO clock
polarity has been changed via the SPI. See Figure 2 and Figure 3
for a graphical timing description.
O
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Data Clock Output (DCO)
LE
The AD9627-11 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the SMI
SDO/OEB pin or through the SPI interface. If the SMI SDO/OEB
pin is low, the output data drivers are enabled. If the SMI SDO/OEB
pin is high, the output data drivers are placed in a high impedance
state. This OEB function is not intended for rapid access to the
data bus. Note that OEB is referenced to the digital output driver
supply (DRVDD) and should not exceed that supply voltage.
The lowest typical conversion rate of the AD9627-11 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
TE
SCLK/DFS
Offset binary (default)
Twos complement
Rev. B | Page 29 of 72
Twos Complement Mode
100 0000 0000
100 0000 0000
000 0000 0000
011 1111 1111
011 1111 1111
OR
1
0
0
0
1
AD9627-11
ADC OVERRANGE AND GAIN CONTROL
Fast Detect
Mode Select Bits
(Register 0x104[3:1])
000
001
010
011
100
101
1
Information Presented on
Fast Detect (FD) Pins of Each ADC1, 2
FD[3]
FD[2]
FD[1] FD[0]
ADC fast magnitude
(see Table 15)
OR
ADC fast magnitude
(see Table 16)
OR
F_LT
ADC fast magnitude
(see Table 17)
F_LT
ADC fast magnitude C_UT
(see Table 17)
OR
C_UT
F_UT
F_LT
OR
F_UT
IG
DG
The fast detect pins are FD0A/FD0B to FD9A/FD9B for the CMOS mode
configuration and FD0+/FD0− to FD9+/FD9− for the LVDS mode
configuration.
2
See the ADC Overrange (OR) and Gain Switching sections for more
information about OR, C_UT, F_UT, F_LT, IG, and DG.
LE
Using the SPI port, the user can provide a threshold above which
an overrange output is active. As long as the signal is below that
threshold, the output should remain low. The fast detect outputs
can also be programmed via the SPI port so that one of the pins
functions as a traditional overrange pin for customers who
currently use this feature. In this mode, all 11 bits of the converter
are examined in the traditional manner, and the output is high for
the condition normally defined as overflow. In either mode, the
magnitude of the data is considered in the calculation of the
condition (but the sign of the data is not considered). The
threshold detection responds identically to positive and negative
signals outside the desired range (magnitude).
Table 14. Fast Detect Mode Select Bits Settings
TE
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness.
Therefore, it is helpful to have a programmable threshold below
full scale that allows time to reduce the gain before the clip
actually occurs. In addition, because input signals can have
significant slew rates, latency of this function is of major concern.
Highly pipelined converters can have significant latency. A good
compromise is to use the output bits from the first stage of the
ADC for this function. Latency for these output bits is very low,
and overall resolution is not highly significant. Peak input signals
are typically between full scale and 6 dB to 10 dB below full
scale. A 3-bit or 4-bit output provides adequate range and
resolution for this function.
ADC FAST MAGNITUDE
B
SO
When the fast detect output pins are configured to output the ADC
fast magnitude (that is, when the fast detect mode select bits are
set to 0b000), the information presented is the ADC level from
an early converter stage with a latency of only two clock cycles
(when in CMOS output mode). Using the fast detect output pins in
this configuration provides the earliest possible level indication
information. Because this information is provided early in the
datapath, there is significant uncertainty in the level indicated.
The nominal levels, along with the uncertainty indicated by the
ADC fast magnitude, are shown in Table 15.
FAST DETECT OVERVIEW
O
The AD9627-11 contains circuitry to facilitate fast overrange detection, allowing very flexible external gain control implementations.
Each ADC has four fast detect (FD) output pins that are used to
output information about the current state of the ADC input
level. The function of these pins is programmable via the fast detect
mode select bits and the fast detect enable bits in Register 0x104,
allowing range information to be output from several points in
the internal datapath. These output pins can also be set up to
indicate the presence of overrange or underrange conditions,
according to programmable threshold levels. Table 14 shows the
six configurations available for the fast detect pins.
Table 15. ADC Fast Magnitude Nominal Levels
with Fast Detect Mode Select Bits = 000
ADC Fast
Magnitude on
FD[3:0] Pins
0000
0001
0010
0011
0100
0101
0110
0111
1000
Rev. B | Page 30 of 72
Nominal Input
Magnitude
Below FS (dB)
工商网监
湘ICP备2023018690号
