AD9640-125EBZ

14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9640 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD SDIO/ SCLK/ DCS DFS CSB FD(0:3)A FD BITS/THRESHOLD DETECT DRVDD SPI PROGRAMMING DATA VIN+A SHA ADC VIN–A SIGNAL MONITOR VREF D13A D0A CLK+ CLK– CML DIVIDE 1 TO 8 REF SELECT DCO GENERATION DUTY CYCLE STABILIZER RBIAS VIN–B SHA ADC VIN+B SIGNAL MONITOR DATA MULTICHIP SYNC AGND SYNC FD BITS/THRESHOLD DETECT FD(0:3)B DCOA DCOB D13B D0B SIGNAL MONITOR INTERFACE SMI SMI SMI DRGND SDFS SCLK/ SDO/ PDWN OEB 06547-001 SENSE CMOS OUTPUT BUFFER SNR = 71.8 dBc (72.8 dBFS) to 70 MHz @ 125 MSPS SFDR = 85 dBc to 70 MHz @ 125 MSPS Low power: 750 mW @ 125 MSPS SNR = 71.6 dBc (72.6 dBFS) to 70 MHz @ 150 MSPS SFDR = 84 dBc to 70 MHz @ 150 MSPS Low power: 820 mW @ 150 MSPS 1.8 V analog supply operation 1.8 V to 3.3V CMOS output supply or 1.8 V LVDS output supply Integer 1 to 8 input clock divider IF sampling frequencies to 450 MHz Internal ADC voltage reference Integrated ADC sample-and-hold inputs Flexible analog input range: 1 V p-p to 2 V p-p Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer 95 dB channel isolation/crosstalk Serial port control User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes Integrated receive features Fast detect/threshold bits Composite signal monitor CMOS OUTPUT BUFFER FEATURES Figure 1. PRODUCT HIGHLIGHTS APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, WCDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems General-purpose software radios Broadband data applications 1. 2. 3. 4. 5. 6. 7. Integrated dual 14-bit, 80/105/125/150 MSPS ADC. Fast overrange detect and signal monitor with serial output. Signal monitor block with dedicated serial output mode. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 450 MHz. Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families. A standard serial port interface that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode. Pin compatibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2009 Analog Devices, Inc. All rights reserved. AD9640 TABLE OF CONTENTS Features .............................................................................................. 1 Clock Input Considerations ...................................................... 28 Applications ....................................................................................... 1 Power Dissipation and Standby Mode .................................... 30 Functional Block Diagram .............................................................. 1 Digital Outputs ........................................................................... 31 Product Highlights ........................................................................... 1 Timing ......................................................................................... 31 Revision History ............................................................................... 3 ADC Overrange and Gain Control .............................................. 32 General Description ......................................................................... 4 Fast Detect Overview ................................................................. 32 Specifications..................................................................................... 5 ADC Fast Magnitude ................................................................. 32 ADC DC Specifications—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, and AD9640BCPZ-105......................................................................... 5 ADC Overrange (OR)................................................................ 33 ADC DC Specifications—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ-150......................................................................... 6 ADC AC Specifications—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, and AD9640BCPZ-105......................................................................... 7 Gain Switching ............................................................................ 33 Signal Monitor ................................................................................ 35 Peak Detector Mode................................................................... 35 RMS/MS Magnitude Mode ......................................................... 35 Threshold Crossing Mode ......................................................... 36 Additional Control Bits ............................................................. 36 DC Correction ............................................................................ 36 ADC AC Specifications—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ 150 ......................................................................... 8 Built-In Self-Test (BIST) and Output Test .................................. 38 Digital Specifications ................................................................... 9 Built-In Self-Test (BIST) ............................................................ 38 Switching Specifications—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, and AD9640BCPZ-105 ..................................................................... 10 Output Test Modes ..................................................................... 38 Channel/Chip Synchronization .................................................... 39 Switching Specifications—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, and AD9640BCPZ-150 ..................................................................... 11 Configuration Using the SPI ..................................................... 40 Signal Monitor SPORT Output ................................................ 37 Serial Port Interface (SPI) .............................................................. 40 Hardware Interface..................................................................... 40 Timing Specifications ................................................................ 12 Configuration Without the SPI ................................................ 41 Absolute Maximum Ratings.......................................................... 14 SPI Accessible Features .............................................................. 41 Thermal Characteristics ............................................................ 14 Memory Map .................................................................................. 42 ESD Caution ................................................................................ 14 Reading the Memory Map Table .............................................. 42 Pin Configurations and Function Descriptions ......................... 15 External Memory Map .............................................................. 43 Equivalent Circuits ......................................................................... 19 Memory Map Register Description ......................................... 46 Typical Performance Characteristics ........................................... 20 Applications Information .............................................................. 49 Theory of Operation ...................................................................... 25 Design Guidelines ...................................................................... 49 ADC Architecture ...................................................................... 25 Outline Dimensions ....................................................................... 50 Analog Input Considerations.................................................... 25 Ordering Guide .......................................................................... 51 Voltage Reference ....................................................................... 27 Rev. B | Page 2 of 52 AD9640 REVISION HISTORY 12/09—Rev. A to Rev. B Added CP-64-6 Package .................................................... Universal Changes to Ordering Guide ...........................................................51 6/09—Rev. 0 to Rev. A Changes to Applications Section and Product Highlights Section ............................................................................. 1 Changes to General Description Section ....................................... 3 Changes to Specifications Section................................................... 4 Changes to Figure 2.........................................................................11 Changes to Figure 3.........................................................................12 Changes to Pin Configurations and Functional Descriptions Section .......................................................................12 Changes to Figure 11, Figure 12, Figure 14 ................................. 18 Change to Table 15 .......................................................................... 30 Changes to ADC Overrange and Gain Control Section ............ 31 Changes to Signal Monitor Section .............................................. 34 Changes to Table 25 ........................................................................ 42 Changes to Signal Monitor Period (Register 0x113 to Register 0x115) Section .................................................................. 47 Added LVDS Operation Section ................................................... 48 Added Exposed Pad Notation to Outline Dimensions .............. 49 6/07—Revision 0: Initial Version Rev. B | Page 3 of 52 AD9640 GENERAL DESCRIPTION The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-todigital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The AD9640 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency. In addition, the programmable threshold detector allows monitoring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly turn down the system gain to avoid an overrange condition. The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system. The ADC output data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS. Flexible power-down options allow significant power savings, when desired. Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface. The AD9640 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. Rev. B | Page 4 of 52 AD9640 SPECIFICATIONS ADC DC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 1. AD9640ABCPZ80/AD9640BCPZ-80 Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 2 VREF INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD, DVDD DRVDD (CMOS Mode) DRVDD (LVDS Mode) Supply Current IAVDD1, 3 IDVDD1, 3 IDRVDD1 (3.3 V CMOS) IDRVDD1 (1.8 V CMOS) IDRVDD1 (1.8 V LVDS) POWER CONSUMPTION DC Input Sine Wave Input1 (DRVDD = 1.8 V) Sine Wave Input1 (DRVDD = 3.3 V) Standby Power 4 Power-Down Power Temperature Full Min 14 Typ Max AD9640ABCPZ105/AD9640BCPZ-105 Min 14 Typ Max Unit Bits Full Full Full Full 25°C Full 25°C Guaranteed ±0.3 ±0.6 ±0.2 ±3.0 ±0.9 ±0.4 ±5.0 ±2.0 Guaranteed ±0.3 ±0.6 ±0.2 ±3.0 ±0.9 ±0.4 ±5.0 ±2.0 % FSR % FSR LSB LSB LSB LSB Full Full ±0.3 ±0.1 ±0.4 ±0.1 % FSR % FSR Full Full ±15 ±95 Full Full ±2 7 25°C 1.3 1.3 LSB rms Full Full Full 2 8 6 2 8 6 V p-p pF kΩ Full Full Full 1.7 1.7 1.7 1.8 3.3 1.8 Full Full Full Full Full 233 26 27 12 54 Full Full Full Full Full 452 487 550 52 2.5 1 ±0.6 ±0.5 ±0.7 ±0.5 ±15 ±95 ±15 1.9 3.6 1.9 277 492 6 ±2 7 1.7 1.7 1.7 1.8 3.3 1.8 310 34 35 18 55 603 645 730 68 2.5 ppm/°C ppm/°C ±15 1.9 3.6 1.9 371 657 6 mV mV V V V mA mA mA mA mA mW mW mW mW mW Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. 3 The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND). 2 Rev. B | Page 5 of 52 AD9640 ADC DC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 2. AD9640ABCPZ-125/ Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) 1 Integral Nonlinearity (INL)1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error (1 V Mode) Load Regulation @ 1.0 mA INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance 2 VREF INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD, DVDD DRVDD (CMOS Mode) DRVDD (LVDS Mode) Supply Current IAVDD1, 3 IDVDD1, 3 IDRVDD1 (3.3 V CMOS) IDRVDD1 (1.8 V CMOS) IDRVDD1 (1.8 V LVDS) POWER CONSUMPTION DC Input Sine Wave Input1 (DRVDD = 1.8 V) Sine Wave Input1 (DRVDD = 3.3 V) Standby Power 4 Power-Down Power Temperature Full AD9640BCPZ-125 Min Typ Max 14 Full Full Full Full 25°C Full 25°C AD9640ABCPZ-150/ Min 14 Guaranteed ±0.3 ±0.6 ±0.2 ±3.0 ±0.9 ±0.4 ±5.0 ±2 Unit Bits Guaranteed ±0.3 ±0.6 ±0.2 ±3.0 −0.95/+1.5 −0.4/+0.6 ±5.0 ±2 % FSR % FSR LSB LSB LSB LSB ±0.4 ±0.2 % FSR % FSR 25°C 25°C ±0.4 ±0.1 Full Full ±15 ±95 Full Full ±2 7 25°C 1.3 1.3 LSB rms Full Full Full 2 8 6 2 8 6 V p-p pF kΩ Full Full Full 1.7 1.7 1.7 1.8 3.3 1.8 Full Full Full Full 385 42 44 22 56 Full Full Full Full Full 750 810 910 77 2.5 1 ±0.7 ±0.6 AD9640BCPZ-150 Typ Max ±0.7 ±0.6 ±15 ±95 ±15 1.9 3.6 1.9 470 846 6 ±3 7 1.7 1.7 1.7 1.8 3.3 1.8 419 50 53 27 57 820 895 1000 77 2.5 ppm/°C ppm/°C ±15 1.9 3.6 1.9 517 938 6 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. See Figure 8 for the equivalent analog input structure. The maximum limit applies to the combination of IAVDD and IDVDD currents. 4 Standby power is measured with a dc input and with the CLK pins (CLK+, CLK−) inactive (set to AVDD or AGND). 2 3 Rev. B | Page 6 of 52 mV mV V V V mA mA mA mA mW mW mW mW mW AD9640 ADC AC SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 3. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz WORST OTHER HARMONIC OR SPUR fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz TWO TONE SFDR fIN = 29.1 MHz, 32.1 MHz (−7 dBFS) fIN = 169.1 MHz, 172.1 MHz (−7 dBFS) CROSSTALK 2 ANALOG INPUT BANDWIDTH 1 2 Temperature 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C AD9640ABCPZ-80/ AD9640ABCPZ-105/ AD9640BCPZ-80 Min Typ Max AD9640BCPZ-105 Min Typ Max 72.5 72.1 72.3 71.9 70.5 dB dB dB dB dB 70.2 71.6 71.0 71.3 70.3 72.2 71.6 72.0 71.6 Unit 71.1 70.4 70.9 70.0 dB dB dB dB dB 25°C 25°C 25°C 25°C 11.9 11.8 11.7 11.6 11.8 11.8 11.7 11.5 Bits Bits Bits Bits 25°C 25°C Full 25°C 25°C −87 −85 −87 −85 −84 −83 −84 −83 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C 87 85 87 85 69 69.5 −75 75 −74 dBc dBc dBc dBc dBc 74 84 83 84 83 25°C 25°C Full 25°C 25°C −93 −89 −93 −89 −89 −89 −89 −89 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 85 82 −95 650 85 82 −95 650 dBc dBc dB MHz −82 See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel. Rev. B | Page 7 of 52 −81 AD9640 ADC AC SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ 150 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect outputs disabled, and signal monitor disabled, unless otherwise noted. Table 4. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz WORST OTHER HARMONIC OR SPUR fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz TWO TONE SFDR fIN = 29.1 MHz, 32.1 MHz (−7 dBFS) fIN = 169.1 MHz, 172.1 MHz (−7 dBFS) CROSSTALK 2 ANALOG INPUT BANDWIDTH 1 2 Temperature 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C AD9640ABCPZ-125 AD9640ABCPZ-150/ AD9640BCPZ-125 Min Typ Max AD9640BCPZ-150 Min Typ Max 72.1 71.8 71.9 71.6 70.2 dB dB dB dB dB 69.5 71.4 70.8 70.9 70.0 71.8 71.4 71.6 71.0 Unit 71.0 70.3 70.5 69.9 dB dB dB dB dB 25°C 25°C 25°C 25°C 11.8 11.7 11.7 11.6 11.8 11.8 11.6 11.5 Bits Bits Bits Bits 25°C 25°C Full 25°C 25°C −86.5 −85 −86.5 −84 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C 69.5 67.5 −74 −73 −84 −83 −83.5 −77 86.5 85 86.5 84 74 dBc dBc dBc dBc dBc 73 84 83 83.5 77 25°C 25°C Full 25°C 25°C −92 −89 −92 −90 −89 −89 −90 −90 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 85 82 −95 650 85 82 −95 650 dBc dBc dB MHz −80 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Crosstalk is measured at 100 MHz with −1 dBFS on one channel and no input on the alternate channel. Rev. B | Page 8 of 52 −80 AD9640 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 5. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance SYNC INPUT Logic Compliance Internal Bias Input Voltage Range High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB) 1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK/DFS) 2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 3.3 V) Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS/OUTPUTS (SDIO/DCS, SMI SDFS)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 3.3 V) Low Level Input Current Input Resistance Input Capacitance Temperature Min Full Full Full Full Full Full Full Full Full Full CMOS/LVDS/LVPECL 1.2 0.2 6 AVDD + 1.6 AGND − 0.3 1.1 AVDD 1.2 3.6 0 0.8 −10 +10 −10 +10 4 8 10 12 Full Full Full Full Full Full Full Full Max CMOS 1.2 AGND − 0.3 1.2 0 −10 −10 8 Full Full Full Full Full Full 1.22 0 −10 40 Full Full Full Full Full Full 1.22 0 −92 −10 Full Full Full Full Full Full 1.22 0 −10 38 Full Full Full Full Full Full 1.22 0 −90 −10 Rev. B | Page 9 of 52 Typ AVDD + 1.6 3.6 0.8 +10 +10 4 10 12 V V p-p V V V V μA μA pF kΩ V V V V μA μA pF kΩ 3.6 0.6 +10 132 V V μA μA kΩ pF 3.6 0.6 −135 +10 V V μA μA kΩ pF 3.6 0.6 +10 128 V V μA μA kΩ pF 3.6 0.6 −134 +10 V V μA μA kΩ pF 26 2 26 2 26 5 26 5 Unit AD9640 Parameter DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage (IOH = 50 μA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 μA) CMOS Mode—DRVDD = 1.8 V High Level Output Voltage (IOH = 50 μA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 μA) LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode 1 2 Temperature Min Full Full Full Full 3.29 3.25 Full Full Full Full 1.79 1.75 Full Full Full Full 250 1.15 150 1.15 Typ 350 1.25 200 1.25 Max Unit 0.2 0.05 V V V V 0.2 0.05 V V V V 450 1.35 280 1.35 mV V mV V Pull up. Pull down. SWITCHING SPECIFICATIONS—AD9640ABCPZ-80, AD9640BCPZ-80, AD9640ABCPZ-105, AND AD9640BCPZ-105 AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 6. AD9640ABCPZ-80 Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate DCS Enabled 1 DCS Disabled1 CLK Period—Divide by 1 Mode (tCLK) CLK Pulse Width High Divide by 1 Mode, DCS Enabled Divide by 1 Mode, DCS Disabled Divide by 2 Mode, DCS Enabled Divide by 3 Through 8, DCS Enabled DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode—DRVDD = 3.3 V Data Propagation Delay (tPD) 2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) LVDS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) Temp Min AD9640BCPZ-80 Typ Max Full AD9640ABCPZ-105/ Min AD9640BCPZ-105 Typ Max 625 Full Full Full 20 10 12.5 Full Full Full Full 3.75 5.63 1.6 0.8 Full Full Full Full Unit 625 MHz 105 105 MSPS MSPS ns 80 80 20 10 9.5 6.25 6.25 8.75 6.88 2.85 4.28 1.6 0.8 4.75 4.75 6.65 5.23 ns ns ns ns 2.2 3.8 4.5 5.0 6.25 5.75 6.4 6.8 2.2 3.8 4.5 5.0 5.25 4.25 6.4 6.8 ns ns ns ns Full Full 2.4 4.0 5.2 5.6 6.9 7.3 2.4 4.0 5.2 5.6 6.9 7.3 ns ns Full Full 3.0 5.4 3.7 7.0 4.4 8.4 3.0 5.2 3.7 6.4 4.4 7.6 ns ns Rev. B | Page 10 of 52 AD9640 AD9640ABCPZ-80 Parameter CMOS Mode Pipeline Delay (Latency) LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time 3 OUT-OF-RANGE RECOVERY TIME 1 2 3 Temp Full AD9640ABCPZ-105/ AD9640BCPZ-80 Typ Max 12 12/12.5 Min Full Full Full Full Min 1.0 0.1 350 2 AD9640BCPZ-105 Typ Max 12 12/12.5 1.0 0.1 350 2 Unit Cycles Cycles ns ps rms μs Cycles Conversion rate is the clock rate after the divider. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. Wake-up time is dependent on the value of the decoupling capacitors. SWITCHING SPECIFICATIONS—AD9640ABCPZ-125, AD9640BCPZ-125, AD9640ABCPZ-150, AND AD9640BCPZ-150 AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 7. AD9640ABCPZ-125/ Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate DCS Enabled 1 DCS Disabled1 CLK Period—Divide by 1 Mode (tCLK) CLK Pulse Width High Divide by 1 Mode, DCS Enabled Divide by 1 Mode, DCS Disabled Divide by 2 Mode, DCS Enabled Divide by 3 Through 8, DCS Enabled DATA OUTPUT PARAMETERS (DATA, FD) CMOS Mode—DRVDD = 3.3 V Data Propagation Delay (tPD) 2 DCO Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) CMOS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) LVDS Mode—DRVDD = 1.8 V Data Propagation Delay (tPD)2 DCO Propagation Delay (tDCO) CMOS Mode Pipeline Delay (Latency) LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Wake-Up Time 3 OUT-OF-RANGE RECOVERY TIME 1 2 3 Temperature Min AD9640BCPZ-125 Typ Max Full AD9640ABCPZ-150/ Min AD9640BCPZ-150 Typ Max 625 Full Full Full 20 10 8 Full Full Full Full 2.4 3.6 1.6 0.8 Full Full Full Full Unit 625 MHz 150 150 MSPS MSPS ns 125 125 20 10 6.66 4 4 5.6 4.4 2.0 3.0 1.6 0.8 3.33 3.33 4.66 3.66 ns ns ns ns 2.2 3.8 4.5 5.0 4.5 3.5 6.4 6.8 2.2 3.8 4.5 5.0 3.83 2.83 6.4 6.8 ns ns ns ns Full Full 2.4 4.0 5.2 5.6 6.9 7.3 2.4 4.0 5.2 5.6 6.9 7.3 ns ns Full Full Full 3.0 5.0 3.8 6.2 12 12/12.5 4.5 7.4 3.0 4.8 3.8 5.9 12 12/12.5 4.5 7.3 ns ns Cycles Cycles Full Full Full Full 1.0 0.1 350 3 Conversion rate is the clock rate after the divider. Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load. Wake-up time is dependent on the value of the decoupling capacitors. Rev. B | Page 11 of 52 1.0 0.1 350 3 ns ps rms μs Cycles AD9640 TIMING SPECIFICATIONS Table 8. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO SPORT TIMING REQUIREMENTS tCSSCLK tSSCLKSDO tSSCLKSDFS Conditions Min Typ SYNC to rising edge of CLK setup time SYNC to rising edge of CLK hold time Max 0.24 0.40 Unit ns ns Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns Delay from rising edge of CLK+ to rising edge of SMI SCLK Delay from rising edge of SMI SCLK to SMI SDO Delay from rising edge of SMI SCLK to SMI SDFS 3.2 −0.4 −0.4 4.5 0 0 6.2 +0.4 +0.4 Timing Diagrams N+2 N+1 N+3 N N+4 tA N+8 N+5 N+6 N+7 tCLK CLK+ CLK– CH A/B DATA N – 13 N – 12 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 CH A/B FAST DETECT N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 tS tH tDCO tCLK DCOA/DCOB Figure 2. CMOS Output Mode Data and Fast Detect Output Timing (Fast Detect Mode 0) Rev. B | Page 12 of 52 06547-021 tPD ns ns ns AD9640 N+2 N+1 N+3 N N+4 N+8 tA N+5 N+6 N+7 tCLK CLK+ CLK– tPD CH A/CH B DATA A CH A/CH B FAST DETECT A B N – 13 B N–7 A B N – 12 A B N–6 A B N – 11 A B N–5 A B N – 10 A B N–4 A B N–9 A B N–3 A B N–8 A B N–2 tDCO A B N–7 A B N–1 A B A N–6 A B B N–5 A N B N+1 A N–4 A N+2 tCLK 06547-089 DCO+ DCO– Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode 1 Through Fast Detect Mode 5) CLK+ tHSYNC 06547-072 tSSYNC SYNC Figure 4. SYNC Input Timing Requirements CLK+ CLK– tCSSCLK SMI SCLK tSSCLKSDFS tSSCLKSDO SMI SDO DATA Figure 5. Signal Monitor SPORT Output Timing (Divide by 2 Mode) Rev. B | Page 13 of 52 DATA 06547-082 SMI SDFS AD9640 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 9. Parameter ELECTRICAL AVDD, DVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to AGND VREF to AGND SENSE to AGND CML to AGND RBIAS to AGND CSB to AGND SCLK/DFS to DRGND SDIO/DCS to DRGND SMI SDO/OEB SMI SCLK/PDWN SMI SDFS D0A/D0B through D13A/D13B to DRGND FD0A/FD0B through FD3A/FD3B to DRGND DCOA/DCOB to DRGND ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the customer board increases the reliability of the solder joints and maximizes the thermal capability of the package. −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +0.3 V −3.9 V to +2.0 V −0.3 V to AVDD + 0.2 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DRVDD + 0.3 V Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes, reduces the θJA. −0.3 V to DRVDD + 0.3 V ESD CAUTION Table 10. Thermal Resistance Package Type 64-lead LFCSP 9 mm × 9 mm Airflow Velocity (m/s) 0 1.0 2.0 θJA1, 2 18.8 16.5 15.8 θJC1, 3 0.6 θJB1, 4 6.0 Unit °C/W °C/W °C/W 1 JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 2 −0.3 V to DRVDD + 0.3 V −40°C to +85°C 150°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 14 of 52 AD9640 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DRGND D5B D4B D3B D2B D1B D0B (LSB) DVDD FD3B FD2B FD1B FD0B SYNC CSB CLK– CLK+ PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9640 PARALLEL CMOS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN–B RBIAS CML SENSE VREF VIN–A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB NOTES 1. NC = NO CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 06547-002 D5A D6A D7A DRGND DRVDD D8A D9A DVDD D10A D11A D12A D13A (MSB) FD0A FD1A FD2A FD3A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DRVDD D6B D7B D8B D9B D10B D11B D12B D13B (MSB) DCOB DCOA D0A (LSB) D1A D2A D3A D4A Figure 6. Pin Configuration, LFCSP Parallel CMOS (Top View) Table 11. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic ADC Power Supplies 20, 64 DRGND 1, 21 DRVDD 24, 57 DVDD 36, 45, 46 AVDD 0 AGND, Exposed Pad ADC Analog 37 VIN+A 38 VIN−A 44 VIN+B 43 VIN−B 39 VREF 40 SENSE 42 RBIAS 41 CML 49 CLK+ 50 CLK− Type Description Ground Supply Supply Supply Ground Digital Output Ground. Digital Output Driver Supply (1.8 V to 3.3 V). Digital Power Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. Input Input Input Input Input/Output Input Input/Output Output Input Input Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Voltage Reference Mode Select. See Table 14 for details. External Reference Bias Resistor. Common Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Rev. B | Page 15 of 52 AD9640 Pin No. Mnemonic ADC Fast Detect Outputs 29 FD0A 30 FD1A 31 FD2A 32 FD3A 53 FD0B 54 FD1B 55 FD2B 56 FD3B Digital Inputs 52 SYNC Digital Outputs 12 D0A (LSB) 13 D1A 14 D2A 15 D3A 16 D4A 17 D5A 18 D6A 19 D7A 22 D8A 23 D9A 25 D10A 26 D11A 27 D12A 28 D13A (MSB) 58 D0B (LSB) 59 D1B 60 D2B 61 D3B 62 D4B 63 D5B 2 D6B 3 D7B 4 D8B 5 D9B 6 D10B 7 D11B 8 D12B 9 D13B (MSB) 11 DCOA 10 DCOB SPI Control 48 SCLK/DFS 47 SDIO/DCS 51 CSB Serial Port 33 SMI SDO/OEB 35 SMI SDFS 34 SMI SCLK/PDWN Type Description Output Output Output Output Output Output Output Output Channel A Fast Detect Indicator. See Table 18 for details. Channel A Fast Detect Indicator. See Table 18 for details. Channel A Fast Detect Indicator. See Table 18 for details. Channel A Fast Detect Indicator. See Table 18 for details. Channel B Fast Detect Indicator. See Table 18 for details. Channel B Fast Detect Indicator. See Table 18 for details. Channel B Fast Detect Indicator. See Table 18 for details. Channel B Fast Detect Indicator. See Table 18 for details. Input Digital Synchronization Pin. Slave mode only. Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel A Data Clock Output. Channel B Data Clock Output. Input Input/Output Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode. SPI Chip Select (Active Low). Input/Output Output Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev. B | Page 16 of 52 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DRGND D0+ (LSB) D0– (LSB) FD3+ FD3– FD2+ FD2– DVDD FD1+ FD1– FD0+ FD0– SYNC CSB CLK– CLK+ AD9640 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9640 PARALLEL LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN+B VIN–B RBIAS CML SENSE VREF VIN–A VIN+A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB NOTES 1. NC = NO CONNECT. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 06547-003 D7+ D8– D8+ DRGND DRVDD D9– D9+ DVDD D10– D10+ D11– D11+ D12– D12+ D13– (MSB) D13+ (MSB) 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DRVDD D1– D1+ D2– D2+ D3– D3+ D4– D4+ DCO– DCO+ D5– D5+ D6– D6+ D7– Figure 7. Pin Configuration, LFCSP LVDS (Top View) Table 12. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic ADC Power Supplies 20, 64 DRGND 1, 21 DRVDD 24, 57 DVDD 36, 45, 46 AVDD 0 AGND, Exposed Pad ADC Analog 37 VIN+A 38 VIN−A 44 VIN+B 43 VIN−B 39 VREF 40 SENSE 42 RBIAS 41 CML 49 CLK+ 50 CLK− ADC Fast Detect Outputs 54 FD0+ 53 FD0− 56 FD1+ 55 FD1− 59 FD2+ 58 FD2− 61 FD3+ 60 FD3− Type Function Ground Supply Supply Supply Ground Digital Output Ground. Digital Output Driver Supply (1.8 V to 3.3 V). Digital Power Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. Input Input Input Input Input/Output Input Input/Output Output Input Input Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Voltage Reference Mode Select. See Table 14 for details. External Reference Bias Resistor. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Output Output Output Output Output Output Output Output Channel A/Channel B LVDS Fast Detect Indicator 0—True. See Table 18 for details. Channel A/Channel B LVDS Fast Detect Indicator 0—Complement. See Table 18 for details. Channel A/Channel B LVDS Fast Detect Indicator 1—True. See Table 18 for details. Channel A/Channel B LVDS Fast Detect Indicator 1—Complement. See Table 18 for details. Channel A/Channel B LVDS Fast Detect Indicator 2—True. See Table 18 for details. Channel A/Channel B LVDS Fast Detect Indicator 2—Complement. See Table 18 for details. Channel A/Channel B LVDS Fast Detect Indicator 3—True. See Table 18 for details. Channel A/Channel B LVDS Fast Detect Indicator 3—Complement. See Table 18 for details. Rev. B | Page 17 of 52 AD9640 Pin No. Mnemonic Digital Inputs 52 SYNC Digital Outputs 63 D0+ (LSB) 62 D0− (LSB) 3 D1+ 2 D1− 5 D2+ 4 D2− 7 D3+ 6 D3− 9 D4+ 8 D4− 13 D5+ 12 D5− 15 D6+ 14 D6− 17 D7+ 16 D7− 19 D8+ 18 D8− 23 D9+ 22 D9− 26 D10+ 25 D10− 28 D11+ 27 D11− 30 D12+ 29 D12− 32 D13+ (MSB) 31 D13− (MSB) 11 DCO+ 10 DCO− SPI Control 48 SCLK/DFS 47 SDIO/DCS 51 CSB Signal Monitor Ports 33 SMI SDO/OEB 35 SMI SDFS 34 SMI SCLK/PDWN Type Function Input Digital Synchronization Pin. Slave mode only. Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Channel A/Channel B LVDS Output Data 0—True. Channel A/Channel B LVDS Output Data 0—Complement. Channel A/Channel B LVDS Output Data 1—True. Channel A/Channel B LVDS Output Data 1—Complement. Channel A/Channel B LVDS Output Data 2—True. Channel A/Channel B LVDS Output Data 2—Complement. Channel A/Channel B LVDS Output Data 3—True. Channel A/Channel B LVDS Output Data 3—Complement. Channel A/Channel B LVDS Output Data 4—True. Channel A/Channel B LVDS Output Data 4—Complement. Channel A/Channel B LVDS Output Data 5—True. Channel A/Channel B LVDS Output Data 5—Complement. Channel A/Channel B LVDS Output Data 6 —True. Channel A/Channel B LVDS Output Data 6—Complement. Channel A/Channel B LVDS Output Data 7—True. Channel A/Channel B LVDS Output Data 7—Complement. Channel A/Channel B LVDS Output Data 8—True. Channel A/Channel B LVDS Output Data 8—Complement. Channel A/Channel B LVDS Output Data 9—True. Channel A/Channel B LVDS Output Data 9—Complement. Channel A/Channel B LVDS Output Data 10—True. Channel A/Channel B LVDS Output Data 10—Complement. Channel A/Channel B LVDS Output Data 11—True. Channel A/Channel B LVDS Output Data 11—Complement. Channel A/Channel B LVDS Output Data 12—True. Channel A/Channel B LVDS Output Data 12—Complement. Channel A/Channel B LVDS Output Data 13—True. Channel A/Channel B LVDS Output Data 13—Complement. Channel A/Channel B LVDS Data Clock Output—True. Channel A/Channel B LVDS Data Clock Output—Complement. Input Input/Output Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode. SPI Chip Select (Active Low). Input/Output Output Input/Output Signal Monitor Serial Data Output/Output Enable Input (Active Low) in External Pin Mode. Signal Monitor Serial Data Frame Sync. Signal Monitor Serial Clock Output/Power-Down Input in External Pin Mode. Rev. B | Page 18 of 52 AD9640 EQUIVALENT CIRCUITS DVDD 1kΩ SCLK/DFS VIN 06547-011 06547-004 26kΩ Figure 8. Equivalent Analog Input Circuit Figure 12. Equivalent SCLK/DFS Input Circuit AVDD 1kΩ 1.2V 10kΩ SENSE 10kΩ CLK+ 06547-005 06547-009 CLK– Figure 13. Equivalent SENSE Circuit Figure 9. Equivalent Clock Input Circuit DRVDD DVDD 26kΩ DVDD 1kΩ 06547-081 06547-010 CSB DRGND Figure 10. Digital Output Figure 14. Equivalent CSB Input Circuit DRVDD AVDD DVDD 26kΩ DVDD 1kΩ VREF SDIO/DCS 6kΩ 06547-096 06547-007 DRVDD Figure 11. Equivalent SDIO/DCS or SMI SDFS Circuit Figure 15. Equivalent VREF Circuit Rev. B | Page 19 of 52 AD9640 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V; DVDD = 1.8 V; DRVDD = 3.3 V; sample rate = 150 MSPS, DCS enabled, 1 V internal reference; 2 V p-p differential input; VIN = −1.0 dBFS; and 64k sample; TA = 25°C, unless otherwise noted. 0 0 150MSPS 2.3MHz @ –1dBFS SNR = 71.9dBc (72.9dBFS) ENOB = 11.8 BITS SFDR = 86dBc –20 AMPLITUDE (dBFS) –40 –60 SECOND HARMONIC THIRD HARMONIC –80 –60 SECOND HARMONIC THIRD HARMONIC –80 –100 06547-050 –100 –40 –120 0 10 20 30 40 50 60 06547-053 AMPLITUDE (dBFS) –20 150MSPS 140.3MHz @ –1dBFS SNR = 70.9dBc (71.9dBFS) ENOB = 11.6 BITS SFDR = 85.1dBc –120 0 70 10 20 FREQUENCY (MHz) Figure 16. AD9640-150 Single-Tone FFT with fIN = 2.3 MHz 50 60 70 0 150MSPS 30.3MHz @ –1dBFS SNR = 71.7dBc (72.7dBFS) ENOB = 11.8 BITS SFDR = 89.9dBc –40 –60 SECOND HARMONIC THIRD HARMONIC –80 150MSPS 200.3MHz @ –1dBFS SNR = 70dBc (71dBFS) ENOB = 11.5 BITS SFDR = 80dBc –20 AMPLITUDE (dBFS) –20 SECOND HARMONIC –60 THIRD HARMONIC –80 –100 06547-051 –100 –40 –120 0 10 20 30 40 50 60 06547-054 AMPLITUDE (dBFS) 40 Figure 19. AD9640-150 Single-Tone FFT with fIN = 140.3 MHz 0 –120 0 70 10 20 FREQUENCY (MHz) 30 40 50 60 70 FREQUENCY (MHz) Figure 17. AD9640-150 Single-Tone FFT with fIN = 30.3 MHz Figure 20. AD9640-150 Single-Tone FFT with fIN = 200.3 MHz 0 0 150MSPS 70MHz @ –1dBFS SNR = 71.5dBc (72.5dBFS) ENOB = 11.7 BITS SFDR = 84dBc –40 –60 THIRD HARMONIC SECOND HARMONIC –80 150MSPS 337MHz @ –1dBFS SNR = 68dBc (69dBFS) ENOB = 11 BITS SFDR = 72.4dB –20 AMPLITUDE (dBFS) –20 –40 THIRD HARMONIC –60 SECOND HARMONIC –80 –100 –120 0 10 20 30 40 50 60 06547-085 –100 06547-052 AMPLITUDE (dBFS) 30 FREQUENCY (MHz) –120 0 70 FREQUENCY (MHz) 10 20 30 40 50 60 70 FREQUENCY (MHz) Figure 18. AD9640-150 Single-Tone FFT with fIN = 70 MHz Figure 21. AD9640-150 Single-Tone FFT with fIN = 337 MHz Rev. B | Page 20 of 52 AD9640 0 0 150MSPS 440MHz @ –1dBFS SNR = 65dBc (66dBFS) ENOB = 10.4 BITS SFDR = 70.0dB –20 AMPLITUDE (dBFS) –40 SECOND HARMONIC –60 THIRD HARMONIC –80 –60 THIRD HARMONIC SECOND HARMONIC –80 –100 06547-086 –100 –40 –120 0 10 20 30 40 50 60 06547-093 AMPLITUDE (dBFS) –20 125MSPS 70MHz @ –1dBFS SNR = 71.8dBc (72.8dBFS) ENOB = 11.7 BITS SFDR = 85dBc –120 0 70 10 20 FREQUENCY (MHz) Figure 22. AD9640-150 Single-Tone FFT with fIN = 440 MHz 40 50 60 Figure 25. AD9640-125 Single-Tone FFT with fIN = 70 MHz 0 0 125 MSPS 2.3MHz @ –1dBFS SNR = 72.3dBc (73.3dBFS) ENOB = 11.8 BITS SFDR = 88.4dBc 125 MSPS 140MHz @ –1dBFS SNR = 71.4dBc (72.4dBFS) ENOB = 11.7 BITS SFDR = 87.1dBc –20 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 30 FREQUENCY (MHz) –40 –60 SECOND HARMONIC –80 –40 SECOND HARMONIC –60 THIRD HARMONIC –80 THIRD HARMONIC –100 –120 0 10 20 30 40 50 06547-059 06547-057 –100 –120 60 0 10 20 FREQUENCY (MHz) Figure 23. AD9640-125 Single-Tone FFT with fIN = 2.3 MHz 40 50 60 Figure 26. AD9640-125 Single-Tone FFT with fIN = 140 MHz 0 0 125 MSPS 30.3MHz @ –1dBFS SNR = 72.1dBc (73.1dBFS) ENOB = 11.8 BITS SFDR = 89.1dBc –40 THIRD HARMONIC –60 SECOND HARMONIC –80 125 MSPS 200MHz @ –1dBFS SNR = 70.8dBc (71.8dBFS) ENOB = 11.6 BITS SFDR = 80.5dBc –20 AMPLITUDE (dBFS) –20 –40 THIRD HARMONIC –60 SECOND HARMONIC –80 –120 0 10 20 30 40 50 06547-060 –100 –100 06547-058 AMPLITUDE (dBFS) 30 FREQUENCY (MHz) –120 0 60 10 20 30 40 50 60 FREQUENCY (MHz) FREQUENCY (MHz) Figure 24. AD9640-125 Single-Tone FFT with fIN = 30.3 MHz Figure 27. AD9640-125 Single-Tone FFT with fIN = 200 MHz Rev. B | Page 21 of 52 AD9640 120 95 SFDR = +25°C 85 SNR (dBFS) 60 SFDR (dBc) 40 SNR (dBc) 20 –70 –60 –50 –40 –30 –20 75 SFDR = +85°C SNR = –40°C 65 06547-061 –80 SFDR = –40°C 70 85dB REFERENCE LINE 0 –90 80 SNR = +25°C SNR = +85°C 60 0 0 –10 50 100 INPUT AMPLITUDE (dBFS) 06547-088 80 SNR/SFDR (dBc) SNR/SFDR (dBc AND dBFS) 90 SFDR (dBFS) 100 150 200 250 300 350 400 450 INPUT FREQUENCY (MHz) Figure 31. AD9640-150 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 1 V p-p Full Scale Figure 28. AD9640-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 2.3 MHz 0.8 120 SFDR (dBFS) 0.6 80 GAIN/OFFSET ERROR (%FSR) SNR (dBFS) 60 SFDR (dBc) 40 SNR (dBc) 20 OFFSET 0.4 0.2 0 –0.2 –0.4 –0.6 GAIN –80 –70 –60 –50 –40 –30 –20 –0.8 –1.0 –40 0 –10 06547-098 0 –90 06547-062 85dB REFERENCE LINE –20 0 40 60 80 Figure 32. AD9640 Gain and Offset vs. Temperature Figure 29. AD9640-150 Single-Tone SFDR vs. Input Amplitude with fIN = 98.12 MHz 0 95 90 –20 SNR/SFDR (dBc AND dBFS) SFDR = +25°C 85 SFDR = –40°C 80 SNR = –40°C SFDR = +85°C 75 70 SNR = +25°C 65 SNR = +85°C 60 0 50 100 150 200 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 06547-087 SNR/SFDR (dBc) 20 TEMPERATURE (°C) INPUT AMPLITUDE (dBFS) 250 300 350 400 IMD3 (dBFS) –120 –90 450 –78 –66 –54 –42 –30 –18 –6 INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (MHz) Figure 30. AD9640-150 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and Temperature with 2 V p-p Full Scale 06547-063 SNR/SFDR (dBc AND dBFS) 100 Figure 33. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz, fS = 150 MSPS Rev. B | Page 22 of 52 AD9640 0 0 –20 SFDR (dBc) AMPLITUDE (dBFS) –40 –60 IMD3 (dBc) IMD3 (dBFS) –80 –40 –60 –80 SFDR (dBFS) –100 –120 –90 06547-064 –100 –78 –66 –54 –42 –30 –120 –6 –18 06547-066 SNR/SFDR (dBc AND dBFS) –20 150 MSPS 169.1MHz @–7dBFS 172.1MHz @–7dBFS SFDR = 83.8dBc (90.8dBFS) 0 10 20 INPUT AMPLITUDE (dBFS) Figure 34. AD9640-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS 50 60 70 0 NPR = 64.7dBc NOTCH @ 18.5MHz NOTCH WIDTH = 3MHz –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –60 –80 –100 06547-102 –100 –40 –120 0 15.36 30.72 46.08 06547-100 AMPLITUDE (dBFS) 40 Figure 37. AD9640-150 Two-Tone FFT with fIN1 = 169.1 MHz and fIN2 = 172.1 MHz 0 –120 15.625 0 61.44 FREQUENCY (MHz) 31.25 46.875 62.5 FREQUENCY (MHz) Figure 35. AD9640-125, Two 64 k WCDMA Carriers with fIN = 170 MHz, fS = 122.88 MSPS Figure 38. AD9640 Noise Power Ratio (NPR) 0 100 150 MSPS 29.1MHz @–7dBFS 32.1MHz @–7dBFS SFDR = 86.1dBc (93dBFS) –20 95 SFDR—SIDE A –40 SNR/SFDR (dBc) AMPLITUDE (dBFS) 30 FREQUENCY (MHz) –60 –80 90 85 SFDR—SIDE B 80 SNR—SIDE B SNR—SIDE A –120 0 10 20 30 40 50 60 06547-067 75 06547-065 –100 70 70 0 FREQUENCY (MHz) 25 50 75 100 125 150 CLOCK FREQUENCY (Msps) Figure 36. AD9640-150 Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz Figure 39. AD9640-125 Single-Tone SNR/SFDR vs. Clock Frequency (fS) with fIN = 2.3 MHz Rev. B | Page 23 of 52 AD9640 10 100 1.3 LSB rms 95 SFDR DCS ON 90 SNR/SFDR (dBc) NUMBER OF HITS (1M) 8 6 4 85 SFDR DCS OFF 80 SNR DCS ON 75 70 2 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 OUTPUT CODE N+4 60 20 06547-079 0 Figure 43. AD9640 SNR/SFDR vs. Duty Cycle with fIN = 10.3 MHz 2.0 90 SFDR 1.5 1.0 85 SNR/SFDR (dBc) 0.5 0 –0.5 –1.0 80 75 SNR 06547-068 –1.5 –2.0 0 2048 4096 6144 8192 70 0.5 10,240 12,288 14,336 16,384 OUTPUT CODE 0.4 0.3 0.2 0.1 0 –0.1 –0.2 06547-069 –0.3 0 2048 4096 6144 8192 0.8 0.9 1.0 1.1 1.2 1.3 Figure 44. AD9640 SNR/SFDR vs. Input Common Mode Voltage (VCM) with fIN = 30 MHz 0.5 –0.5 0.7 INPUT COMMON-MODE VOLTAGE (V) Figure 41. AD9640 INL with fIN = 10.3 MHz –0.4. 0.6 06547-091 INL ERROR (LSB) 80 60 DUTY CYCLE (%) Figure 40. AD9640 Grounded Input Histogram DNL ERROR (LSB) 40 06547-090 SNR DCS OFF 65 10,240 12,288 14,336 16,384 OUTPUT CODE Figure 42. AD9640 DNL with fIN = 10.3 MHz Rev. B | Page 24 of 52 AD9640 THEORY OF OPERATION The AD9640 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation to 450 MHz analog input is permitted but occurs at the expense of increased ADC distortion. In nondiversity applications, the AD9640 can be used as a baseband receiver, where one ADC is used for I input data and the other is used for Q input data. Synchronizaton capability is provided to allow synchronized timing between multiple channels or multiple devices. Programming and control of the AD9640 are accomplished using a 3-bit SPI-compatible serial interface. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In intermediate frequency (IF) undersampling applications, any shunt capacitors should be reduced. In combination with the driving source impedance, they limit the input bandwidth. See the AN-742 Application Note, Frequency Domain Response of Switched-Capacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, “Transformer-Coupled Front-End for Wideband A/D Converters” for more information on this subject. S ADC ARCHITECTURE CH The AD9640 architecture consists of a dual front-end sampleand-hold amplifier (SHA), followed by a pipelined, switched capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, and the remaining stages operate on preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage of each channel contains a differential SHA that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, carries out error correction, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing adjustment of the output voltage swing. During power-down, the output buffers go into a high impedance state. ANALOG INPUT CONSIDERATIONS The analog input to the AD9640 is a differential switched capacitor SHA that has been designed for optimum performance while processing a differential input signal. The clock signal alternatively switches the SHA between sample mode and hold mode (see Figure 45). When the SHA is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within ½ of a clock cycle. S CS VIN+ CPIN, PAR S H CS VIN– S 06547-024 CH CPIN, PAR Figure 45. Switched-Capacitor SHA Input For best dynamic performance, the source impedances driving VIN+ and VIN− should be matched. An internal differential reference buffer creates positive and negative reference voltages that define the input span of the ADC core. The span of the ADC core is set by the buffer to 2 × VREF. Input Common Mode The analog inputs of the AD9640 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.55 × AVDD is recommended for optimum performance, but the device functions over a wider range with reasonable performance (see Figure 44). An on-board common-mode voltage reference is included in the design and is available from the CML pin. Optimum performance is achieved when the common-mode voltage of the analog input is set by the CML pin voltage (typically 0.55 × AVDD). The CML pin must be decoupled to ground by a 0.1 μF capacitor, as described in the Applications Information section. Differential Input Configurations Optimum performance is achieved while driving the AD9640 in a differential input configuration. For baseband applications, the AD8138 differential driver provides excellent performance and a flexible interface to the ADC. Rev. B | Page 25 of 52 AD9640 The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9640 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. An alternative to using a transformer coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 50. See the AD8352 data sheet for more information. 499Ω VIN+ In any configuration, the value of Shunt Capacitor C is dependent on the input frequency and source impedance and may need to be reduced or removed. Table 13 displays recommended values to set the RC network. However, these values are dependent on the input signal and should be used only as a starting guide. AVDD 499Ω R CML VIN– 06547-025 523Ω AD9640 C AD8138 499Ω Table 13. Example RC Network Figure 46. Differential Input Configuration Using the AD8138 R 2V p-p C AD9640 R A single-ended input can provide adequate performance in cost sensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the source impedances on each input are matched, there should be little effect on SNR performance. Figure 48 details a typical single-ended input configuration. CML 06547-026 VIN– 0.1µF Figure 47. Differential Transformer-Coupled Configuration The signal characteristics must be considered when selecting a transformer. Most RF transformers saturate at frequencies below a few MHz, and excessive signal power can also cause core saturation, which leads to distortion. 10µF R 49.9Ω 1V p-p 0.1µF 0.1µF AD9640 C 1kΩ 10µF VIN+ 1kΩ AVDD R VIN– 1kΩ Figure 48. Single-Ended Input Configuration 0.1µF 0.1µF AVDD 1kΩ At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9640. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 49 for an example). R VIN+ 2V p-p 25Ω PA S S P AD9640 C 25Ω 0.1µF 0.1µF R VIN– CML Figure 49. Differential Double Balun Input Configuration VCC 0.1µF 0Ω ANALOG INPUT 16 0.1µF 8, 13 1 11 0.1µF RD RG 3 200Ω AD8352 10 4 5 ANALOG INPUT 0.1µF 0Ω R VIN+ 2 CD C Differential (pF) 15 5 5 Open Single-Ended Input Configuration VIN+ 49.9Ω R Series (Ω Each) 33 33 15 15 Frequency Range (MHz) 0 to 70 70 to 200 200 to 300 >300 For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 47. To bias the analog input, the CML voltage can be connected to the center tap of the transformer’s secondary winding. 06547-028 0.1µF 06547-071 R 49.9Ω C 0.1µF 200Ω R AD9640 VIN– CML 14 0.1µF 0.1µF Figure 50. Differential Input Configuration Using the AD8352 Rev. B | Page 26 of 52 06547-070 1V p-p AD9640 VOLTAGE REFERENCE VIN+A/VIN+B VIN–A/VIN–B A stable and accurate voltage reference is built into the AD9640. The input range can be adjusted by varying the reference voltage applied to the AD9640, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in the next few sections. The Reference Decoupling section describes the best practices PCB layout of the reference. ADC CORE VREF 1.0µF 0.1µF R2 SELECT LOGIC SENSE Internal Reference Connection AD9640 06547-031 0.5V R1 Figure 52. Programmable Reference Configuration If the internal reference of the AD9640 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 53 shows how the internal reference voltage is affected by loading. 0 VREF = 0.5V R2 ⎞ VREF = 0.5 × ⎛⎜1 + ⎟ R1 ⎠ ⎝ The input range of the ADC always equals twice the voltage at the reference pin for either an internal or an external reference. VIN+A/VIN+B VIN–A/VIN–B ADC CORE –0.25 VREF = 1V –0.50 –0.75 –1.00 –1.25 0 0.5 1.0 1.5 LOAD CURRENT (mA) VREF 1.0µF 2.0 06547-080 REFERENCE VOLTAGE ERROR (%) A comparator within the AD9640 detects the potential at the SENSE pin and configures the reference into four possible modes, which are summarized in Table 14. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 51), setting VREF to 1 V. Connecting the SENSE pin to VREF switches the reference amplifier output to the SENSE pin, completing the loop and providing a 0.5 V reference output. If a resistor divider is connected external to the chip, as shown in Figure 52, the switch again sets to the SENSE pin. This puts the reference amplifier in a noninverting mode with the VREF output defined as Figure 53. VREF Accuracy vs. Load 0.1µF External Reference Operation SELECT LOGIC The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 54 shows the typical drift characteristics of the internal reference in 1 V mode. SENSE AD9640 06547-030 0.5V Figure 51. Internal Reference Configuration Table 14. Reference Configuration Summary Selected Mode External Reference Internal Fixed Reference Programmable Reference SENSE Voltage AVDD VREF 0.2 V to VREF Resulting VREF (V) N/A 0.5 Internal Fixed Reference AGND to 0.2 V 1.0 R2 ⎞ (see Figure 52) ⎛ 0 .5 × ⎜ 1 + ⎟ R1 ⎠ ⎝ Resulting Differential Span (V p-p) 2 × External Reference 1.0 2 × VREF 2.0 Rev. B | Page 27 of 52 AD9640 This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9640, while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. 2.0 1.5 1.0 0 MINI-CIRCUITS ADT1–1WT, 1:1Z 0.1µF XFMR 0.1µF –0.5 CLOCK INPUT –1.0 CLK+ ADC AD9640 100Ω 50Ω 0.1µF CLK– –1.5 –2.5 –40 –20 0 20 40 60 06547-035 –2.0 SCHOTTKY DIODES: HSMS2822 0.1µF 06547-099 REFERENCE VOLTAGE ERROR (mV) 2.5 Figure 56. Transformer Coupled Differential Clock (Up to 200 MHz) 80 TEMPERATURE (°C) Figure 54. Typical VREF Drift CLOCK INPUT CONSIDERATIONS For optimum performance, the AD9640 sample clock inputs CLK+, and CLK− should be clocked with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 55) and require no external bias. 1nF 0.1µF CLOCK INPUT CLK+ ADC AD9640 50Ω 0.1µF 1nF CLK– SCHOTTKY DIODES: HSMS2822 Figure 57. Balun Coupled Differential Clock (Up to 625 MHz) If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 58. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance. AVDD 0.1µF 0.1µF CLOCK INPUT CLK+ 1.2V 0.1µF CLOCK INPUT 2pF 0.1µF ADC AD9640 CLK– 50kΩ 50kΩ 240Ω 240Ω Figure 58. Differential PECL Sample Clock (Up to 625 MHz) 06547-034 2pF 100Ω 06547-036 CLK– AD951x PECL DRIVER A third option is to ac-couple a differential LVDS signal to the sample clock input pins, as shown in Figure 59. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516 clock drivers offer excellent jitter performance. Figure 55. Equivalent Clock Input Circuit Clock Input Options The AD9640 has a very flexible clock input structure. Clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, the jitter of the clock source is of the most concern, as described in the Jitter Considerations section. Figure 56 and Figure 57 show two preferred methods for clocking the AD9640 (at clock rates to 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using either an RF balun or an RF transformer. The RF balun configuration is recommended for clock frequencies between 125 MHz and 625 MHz, and the RF transformer is recommended for clock frequencies from 10 MHz to 200MHz. The back-to-back Schottky diodes across the transformer/balun secondary limit clock excursions into the AD9640 to approximately 0.8 V p-p differential. 0.1µF 0.1µF CLOCK INPUT CLK+ 0.1µF CLOCK INPUT AD951x LVDS DRIVER 100Ω 0.1µF ADC AD9640 CLK– 50kΩ 50kΩ 06547-037 CLK+ 06547-101 When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 6 kΩ load (see Figure 15). The internal buffer generates the positive and negative full-scale references for the ADC core. Therefore, the external reference must be limited to a maximum of 1 V. Figure 59. Differential LVDS Sample Clock (Up to 625 MHz) In some applications, it may be acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be directly driven from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 60). Rev. B | Page 28 of 52 AD9640 CLK+ can be directly driven from a CMOS gate. Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages up to 3.6 V, making the selection of the drive logic voltage very flexible. VCC 0.1µF 1kΩ CLOCK INPUT OPTIONAL 0.1µF 100Ω AD951x CMOS DRIVER CLK+ ADC AD9640 1kΩ 50Ω1 CLK– 150Ω 39kΩ 06547-038 0.1µF RESISTOR IS OPTIONAL Figure 60. Single-Ended 1.8 V CMOS Sample Clock (Up to 150 MSPS) Jitter in the rising edge of the input is still of paramount concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz nominally. The loop has a time constant associated with it that needs to be considered where the clock rate can change dynamically. This requires a wait time of 1.5 μs to 5 μs after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR from the low frequency SNR (SNRLF) at a given input frequency (fINPUT) due to jitter (tJRMS) can be calculated by VCC 50Ω1 1kΩ AD951x CMOS DRIVER 1kΩ 0.1µF CLK+ ADC AD9640 SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( − SNRLF /10) ] 06547-039 CLK– 150Ω RESISTOR IS OPTIONAL Figure 61. Single-Ended 3.3 V CMOS Sample Clock (Up to 150 MSPS) Input Clock Divider In the equation, the rms aperture jitter represents the clock input jitter specification. IF undersampling applications are particularly sensitive to jitter, as illustrated in Figure 62. 75 The AD9640 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. If a divide ratio other than 1 is selected, the duty cycle stabilizer is automatically enabled. MEASURED PERFORMANCE 65 SNR (dBc) The AD9640 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. 0.05ps 70 0.20ps 60 0.5ps 55 1.0ps 50 1.50ps 2.00ps 45 40 Clock Duty Cycle 2.50ps 3.00ps 1 10 100 1000 INPUT FREQUENCY (MHz) Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. 06547-041 0.1µF CLOCK INPUT OPTIONAL 0.1µF 100Ω Figure 62. SNR vs. Input Frequency and Jitter The AD9640 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9640. Noise and distortion performance are nearly flat for a wide range of duty cycles with the DCS on, as shown in Figure 43. The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9640. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. See the AN-501 Application Note and AN-756 Application Note for more information about jitter performance as it relates to ADCs. Rev. B | Page 29 of 52 AD9640 IAVDD 0.5 0.3 TOTAL POWER 0.5 0.2 IDRVDD 0.25 0 25 50 75 100 125 0 150 0.5 TOTAL POWER 0.5 0.2 IDRVDD 0.25 0.1 IDVDD 0 0 25 50 75 100 SUPPLY CURRENT (A) 0.3 0.75 0 125 ENCODE FREQUENCY (MHz) Figure 64. AD9640-125 Power and Current vs. Clock Frequency 06547-075 TOTAL POWER (W) 0.4 IAVDD 25 0 50 75 100 ENCODE FREQUENCY (MHz) Figure 65. AD9640-105 Power and Current vs. Clock Frequency 0.75 0.3 IAVDD 0.5 0.2 TOTAL POWER 0.1 0.25 IDRVDD IDVDD 0 0 20 40 60 0 80 ENCODE FREQUENCY (MHz) ENCODE FREQUENCY (MHz) 1.0 0 0 Figure 66. AD9640-80 Power and Current vs. Clock Frequency Figure 63. AD9640-150 Power and Current vs. Clock Frequency 1.25 IDRVDD IDVDD 0.1 IDVDD 0 SUPPLY CURRENT (A) 0.75 0.4 06547-076 TOTAL POWER (W) 1.0 0.1 0.25 TOTAL POWER (W) Reducing the capacitive load presented to the output drivers can minimize digital power consumption. The data in Figure 63 was taken with the same operating conditions as the Typical Performance Characteristics, with a 5 pF load on each output driver. SUPPLY CURRENT (A) where N is the number of output bits (30 in the case of the AD9640 with the FD bits disabled). This maximum current occurs when every output bit switches on every clock cycle, that is, a fullscale square wave at the Nyquist frequency of fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. 0.2 SUPPLY CURRENT (A) IDRVDD = VDRVDD × CLOAD × fCLK × N TOTAL POWER 0.5 06547-074 TOTAL POWER (W) The maximum DRVDD current (IDRVDD) can be calculated as IAVDD 0.3 0.75 06547-073 As shown in Figure 63, the power dissipated by the AD9640 is proportional to its sample rate. In CMOS output mode, the digital power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. 1.25 0.4 1 POWER DISSIPATION AND STANDBY MODE By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9640 is placed in power-down mode. In this state, the ADC typically dissipates 2.5 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9640 to its normal operational mode. Note that PDWN is referenced to the digital supplies (DRVDD) and should not exceed that supply voltage. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map Register Description section for more details. Rev. B | Page 30 of 52 AD9640 DIGITAL OUTPUTS Digital Output Enable Function (OEB) The AD9640 output drivers can be configured to interface with 1.8 V to 3.3 V CMOS logic families by matching DRVDD to the digital supply of the interfaced logic. The AD9640 can also be configured for LVDS outputs using a DRVDD supply voltage of 1.8 V. The AD9640 has a flexible three-state ability for the digital output pins. The three-state mode is enabled using the SMI SDO/OEB pin or through the SPI interface. If the SMI SDO/OEB pin is low, the output data drivers are enabled. If the SMI SDO/OEB pin is high, the output data drivers are placed in a high impedance state. This OEB function is not intended for rapid access to the data bus. Note that OEB is referenced to the digital supplies (DRVDD) and should not exceed that supply voltage. In CMOS output mode, the output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause current glitches on the supplies that may affect converter performance. Applications requiring the ADC to drive large capacitive loads or large fan-outs may require external buffers or latches. The output data format can be selected for either offset binary or twos complement by setting the SCLK/DFS pin when operating in the external pin mode (see Table 15). As detailed in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, the data format can be selected for offset binary, twos complement, or gray code when using the SPI control. Table 15. SCLK/DFS Mode Selection (External Pin Mode) Voltage at Pin AGND AVDD SCLK/DFS Offset binary (default) Twos complement SDIO/DCS DCS disabled DCS enabled (default) When using the SPI interface, the data and fast detect outputs of each channel can be independently three-stated by using the output enable bar bit in Register 0x14. TIMING The AD9640 provides latched data with a pipeline delay of twelve clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. The length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9640. These transients can degrade converter dynamic performance. The lowest typical conversion rate of the AD9640 is 10 MSPS. At clock rates below 10 MSPS, dynamic performance can degrade. Data Clock Output (DCO) The AD9640 provides two data clock output (DCO) signals intended for capturing the data in an external register. The data outputs are valid on the rising edge of DCO, unless the DCO clock polarity has been changed via the SPI. See Figure 2 and Figure 3 for a graphical timing description. Table 16. Output Data Format Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− Condition (V) < −VREF − 0.5 LSB = −VREF =0 = +VREF − 1.0 LSB > +VREF − 0.5 LSB Offset Binary Output Mode 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1111 Rev. B | Page 31 of 52 Twos Complement Mode 10 0000 0000 0000 10 0000 0000 0000 00 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1111 OVR 1 0 0 0 1 AD9640 ADC OVERRANGE AND GAIN CONTROL In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, latency of this function is of major concern. Highly pipelined converters can have significant latency. A good compromise is to use the output bits from the first stage of the ADC for this function. Latency for these output bits is very low, and overall resolution is not highly significant. Peak input signals are typically between full scale and 6 dB to 10 dB below full scale. A 3-bit or 4-bit output provides adequate range and resolution for this function. Using the SPI port, the user can provide a threshold above which an overrange output is active. As long as the signal is below that threshold, the output should remain low. The fast detect outputs can also be programmed via the SPI port so that one of the pins functions as a traditional overrange pin for customers who currently use this feature. In this mode, all 14 bits of the converter are examined in the traditional manner, and the output is high for the condition normally defined as overflow. In either mode, the magnitude of the data is considered in the calculation of the condition (but the sign of the data is not considered). The threshold detection responds identically to positive and negative signals outside the desired range (magnitude). FAST DETECT OVERVIEW The AD9640 contains circuitry to facilitate fast overrange detection, allowing very flexible external gain control implementations. Each ADC has four fast detect (FD) output pins that are used to output information about the current state of the ADC input level. The function of these pins is programmable via the fast detect mode select bits and the fast detect enable bit in Register 0x104, allowing range information to be output from several points in the internal datapath. These output pins can also be set up to indicate the presence of overrange or underrange conditions, according to programmable threshold levels. Table 17 shows the six configurations available for the fast detect pins. Table 17. Fast Detect Mode Select Bits Settings Fast Detect Mode Select Bits (Register 0x104[3:1]) 000 001 010 011 100 101 Information Presented on Fast Detect (FD) Pins of Each ADC1, 2 FD3 FD2 FD1 FD0 ADC fast magnitude (see Table 18) OR ADC fast magnitude (see Table 19) OR F_LT ADC fast magnitude (see Table 20) C_UT F_LT ADC fast magnitude (see Table 20) OR C_UT F_UT F_LT OR F_UT IG DG 1 The fast detect pins are FD0A/FD0B to FD3A/FD3B for the CMOS mode configuration and FD0+/FD0− to FD3+/FD3− for the LVDS mode configuration. 2 See the ADC Overrange (OR) and Gain Switching sections for more information about OR, C_UT, F_UT, F_LT, IG, and DG. ADC FAST MAGNITUDE When the fast detect output pins are configured to output the ADC fast magnitude (that is, when the fast detect mode select bits are set to 0b000), the information presented is the ADC level from an early converter stage with a latency of only two clock cycles (when in CMOS output mode). Using the fast detect output pins in this configuration provides the earliest possible level indication information. Because this information is provided early in the datapath, there is significant uncertainty in the level indicated. The nominal levels, along with the uncertainty indicated by the ADC fast magnitude, are shown in Table 18. Table 18. ADC Fast Magnitude Nominal Levels with Fast Detect Mode Select Bits = 000 ADC Fast Magnitude on FD[3:0] Pins 0000 0001 0010 0011 0100 0101 0110 0111 1000 Rev. B | Page 32 of 52 Nominal Input Magnitude Below FS (dB)