14-Bit, 80 MSPS/155 MSPS, 1.8 V
Serial Output Analog-to-Digital Converter (ADC)
AD9641
Data Sheet
FEATURES
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
AVDD
SDIO SCLK CSB
DRVDD
SPI
AD9641
PROGRAMMING DATA
DATA SERIALIZER,
ENCODER,
AND CML DRIVERS
VIN+
ADC
VIN–
VCM
REFERENCE
DOUT+
DOUT–
DSYNC+
DSYNC–
DATA RATE
MULTIPLIER
DUTY CYCLE
STABILIZER
MULTICHIP
SYNC
AGND
SYNC
CLK+
DIVIDE-BY-1
TO
DIVIDE-BY-8
PDWN
CLK–
DRGND
Figure 1.
The ADC output data is routed directly to the JESD204A serial
output port. This output is at CML voltage levels. A CMOS or
LVDS synchronization input (DSYNC) is provided.
Communications
Diversity radio systems
Multimode digital receivers (3G and 4G)
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
The AD9641 is available in a 32-lead LFCSP and is specified over
the industrial temperature range of −40°C to +85°C.
GENERAL DESCRIPTION
This product is protected by a U.S. patent.
The AD9641 is a 14-bit, 80 MSPS/155 MSPS analog-to-digital
converter (ADC) with a high speed serial output interface. The
AD9641 is designed to support communications applications
where high performance, combined with low cost, small size, and
versatility, is desired. The JESD204A high speed serial interface
reduces board routing requirements and lowers pin count
requirements for the receiving device.
PRODUCT HIGHLIGHTS
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth, differential sample-and-hold,
analog input amplifiers that support a variety of user-selectable
input ranges. An integrated voltage reference eases the design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converter to maintain excellent performance.
09210-001
JESD204A coded serial digital outputs
SNR = 73.7 dBFS at 70 MHz/80 MSPS
SNR = 72.8 dBFS at 70 MHz and 155 MSPS
SFDR = 94 dBc at 70 MHz and 80 MSPS
SFDR = 90 dBc at 70 MHz and 155 MSPS
Low power: 238 mW at 80 MSPS, 313 mW at 155 MSPS
1.8 V supply operation
Integer 1-to-8 input clock divider
IF sampling frequencies to 250 MHz
−148.6 dBFS/Hz input noise at 180 MHz and 80 MSPS
−148.1 dBFS/Hz input noise at 180 MHz and 155 MSPS
Programmable internal ADC voltage reference
Flexible analog input range: 1.4 V p-p to 2.1 V p-p
ADC clock duty cycle stabilizer (DCS)
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
The flexible power-down options allow significant power savings,
when desired.
Programming for setup and control is accomplished using a 3-wire
SPI-compatible serial interface.
1.
2.
3.
4.
5.
An on-chip PLL allows users to provide a single ADC
sampling clock. The PLL multiplies the ADC sampling clock
to produce the corresponding JESD204A data rate clock.
The configurable JESD204A output block coded data rate
supports up to 1.6 Gbps.
A proprietary differential input maintains excellent SNR
performance for input frequencies of up to 250 MHz.
Operation is from a single 1.8 V power supply.
The standard serial port interface (SPI) supports various
product features and functions, such as data formatting
(offset binary, twos complement, or Gray coding), controlling the clock DCS, power-down, test modes, voltage
reference mode, and serial output configuration.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
AD9641
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Reference ....................................................................... 19
Applications ....................................................................................... 1
Clock Input Considerations ...................................................... 19
General Description ......................................................................... 1
Chip Synchronization ................................................................ 20
Functional Block Diagram .............................................................. 1
Power Dissipation and Standby Mode .................................... 21
Product Highlights ........................................................................... 1
Digital Outputs ........................................................................... 21
Revision History ............................................................................... 2
Built-In Self-Test (BIST) and Output Test .................................. 25
Specifications..................................................................................... 3
Built-In Self-Test (BIST) ............................................................ 25
ADC DC Specifications ............................................................... 3
Output Test Modes ..................................................................... 25
ADC AC Specifications ............................................................... 4
Serial Port Interface (SPI) .............................................................. 27
Digital Specifications ................................................................... 5
Configuration Using the SPI ..................................................... 27
Switching Specifications .............................................................. 6
Hardware Interface..................................................................... 28
Timing Specifications .................................................................. 7
SPI Accessible Features .............................................................. 28
Absolute Maximum Ratings............................................................ 8
Memory Map .................................................................................. 29
Thermal Characteristics .............................................................. 8
Reading the Memory Map Register Table............................... 29
ESD Caution .................................................................................. 8
Memory Map Register Table ..................................................... 29
Pin Configuration and Function Descriptions ............................. 9
Memory Map Register Descriptions ........................................ 32
Typical Performance Characteristics ........................................... 10
Applications Information .............................................................. 35
Equivalent Circuits ......................................................................... 16
Design Guidelines ...................................................................... 35
Theory of Operation ...................................................................... 17
Outline Dimensions ....................................................................... 36
ADC Architecture ...................................................................... 17
Ordering Guide .......................................................................... 36
Analog Input Considerations.................................................... 17
REVISION HISTORY
1/12—Rev. A to Rev. B
Change to General Description Section ........................................ 1
Changes to Table 2 ............................................................................ 4
8/11—Rev. 0 to Rev. A
Added Model -155 ......................................................... Throughout
Changes to Features.......................................................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 4
Changes to Table 4 ............................................................................ 6
Changes to Figure 11 to Figure 14 Captions ............................... 11
Added Figure 23 to Figure 40; Renumbered Sequentially ........ 13
Changes to Clock Input Considerations Section ....................... 19
Changes to Digital Outputs and Timing Section ....................... 23
Moved Figure 65 and Figure 66 .................................................... 23
Added Figure 68 ............................................................................. 24
Changes to Output Test Modes Section ...................................... 25
Changes to SPI Accessible Features Section ............................... 28
Changes to Addr (Hex) 0x02, Table 17 ........................................ 29
Changes to Ordering Guide .......................................................... 36
7/10—Revision 0: Initial Version
Rev. B | Page 2 of 36
Data Sheet
AD9641
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
ANALOG INPUT
Input Span
Input Capacitance2
Input Resistance
VCM OUTPUT LEVEL
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1
POWER CONSUMPTION
Sine Wave Input1
Standby Power3
Power-Down Power
1
2
3
Temperature
Full
Full
Full
Full
Full
25°C
Full
25°C
Min
14
−7
Full
Full
Guaranteed
±2
−2.5
±10
+1
±0.55
Min
14
AD9641-155
Typ
Max
Guaranteed
±2
−2.5
±0.5
±0.5
±2
±35
0.7
±2
±35
0.7
ppm/°C
ppm/°C
LSB rms
±0.3
±1.1
1.383
±1.2
2.087
1.383
0.88
1.75
6
20
0.9
0.92
1.7
1.7
1.8
1.8
1.9
1.9
Full
Full
96
36
Full
Full
Full
238
56
7
2.087
0.87
1.75
5
20
0.9
0.92
V p-p
pF
kΩ
V
1.7
1.7
1.8
1.8
1.9
1.9
V
V
100
40
121
51
132
54
mA
mA
252
310
56
7
335
mW
mW
mW
18
Measured with a low input frequency, full-scale sine wave.
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
Standby power is measured with a dc input and with the CLK pins inactive (set to AVDD or AGND).
Rev. B | Page 3 of 36
±11
+1
±0.55
Unit
Bits
mV
% FSR
LSB
LSB
LSB
LSB
−7.5
±0.3
Full
Full
25°C
Full
Full
Full
Full
AD9641-80
Typ
Max
18
AD9641
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, DCS enabled,
unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 10 MHz
fIN = 70 MHz
fIN = 180 MHz
fIN = 220 MHz
TWO-TONE SFDR
fIN = 30 MHz (−7 dBFS ), 33 MHz (−7 dBFS )
fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS )
ANALOG INPUT BANDWIDTH2
1
2
Temperature
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
Min
AD9641-80
Typ
Max
Min
73.8
73.7
72.6
AD9641-155
Typ
Max
72.0
71.7
71.3
71.8
dBFS
dBFS
dBFS
dBFS
dBFS
69.8
71.3
71.2
73.7
73.6
72.5
71.0
70.6
70.2
Unit
71.2
70.1
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
12.0
11.9
11.8
11.5
11.5
11.4
11.4
11.4
Bits
Bits
Bits
Bits
25°C
25°C
25°C
Full
25°C
−94
−94
−91
−91
−91
−90
−90
−89
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
Full
25°C
94
94
91
91
91
90
71.4
68.7
−80
80
−80
dBc
dBc
dBc
dBc
dBc
80
90
89
25°C
25°C
25°C
Full
25°C
−98
−98
−96
−96
−98
−94
−90
−90
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
93
89
780
89
89
780
dBc
dBc
MHz
−90
−87
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
The analog input bandwidth parameter specifies the −3 dB input BW of the AD9641 input. The usable full-scale BW of the part with good performance is 250 MHz.
Rev. B | Page 4 of 36
Data Sheet
AD9641
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
DSYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
LOGIC INPUT (CSB)1
Logic Compliance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK)2
Logic Compliance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Input Capacitance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
Typ
Max
CMOS/LVDS/LVPECL
0.9
0.3
AGND
0.9
−100
−100
8
3.6
AVDD
1.4
+100
+100
4
10
12
CMOS
0.9
AGND
1.2
AGND
−100
−100
12
AVDD
AVDD
0.6
+100
+100
1
16
20
CMOS/LVDS
0.9
AGND
1.2
AGND
−100
−100
12
AVDD
AVDD
0.6
+100
+100
1
16
20
Unit
V
V p-p
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
V
V
V
V
μA
μA
pF
kΩ
CMOS
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
2.1
0.6
+10
132
V
V
μA
μA
kΩ
pF
2.1
0.6
−135
+10
V
V
μA
μA
kΩ
pF
26
2
CMOS
Rev. B | Page 5 of 36
26
2
AD9641
Data Sheet
Parameter
LOGIC INPUT/OUTPUT (SDIO)1
Logic Compliance
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
1
2
Temperature
Min
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
Typ
Max
Unit
2.1
0.6
+10
128
V
V
μA
μA
kΩ
pF
1.1
1.05
V
V
CMOS
26
5
Full
Full
Full
CML
0.8
DRVDD/2
0.6
0.75
Pull up.
Pull down.
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and DCS enabled,
unless otherwise noted.
Table 4.
Parameter
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
CLK Period—Divide-by-1 Mode (tCLK)
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
Data Output Period or UI (Unit Interval)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (tLOCK)
Wake Up Time (Standby)
Wake Up Time (Power-Down)2
Pipeline Delay (Latency)
Data Rate (NRZ)
Deterministic Jitter
Random Jitter at 1.6 Gbps
Random Jitter at 3.1 Gbps
Output Rise/Fall Time
TERMINATION CHARACTERISTICS
Differential Termination Resistance
OUT-OF-RANGE RECOVERY TIME
1
2
Temperature
Min
Full
Full
Full
40
12.5
Full
Full
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
3.75
5.95
0.8
AD9641-80
Typ
Max
640
80
6.25
6.25
8.75
6.55
Min
AD9641-155
Typ
Max
40
6.45
1.935
3.065
0.8
0.78
0.125
3.225
3.225
640
155
MHz
MSPS
ns
4.515
3.385
ns
ns
ns
ns
ps rms
0.78
0.125
1/(20 × fCLK)
1/(20 × fCLK)
50
50
0.8
4
0.75
4
5
5
Unit
50
5.2
50
sec
%
UI
μs
μs
ms
CLK cycles
Gbps
ps
ps rms
ps rms
ps
100
2
100
2
Ω
CLK cycles
2.5
23
2.5
24
1.6
40
9.5
Conversion rate is the clock rate after the divider.
Wake-up time is defined as the time required to return to normal operation from power-down mode.
Rev. B | Page 6 of 36
23
24
3.1
40
Data Sheet
AD9641
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
Test Conditions
Limit
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
0.30 ns typ
0.30 ns typ
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge
Time required for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge
2 ns min
2 ns min
40 ns min
2 ns min
2 ns min
10 ns min
10 ns min
10 ns min
10 ns min
Timing Diagrams
SAMPLE
N
N – 23
ANALOG
INPUT
SIGNAL
N – 22
N+1
N – 21
N–1
N – 20
CLK–
CLK+
CLK–
CLK+
DOUT+
SAMPLE N – 23
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 22
ENCODED INTO 2
8b/10b SYMBOLS
SAMPLE N – 21
ENCODED INTO 2
8b/10b SYMBOLS
Figure 2. Data Output Timing
CLK+
tHSYNC
09210-003
tSSYNC
SYNC
Figure 3. SYNC Input Timing Requirements
Rev. B | Page 7 of 36
09210-002
DOUT–
AD9641
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
ELECTRICAL
AVDD to AGND
DRVDD to AGND
VIN+, VIN− to AGND
CLK+, CLK− to AGND
SYNC to AGND
VCM to AGND
CSB to AGND
SCLK to AGND
SDIO to AGND
PDWN to AGND
DOUT+, DOUT− to AGND
DSYNC+, DSYNC− to AGND
ENVIRONMENTAL
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−40°C to +85°C
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints and maximizes the
thermal capability of the package.
Table 7. Thermal Resistance
Package Type
32-Lead LFCSP
5 mm × 5 mm
(CP-32-12)
Airflow
Velocity
(m/sec)
0
1.0
2.5
θJA1, 2
36
32
28
θJC1, 3
3
θJB1, 4
20
Unit
°C/W
°C/W
°C/W
1
Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
2
3
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. As shown in Table 7, airflow improves heat dissipation,
which reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces θJA.
150°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. B | Page 8 of 36
Data Sheet
AD9641
32
31
30
29
28
27
26
25
AVDD
AVDD
AVDD
VIN+
VIN–
AVDD
AVDD
VCM
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
PIN 1
INDICATOR
AD9641
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
PDWN
DNC
CSB
SCLK
SDIO
DRVDD
DRVDD
DRGND
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD
MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
09210-004
DSYNC–
DSYNC+
DRGND
DRVDD
DRGND
DOUT–
DOUT+
DRVDD
9
10
11
12
13
14
15
16
AVDD
DNC
AVDD
CLK+
CLK–
AVDD
SYNC
AVDD
Figure 4. LFCSP Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
ADC Power Supplies
12, 16, 18, 19
1, 3, 6, 8, 26, 27, 30, 31, 32
2, 23
11, 13, 17
0
ADC Analog
29
28
25
4
5
Digital Inputs
7
10
9
Digital Outputs
15
14
SPI Control
21
20
22
ADC Configuration
24
Mnemonic
Type
Description
DRVDD
AVDD
DNC
DRGND
AGND, Exposed pad
Supply
Supply
Driver ground
Ground
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
Do Not Connect.
Digital Driver Supply Ground.
The exposed thermal pad on the bottom of the package provides
the analog ground for the part. This exposed pad must be connected
to ground for proper operation.
VIN+
VIN−
VCM
CLK+
CLK−
Input
Input
Output
Input
Input
Differential Analog Input Pin (+).
Differential Analog Input Pin (−).
Common-Mode Level Bias Output.
ADC Clock Input—True.
ADC Clock Input—Complement.
SYNC
DSYNC+
Input
Input
DSYNC−
Input
Input Clock Divider Synchronization Pin.
Active Low JESD204A LVDS Sync Input—True/Active Low
JESD204A CMOS Sync Input.
Active Low JESD204A LVDS Sync Input—Complement.
DOUT+
DOUT−
Output
Output
CML Output Data—True.
CML Output Data—Complement.
SCLK
SDIO
CSB
Input
Input/output
Input
SPI Serial Clock.
SPI Serial Data I/O.
SPI Chip Select (Active Low).
PDWN
Input
Power-Down Input. Using the SPI interface, this input can be
configured as power-down or standby.
Rev. B | Page 9 of 36
AD9641
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = maximum sample rate per speed grade, DCS enabled, 1.75 V p-p differential input, VIN =
−1.0 dBFS, and 32k sample, TA = 25°C, unless otherwise noted.
0
0
80MSPS
10.1MHz @ –1dBFS
SNR = 73.0dB (74.0dBFS)
SFDR = 95dBc
–20
–40
AMPLITUDE (dBFS)
–60
–80
THIRD HARMONIC
–100
0
10
20
30
40
FREQUENCY (MHz)
–140
0
10
20
30
Figure 8. AD9641-80 Single-Tone FFT with fIN = 140.1 MHz
0
0
80MSPS
30.1MHz @ –1dBFS
SNR = 72.7dB (73.7dBFS)
SFDR = 94dBc
–60
SECOND HARMONIC
–80
THIRD HARMONIC
–100
–40
–60
SECOND HARMONIC
–80
–100
–120
10
20
30
40
FREQUENCY (MHz)
–140
09210-006
0
0
10
20
30
Figure 9. AD9641-80 Single-Tone FFT with fIN = 180.1 MHz
0
0
80MSPS
70.1MHz @ –1dBFS
SNR = 72.5dB (73.5dBFS)
SFDR = 94.0dBc
AMPLITUDE (dBFS)
–60
SECOND HARMONIC
–80
THIRD HARMONIC
–40
–60
THIRD HARMONIC
–80
–100
–120
–120
0
10
20
30
FREQUENCY (MHz)
40
09210-007
–100
–140
80MSPS
220.1MHz @ –1dBFS
SNR = 71.1dB (72.1dBFS)
SFDR = 92dBc
–20
–40
40
FREQUENCY (MHz)
Figure 6. AD9641-80 Single-Tone FFT with fIN = 30.1 MHz
–20
40
09210-009
–120
–140
80MSPS
180.1MHz @ –1dBFS
SNR = 71.6dB (72.6dBFS)
SFDR = 93dBc
–20
–40
40
FREQUENCY (MHz)
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–100
Figure 5. AD9641-80 Single-Tone FFT with fIN = 10.1 MHz
–20
AMPLITUDE (dBFS)
–80
–120
09210-005
–140
–60
09210-008
–120
–40
09210-010
AMPLITUDE (dBFS)
–20
80MSPS
140.3MHz @ –1dBFS
SNR = 72.2dB (73.2dBFS)
SFDR = 94.0dBc
–140
SECOND HARMONIC
0
10
20
30
FREQUENCY (MHz)
Figure 10. AD9641-80 Single-Tone FFT with fIN = 220.1 MHz
Figure 7. AD9641-80 Single-Tone FFT with fIN = 70.1 MHz
Rev. B | Page 10 of 36
Data Sheet
AD9641
100
120
95
SNR/SFDR (dBFS/dBc)
80
SFDR (dBFS)
SFDR (dBc)
SNR (dBFS)
SNR (dBc)
60
40
20
80
75
Figure 11. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 10.1 MHz, fS = 80 MSPS
–20
SFDR/IMD3 (dBc/dBFS)
100
SFDR (dBFS)
SFDR (dBc)
SNR (dBFS)
SNR (dBc)
40
150
200
250
Figure 14. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 2.0 V p-p Full Scale, fS = 80 MSPS
0
60
100
INPUT FREQUENCY (MHz)
120
80
50
09210-014
0
09210-011
–5
0
–20
–15
–10
–35
–30
–25
–100
–95
–90
–85
–80
–75
–70
–65
–60
–55
–50
–45
–40
65
INPUT AMPLITUDE (dBFS)
–40
–60
–80
SFDR (dBc)
IMD3 (dBc)
SFDR (dBFS)
IMD3 (dBFS)
–100
20
–120
–90
INPUT AMPLITUDE (dBFS)
09210-012
0
–20
–15
–10
–5
–50
–45
–40
–35
–30
–25
–100
–95
–90
–85
–80
–75
–70
–65
–60
–55
0
Figure 12. AD9641-80 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 180 MHz, fS = 80 MSPS
–78
–66
–54
–42
–30
–18
–6
INPUT AMPLITUDE (dBFS)
09210-015
SNR/SFDR (dBc/dBFS)
SNR @ –40°C
SFDR @ –40°C
SNR @ +25°C
SFDR @ +25°C
SNR @ +85°C
SFDR @ +85°C
85
70
0
Figure 15. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.9 MHz, fIN2 = 32.9 MHz, fS = 80 MSPS
0
100
95
–20
90
SFDR/IMD3 (dBc/dBFS)
SNR/SFDR (dBFS/dBc)
90
SNR @ –40°C
SFDR @ –40°C
SNR @ +25°C
SFDR @ +25°C
SNR @ +85°C
SFDR @ +85°C
85
80
75
–40
–60
–80
SFDR (dBc)
IMD3 (dBc)
SFDR (dBFS)
IMD3 (dBFS)
–100
70
0
50
100
150
INPUT FREQUENCY (MHz)
200
250
–120
–90
09210-013
65
Figure 13. AD9641-80 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1.75 V p-p Full Scale, fS = 80 MSPS
–78
–66
–54
–42
–30
INPUT AMPLITUDE (dBFS)
–18
–6
09210-016
SNR/SFDR (dBc/dBFS)
100
Figure 16. AD9641-80 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 80 MSPS
Rev. B | Page 11 of 36
AD9641
Data Sheet
0
14,000
80MSPS
29.9MHz @ –7dBFS
32.9MHz @ –7dBFS
SFDR = 94.4dBc (101.4dBFS)
–20
12,000
10,000
NUMBER OF HITS
–60
–80
8000
6000
–100
4000
–120
2000
0
10
20
30
40
FREQUENCY (MHz)
0
09210-017
–140
N
N+1 N+2 N+3 N+4
OUTPUT CODE
Figure 17. AD9641-80 Two-Tone FFT with fIN1 = 29.9 MHz and fIN2 = 32.9 MHz
Figure 20. AD9641-80 Grounded Input Histogram
1.0
0
80MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
SFDR = 91.9dBc (98.9dBFS)
–20
0.8
0.6
–40
0.4
INL ERROR (LSB)
AMPLITUDE (dBFS)
N–4 N–3 N–2 N–1
09210-020
AMPLITUDE (dBFS)
–40
–60
–80
0.2
0
–0.2
–0.4
–100
–0.6
–120
0
10
20
30
40
FREQUENCY (MHz)
–1.0
0
200
400
600
800
1000
1200
1400
1600
OUTPUT CODE
09210-021
–0.8
09210-018
–140
Figure 21. AD9641-80 INL with fIN = 30.3 MHz
Figure 18. AD9641-80 Two-Tone FFT with fIN1 = 169.1 MHz and
fIN2 = 172.1 MHz
0.50
100
SFDR
0.25
90
DNL ERROR (LSB)
SNR/SFDR (dBFS/dBc)
95
85
80
0
–0.25
75
50
55
60
65
70
75
80
SAMPLE RATE (MSPS)
–0.50
0
2000
4000
6000
8000
10,000 12,000 14,000 16,000
OUTPUT CODE
Figure 22. AD9641-80 DNL with fIN = 30.3 MHz
Figure 19. AD9641-80 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 70.1 MHz
Rev. B | Page 12 of 36
09210-022
45
09210-019
SNR
70
Data Sheet
AD9641
0
0
155MSPS
10.1MHz @ –1dBFS
SNR = 71.0dB (72.0dBFS)
SFDR = 95dBc
–20
–40
–60
AMPLITUDE (dBFS)
SECOND HARMONIC
THIRD HARMONIC
–80
–100
7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50
FREQUENCY (MHz)
7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50
FREQUENCY (MHz)
0
155MSPS
180.1MHz @ –1dBFS
SNR = 70.3dB (71.3dBFS)
SFDR = 92dBc
–20
–40
–60
AMPLITUDE (dBFS)
–40
THIRD HARMONIC
SECOND HARMONIC
–80
–100
–120
–60
THIRD HARMONIC
SECOND HARMONIC
–80
–100
–120
7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50
FREQUENCY (MHz)
–140
09210-123
0
Figure 24. AD9641-155 Single-Tone FFT with fIN = 30.1 MHz
0
7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50
FREQUENCY (MHz)
09210-126
AMPLITUDE (dBFS)
0
Figure 26. AD9641-155 Single-Tone FFT with fIN = 140.1 MHz
155MSPS
30.1MHz @ –1dBFS
SNR = 70.9dB (71.9dBFS)
SFDR = 95dBc
–20
Figure 27. AD9641-155 Single-Tone FFT with fIN = 180.1 MHz
0
0
155MSPS
70.1MHz @ –1dBFS
SNR = 70.7dB (71.7dBFS)
SFDR = 93dBc
–20
155MSPS
220.1MHz @ –1dBFS
SNR = 70.2dB (71.2dBFS)
SFDR = 89dBc
–20
–40
AMPLITUDE (dBFS)
–40
–60
THIRD HARMONIC
–80
SECOND HARMONIC
–100
–120
THIRD HARMONIC
–60
SECOND HARMONIC
–80
–100
–120
0
7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50
FREQUENCY (MHz)
09210-124
AMPLITUDE (dBFS)
–100
–140
09210-122
0
0
–140
–80
–120
Figure 23. AD9641-155 Single-Tone FFT with fIN = 10.1 MHz
–140
THIRD HARMONIC
SECOND HARMONIC
09210-125
–120
–60
Figure 25. AD9641-155 Single-Tone FFT with fIN = 70.1 MHz
–140
0
7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50
FREQUENCY (MHz)
Figure 28. AD9641-155 Single-Tone FFT with fIN = 220.1 MHz
Rev. B | Page 13 of 36
09210-127
AMPLITUDE (dBFS)
–40
–140
155MSPS
140.1MHz @ –1dBFS
SNR = 70.7dB (71.7dBFS)
SFDR = 93dBc
–20
AD9641
Data Sheet
120
100
SFDR (dBFS)
95
80
SNR/SFDR (dBFS AND dBc)
SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
20
SNR @ –40°C
SFDR @ –40°C
SNR @ +25°C
SFDR @ +25°C
SNR @ +85°C
SFDR @ +85°C
85
80
75
70
–80
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBFS)
–20
–10
0
65
09210-128
0
–90
90
Figure 29. AD9641-155 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 10.1 MHz, fS = 155 MSPS
0
50
100
150
200
INPUT FREQUENCY (MHz)
250
300
09210-131
SNR/SFDR (dBc AND dBFS)
100
Figure 32. AD9641-155 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 2.0 V p-p Full Scale, fS = 155 MSPS
0
120
SFDR (dBFS)
–20
80
SFDR/IMD3 (dBc AND dBFS)
SNR/SFDR (dBc AND dBFS)
100
SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
–40
SFDR (dBc)
–60
IMD3 (dBc)
–80
–100
20
SFDR (dBFS)
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBFS)
–20
–10
0
09210-129
–80
–120
–90
Figure 30. AD9641-155 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 180 MHz, fS = 155 MSPS
–66
–54
–42
–30
INPUT AMPLITUDE (dBFS)
–18
–6
Figure 33. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.9 MHz, fIN2 = 32.9 MHz, fS = 155 MSPS
0
100
95
–20
SFDR/IMD3 (dBc AND dBFS)
SNR/SFDR (dBFS AND dBc)
–78
09210-132
IMD3 (dBFS)
0
–90
90
SNR @ –40°C
SFDR @ –40°C
SNR @ +25°C
SFDR @ +25°C
SNR @ +85°C
SFDR @ +85°C
85
80
75
–40
SFDR (dBc)
–60
IMD3 (dBc)
–80
SFDR (dBFS)
–100
70
50
100
150
200
INPUT FREQUENCY (MHz)
250
300
09210-130
0
–120
–90
Figure 31. AD9641-155 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1.75 V p-p Full Scale, fS = 155 MSPS
–78
–66
–54
–42
–30
INPUT AMPLITUDE (dBFS)
–18
–6
09210-133
IMD3 (dBFS)
65
Figure 34. AD9641-155 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 155 MSPS
Rev. B | Page 14 of 36
Data Sheet
AD9641
0
6000
155MSPS
29.9MHz @ –7dBFS
32.9MHz @ –7dBFS
SFDR = 88.7dBc (95.7dBFS)
–20
5000
NUMBER OF HITS
–60
–80
–100
3000
2000
1000
–120
0
0
09210-134
–140
4000
7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50
FREQUENCY (MHz)
Figure 35. AD9641-155 Two-Tone FFT with fIN1 = 29.9 MHz and fIN2 = 32.9 MHz
Figure 38. AD9641-155 Grounded Input Histogram
0
1.0
155MSPS
169.1MHz @ –7dBFS
172.1MHz @ –7dBFS
SFDR = 89.8dBc (96.8dBFS)
–20
0.8
0.6
–40
0.4
INL ERROR (LSB)
AMPLITUDE (dBFS)
N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4
OUTPUT CODE
09210-137
AMPLITUDE (dBFS)
–40
–60
–80
–100
0.2
0
–0.2
–0.4
–0.6
–120
–1.0
09210-135
0
7.75 15.50 23.25 31.00 38.75 46.50 54.25 62.00 69.75 77.50
FREQUENCY (MHz)
0
Figure 36. AD9641-155 Two-Tone FFT with fIN1 = 169.1 MHz and
fIN2 = 172.1 MHz
2000
4000
6000
8000 10,000 12,000 14,000 16,000
OUTPUT CODE
09210-138
–0.8
–140
Figure 39. AD9641-155 INL with fIN = 30.3 MHz
105
0.50
SFDR
0.25
DNL ERROR (LSB)
95
90
85
80
0
–0.25
75
65
80
95
110
125
SAMPLE RATE (MSPS)
140
155
Figure 37. AD9641-155 Single-Tone SNR/SFDR vs. Sample Rate (fS)
with fIN = 70.1 MHz
–0.50
0
2000
4000
6000
8000 10,000 12,000 14,000 16,000
OUTPUT CODE
Figure 40. AD9641-155 DNL with fIN = 30.3 MHz
Rev. B | Page 15 of 36
09210-139
70
50
SNR
09210-136
SNR/SFDR (dBFS AND dBc)
100
AD9641
Data Sheet
EQUIVALENT CIRCUITS
AVDD
350Ω
SCLK
OR
PDWN
30kΩ
09210-027
09210-023
VIN
Figure 45. Equivalent SCLK or PDWN Input Circuit
Figure 41. Equivalent Analog Input Circuit
AVDD
AVDD
AVDD
AVDD
30kΩ
0.9V
15kΩ
350Ω
CLK–
09210-028
09210-024
CLK+
CSB
15kΩ
Figure 42. Equivalent Clock Input Circuit
Figure 46. Equivalent CSB Input Circuit
DRVDD
VCM
DOUT+
AVDD
4mA
RTERM
DOUT–
DSYNC±
OR SYNC
0.9V
Figure 47. Equivalent SYNC and DSYNC Input Circuit
Figure 43. Digital CML Output
DRVDD
350Ω
30kΩ
09210-026
SDIO
0.9V
16kΩ
4mA
09210-025
4mA
AVDD
09210-029
4mA
Figure 44. Equivalent SDIO Circuit
Rev. B | Page 16 of 36
Data Sheet
AD9641
THEORY OF OPERATION
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9641 are accomplished
using a 3-wire, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9641 architecture consists of a front-end sample-andhold circuit, followed by a pipelined, switched-capacitor ADC.
The quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample
and the remaining stages to operate on the preceding samples.
Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution, flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residue amplifier
(MDAC). The MDAC magnifies the difference between the
reconstructed DAC output and the flash input for the next stage
in the pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage consists
of a flash ADC.
The input stage contains a differential sampling circuit that can
be ac- or dc-coupled in differential or single-ended modes. The
output staging block aligns the data, corrects errors, and passes the
data to the output buffers. The output buffers are powered from
a separate supply, allowing digital output noise to be separated
from the analog core. During power-down, the output buffers go
into a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9641 is a differential switchedcapacitor circuit that has been designed for optimum performance
while processing a differential input signal.
The clock signal switches the input alternatively between sample
mode and hold mode (see Figure 48). When the input is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within 1/2 of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source. A shunt capacitor can be placed across the
inputs to provide dynamic charging currents. This passive
network creates a low-pass filter at the ADC input; therefore,
the precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, any
shunt capacitors should be reduced because the input sample
capacitor is unbuffered. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth.
Refer to the AN-742 Application Note, Frequency Domain
Response of Switched-Capacitor ADCs; the AN-827 Application
Note, A Resonant Approach to Interfacing Amplifiers to SwitchedCapacitor ADCs; and the Analog Dialogue article, “TransformerCoupled Front-End for Wideband A/D Converters,” for more
information on this subject (refer to www.analog.com).
BIAS
S
S
CFB
CS
VIN+
CPAR1
CPAR2
H
S
S
CS
VIN–
CPAR1
CPAR2
S
S
CFB
BIAS
09210-030
The AD9641 can sample any fS/2 frequency segment from dc to
250 MHz, using appropriate low-pass or band-pass filtering at
the ADC inputs with little loss in ADC performance.
Figure 48. Switched-Capacitor Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched, and the inputs should be
differentially balanced.
Input Common Mode
The analog inputs of the AD9641 are not internally dc biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = 0.5 × AVDD (or
0.9 V) is recommended for optimum performance. An on-board,
common-mode voltage reference is included in the design and
is available from the VCM pin. Using the VCM output to set the
input common mode is recommended. Optimum performance
is achieved when the common-mode voltage of the analog input
is set by the VCM pin voltage (typically, 0.5 × AVDD). The VCM
pin must be decoupled to ground by a 0.1 μF capacitor. This
decoupling capacitor should be placed close to the pin to minimize
the series resistance and inductance between the part and this
capacitor.
Differential Input Configurations
Optimum performance is achieved while driving the AD9641 in a
differential input configuration. For baseband applications, the
AD8138, ADA4937-2, and ADA4938-2 differential drivers provide
excellent performance and a flexible interface to the ADC.
Rev. B | Page 17 of 36
AD9641
Data Sheet
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz (MHz). Excessive signal power can also
cause core saturation, which leads to distortion.
The output common-mode voltage of the ADA4938-2 is easily
set with the VCM pin of the AD9641 (see Figure 49), and the
driver can be configured in a Sallen-Key filter topology to provide
band limiting of the input signal.
15pF
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9641. For applications where
SNR is a key parameter, differential double balun coupling is the
recommended input configuration (see Figure 51). In this configuration, the input is ac-coupled, and the common-mode voltage
(VCM) is provided to each input through a 33 Ω resistor. These
resistors compensate for losses in the input baluns to provide
a 50 Ω impedance to the driver.
200Ω
76.8Ω
VIN
33Ω
90Ω
15Ω
VIN–
AVDD
5pF
ADA4938-2
0.1µF
ADC
33Ω
15Ω
120Ω
VCM
VIN+
200Ω
09210-031
15pF
Figure 49. Differential Input Configuration Using the ADA4938-2
For baseband applications in which SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 50. To bias the
analog input, the voltage of VCM can be connected to the
center tap of the secondary winding of the transformer.
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted, or some components may need to be removed. Table 9
displays recommended values to set the RC network for different
input frequency ranges. However, these values are dependent on
the input signal and bandwidth and should be used only as
a starting guide.
C2
R3
R2
VIN+
R1
49.9Ω
C1
ADC
R2
R1
0.1µF
VIN–
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use the AD8376 variable gain
amplifier. An example drive circuit including a band-pass filter
is shown in Figure 52. See the AD8376 data sheet for more
information.
VCM
R3
09210-032
2V p-p
C2
Figure 50. Differential Transformer-Coupled Configuration
C2
R3
R1
0.1µF
0.1µF
2V p-p
R2
VIN+
33Ω
PA
S
P
S
0.1µF
33Ω
C1
0.1µF
R1
ADC
R2
VCM
VIN–
09210-033
R3
C2
Figure 51. Differential Double Balun Input Configuration
Table 9. Example RC Network
R1 Series (Ω Each)
33
15
C1 Differential (pF)
8.2
3.9
1000pF
1µH
165Ω
VPOS
301Ω
5.1pF
1nF
1000pF
C2 Shunt (pF Each)
8.2
Open
180nH 220nH
1µH
AD8376
R2 Series (Ω Each)
0
0
3.9pF
165Ω
15pF
VCM
1nF
68nH
AD9641
180nH 220nH
NOTES
1. ALL INDUCTORS ARE COILCRAFT 0603CS COMPONENTS
WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
Figure 52. Differential Input Configuration Using the AD8376
Rev. B | Page 18 of 36
09210-034
Frequency Range (MHz)
0 to 100
100 to 250
R3 Shunt (Ω Each)
49.9
Open
Data Sheet
AD9641
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the AD9641.
The input full-scale range can be adjusted through the SPI port by
adjusting Bit 0 through Bit 4 of Register 0x18. These bits can be
used to change the full-scale value between 1.383 V p-p and
2.087 V p-p in 0.022 V steps, as shown in Table 17.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9641 sample clock inputs,
CLK+ and CLK−, should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ and CLK− pins
by means of a transformer or a passive component configuration.
These pins are biased internally (see Figure 53) and require no
external bias. If the inputs are floated, the CLK− pin is pulled low
to prevent spurious clocking.
AVDD
0.9V
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins, as shown in Figure 56. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515/AD9516/AD9517/AD9518/
AD9520/AD9522 clock drivers offer excellent jitter performance.
09210-035
The AD9641 has a very flexible clock input structure. Clock input
can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of
the type of signal being used, clock source jitter is of the most
concern, as described in the Jitter Considerations section. The
minimum conversion rate of the AD9641 is 40 MSPS. At clock
rates below 40 MSPS, dynamic performance of the AD9641 can
degrade.
Figure 54 and Figure 55 show two preferred methods for clocking
the AD9641 (at clock rates up to 640 MHz). A low jitter clock
source is converted from a single-ended signal to a differential
signal using either an RF balun or an RF transformer.
CLK+
0.1µF
CLK–
Figure 54. Transformer-Coupled Differential Clock (Up to 200 MHz)
240Ω
50kΩ
0.1µF
0.1µF
CLOCK
INPUT
CLK+
AD95xx
0.1µF
CLOCK
INPUT
LVDS DRIVER
100Ω
ADC
0.1µF
CLK–
50kΩ
50kΩ
Figure 57. Differential LVDS Sample Clock (Up to 640 MHz)
VCC
CLOCK
INPUT
0.1µF
1kΩ
AD95xx
OPTIONAL
0.1µF
100Ω
CMOS DRIVER
50Ω*
CLK+
ADC
1kΩ
0.1µF
CLK–
CLK+
0.1µF
0.1µF
1nF
*50Ω RESISTOR IS OPTIONAL.
CLK–
SCHOTTKY
DIODES:
HSMS2822
09210-037
50Ω
240Ω
Figure 55. Balun-Coupled Differential Clock (Up to 640 MHz)
Rev. B | Page 19 of 36
Figure 58. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
09210-040
1nF
ADC
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 57. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517/
AD9518/AD9520/AD9522 clock drivers offer excellent jitter
performance.
ADC
CLOCK
INPUT
100Ω
0.1µF
CLK–
50kΩ
09210-036
SCHOTTKY
DIODES:
HSMS2822
0.1µF
PECL DRIVER
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended CMOS signal. In such applications, the CLK+ pin should be driven directly from a CMOS gate,
and the CLK− pin should be bypassed to ground with a 0.1 μF
capacitor (see Figure 58).
ADC
100Ω
50Ω
0.1µF
Figure 56. Differential PECL Sample Clock (Up to 640 MHz)
Clock Input Options
0.1µF
CLK+
09210-038
CLOCK
INPUT
Figure 53. Equivalent Clock Input Circuit
CLOCK
INPUT
0.1µF
AD95xx
4pF
Mini-Circuits®
ADT1-1WT, 1:1Z
0.1µF
XFMR
0.1µF
CLOCK
INPUT
CLK–
4pF
This limit helps prevent the large voltage swings of the clock
from feeding through to other portions of the AD9641 while
preserving the fast rise and fall times of the signal that are
critical to a low jitter performance.
09210-039
CLK+
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 640 MHz, and the RF transformer is
recommended for clock frequencies from 40 MHz to 200 MHz.
The back-to-back Schottky diodes across the transformer/balun
secondary limit clock excursions into the AD9641 to approximately 0.8 V p-p differential.
AD9641
Data Sheet
The AD9641 contains an input clock divider with the ability
to divide the input clock by integer values between 1 and 8.
For divide ratios of 1, 2, or 4, the duty cycle stabilizer (DCS)
is optional. For other divide ratios, such as 3, 5, 6, 7, and 8, the
DCS must be enabled for proper part operation.
The AD9641 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x03A allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers
aligned to guarantee simultaneous input sampling.
In the equation, the rms aperture jitter represents the clock input
jitter specification. IF undersampling applications are particularly
sensitive to jitter, as illustrated in Figure 59. The measured curve
in Figure 59 was taken using an ADC clock source with approximately 65 fS of jitter, which combines with the 125 fS of jitter
inherent in the AD9641 to produce the result shown.
75
70
SNR (dBFS)
Input Clock Divider
0.05ps
0.2ps
0.5ps
1ps
1.5ps
MEASURED
65
60
Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. The AD9641 requires a tight
tolerance on the clock duty cycle to maintain dynamic
performance characteristics.
50
10
100
INPUT FREQUENCY (MHz)
The AD9641 contains a DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD9641. Noise and distortion performance are nearly flat for a
wide range of duty cycles with the DCS enabled.
Jitter in the rising edge of the input is still of paramount concern
and is not easily reduced by the internal stabilization circuit.
The duty cycle control loop does not function for clock rates
of less than 20 MHz, nominally. The loop has a time constant
associated with it that must be considered in applications in
which the clock rate can change dynamically. A wait time of
1.5 μs to 5 μs is required after a dynamic clock frequency
increase or decrease before the DCS loop is relocked to the
input signal. During the time when the loop is not locked, the
DCS loop is bypassed, and internal device timing is dependent
on the duty cycle of the input clock signal. In such applications,
it may be appropriate to disable the DCS. In all other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. For inputs near full scale, the degradation in
SNR from the low frequency SNR (SNRLF) at a given input
frequency (fINPUT) due to jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 ( SNRLF /10) ]
1
1000
09210-041
55
Figure 59. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9641.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756 Application
Note for more information about jitter performance as it relates
to ADCs.
CHIP SYNCHRONIZATION
The AD9641 has a SYNC input that offers the user flexible
synchronization options for synchronizing the clock divider.
The clock divider sync feature is useful for guaranteeing synchronized sample clocks across multiple ADCs. The input clock
divider can be enabled to synchronize on a single occurrence of
the SYNC signal or on every occurrence.
The SYNC input is internally synchronized to the sample clock;
however, to ensure that there is no timing uncertainty between
multiple parts, the SYNC input signal should be externally synchronized to the input clock signal, meeting the setup and hold
times shown in Table 5. The SYNC input should be driven using
a single-ended CMOS-type signal.
Rev. B | Page 20 of 36
Data Sheet
AD9641
POWER DISSIPATION AND STANDBY MODE
DIGITAL OUTPUTS
As shown in Figure 60, the power dissipated by the AD9641
varies with its sample rate. The data in Figure 60 was taken
in JESD204A serial output mode, using the same operating
conditions as those used for the Typical Performance
Characteristics.
JESD204A Transmit Top Level Description
0.30
0.15
0.20
0.10
IAVDD
0.10
0.05
SUPPLY CURRENT (A)
TOTAL POWER (W)
TOTAL
POWER
0
40
50
60
70
0
80
ENCODE FREQUENCY (MSPS)
09210-042
IDRVDD
Figure 60. Power and Current vs. Encode Frequency
The AD9641 is placed in power-down mode using Register 0x08,
Bits[1:0] or by asserting the PDWN pin high. In this state, the
ADC typically dissipates 7 mW. During power-down, the output
drivers are placed in a high impedance state. Pulling the PDWN
pin low returns the AD9641 to its normal operating mode. Low
power dissipation in power-down mode is achieved by shutting
down the reference, reference buffer, biasing networks, and clock.
Internal capacitors are discharged when entering power-down
mode and then must be recharged when returning to normal
operation.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode (Register 0x08, Bits[1:0]).
Standby mode allows the user to keep the internal reference
circuitry powered and the JESD204A outputs running when
faster wake-up times are required.
The AD9641 digital output complies with the JEDEC Standard
No. 204A (JESD204A), which describes a serial interface for
data converters. JESD204A uses 8b/10b encoding, as well as
optional scrambling. K28.5 and K28.7 comma symbols are used
for frame synchronization, and the K28.3 control symbol is used
for lane synchronization. The receiver is required to lock onto
the serial data stream and recover the clock with the use of a PLL.
For details on the output interface, users are encouraged to refer
to the JESD204A standard.
The JESD204A link is described according to the following
nomenclature:
S = samples transmitted per single converter per
frame cycle
M = number of converters per converter device (link)
L = number of lanes per converter device (link)
N = converter resolution
N’ = total number of bits per sample
CF = number of control words per frame clock cycle per
converter device (link)
CS = number of control bits per conversion sample
K = number of frames per multiframe
HD = high density mode
F = number of octets per frame
C = control bit (overrange, overflow, underflow)
T = tail bit
SCR = scrambling enabled
FCHK = checksum
The JESD204A block for the AD9641 is designed to support the
configurations described in Table 10.
Table 10. AD9641 JESD204A Typical Configuration
Configuration
One Converter
One JESD204A Link
One Lane Per Link
JESD204A Link Settings
M = 1; L = 1; S = 1; F = 2
N’ = 16; CF = 0
CS = 0, 1, 2; K = N/A
SCR = 0, 1; HD = 0
Rev. B | Page 21 of 36
Comments
Maximum sample rate = 80 or 155 MSPS
AD9641
Data Sheet
Figure 61 shows a simplified block diagram of the JESD204A link
for the AD9641. The 8b/10b encoding works by taking eight bits of
data (an octet) and encoding them into a 10-bit symbol. By default
in the AD9641, the 14-bit converter word is broken into two octets.
Bit 13 through Bit 6 are in the first octet. The second octet contains
Bit 5 through Bit 0 and two tail bits. The MSB of the tail bits can
also be used to indicate an out-of-range condition. The tail bits
are configured using the JESD204A link control in JESD204A
Link Control Register 1, Address 0x60, Bit 6.
JESD204 A LINK
(M = 0, 1; L = 0, 1)
OUTPUT
LANE
Refer to JEDEC Standard No. 204A, April 2008, Section 5.1, for
complete transport layer and data format details. See Section 5.2
for a complete explanation of scrambling and descrambling.
Figure 61. AD9641 Transmit Link Simplified Block Diagram
DATA
FROM
ADC
FRAME
ASSEMBLER
(ADD TAIL BITS)
OPTIONAL
SCRAMBLER
1 + x14 + x15
8B/10B
ENCODER
TO
RECEIVER
09210-044
CONVERTER
SAMPLE
09210-043
CONVERTER
The scrambler uses a self-synchronizing, polynomial-based
algorithm defined by the following equation: 1 + x14 + x15. The
descrambler in the receiver should be a self-synchronizing
version of the scrambler polynomial. Figure 64 shows the
corresponding receiver data path.
LINK
DSYNC
AD9641 ADC
Figure 62. ADC Output Data Path
WORD 0[13:6]
SYMBOL 0[9:0]
WORD 0[5:0], TAIL BITS[1:0]
SYMBOL 1[9:0]
WORD 1[13:6]
SYMBOL 2[9:0]
WORD 1[5:0], TAIL BITS[1:0]
SYMBOL 3[9:0]
FRAME 0
TIME
09210-045
FRAME 1
Figure 63. 14-Bit Data Transmission with Tail Bits
FROM
TRANSMITTER
8B/10B
DECODER
OPTIONAL
DESCRAMBLER
1 + x14 + x15
FRAME
ALIGNMENT
Figure 64. Required Receiver Data Path
Rev. B | Page 22 of 36
DATA
OUT
09210-046
CONVERTER
INPUT
The two resulting octets are optionally scrambled and encoded
into their corresponding 10-bit code. The scrambler function is
controlled by the JESD204A scrambling and lane configuration
register, Address 0x06E, Bit 7. Figure 62 shows how the 14-bit
data is taken from the ADC, the tail bits are added, the two octets
are scrambled, and the octets are encoded into two 10-bit symbols.
Figure 63 illustrates the default data format.
Data Sheet
AD9641
Initial Frame Synchronization
The serial interface must synchronize to the frame boundaries
before data can be properly decoded. The JESD204A standard
has a synchronization routine to identify the frame boundary.
When the DSYNC pin is taken low for at least two clock cycles,
the AD9641 enters the code group synchronization mode. The
AD9641 transmits the K28.5 comma symbol until the receiver
achieves synchronization. The receiver should then deassert the
sync signal (take DSYNC high), and the AD9641 begins the initial
lane alignment sequence (when enabled through Address 0x60,
Bits[3:2]) and, subsequently, begins transmitting sample data. The
first non-K28.5 symbol corresponds to the first octet in a frame.
The DSYNC input can be driven either from a differential LVDS
source or by using a single-ended CMOS driver circuit. The
DSYNC input default to LVDS mode but can be set to CMOS
mode by setting Bit 4 in Address 0x61. If it is driven differentially from an LVDS source, an external 100 Ω termination
resistor should be provided. If the DSYNC input is driven single
endedly, the CMOS signal should be connected to the DSYNC+
signal, and the DSYNC− signal should be left disconnected.
A 100 Ω differential termination resistor should be placed at each
receiver input to result in a nominal 400 mV peak-to-peak swing at
the receiver (see Figure 65). Alternatively, single-ended 50 Ω
termination can be used. When single-ended termination is
used, the termination voltage should be DRVDD/2; otherwise,
ac coupling capacitors can be used to terminate to any singleended voltage.
The AD9641 digital outputs can interface with custom ASICs and
FPGA receivers, providing superior switching performance in
noisy environments. Single point-to-point network topologies are
recommended with a single differential 100 Ω termination resistor
placed as close as possible to the receiver logic. The common
mode of the digital output automatically biases itself to half the
supply of the receiver (that is, the common-mode voltage is 0.9 V
for a receiver supply of 1.8 V) if dc-coupled connecting is used
(see Figure 66).
100Ω
DIFFERENTIAL
TRACE PAIR
DRVDD
DOUT + x
RECEIVER
100Ω
DOUT – x
Based on the operating mode, the receiver can ensure that it is
still synchronized to the frame boundary by correctly receiving
the replace characters.
Digital Outputs and Timing
The AD9641 has differential digital outputs that power up
by default. The driver current is derived on-chip and sets the
output current at each output equal to a nominal 4 mA. Each
output presents a 100 Ω dynamic internal termination to reduce
unwanted reflections.
VCM = DRVDD/2
OUTPUT SWING = 400mV p-p
Figure 65. AC-Coupled Digital Output Termination Example
VRXCM
DRVDD
100Ω
DIFFERENTIAL
0.1µF TRACE PAIR
DOUT+x
100Ω
DOUT–x
OR
RECEIVER
0.1µF
OUTPUT SWING = 400mV p-p
VCM = Rx VCM
09210-048
Frame alignment monitoring and correction is part of the
JESD204A specification. The 14-bit word requires two octets to
transmit all the data. The two octets (MSB and LSB), where
F = 2, make up a frame. During normal operating conditions,
frame alignment is monitored via alignment characters, which
are inserted under certain conditions at the end of a frame.
Table 11 summarizes the conditions for character insertion,
along with the expected characters under the various operation
modes. If lane synchronization is enabled, the replacement
character value depends on whether the octet is at the end of
a frame or at the end of a multiframe.
09210-047
Frame and Lane Alignment Monitoring and Correction
Figure 66. DC-Coupled Digital Output Termination Example
For receiver logic that is not within the bounds of the DRVDD
supply, an ac-coupled connection should be used. Place a 0.1 μF
capacitor on each output pin and derive a 100 Ω differential
termination close to the receiver side.
If there is no far-end receiver termination or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than 8 inches and that the differential output traces be close
together and at equal lengths.
Table 11. AD9641 JESD204A Frame Alignment Monitoring and Correction Replacement Characters
Scrambling
Off
Off
Off
On
On
On
Lane
Synchronization
On
On
Off
On
On
Off
Character to Be Replaced
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame repeated from previous frame
Last octet in frame equals D28.7 (0xFC)
Last octet in frame equals D28.3 (0x7C)
Last octet in frame equals D28.7 (0x7C)
Rev. B | Page 23 of 36
Last Octet in Multiframe
No
Yes
Not applicable
No
Yes
Not applicable
Replacement
Character
K28.7 (0xFC)
K28.3 (0x7C)
K28.7 (0xFC)
K28.7 (0xFC)
K28.3 (0x7C)
K28.7 (0xFC)
AD9641
Data Sheet
The lowest typical clock rate is 40 MSPS. For clock rates slower
than 60 MSPS, Bit 3 should be set to 0 in the PLL control register
(Address 0x21 in Table 17). This option sets the PLL loop bandwidth to use clock rates between 40 MSPS and 60 MSPS.
Figure 67 shows an example of the digital output (default) data
eye and a time interval error (TIE) jitter histogram.
Additional SPI options allow the user to further increase the output
driver voltage swing of all four outputs to drive longer trace lengths
(see Address 0x15 in Table 17). Even though this produces sharper
rise and fall times on the data edges and is less prone to bit errors,
the power dissipation of the DRVDD supply increases when this
option is used. See the Memory Map section for more details.
Setting Bit 2 in the output mode register (Address 0x14) allows
the user to invert the digital samples from their nominal state.
As shown in Figure 63, the MSB is transmitted first in the data
output serial stream.
The format of the output data is twos complement, by default.
Table 12 provides an example of this output coding format.
To change the output data format to offset binary or Gray code,
see the Memory Map section (Address 0x14 in Table 17).
HEIGHT1: EYE DIAGRAM
PERIOD1: HISTOGRAM
1
25,000
–
100
4
+
WIDTH@BER1: BATHTUB
3
+
10–2
400
20,000
10–4
0
10–6
15,000
BER
HITS
10–8
10,000
–200
10–10
5000
–400
EYE: TRANSITION BITS
OFFSET: –0.004
UIS: 8000; 639999, TOTAL: 8000; 639999
–600 –400 –200
0
200
TIME (ps)
400
0
600
10–12
610
615
620 625 630
TIME (ps)
10–14
–0.5
635
0.781
0
ULS
09210-050
VOLTAGE (mV)
200
0.5
Figure 67. AD9641-80 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations
600
HEIGHT1: EYE DIAGRAM
PERIOD1: HISTOGRAM
100
4
1
–
–
400k
WIDTH@BER1: BATHTUB
3
–
10–2
400
350k
10–4
300k
0
10–6
250k
BER
HITS
VOLTAGE (mV)
200
200k
150k
–200
10–8
10–10
100k
–600
EYE: TRANSITION BITS
OFFSET: –0.002
UIS: 8000; 1239996, TOTAL: 48000; 7439996
–300 –200 –100
100
0
TIME (ps)
200
300
10–12
50k
0
305
310
315
320 325 330
TIME (ps)
335
10–14
–0.5
0.75
0
ULS
0.5
Figure 68. AD9641-155 Digital Outputs Data Eye, Histogram, and Bathtub, External 100 Ω Terminations
Table 12. Digital Output Coding
Code
8191
0
−1
−8192
(VIN+) − (VIN−), Input Span = 1.75 V p-p (V)
+0.875
0.00
−0.000107
−0.875
Digital Output Twos Complement ([D13:D0])
01 1111 1111 1111
00 0000 0000 0000
11 1111 1111 1111
10 0000 0000 0000
Rev. B | Page 24 of 36
09210-068
–400
Data Sheet
AD9641
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9641 includes built-in test features designed to enable
verification of the integrity of the channel as well as facilitate
board level debugging. A BIST (built-in self-test) feature is included
that verifies the integrity of the digital datapath of the AD9641.
Various output test options are also provided to place predictable
values on the outputs of the AD9641.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9641 signal path. When enabled, the test runs from an internal
pseudorandom noise (PN) source through the digital datapath
starting at the ADC block output. The BIST sequence runs
for 512 cycles and stops. The BIST signature value is placed in
Register 0x24 and Register 0x25. The outputs are not disconnected
during this test; therefore, the PN sequence can be observed as
it runs. The PN sequence can be continued from its last value or
reset from the beginning, based on the value programmed in
Register 0x0E, Bit 2. The BIST signature result varies based on
the channel configuration.
ADC TEST PATTERNS
14-BIT
SPI REGISTER 0x0D
BITS [3:0] ≠ 0000
OUTPUT TEST MODES
Digital test patterns can be inserted at various points along the
signal path within the AD9641 as shown in Figure 69. The ability
to inject these signals at several locations facilitates debugging
of the JESD204A serial communication link.
Register 0x0D allows test signals generated at the output of the
ADC core to be fed directly into the input of the serial link. The
output test options available from Register 0x0D are shown in
Table 14. When an output test mode is enabled, the analog
section of the ADC is disconnected from the digital back end
blocks and the test pattern is run through the output formatting
block. Some of the test patterns are subject to output formatting,
and some are not. The seed value for the PN sequence tests can be
forced if the PN reset bits are used to hold the generator in reset
mode by setting Bit 4 or Bit 5 of Register 0x0D. These tests can
be performed with or without an analog signal (if present, the
analog signal is ignored), but they do require an encode clock.
For more information, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
JESD204A TEST PATTERNS
10-BIT
SPI REGISTER 0x62 BITS [5:4] =
01 AND BITS [2:0] ≠ 000
JESD204A TEST PATTERNS
16-BIT
SPI REGISTER 0x62 BITS [5:4] =
00 AND BITS [2:0] ≠ 000
SERIALIZER
JESD204A
SAMPLE
CONSTRUCTION
ADC CORE
FRAME
CONSTRUCTION
SCRAMBLER
(OPTIONAL)
8-BIT/10-BIT
ENCODER
OUTPUT
09210-051
FRAMER
TAIL BITS
Figure 69. Block Diagram Showing Digital Test Modes
Rev. B | Page 25 of 36
AD9641
Data Sheet
There are nine digital output test pattern options available that
can be initiated through the SPI (see Table 14 for the output bit
sequencing options). This feature is useful when validating
receiver capture and timing. Some test patterns have two serial
sequential words and can be alternated in various ways, depending
on the test pattern selected. Note that some patterns do not
adhere to the data format select option. In addition, custom
user-defined test patterns can be assigned in the user pattern
registers (Address 0x19 and Address 0x20).
The PN sequence short pattern produces a pseudorandom bit
sequence that repeats itself every 29 − 1 (511) bits. A description
of the PN sequence short and how it is generated can be found
in Section 5.1 of the ITU-T O.150 (05/96) recommendation.
The only difference is that the starting value must be a specific
value instead of all 1s (see Table 13 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 − 1 (8,388,607) bits.
A description of the PN sequence long and how it is generated
can be found in Section 5.6 of the ITU-T O.150 (05/96) standard.
The only differences are that the starting value must be a specific
value instead of all 1s (see Table 13 for the initial values) and
that the AD9641 inverts the bit stream with relation to the ITU-T
standard.
Table 13. PN Sequence
Sequence
PN Sequence Short
PN Sequence Long
Initial
Value
0x0092
0x3AFF
First Three Output Samples
(MSB First)
0x125B, 0x3C9A, 0x2660
0x3FD7, 0x0002, 0x36E0
Register 0x62 allows patterns that are similar to those described
in Table 14 to be input at different points along the datapath.
This allows the user to provide predictable output data on the
serial link without it having been manipulated by the internal
formatting logic. Refer to Table 17 for additional information
on the test modes available in Register 0x62.
Table 14. Flexible Output Test Modes from SPI Register 0x0D
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
PN sequence long
PN sequence short
One-/zero-word toggle
User test mode
1001 to 1110
1111
Not used
Ramp output
Digital Output Word 1 (Default
Twos Complement Format)
Not applicable
00 0000 0000 0000
01 1111 1111 1111
10 0000 0000 0000
10 1010 1010 1010
Not applicable
Not applicable
1111 1111 1111
User data from Register 0x19 to
Register 0x20
Not applicable
N
Rev. B | Page 26 of 36
Digital Output Word 2 (Default
Twos Complement Format)
Not applicable
Same
Same
Same
01 0101 0101 0101
Not applicable
Not applicable
0000 0000 0000
User data from Register 0x19 to
Register 0x20
Not applicable
N+1
Subject to Data
Format Select
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
No
Data Sheet
AD9641
SERIAL PORT INTERFACE (SPI)
The AD9641 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. The SPI
gives the user added flexibility and customization, depending on
the application. Addresses are accessed via the serial port and
can be written to or read from via the port. Memory is organized
into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 70
and Table 5.
CONFIGURATION USING THE SPI
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and W1 bits.
Other modes involving the CSB are available. The CSB can be
held low indefinitely, which permanently enables the device;
this is called streaming. The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high, SPI
functions are placed in high impedance mode.
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CSB pin (see Table 15). The SCLK (a serial clock) is
used to synchronize the read and write data presented from and
to the ADC. The SDIO (serial data input/output) is a dual-purpose
pin that allows data to be sent to and read from the internal ADC
memory map registers. The CSB (chip select bar) is an activelow control that enables or disables the read and write cycles.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. The first bit of the first byte in
a multibyte serial data transfer frame indicates whether a read
command or a write command is issued. If the instruction is
a readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an input
to an output at the appropriate point in the serial frame.
Table 15. Serial Port Interface Pins
SDIO
CSB
Function
Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active-low control that gates the read
and write cycles.
tHIGH
tDS
tS
tDH
All data is composed of 8-bit words. Data can be sent in MSBfirst mode or in LSB-first mode. MSB first is the default on
power-up and can be changed via the SPI port configuration
register. For more information about this and other features,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
tCLK
tH
tLOW
CSB
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 70. Serial Port Interface Timing Diagram
Rev. B | Page 27 of 36
D4
D3
D2
D1
D0
DON’T CARE
09210-049
Pin
SCLK
AD9641
Data Sheet
HARDWARE INTERFACE
SPI ACCESSIBLE FEATURES
The pins described in Table 15 comprise the physical interface
between the user programming device and the serial port of
the AD9641. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9641 part-specific features are described in detail in
the Reading the Memory Map Register Table section.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD9641 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
Table 16. Features Accessible Using the SPI
Feature Name
Mode
Clock
Offset
Test I/O
Full Scale
JESD204A
Rev. B | Page 28 of 36
Description
Allows the user to set either power-down mode
or standby mode
Allows the user to access the DCS, set the
clock divider, set the clock divider phase, and
enable the sync
Allows the user to digitally adjust the
converter offset
Allows the user to set test modes to have
known data on output bits
Allows the user to set the input full-scale
voltage
Allows user to configure the JESD204A output
Data Sheet
AD9641
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Default Values
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into four sections: the chip
configuration registers (Address 0x00 to Address 0x02); the transfer
register (Address 0xFF); the ADC functions registers, including
setup, control, and test (Address 0x08 to Address 0x3A); and the
JESD204A configuration registers (Address 0x60 to Address 0x78).
After the AD9641 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
Logic Levels
An explanation of logic level terminology follows:
The memory map register table (see Table 17) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x18, the input
span select register, has a hexadecimal default value of 0x00. This
means that Bit 0 through Bit 4 = 0, and the remaining bits are 0s.
This setting is the default reference selection setting. The default
value uses a 1.75 V p-p reference. For more information on this
function and others, see the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI. This application note details the
functions controlled by Register 0x00 to Register 0xFF.
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Address 0x08 through Address 0x78 are shadowed. Writes to the
addresses do not affect part operation until a transfer command is
issued by writing 0x01 to Address 0xFF, setting the transfer bit.
This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes
place when the transfer bit is set, and the bit autoclears.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x18). If the entire address location
is open (for example, Address 0x13), this address location should
not be written.
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Addr
Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0x00
0
SPI port
configuration
0x01
Chip ID
0x02
Chip grade
Transfer Register
0xFF
Transfer
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB first
Soft reset
1
1
Soft reset
LSB first
0
Open
Open
Open
Open
8-bit chip ID[7:0]
(AD9641 = 0x80)
(default)
Speed grade ID
Open
00 = 80 MSPS
10 = 155 MSPS
Open
Open
Open
Rev. B | Page 29 of 36
Default
Value
(Hex)
Default
Notes/
Comments
0x18
Nibbles are
mirrored so
LSB- or MSBfirst mode
registers
correctly,
regardless of
shift mode
Read only
0x80
Open
Open
Open
Open
Open
Transfer
Speed grade
ID used to
differentiate
devices;
read only
0x00
Synchronous
transfer of
data from
the master
shift register
to the slave
AD9641
Addr
Register
(Hex)
Name
ADC Functions
0x08
Power
modes
Data Sheet
Determines
various
generic
modes of
chip
operation.
Open
0x01
Bit 3
Bit 2
Bit 1
Open
Open
External
powerdown pin
function
0 = PDWN
1 = STNDBY
Open
Open
Open
Open
Open
Open
Open
Open
0x0A
0x0B
PLL status
Clock divide
PLL locked
Open
Open
Open
0x0D
Test mode
User test
mode
control
0=
continuous/
repeat
pattern
1 = single
pattern
Open
0x0E
BIST enable
Open
Open
0x10
Offset adjust
Open
Open
0x14
Output
mode
Open
Open
0x15
Output
adjust
Open
Open
0x18
Input span
select
0x19
User Test
Pattern 1 LSB
User Test
Pattern 1 MSB
User Test
Pattern 2 LSB
User Test
Pattern 2 MSB
User Test
Pattern 3 LSB
0x1D
0x00
Bit 4
Open
0x1C
Internal power-down mode
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
Bit 5
Global clock
0x1B
Default
Notes/
Comments
Bit 6
0x09
0x1A
Default
Value
(Hex)
Bit 7
(MSB)
Open
Open
Bit 0
(LSB)
Duty cycle
stabilizer
(default)
Open
Open
Open
Open
Open
Open
Input clock divider phase adjust
Clock divide ratio
000 = no delay
000 = divide-by-1
001 = 1 input clock cycle
001 = divide-by-2
010 = 2 input clock cycles
010 = divide-by-3
011 = 3 input clock cycles
011 = divide-by-4
100 = 4 input clock cycles
100 = divide-by-5
101 = 5 input clock cycles
101 = divide-by-6
110 = 6 input clock cycles
110 = divide-by-7
111 = 7 input clock cycles
111 = divide-by-8
Output test mode
Reset PN
Reset PN
long gen
short gen
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN long sequence
0110 = PN short sequence
0111 = one-/zero- word toggle
1000 = user test mode
1001 to 1110 = unused
1111 = ramp output
Open
Open
Open
Open
BIST enable
Reset BIST
sequence
Offset adjust in LSBs from +31 to −32
(twos complement format)
Open
Open
Output format
Output
Output
disable
invert
00 = offset binary
01 = twos complement
(default)
01 = Gray code
11 = offset binary
Open
Open
Open
Open
Output drive level adjust
11 = 320 mV
00 = 400 mV
10 = 440 mV
01 = 500 mV
Open
Full scale input voltage selection
01111 = 2.087 V p-p
…
00001 = 1.772 V p-p
00000 = 1.75 V p-p (default)
11111 = 1.727 V p-p
…
10000 = 1.383 V p-p
User Test Pattern 1, Bits[7:0]
0x00
0x00
Read only.
Clock divide
values other
than 000
cause the
duty cycle
stabilizer to
become
active.
0x00
When this
register is
set, the
test data is
placed on
the output
pins in place
of normal
data.
0x00
0x00
0x01
0x00
0x00
0x00
User Test Pattern 1, Bits[15:8]
0x00
User Test Pattern 2, Bits[7:0]
0x00
User Test Pattern 2, Bits[15:8]
0x00
User Test Pattern 3, Bits[7:0]
0x00
Rev. B | Page 30 of 36
Configures
the outputs
and the
format of
the data.
Full-scale
input
adjustment
in 0.022 V
steps.
Data Sheet
Addr
(Hex)
0x1E
0x1F
0x20
0x21
0x24
0x25
0x3A
Register
Name
User Test
Pattern 3 MSB
User Test
Pattern 4 LSB
User Test
Pattern 4 MSB
PLL control
BIST
signature LSB
BIST
signature
MSB
Sync control
AD9641
Bit 7
(MSB)
Open
Open
JESD204A Configuration Registers
0x60
Open
JESD204A
Link Control
Register 1
0x61
JESD204A
Link Control
Register 2
0x62
JESD204A
Link Control
Register 3
0x63
JESD204A
Link Control
Register 4
JESD204A
device
identification
number
(DID)
JESD204A
bank
identification
number
(BID)
JESD204A
lane
identification
number
(LID)
JESD204A
scrambler
(SCR) and
lane (L)
configuration
0x64
0x65
0x66
0x6E
Bit 6
Open
Bit 5
Open
Bit 4
Bit 3
Bit 2
User Test Pattern 3, Bits[15:8]
0x00
User Test Pattern 4, Bits[15:8]
0x00
Open
PLL low
encode
rate enable
Open
Open
Open
BIST signature, Bits[7:0]
0x00
BIST signature, Bits[15:8]
0x00
Read only.
Open
Open
Serial tail
bit enable
Serial test
sample
enable
Serial lane
synchronization
enable
DSYNC
pin input
inverted
CMOS
DSYNC
input
0 = LVDS
1 = CMOS
Serial lane alignment
sequence mode
00 = disabled
01 = enabled
10 = reserved
11 = always on
test mode
Open
Bypass
8b/10b
encoding
Clock
divider
next sync
only
Clock
divider
sync
enable
Master sync
buffer
enable
0x00
Frame
alignment
character
insertion
disable
Serial
transmit link
power- down
0x00
Invert
transmit
bits
Mirror serial
output bits
0x00
Open
Link test generation mode
Link test generation
input selection
000 = normal operation
00 = 16-bit data injected
001 = alternating checkerboard
at sample input to the
010 = 1/0 word toggle
link
011 = PN sequence, long
01 = 10-bit data injected
100 = PN sequence, short
at output of 8b/10b
101
=
user
test pattern data continuous
encoder
110 = user test pattern data single
10 = reserved
111 = ramp output
11 = reserved
Initial lane assignment sequence repeat count
JESD204A serial device identification (DID) number
Open
Open
Open
Open
Open
Enable
serial
scrambler
mode (SCR)
Open
Open
0x00
Default
Notes/
Comments
Bit 3 must
be enabled
if the ADC
clock rate is
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