AD9653BCPZ-125

FUNCTIONAL BLOCK DIAGRAM SENSE AGND VIN+C VIN–C PIPELINE ADC VIN+D VIN–D PIPELINE ADC SERIAL PORT INTERFACE SCLK/DTP VCM DIGITAL SERIALIZER SERIAL LVDS D0+B D0–B SERIAL LVDS SERIAL LVDS D1+B D1–B FCO+ FCO– D0+C D0–C D1+C D1–C SERIAL LVDS D0+D D0–D SERIAL LVDS D1+D D1–D DCO+ DCO– AD9653 1V REF SELECT SERIAL LVDS 16 16 SERIAL LVDS DIGITAL SERIALIZER DIGITAL SERIALIZER CLOCK MANAGEMENT 10538-001 PIPELINE ADC VIN–B RBIAS VREF 16 D0+A D0–A D1+A D1–A SERIAL LVDS DIGITAL SERIALIZER CLK– VIN+B 16 Figure 1. GENERAL DESCRIPTION The AD9653 is a quad, 16-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The AD9653 is available in a RoHS-compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. 1. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such 3. Rev. F PIPELINE ADC DRVDD CLK+ VIN+A VIN–A APPLICATIONS Medical ultrasound and MRI High speed imaging Quadrature radio receivers Diversity radio receivers Test equipment PDWN AVDD CSB 1.8 V supply operation Low power: 164 mW per channel at 125 MSPS SNR = 76.5 dBFS at 70 MHz (2.0 V p-p input span) SNR = 77.5 dBFS at 70 MHz (2.6 V p-p input span) SFDR = 90 dBc (to Nyquist, 2.0 V p-p input span) DNL = ±0.7 LSB; INL = ±3.5 LSB (2.0 V p-p input span) Serial LVDS (ANSI-644, default) and low power, reduced range option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input voltage range (supports up to 2.6 V p-p) Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Multichip sync and clock divider Programmable output clock and data alignment Standby mode SYNC FEATURES SDIO/OLM Data Sheet Quad, 16-Bit, 125 MSPS, Serial LVDS 1.8 V Analog-to-Digital Converter AD9653 2. 4. 5. Small Footprint. Four ADCs are contained in a small, space-saving package. Low power of 164 mW/channel at 125 MSPS with scalable power options. Pin compatible to the AD9253 14-bit quad and the AD9633 12-bit quad ADC. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9653 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Power-Down Mode ........................... 27 Applications ....................................................................................... 1 Digital Outputs and Timing ..................................................... 27 General Description ......................................................................... 1 Output Test Modes ..................................................................... 30 Functional Block Diagram .............................................................. 1 Serial Port Interface (SPI) .............................................................. 31 Product Highlights ........................................................................... 1 Configuration Using the SPI ..................................................... 31 Revision History ............................................................................... 3 Hardware Interface ..................................................................... 32 Specifications..................................................................................... 4 Configuration Without the SPI ................................................ 32 DC Specifications ......................................................................... 4 SPI Accessible Features .............................................................. 32 AC Specifications.......................................................................... 6 Memory Map .................................................................................. 33 Digital Specifications ................................................................... 8 Reading the Memory Map Register Table............................... 33 Switching Specifications .............................................................. 9 Memory Map Register Table ..................................................... 34 Timing Specifications ................................................................ 10 Memory Map Register Descriptions ........................................ 37 Absolute Maximum Ratings .......................................................... 12 Applications Information .............................................................. 39 Thermal Resistance .................................................................... 12 Design Guidelines ...................................................................... 39 ESD Caution ................................................................................ 12 Power and Ground Recommendations ................................... 39 Pin Configuration and Function Descriptions ........................... 13 Clock Stability Considerations ................................................. 39 Typical Performance Characteristics ........................................... 14 Exposed Pad Thermal Heat Slug Recommendations ............ 39 VREF = 1.0 V ................................................................................. 14 VCM ............................................................................................. 39 VREF = 1.3 V ................................................................................. 17 Reference Decoupling ................................................................ 39 Equivalent Circuits ......................................................................... 21 SPI Port ........................................................................................ 39 Theory of Operation ...................................................................... 22 Crosstalk Performance .............................................................. 40 Analog Input Considerations.................................................... 22 Outline Dimensions ....................................................................... 41 Voltage Reference ....................................................................... 23 Ordering Guide .......................................................................... 41 Clock Input Considerations ...................................................... 25 Rev. F | Page 2 of 41 Data Sheet AD9653 REVISION HISTORY 11/2017—Rev. E to Rev. F Changes to Table 10 ........................................................................13 Changes to Power Dissipation and Power-Down Mode Section... 27 Updated Outline Dimensions ................................................................. 41 Changes to Ordering Guide .................................................................... 41 3/2016—Rev. D to Rev. E Changes to General Description Section ....................................... 1 Changes to Figure 15 ......................................................................15 Changes to Table 13 ........................................................................29 11/2015—Rev. C to Rev. D Changes to General Description Section ....................................... 1 Added Note 4, Table 6....................................................................... 8 Changes to Digital Outputs and Timing Section ........................28 8/2015—Rev. B to Rev. C Change to Applications Section ...................................................... 1 Change to Jitter Considerations Section ......................................25 11/2014—Rev. 0 to Rev. A Changed Output Voltage (1.0 V Mode) from 1.01 V to 1.02 V (max); Table 1 ........................................................................ 3 Changes to Table 3 ............................................................................ 5 Added tPD of 1.5 ns (min) and 3.1 ns (max); Table 6 .................... 8 Changed tSSYNC from 0.24 ns (typ) to 1.2 ns (min) and Changed tHSYNC from 0.40 ns (typ) to −0.2 ns (min); Table 7 ....................... 9 Changes to Table 10 ........................................................................ 12 Changes to Clock Input Options Section .................................... 24 Changes to Digital Outputs and Timing Section ........................ 27 Changes to Table 13 ........................................................................ 28 Changes to Table 14 ........................................................................ 29 Changes to Channel-Specific Registers Section ......................... 32 Changes to Register 0x14 Bit 1 and Default Value ..................... 34 Changes to Register 0x16; Bits[6:4]—Input Clock Phase Adjust Section and Sample Rate Override (Register 0x100) Section ... 37 Added Clock Stability Considerations Section ........................... 38 5/2012—Revision 0: Initial Version 7/2015—Rev. A to Rev. B Added Patent Note, Note 1............................................................... 1 Change to Applications Section and General Description Section ................................................................................................ 1 Change to Effective Number of Bits (ENOB) Parameter, Table 3 ................................................................................................. 5 Changes to Table 5 ............................................................................ 7 Change to Table 8 ............................................................................11 Changes to Reading the Memory Map Register Table Section and Channel-Specific Registers Section .......................................32 Changes to Table 19 ........................................................................33 Changes to Device Index (Register 0x04, Register 0x05) Section ..............................................................................................36 Changes to Clock Stability Considerations Section....................38 Rev. F | Page 3 of 41 AD9653 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input at −1.0 dBFS; VREF = 1.0 V, DCS off, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Temperature Full Full Full Full Full Full 25°C Full 25°C Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1.0 V Mode) Load Regulation at 1.0 mA (VREF = 1.0 V) Input Resistance INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage (VREF = 1.0 V) Common-Mode Voltage Common-Mode Range Differential Input Resistance Differential Input Capacitance POWER SUPPLY AVDD DRVDD IAVDD 2 IDRVDD (ANSI-644 Mode)2 IDRVDD (Reduced Range Mode)2 TOTAL POWER CONSUMPTION DC Input Sine Wave Input (Four Channels Including Output Drivers, ANSI-644 Mode) Sine Wave Input (Four Channels Including Output Drivers, Reduced Range Mode) Power-Down Standby 3 Min 16 −0.49 −0.14 −12.3 1.0 −0.77 Max Unit Bits 0.17 0.39 2.37 5.8 0.95 ±3.5 % FSR % FSR % FSR % FSR LSB LSB LSB LSB 3.5 ppm/°C Guaranteed −0.3 +0.2 −5 1.1 ±0.7 −7.26 Full Full Full 25°C Typ 0.98 8.18 1.0 2 7.5 1.02 25°C 2.7 LSB rms Full Full 25°C 25°C 25°C 2 0.9 V p-p V V kΩ pF Full Full Full Full 25°C Full Full 25°C 25°C Full 0.5 1.3 2.6 7 1.7 1.7 1.8 1.8 305 60 45 1.9 1.9 330 64 V V mA mA mA 607 657 630 2 356 649 708 mW mW mW mW mW 392 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured with a low input frequency, full-scale sine wave on all four channels. 3 Can be controlled via the SPI. 1 2 Rev. F | Page 4 of 41 V mV kΩ Data Sheet AD9653 AVDD = 1.8 V, DRVDD = 1.8 V, 2.6 V p-p full-scale differential input at −1.0 dBFS; VREF = 1.3 V; 0°C to 85°C, DCS off, unless otherwise noted. Table 2. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error INTERNAL VOLTAGE REFERENCE Output Voltage (1.3 V Programmable Mode) Load Regulation at 1.0 mA (VREF = 1.3 V) Input Resistance INPUT-REFERRED NOISE VREF = 1.3 V ANALOG INPUTS Differential Input Voltage (VREF = 1.3 V) Common-Mode Voltage Common-Mode Range Differential Input Resistance Differential Input Capacitance POWER SUPPLY AVDD DRVDD IAVDD 2 IDRVDD (ANSI-644 Mode)2 IDRVDD (Reduced Range Mode)2 TOTAL POWER CONSUMPTION DC Input Sine Wave Input (Four Channels Including Output Drivers, ANSI-644 Mode) Sine Wave Input (Four Channels Including Output Drivers, Reduced Range Mode) Power-Down Standby 3 Temperature Min 16 Typ Max 25°C 25°C 25°C 25°C 25°C 25°C 25°C Guaranteed −0.3 +0.2 −5 1.1 ±0.8 ±5.0 % FSR % FSR % FSR % FSR LSB LSB 25°C 3.5 ppm/°C 25°C 25°C 25°C 1.3 6.5 7.5 V mV kΩ 25°C 2.1 LSB rms 25°C 25°C 25°C 25°C 25°C 2.6 0.9 2.6 7 V p-p V V kΩ pF 25°C 25°C 25°C 25°C 25°C 1.8 1.8 314 60 45 V V mA mA mA 25°C 25°C 25°C 25°C 25°C 614 673 646 2 371 mW mW mW mW mW 0.6 1.3 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured with a low input frequency, full-scale sine wave on all four channels. 3 Can be controlled via the SPI. 1 2 Rev. F | Page 5 of 41 Unit Bits AD9653 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2.0 V p-p full-scale differential input at −1.0 dBFS; VREF = 1.0 V, DCS off, unless otherwise noted. Table 3. Temperature Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz Min Typ 75.5 78 77.8 76.5 73.9 71.5 dBFS dBFS dBFS dBFS dBFS 74.6 78 77.7 76.1 73.6 70.3 dBFS dBFS dBFS dBFS dBFS 12.1 12.7 12.6 12.3 11.9 11.4 Bits Bits Bits Bits Bits 78 96 93 89 87 77 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C −98 −93 −89 −87 −77 −78 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C −96 −98 −94 −89 −83 −85 dBc dBc dBc dBc dBc 25°C 25°C 25°C −90 −91 −87 dBc dB dB 25°C 25°C 25°C 31 79 650 dB dB MHz 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C Max Unit WORST OTHER HARMONIC OR SPUR fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 70.5 MHz, fIN2 = 72.5 MHz CROSSTALK 2 CROSSTALK (OVERRANGE CONDITION) 3 POWER SUPPLY REJECTION RATIO (PSRR) 4 AVDD DRVDD ANALOG INPUT BANDWIDTH, FULL POWER See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. Overrange condition is defined as the input being 3 dB above full scale. 4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels. 1 2 3 Rev. F | Page 6 of 41 Data Sheet AD9653 AVDD = 1.8 V, DRVDD = 1.8 V, 2.6 V p-p full-scale differential input at −1.0 dBFS; VREF = 1.3 V; 0°C to 85°C, DCS off, unless otherwise noted. Table 4. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz WORST OTHER HARMONIC OR SPUR fIN = 9.7 MHz fIN = 15 MHz fIN = 70 MHz fIN = 128 MHz fIN = 200 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 70.5 MHz, fIN2 = 72.5 MHz CROSSTALK 2 CROSSTALK (OVERRANGE CONDITION) 3 POWER SUPPLY REJECTION RATIO (PSRR) 4 AVDD DRVDD ANALOG INPUT BANDWIDTH, FULL POWER Temperature Min Typ Max Unit 25°C 25°C 25°C 25°C 25°C 80 79.4 77.5 74.4 71.7 dBFS dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 25°C 79.8 79.2 76.1 74 69.9 dBFS dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 25°C 13 12.9 12.3 12 11.3 Bits Bits Bits Bits Bits 25°C 25°C 25°C 25°C 25°C 94 94 82 86 75 dBc dBc dBc dBc dBc 25°C 25°C 25°C 25°C 25°C −94 −94 −82 −87 −75 dBc dBc dBc dBc dBc 25°C 25°C 25°C 25°C 25°C −100 −99 −96 −86 −84 dBc dBc dBc dBc dBc 25°C 25°C 25°C −90 91 87 dBc dB dB 25°C 25°C 25°C 31 79 650 dB dB MHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Crosstalk is measured at 70 MHz with −1.0 dBFS analog input on one channel and no input on the adjacent channel. Overrange condition is defined as the input being 3 dB above full scale. 4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels. 1 2 3 Rev. F | Page 7 of 41 AD9653 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted. Table 5. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Voltage Range Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SYNC, SCLK) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO) 3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) Temp Min Full Full Full 25°C 25°C 0.2 AGND − 0.2 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Typ Max Unit 3.6 AVDD + 0.2 V p-p V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF CMOS/LVDS/LVPECL 0.9 15 4 30 2 26 2 26 5 Full Full 1.79 0.05 V V Full Full ±290 1.15 LVDS ±345 ±400 1.25 1.35 Twos complement mV V Full Full ±160 1.15 LVDS ±200 ±230 1.25 1.35 Twos complement mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO/OLM pins sharing the same connection. 1 2 Rev. F | Page 8 of 41 Data Sheet AD9653 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, unless otherwise noted. Table 6. Parameter 1, 2 CLOCK 3 Input Clock Rate Conversion Rate 4 Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 5 DCO to Data Delay (tDATA)5 DCO to FCO Delay (tFRAME)5 Lane Delay (tLD) Data to Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) 6 Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out-of-Range Recovery Time Temp Min Full Full Full Full 20 20 Full Full Full Full Full Full Full 1.5 Typ Max Unit 1000 125 MHz MSPS ns ns 3.1 ns ps ps ns ns ps ps ps ps ns μs 4.00 4.00 Full 25°C 25°C Full 2.3 300 300 2.3 tFCO + (tSAMPLE/16) (tSAMPLE/16) (tSAMPLE/16) 90 ±50 250 375 16 25°C 25°C 25°C 1 135 1 1.5 (tSAMPLE/16) − 300 (tSAMPLE/16) − 300 3.1 (tSAMPLE/16) + 300 (tSAMPLE/16) + 300 ±200 Clock cycles ns fs rms Clock cycles See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section for the maximum conversion rate in one-lane output mode. 5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. 1 2 Rev. F | Page 9 of 41 AD9653 Data Sheet TIMING SPECIFICATIONS Table 7. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description Limit Unit SYNC to rising edge of CLK+ setup time SYNC to rising edge of CLK+ hold time See Figure 75 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 75) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 75) 1.2 −0.2 ns min ns min 2 2 40 2 2 10 10 10 ns min ns min ns min ns min ns min ns min ns min ns min 10 ns min Timing Diagrams Refer to the Memory Map Register Descriptions section and Table 23 for SPI register settings. N–1 VIN±x N tA CLK– CLK+ DDR DCO– N+1 tEL tEH tCPD DCO+ SDR DCO FCO– FCO+ BITWISE MODE D0–A D0+A tFRAME tFCO tPD tDATA D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 MSB N – 16 D13 N – 16 D11 N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 LSB N – 17 D07 N – 16 D06 N – 16 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 D08 N – 17 MSB N – 16 D14 N – 16 D13 N – 16 D12 N – 16 D11 N – 16 D10 N – 16 D09 N – 16 D08 N – 16 D12 N – 17 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 MSB N – 17 D13 N – 17 D11 N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 D07 N – 17 D06 N – 17 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 MSB N – 17 D14 N – 17 D13 N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D09 N – 17 D14 N – 16 tLD D1–A D1+A D12 N – 16 D14 N – 17 FCO– BYTEWISE MODE D0–A D0+A D1–A D1+A Figure 2. 16-Bit DDR/SDR, Two-Lane, 1× Frame Mode (Default) Rev. F | Page 10 of 41 10538-002 FCO+ Data Sheet AD9653 N–1 VIN±x N tA tEH CLK– N+1 tEL CLK+ DDR tCPD DCO– DCO+ SDR DCO tFCO FCO– FCO+ BITWISE MODE tFRAME tPD D0–A tDATA D0+A D14 N – 17 D12 N – 17 D10 N – 17 D08 N – 17 D06 N – 17 D04 N – 17 D02 N – 17 LSB N – 17 MSB N – 17 D13 N – 17 D11 N – 17 D09 N – 17 D07 N – 17 D05 N – 17 D03 N – 17 D01 N – 17 D07 N – 17 D06 N – 17 D05 N – 17 D04 N – 17 D03 N – 17 D02 N – 17 D01 N – 17 MSB N – 17 D14 N – 17 D13 N – 17 D12 N – 17 D11 N – 17 D10 N – 17 D09 N – 17 D14 N – 16 D12 N – 16 D10 N – 16 D08 N – 16 D06 N – 16 D04 N – 16 D02 N – 16 LSB N – 16 MSB N – 16 D13 N – 16 D11 N – 16 D09 N – 16 D07 N – 16 D05 N – 16 D03 N – 16 D01 N – 16 LSB N – 17 D07 N – 16 D06 N – 16 D05 N – 16 D04 N – 16 D03 N – 16 D02 N – 16 D01 N – 16 LSB N – 16 D08 N – 17 MSB N – 16 D14 N – 16 D13 N – 16 D12 N – 16 D11 N – 16 D10 N – 16 D09 N – 16 D08 N – 16 tLD D1–A D1+A FCO– BYTEWISE MODE D0–A D0+A D1–A D1+A 10538-003 FCO+ Figure 3. 16-Bit DDR/SDR, Two-Lane, 2× Frame Mode N–1 VIN±x tA N tEL tEH CLK– CLK+ DCO– tCPD DCO+ FCO– tFCO tFRAME FCO+ MSB D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB MSB D14 D13 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 17 N – 16 N – 16 N – 16 Figure 4. Wordwise DDR, One-Lane, 1× Frame, 16-Bit Output Mode CLK+ tSSYNC tHSYNC SYNC Figure 5. SYNC Input Timing Requirements Rev. F | Page 11 of 41 10538-004 D0+x tDATA tPD 10538-005 D0–x AD9653 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 8. Parameter Electrical AVDD to AGND DRVDD to AGND Digital Outputs (D0±x, D1±x, DCO+, DCO−, FCO+, FCO−) to AGND CLK+, CLK− to AGND VIN+x, VIN−x to AGND SCLK/DTP, SDIO/OLM, CSB to AGND SYNC, PDWN to AGND RBIAS, VCM to AGND VREF, SENSE to AGND Environmental Operating Temperature Range (Ambient, VREF = 1.0 V) Operating Temperature Range (Ambient, VREF = 1.3 V) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating Table 9. Thermal Resistance −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V Package Type 48-Lead LFCSP 7 mm × 7 mm (CP-48-13) −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V Air Flow Velocity (m/sec) 0.0 1.0 2.5 θJA1 23.7 20.0 18.7 θJB 7.8 N/A2 N/A2 θJC 7.1 N/A2 N/A2 Unit °C/W °C/W °C/W θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. 2 N/A means not applicable. 1 ESD CAUTION −40°C to +85°C 0°C to 85°C 150°C 300°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. F | Page 12 of 41 Data Sheet AD9653 48 47 46 45 44 43 42 41 40 39 38 37 VIN+C VIN–C AVDD AVDD SYNC VCM VREF SENSE RBIAS AVDD VIN–B VIN+B PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9653 TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 VIN+A VIN–A AVDD PDWN CSB SDIO/OLM SCLK/DTP DRVDD D0+A D0–A D1+A D1–A NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 10538-006 D1–C D1+C D0–C D0+C DCO– DCO+ FCO– FCO+ D1–B D1+B D0–B D0+B 13 14 15 16 17 18 19 20 21 22 23 24 VIN+D 1 VIN–D 2 AVDD 3 AVDD 4 CLK– 5 CLK+ 6 AVDD 7 DRVDD 8 D1–D 9 D1+D 10 D0–D 11 D0+D 12 Figure 6. 48-Lead LFCSP Pin Configuration, Top View Table 10. Pin Function Descriptions Pin No. 0 1 2 3, 4, 7, 34, 39, 45, 46 5, 6 8, 29 9, 10 11, 12 13, 14 15, 16 17, 18 19, 20 21, 22 23, 24 25, 26 27, 28 30 31 32 33 Mnemonic AGND, Exposed Pad VIN+D VIN−D AVDD CLK−, CLK+ DRVDD D1−D, D1+D D0−D, D0+D D1−C, D1+C D0−C, D0+C DCO−, DCO+ FCO−, FCO+ D1−B, D1+B D0−B, D0+B D1−A, D1+A D0−A, D0+A SCLK/DTP SDIO/OLM CSB PDWN 35 36 37 38 40 41 42 43 VIN−A VIN+A VIN+B VIN−B RBIAS SENSE VREF VCM 44 47 48 SYNC VIN−C VIN+C 1 Description Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. ADC D Analog Input True. ADC D Analog Input Complement. 1.8 V Analog Supply Pins. Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. Digital Output Driver Supply. Channel D Digital Outputs, (Disabled in One-Lane Mode1). Channel D Digital Outputs, (disabled in One-Lane Mode1). Channel C Digital Outputs, (Channel D Digital Outputs in One-Lane Mode1). Channel C Digital Outputs. Data Clock Outputs. Frame Clock Outputs. Channel B Digital Outputs. Channel B Digital Outputs, (Channel A Digital Outputs in One-Lane Mode1). Channel A Digital Outputs, (Disabled in One-Lane Mode1). Channel A Digital Outputs, (Disabled in One-Lane Mode1). SPI Clock Input/Digital Test Pattern. SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode. SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up. Digital Input, 30 kΩ Internal Pull-Down. PDWN high = power-down device. PDWN low = run device, normal operation. ADC A Analog Input Complement. ADC A Analog Input True. ADC B Analog Input True. ADC B Analog Input Complement. Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Reference Mode Selection. Voltage Reference Input and Output. Analog Output at Midsupply Voltage. Sets the common mode of the analog inputs, external to the ADC, as shown in Figure 56 and Figure 57. Digital Input. SYNC input to clock divider. ADC C Analog Input Complement. ADC C Analog Input True. Output channel assignments are shown first for THE default two-lane mode. If one-lane mode is used, output channel assignments change as indicated in parenthesis. Register 0x21 Bits[6:4] invoke one-lane mode. Rev. F | Page 13 of 41 AD9653 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VREF = 1.0 V 0 0 125MSPS 9.7MHz AT –1dBFS SNR = 77.1dB (78.1dBFS) SFDR = 96.8dBc –15 –30 AMPLITUDE (dBFS) –45 –60 –75 –90 + 2 –105 4 3 6 5 –60 –75 2 –90 18 24 30 36 42 48 54 60 –135 0 12 18 24 30 36 42 48 54 60 FREQUENCY (MHz) Figure 10. Single-Tone 16k FFT with fIN = 70 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 0 125MSPS 15MHZ AT –1dBFS SNR = 76.8dB (77.8dBFS) SFDR = 95.2dBc –30 –30 –45 –60 –75 –90 2 + –105 4 3 6 125MSPS 128MHz AT –1dBFS SNR = 73.2dB (74.2dBFS) SFDR = 86.6dBc –15 AMPLITUDE (dBFS) –15 –45 –60 –75 4 3 –105 5 –120 + 2 –90 5 6 –120 6 12 18 24 30 36 42 48 54 –135 10538-008 0 60 FREQUENCY (MHz) 0 12 18 24 30 36 42 48 54 60 FREQUENCY (MHz) Figure 8. Single-Tone 16k FFT with fIN = 15 MHZ, fSAMPLE = 125 MSPS, VREF = 1.0 V Figure 11. Single-Tone 16k FFT with fIN = 128 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 0 125MSPS 64MHz AT –1dBFS SNR = 75.7dB (76.7dBFS) SFDR = 87.2dBc –30 –30 –45 –60 –75 2 –90 3 4 –105 + 5 6 125MSPS 200.5MHz AT –1dBFS SNR = 70.7dB (71.7dBFS) SFDR = 76.6dBc –15 AMPLITUDE (dBFS) –15 –45 –60 3 –75 2 + –90 5 6 4 48 54 –105 –120 –120 0 6 12 18 24 30 36 FREQUENCY (MHz) 42 48 54 60 –135 10538-009 –135 6 10538-011 AMPLITUDE (dBFS) 6 10538-010 12 6 10538-007 0 Figure 7. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V AMPLITUDE (dBFS) + 6 4 –120 FREQUENCY (MHz) –135 3 5 –105 –120 –135 –45 Figure 9. Single-Tone 16k FFT with fIN = 64 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 6 12 18 24 30 36 FREQUENCY (MHz) 42 60 10538-012 AMPLITUDE (dBFS) –30 125MSPS 70MHz AT –1dBFS SNR = 75.6dB (76.6dBFS) SFDR = 85.5dBc –15 Figure 12. Single-Tone 16k FFT with fIN = 200.5 MHz at fSAMPLE = 125 MSPS, VREF = 1.0 V Rev. F | Page 14 of 41 Data Sheet AD9653 120 120 SFDRFS 100 SFDR (dBc) SNRFS 60 SFDR 40 20 SNR –80 –70 –60 –50 –40 –30 –20 –10 0 40 INPUT AMPLITUDE (dBFS) 0 10538-013 –90 SNR (dBFS) 60 20 0 –20 –100 80 Figure 13. SNR/SFDR vs. Input Amplitude (AIN), fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 20 40 60 80 100 120 140 160 180 200 INPUT FREQUENCY (MHz) 10538-016 80 SNR/SFDR (dBFS/dBc) SNR/SFDR (dBFS/dBc) 100 Figure 16. SNR/SFDR vs. fIN, fSAMPLE = 125 MSPS, Clock Divider = 8, VREF = 1.0 V 0 100 –15 95 SNR/SFDR(dBFS/dBc) AMPLITUDE (dBFS) –30 –45 –60 –75 2F1 + F2 2F2 + F1 –90 F2 – F1 2F1 – F2 F2 – F1 F1 + F2 SFDR (dBc) 90 85 80 + –105 SNR (dBFS) 75 0 6 18 12 24 30 36 42 48 54 60 FREQUENCY (MHz) 70 –40 10538-014 –135 –20 0 20 40 60 80 TEMPERATURE (C) Figure 14. Two-Tone 16k FFT with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 10538-017 –120 Figure 17. SNR/SFDR vs. Temperature, fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 0 4.5 3.0 –40 SFDR (dBc) –60 1.5 IMD3 (dBc) INL (LSB) –80 0 –1.5 SFDR (dBFS) –3.0 –100 OUTPUT CODE Figure 15. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V Figure 18. INL, fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V Rev. F | Page 15 of 41 10538-018 60000 54000 48000 42000 36000 30000 24000 –10 18000 –30 12000 –50 INPUT AMPLITUDE (dBFS) 10538-015 –70 6000 –4.5 IMD3 (dBFS) –120 –90 0 SFDR/IMD3 (dBc/dBFS) –20 AD9653 Data Sheet 100 SFDR (dBc) 0.8 SNR/SFDR (dBFS/dBc) 0.6 DNL (LSB) 0.4 0.2 0 –0.2 –0.4 80 SNR (dBFS) 60 40 20 –0.6 OUTPUT CODE 40 2.7 LSB RMS 100 100000 80000 60000 40000 SFDR (dBc) Figure 20. Input-Referred Noise Histogram, fSAMPLE = 125 MSPS, VREF = 1.0 V DRVDD 70 60 50 AVDD 20 10 10 70 FREQUENCY (MHz) 10538-021 PSRR (dB) 40 60 80 100 120 10538-023 40 Figure 23. SNR/SFDR vs. Sample Rate, fIN = 64 MHz, Clock Divider = 4, VREF = 1.0 V 90 1 60 SAMPLE RATE (MSPS) 100 0 SNR (dBFS) 0 20 10538-020 N – 12 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 CODE 30 120 20 20000 40 100 80 SNR/SFDR (dBFS/dBc) NUMBER OF HITS 120000 80 80 Figure 22. SNR/SFDR vs. Sample Rate, fIN = 9.7 MHz, VREF = 1.0 V 140000 0 60 SAMPLE RATE (MSPS) Figure 19. DNL, fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 160000 20 10538-019 60000 54000 48000 42000 36000 30000 24000 18000 12000 6000 0 0 10538-022 –0.8 Figure 21. PSRR vs. Frequency, fSAMPLE = 125 MSPS, VREF = 1.0 V Rev. F | Page 16 of 41 Data Sheet AD9653 VREF = 1.3 V 0 0 125MSPS 9.7MHz AT –1dBFS SNR = 79.1dB (80.1dBFS) SFDR = 93.5dBc –30 –45 –60 –75 –90 3 2 + –75 + 12 18 24 30 36 42 48 54 60 –135 0 12 18 24 30 36 42 48 54 60 Figure 27. Single-Tone 16k FFT with fIN = 70 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V 0 125MSPS 15MHz AT –1dBFS SNR = 78.3dB (79.3dBFS) SFDR = 94.5dBc –30 –30 –45 –60 –75 –90 3 + 2 –105 6 125MSPS 128MHz AT –1dBFS SNR = 73.5dB (74.5dBFS) SFDR = 86.7dBc –15 AMPLITUDE (dBFS) –15 4 5 –45 –60 –75 3 4 –105 –120 + 2 –90 5 6 –120 6 12 18 24 30 36 42 48 54 60 FREQUENCY (MHz) –135 10538-025 0 6 0 12 18 24 30 36 42 48 54 60 FREQUENCY (MHz) Figure 25. Single-Tone 16k FFT with fIN = 15 MHZ, fSAMPLE = 125 MSPS, VREF = 1.3 V 10538-028 AMPLITUDE (dBFS) 6 FREQUENCY (MHz) 0 Figure 28. Single-Tone 16k FFT with fIN = 128 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V 0 0 125MSPS 64MHz AT –1dBFS SNR = 76.9dB (77.9dBFS) SFDR = 82.6dBc –30 –30 –45 –60 –75 3 2 –90 4 6 + 5 –45 –60 –75 –120 18 24 30 36 42 48 54 FREQUENCY (MHz) 60 10538-026 –120 12 Figure 26. Single-Tone 16k FFT with fIN = 64 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V 2 + 6 5 –105 6 3 –90 –105 0 125MSPS 200.5MHz AT –1dBFS SNR = 71.1dB (72.1dBFS) SFDR = 73.7dBc –15 AMPLITUDE (dBFS) –15 AMPLITUDE (dBFS) 6 4 10538-027 6 10538-024 0 Figure 24. Single-Tone 16k FFT with fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V –135 5 –120 FREQUENCY (MHz) –135 3 2 –90 –105 –120 –135 –60 6 5 4 –105 –45 –135 0 4 6 12 18 24 30 36 42 48 54 FREQUENCY (MHz) Figure 29. Single-Tone 16k FFT with fIN = 200.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V Rev. F | Page 17 of 41 60 10538-029 AMPLITUDE (dBFS) –30 125MSPS 70MHz AT –1dBFS SNR = 76.7dB (77.7dBFS) SFDR = 82.1dBc –15 AMPLITUDE (dBFS) –15 AD9653 Data Sheet 0 0 80MSPS 15MHz AT –1dBFS SNR = 79.0dB (80.0dBFS) SFDR = 90.5dBc –30 –45 –60 –75 3 –90 –105 5 + 4 6 2 –75 2F1 + F2 2F2 + F1 –90 F2 – F1 F1 + F2 2F2 – F1 + 2F1 – F2 –120 4 8 12 16 20 24 28 32 36 40 –135 10538-030 0 FREQUENCY (MHz) Figure 30. Single-Tone 16k FFT with fIN = 15 MHz, fSAMPLE = 80 MSPS, VREF = 1.3 V 0 6 18 12 24 30 36 42 48 54 60 FREQUENCY (MHz) Figure 33. Two-Tone 16k FFT with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V 0 0 80MSPS 15MHz AT –1dBFS SNR = 76.7dB (77.7dBFS) SFDR = 82.1dBc –30 –20 SFDR/IMD3 (dBc/dBFS) –15 AMPLITUDE (dBFS) –60 –105 –120 –135 –45 10538-033 AMPLITUDE (dBFS) –30 –15 AMPLITUDE (dBFS) –15 –45 –60 –75 3 –90 + 5 –105 6 2 –40 SFDR (dBc) IMD3 (dBc) –60 –80 SFDR (dBFS) 4 –100 –120 4 8 12 16 20 24 28 32 36 40 FREQUENCY (MHz) –30 –10 Figure 34. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 70.5 MHz and fIN2 = 72.5 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V 100 120 SFDRFS SFDR (dBc) 90 100 80 SNR/SFDR (dBFS/dBc) SNRFS 80 60 SFDR 40 20 SNR 70 SNR (dBFS) 60 50 40 30 20 0 10 –90 –80 –70 –60 –50 –40 –30 –20 –10 INPUT AMPLITUDE (dBFS) Figure 32. SNR/SFDR vs. Input Amplitude (AIN), fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V 0 0 10538-032 SNR/SFDR (dBFS/dBc) –50 INPUT AMPLITUDE (dBFS) Figure 31. Single-Tone 16k FFT with fIN = 64.5 MHz, fSAMPLE = 80 MSPS, VREF = 1.3 V –20 –100 –70 0 20 40 60 80 100 120 140 INPUT FREQUENCY (MHz) 160 180 200 10538-035 0 10538-034 IMD3 (dBFS) –120 –90 10538-031 –135 Figure 35. SNR/SFDR vs. fIN, fSAMPLE = 125 MSPS, Clock Divider = 8, VREF = 1.3 V Rev. F | Page 18 of 41 Data Sheet AD9653 200000 94 2.1 LSB RMS 180000 160000 SFDR (dBc) 88 86 84 140000 120000 100000 82 60000 40000 SNR (dBFS) Figure 36. SNR/SFDR vs. Temperature, fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V CODE 10538-039 N+9 N + 10 N+8 N+7 N+6 N+5 N+4 N+3 N+2 N N+1 N–1 TEMPERATURE (°C) N–2 80 N–3 60 N–4 40 N–5 20 N–6 0 10538-036 0 78 N–7 20000 N–8 80 80000 N–9 90 NUMBER OF HITS SNR/SFDR (dBFS/dBc) 92 Figure 39. Input-Referred Noise Histogram, fSAMPLE = 125 MSPS, VREF = 1.3 V 100 90 3.0 70 1.5 60 0 –1.5 50 40 AVDD 20 –4.5 10 OUTPUT CODE 1 10 FREQUENCY (MHz) 10538-037 60000 54000 48000 42000 36000 30000 24000 18000 12000 6000 0 70 10538-040 30 –3.0 0 DRVDD 80 PSRR (dB) INL (LSB) 4.5 Figure 40. PSRR vs. Frequency, fSAMPLE = 125 MSPS, VREF = 1.3 V Figure 37. INL, fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V 100 0.8 SFDR (dBc) SNR/SFDR (dBFS/dBc) 0.6 0.2 0 –0.2 –0.4 SNR (dBFS) 60 40 20 –0.6 OUTPUT CODE 10538-038 60000 54000 48000 42000 36000 30000 24000 18000 12000 6000 0 Figure 38. DNL, fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V 20 40 60 80 100 120 SAMPLE RATE (MSPS) Figure 41. SNR/SFDR vs. Sample Rate, fIN = 9.7 MHz, VREF = 1.3 V Rev. F | Page 19 of 41 10538-041 –0.8 0 DNL (LSB) 0.4 80 AD9653 Data Sheet 100 SFDR (dBc) SNR/SFDR (dBFS/dBc) 80 SNR (dBFS) 60 40 0 20 40 60 80 SAMPLE RATE (MSPS) 100 120 10538-042 20 Figure 42. SNR/SFDR vs. Sample Rate, fIN = 64 MHz, Clock Divider = 4, VREF = 1.3 V Rev. F | Page 20 of 41 Data Sheet AD9653 EQUIVALENT CIRCUITS AVDD AVDD 350Ω SCLK/DTP, SYNC, AND PDWN 30kΩ 10538-047 10538-043 VIN±x Figure 43. Equivalent Analog Input Circuit Figure 47. Equivalent SCLK/DTP, SYNC, and PDWN Input Circuit AVDD 10Ω CLK+ AVDD 15kΩ 0.9V AVDD 15kΩ 10538-048 10538-044 CLK– 375Ω RBIAS AND VCM 10Ω Figure 44. Equivalent Clock Input Circuit Figure 48. Equivalent RBIAS and VCM Circuit AVDD AVDD 400Ω SDIO/OLM 30kΩ 31kΩ 10538-049 10538-045 CSB 350Ω Figure 45. Equivalent SDIO/OLM Input Circuit Figure 49. Equivalent CS Input Circuit DRVDD AVDD V D0–x, D1–x V V D0+x, D1+x V 375Ω VREF 10538-046 10538-050 7.5kΩ Figure 50. Equivalent VREF Circuit Figure 46. Equivalent Digital Output Circuit Rev. F | Page 21 of 41 AD9653 Data Sheet THEORY OF OPERATION The AD9653 is a multistage, pipelined ADC. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The serializer transmits this converted data in a 16-bit output. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and data clocks. ANALOG INPUT CONSIDERATIONS The analog input to the AD9653 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a differential capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled FrontEnd for Wideband A/D Converters” (Volume 39, April 2005) for more information. In general, the precise values depend on the application. Input Common Mode The analog inputs of the AD9653 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 52 and Figure 53. An on-chip, common-mode voltage reference is included in the design and is available from the VCM pin. The VCM pin must be bypassed to ground by a 0.1 µF capacitor, as described in the Applications Information section. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9653, the input span is dependent on the reference voltage (see Table 11). 110 H H 90 S S S S CSAMPLE SNR/SFDR (dBFS/dBc) CSAMPLE H 10538-051 H CPAR SNRFS (dBFS) 80 70 60 50 40 Figure 51. Switched-Capacitor Input Circuit 30 The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 51). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from Rev. F | Page 22 of 41 20 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 COMMON-MODE VOLTAGE (V) Figure 52. SNR/SFDR vs. Common-Mode Voltage, fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.0 V 1.3 10538-052 VIN+x VIN–x SFDR (dBc) 100 CPAR Data Sheet AD9653 110 Internal Reference Connection SFDR (dBc) 100 A comparator within the AD9653 detects the potential at the SENSE pin and configures the reference into one of three possible modes, which are summarized in Table 11. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 54), setting the voltage at the VREF pin, VREF, to 1.0 V. If SENSE is connected to an external resistor divider (see Figure 55), VREF is defined as SNR/SFDR (dBFS/dBc) 90 SNRFS (dBFS) 80 70 60 50 R2  V REF  0 . 5   1   R1   40 30 where: 0.7 0.8 0.9 1.0 1.1 1.2 COMMON-MODE VOLTAGE (V) 1.3 7 kΩ ≤ (R1 + R2) ≤ 10 kΩ 10538-053 20 0.6 Figure 53. SNR/SFDR vs. Common-Mode Voltage, fIN = 9.7 MHz, fSAMPLE = 125 MSPS, VREF = 1.3 V VIN+A VIN–A Differential Input Configurations ADC CORE There are several ways to drive the AD9653 either actively or passively. However, optimum performance is achieved by driving the analog inputs differentially. Using a differential double balun configuration to drive the AD9653 provides excellent performance and a flexible interface to the ADC (see Figure 56) for baseband applications. VREF 1.0µF 0.1µF SELECT LOGIC SENSE For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 57), because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9653. 10538-054 0.5V AD9653 Figure 54. 1.0 V Internal Reference Configuration Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. VIN+A VIN–A It is not recommended to drive the AD9653 inputs single-ended. VOLTAGE REFERENCE ADC CORE A stable and accurate voltage reference is built into the AD9653. VREF can be configured using either the internal 1.0 V reference, an externally applied 1.0 V to 1.3 V reference voltage, or using an external resistor divider applied to the internal reference to produce a reference voltage of the user’s choice. The various reference modes are summarized in the Internal Reference Connection section and the External Reference Operation section. The VREF pin should be externally bypassed to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. VREF + 0.1µF R2 SENSE SELECT LOGIC R1 0.5V AD9653 10538-055 1.0µF Figure 55. Programmable Internal Reference Configuration Table 11. Reference Configuration Summary Selected Mode Fixed Internal Reference Programmable Internal Reference Fixed External Reference 1 SENSE Voltage (V) AGND to 0.2 Tie to external R-divider (see Figure 55) AVDD Resulting VREF (V) 1.0 internal 0.5 × (1 + R2/R1), example: R1 = 3.5 kΩ, R2 = 5.6 kΩ for VREF = 1.3 V1 1.0 to 1.3 applied to external VREF pin1 Normal operation for VREF = 1.3 V is supported over the 0°C to 85°C temperature range. Rev. F | Page 23 of 41 Resulting Differential Span (V p-p) 2.0 2 × VREF 2.0 to 2.6 AD9653 Data Sheet 0.1µF 0.1µF R 33Ω C 2V p-p ET1-1-I3 C 33Ω 0.1µF *C1 ADC 5pF R 33Ω C VIN+x 33Ω VIN–x VCM *C1 200Ω 0.1µF C 0.1µF *C1 IS OPTIONAL 10538-056 R Figure 56. Differential Double Balun Input Configuration for Baseband Applications ADT1-1WT 1:1 Z RATIO R *C1 VIN+x 33Ω 2V p-p 49.9Ω C R 33Ω ADC 5pF VIN–x VCM *C1 0.1µF 0.1μF *C1 IS OPTIONAL 10538-057 200Ω Figure 57. Differential Transformer-Coupled Configuration for Baseband Applications 0 –0.5 –1.0 –1 –2 INTERNAL VREF = 1.0V –1.5 –4 –5 –6 –9 –3.0 0 0.5 1.0 1.5 2.0 2.5 LOAD CURRENT (mA) –3.5 3.0 10538-059 –8 –2.5 Figure 59. VREF =1.3 V Error vs. Load Current –4.0 External Reference Operation –4.5 –5.0 INTERNAL VREF = 1.3V –3 –7 –2.0 0 0.5 1.0 1.5 2.0 2.5 LOAD CURRENT (mA) Figure 58. VREF = 1.0 V Error vs. Load Current 3.0 10538-058 VREF ERROR (%) 0 VREF ERROR (%) If the internal reference of the AD9653 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 58 and Figure 59 show how the internal reference voltage is affected by loading. The use of an external reference may be necessary to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 60 and Figure 61 show the typical drift characteristics of the internal reference in 1.0 V mode and programmable 1.3 V mode, respectively. Rev. F | Page 24 of 41 Data Sheet AD9653 4 The RF balun configuration is recommended for clock frequencies between 125 MHz and 1 GHz, and the RF transformer is recommended for clock frequencies from 20 MHz to 200 MHz. The antiparallel Schottky diodes across the transformer/balun secondary winding limit clock excursions into the AD9653 to approximately 0.8 V p-p differential. –2 –4 –8 –40 10 –15 35 60 85 TEMPERATURE (°C) 10538-060 –6 This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9653 while preserving the fast rise and fall times of the signal that are critical to achieving low jitter performance. However, the diode capacitance comes into play at frequencies above 500 MHz. Care must be taken in choosing the appropriate signal limiting diode. Mini-Circuits® ADT1-1WT, 1:1 Z Figure 60. Typical VREF = 1.0 V Drift 0.1µF CLOCK INPUT 10 XFMR 0.1µF CLK+ 100Ω 50Ω 5 Figure 62. Transformer-Coupled Differential Clock (Up to 200 MHz) –5 0.1µF CLOCK INPUT –10 CLK+ 50Ω 0.1µF –20 0 20 40 60 80 TEMPERATURE (°C) ADC 0.1µF CLK– SCHOTTKY DIODES: HSMS2822 10538-061 –15 –40 0.1µF 10538-063 VREF ERROR (mV) CLK– SCHOTTKY DIODES: HSMS2822 0.1µF 0 ADC 0.1µF 10538-062 0 Figure 63. Balun-Coupled Differential Clock (Up to 1 GHz) Figure 61. Typical VREF = 1.3 V Drift When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. An internal reference buffer loads the external reference with an equivalent 7.5 kΩ load (see Figure 50). The internal buffer generates the positive and negative full-scale references for the ADC core. If a low jitter clock source is not available, another option is to ac couple a differential PECL signal to the sample clock input pins, as shown in Figure 64. The AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515/AD9516-4/AD9517-4 clock drivers offer excellent jitter performance. It is not recommended to leave the SENSE pin floating. A third option is to ac couple a differential LVDS signal to the sample clock input pins, as shown in Figure 65. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515/AD9516-4/ AD9517-4 clock drivers offer excellent jitter performance. CLOCK INPUT CONSIDERATIONS For optimum performance, clock the AD9653 sample clock inputs, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally (see Figure 44) and require no external bias. Clock Input Options The AD9653 has a flexible clock input structure. The clock input can be a CMOS, LVDS, LVPECL, or sine wave signal. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 62 and Figure 63 show two preferred methods for clocking the AD9653 (at clock rates up to 1 GHz prior to internal clock divider). A low jitter clock source is converted from a singleended signal to a differential signal using either a radio frequency (RF) transformer or an RF balun. In some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 V CMOS signal. In such applications, drive the CLK+ pin directly from a CMOS gate, and bypass the CLK− pin to ground with a 0.1 μF capacitor (see Figure 66). 0.1µF CLOCK INPUT CLOCK INPUT Rev. F | Page 25 of 41 0.1µF 50kΩ 50kΩ 0.1µF AD951x PECL DRIVER 240Ω 100Ω 0.1µF CLK+ ADC CLK– 240Ω Figure 64. Differential PECL Sample Clock (Up to 1 GHz) 10538-064 VREF ERROR (mV) 2 AD9653 Data Sheet 84 100Ω 0.1µF ADC 80 CLK– 50kΩ Figure 65. Differential LVDS Sample Clock (Up to 1 GHz) 50Ω1 1kΩ AD951x CMOS DRIVER OPTIONAL 0.1µF 100Ω 1kΩ 72 CLK+ ADC 70 40 45 150Ω RESISTOR IS OPTIONAL. 55 60 Figure 67. SNR vs. DCS On/Off, VREF = 1.0 V 10538-066 0.1µF 50 DUTY CYCLE (%) CLK– 10538-076 0.1µF SNRFS (DCS OFF) 76 74 VCC CLOCK INPUT SNRFS (DCS ON) 78 84 Figure 66. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz) 82 Input Clock Divider SNRFS (DCS ON) The AD9653 clock divider can be synchronized using the external SYNC input. Bit 0 and Bit 1 of Register 0x109 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. SNR (dBFS) 80 The AD9653 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. SNRFS (DCS OFF) 78 76 74 72 70 40 45 50 55 DUTY CYCLE (%) Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9653 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This feature minimizes performance degradation in cases where the clock input duty cycle deviates from 50% greater than the specified ±5%. Noise and distortion performance are nearly flat for a wider range of duty cycles with the DCS on, as shown in Figure 67 and Figure 68. 60 10538-077 50kΩ AD951x LVDS DRIVER 82 CLK+ 10538-065 CLOCK INPUT 0.1µF 0.1µF SNR (dBFS) 0.1µF CLOCK INPUT Figure 68. SNR vs. DCS On/Off, VREF = 1.3 V Jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates less than 20 MHz, nominally. The loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. A wait time of 1.5 µs to 5 µs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by   1    2π × f A × t J  SNR Degradation = 20 log10  In this equation, the rms aperture jitter represents the root sum square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 69). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9653. Power supplies for clock drivers should be separated from the Rev. F | Page 26 of 41 Data Sheet AD9653 ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. 130 RMS CLOCK JITTER REQUIREMENT 120 DIGITAL OUTPUTS AND TIMING 110 16 BITS 90 14 BITS 80 The AD9653 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SPI. The LVDS driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing (or 700 mV p-p differential) at the receiver. 12 BITS 70 10 BITS 60 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 8 BITS 50 40 1 10538-067 SNR (dB) 100 30 1000 100 10 ANALOG INPUT FREQUENCY (MHz) Figure 69. Ideal SNR vs. Input Frequency and Jitter POWER DISSIPATION AND POWER-DOWN MODE As shown in Figure 70, the power dissipated by the AD9653 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. 0.60 0.55 ANALOG CORE POWER (W) and clock. Internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map section for more details on using these features. 0.50 0.45 VREF = 1.3V VREF = 1.0V 0.40 When operating in reduced range mode, the output current is reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p differential) across a 100 Ω termination at the receiver. The AD9653 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. An example of the FCO and data stream with proper trace length and position is shown in Figure 71. Figure 72 shows the LVDS output timing example in reduced range mode. 0.35 0.30 0.20 20 40 60 80 SAMPLE RATE (MSPS) 100 120 10538-068 0.25 The AD9653 is placed in power-down mode either by the SPI port or by asserting the PDWN pin high. In this state, the ADC typically dissipates 2 mW. During power-down, the output drivers are placed in a high impedance state. Asserting the PDWN pin low returns the AD9653 to its normal operating mode. Note that PDWN is referenced to the analog supply (AVDD) and must not exceed that supply voltage. D0 500mV/DIV D1 500mV/DIV DCO 500mV/DIV FCO 500mV/DIV 4ns/DIV 10538-069 Figure 70. Analog Core Power vs. fSAMPLE for fIN = 9.7 MHz, Four Channels Figure 71. LVDS Output Timing Example in ANSI-644 Mode (Default) Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, Rev. F | Page 27 of 41 AD9653 Data Sheet 500 EYE: ALL BITS ULS: 8000/414024 EYE DIAGRAM VOLTAGE (mV) 400 300 200 100 0 –100 –200 –300 –400 –500 4ns/DIV –0.8ns 10538-070 D0 400mV/DIV D1 400mV/DIV DCO 400mV/DIV FCO 400mV/DIV –0.4ns 0ns 0.4ns –0.8ns 12k An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 73. 500 EYE: ALL BITS ULS: 7000/400354 300 200 8k 6k 4k 2k 100 0k –800ps –600ps –400ps –200ps 0 –100 0ps 200ps 400ps 600ps Figure 74. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End Termination Only –200 –300 Figure 74 shows an example of trace lengths exceeding 24 inches on standard FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. –400 –500 –0.8ns –0.4ns 0ns 0.4ns 0.8ns It is the user’s responsibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all four outputs to drive longer trace lengths. This can be achieved by programming Register 0x15. Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. 7k 6k TIE JITTER HISTOGRAM (Hits) 10k 10538-072 EYE DIAGRAM VOLTAGE (mV) 400 TIE JITTER HISTOGRAM (Hits) Figure 72. LVDS Output Timing Example in Reduced Range Mode 5k 4k 3k 2k 0 200ps 250ps 300ps 350ps 400ps 450ps 500ps 10538-071 1k The format of the output data is twos complement by default. An example of the output coding format can be found in Table 12. To change the output data format to offset binary, see the Memory Map section. Figure 73. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4 Material, External 100 Ω Far-End Termination Only Rev. F | Page 28 of 41 Data Sheet AD9653 Data from each ADC is serialized and provided on a separate channel in two lanes in DDR mode. The data rate for each serial stream is equal to 16 bits times the sample clock rate divided by the number of lanes, with a maximum of 1000 Mbps/lane [(16 bits × 125 MSPS)/2 = 1000 Mbps/lane]. The maximum allowable output data rate is 1 Gbps/lane. If one-lane mode is used, the data rate doubles for a given sample rate. To stay within the maximum data rate of 1 Gbps/lane, the sample rate is limited to a maximum of 62.5 MSPS in one-lane output mode. The lowest typical conversion rate is 20 MSPS. Two output clocks are provided to assist in capturing data from the AD9653. The DCO is used to clock the output data and is equal to four times the sample clock (CLK) rate for the default mode of operation. Data is clocked out of the AD9653 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate in 1× frame mode. See the Timing Diagrams section for more information. When the SPI is used, the DCO phase can be adjusted in 60° increments relative one data cycle (30° relative to one DCO cycle). This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 180° relative to one data cycle (90° relative to one DCO cycle). In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. This can be inverted so that the LSB is first in the data output serial stream by using the SPI. There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 13 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns do not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. Table 12. Digital Output Coding Input (V) VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− VIN+ − VIN− Condition (V) +VREF − 0.5 LSB Offset Binary Output Mode 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1111 Twos Complement Mode 1000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0111 1111 1111 1111 0111 1111 1111 1111 Table 13. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 Pattern Name Off (default) Midscale short Digital Output Word 1 Not applicable 1000 0000 0000 0000 (16-bit) Digital Output Word 2 Not applicable Not applicable Subject to Data Format Select Not applicable Yes 0010 +Full-scale short 1111 1111 1111 1111 (16-bit) Not applicable Yes 0011 −Full-scale short 0000 0000 0000 0000 (16-bit) Not applicable Yes 0100 0101 Checkerboard PN sequence long 1010 1010 1010 1010 (16-bit) Not applicable 0101 0101 0101 0101 (16-bit) Not applicable No Yes 0110 PN sequence short Not applicable Not applicable Yes 0111 1111 1111 1111 1111 (16-bit) 0000 0000 0000 0000 (16-bit) No 1000 1001 1010 1011 One-/zero-word toggle User input 1-/0-bit toggle 1× sync One bit high Register 0x19 to Register 0x1A 1010 1010 1010 1010 (16-bit) 0000 0000 1111 1111 (16-bit) 1000 0000 0000 0000 (16-bit) Register 0x1B to Register 0x1C Not applicable Not applicable Not applicable No No No No 1100 Mixed frequency 1010 0001 1001 1100 (16-bit) Not applicable No Rev. F | Page 29 of 41 Notes Offset binary code shown Offset binary code shown Offset binary code shown PN23 ITU 0.150 X23 + X18 + 1 PN9 ITU 0.150 X9 + X5 + 1 Pattern associated with the external pin AD9653 Data Sheet The pseudorandom number (PN) sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The seed value is all 1s (see Table 14 for the initial values). The output is a parallel representation of the serial PN9 sequence in MSB-first format. The first output word is the first 16 bits of the PN9 sequence in MSB aligned form. The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The seed value is all 1s (see Table 14 for the initial values) and the AD9653 inverts the bit stream with relation to the ITU standard. The output is a parallel representation of the serial PN23 sequence in MSB-first format. The first output word is the first 16 bits of the PN23 sequence in MSB aligned form Table 14. PN Sequence Sequence PN Sequence Short PN Sequence Long Initial Value 0x7F83 0x7FFF Next Three Output Samples (MSB First) Twos Complement 0x5F17, 0xB209, 0xCED1 0x7E00, 0x807C, 0x801F Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. SDIO/OLM Pin For applications that do not require SPI mode operation, the CSB pin is tied to AVDD, and the SDIO/OLM pin controls the output lane mode according to Table 15. Note that, when the CSB pin is tied to AVDD, the AD9653 DCS is on by default and remains on unless the part is placed in SPI mode and controlled via the SPI. Refer to the Clock Duty Cycle section for more information on the DCS. For applications where the SDIO/OLM pin is not used, CSB should be tied to AVDD. When using the one-lane mode, the conversion rate should be ≤62.5 MSPS to meet the maximum output rate of 1 Gbps. Table 15. Output Lane Mode Pin Settings OLM Pin Voltage AVDD (Default) GND Output Mode Two-lane. 1× frame, 16-bit serial output One-lane. 1× frame, 16-bit serial output SCLK/DTP Pin The SCLK/DTP pin is used to select the digital test pattern (DTP) for applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device power-up. When SCLK/DTP is tied to AVDD, the ADC channel outputs shift out the following pattern: 1000 0000 0000 0000. The FCO and DCO function normally while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. This pin has an internal 10 kΩ resistor to GND. It can be left unconnected. Table 16. Digital Test Pattern Pin Settings Selected DTP Normal Operation DTP DTP Voltage 10 kΩ to AGND AVDD Resulting D0±x and D1±x Normal operation 1000 0000 0000 0000 Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section for information about the options available. CSB Pin The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. Note that when the CSB pin is tied to AVDD, the AD9653 DCS is on by default and remains on unless the part is placed in SPI mode and controlled via the SPI. Refer to the Clock Duty Cycle section for more information on the DCS. RBIAS Pin To set the internal core bias current of the ADC, place a 10.0 kΩ, 1% tolerance resistor to ground at the RBIAS pin. OUTPUT TEST MODES The output test options are described in Table 13 and controlled by the output test mode bits at Address 0x0D. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting, and some are not. The PN generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Rev. F | Page 30 of 41 Data Sheet AD9653 SERIAL PORT INTERFACE (SPI) The AD9653 serial port interface (SPI) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI offers the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The falling edge of the CSB, in conjunction with the rising edge of the SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 75 and Table 7. CONFIGURATION USING THE SPI During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and W1 bits. Other modes involving the CSB are available. The CSB can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow for additional external timing. When CSB is tied high, SPI functions are placed in high impedance mode. This mode turns on any SPI pin secondary functions. Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 17). The SCLK (a serial clock) is used to synchronize the read and write data presented from and to the ADC. The SDIO (serial data input/output) is a dualpurpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB (chip select bar) is an active low control that enables or disables the read and write cycles. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. The first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. If the instruction is a readback operation, performing a readback causes the serial data input/output (SDIO) pin to change direction from an input to an output at the appropriate point in the serial frame. Table 17. Serial Port Interface Pins Pin SCLK SDIO CSB Function Serial clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. tHIGH tDS tS tDH All data is composed of 8-bit words. Data can be sent in MSBfirst mode or in LSB-first mode. MSB-first mode is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. tCLK tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 75. Serial Port Interface Timing Diagram Rev. F | Page 31 of 41 D4 D3 D2 D1 D0 DON’T CARE 10538-073 SCLK DON’T CARE AD9653 Data Sheet HARDWARE INTERFACE The pins described in Table 17 comprise the physical interface between the user programming device and the serial port of the AD9653. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9653 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Some pins serve a dual function when the SPI interface is not being used. When the pins are strapped to DRVDD or ground during device power-on, they are associated with a specific function. Table 15 and Table 16 describe the strappable functions supported on the AD9653. CONFIGURATION WITHOUT THE SPI In applications that do not interface to the SPI control registers, the SDIO/OLM pin, the SCLK/DTP pin, and the PDWN pin serve as standalone CMOS-compatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the output lane mode, digital test pattern, and power-down feature control. In this mode, CSB should be connected to AVDD, which disables the serial port interface. Note that, when the CSB pin is tied to AVDD, the AD9653 DCS is on by default and remains on unless the part is placed in SPI mode and controlled via the SPI. Refer to the Clock Duty Cycle section for more information on the DCS. When the device is in SPI mode, the PDWN pin (if enabled) remains active. For SPI control of power-down, the PDWN pin should be set to its default state. SPI ACCESSIBLE FEATURES Table 18 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9653 part-specific features are described in detail following Table 19, the external memory map register table. Table 18. Features Accessible Using the SPI Feature Name Power Mode Clock Offset Test Input/ Ouput Output Mode Output Phase Rev. F | Page 32 of 41 Description Allows the user to set either power-down mode or standby mode Allows the user to set the clock divider, set the clock divider phase, and enable the sync Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set the output mode Allows the user to set the output clock polarity Data Sheet AD9653 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Default Values Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the device index and transfer registers (Address 0x04, Address 0x05, and Address 0xFF); and the global ADC functions registers, including setup, control, and test (Address 0x08 to Address 0x109). After the AD9653 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 19. The memory map register table (see Table 19) lists the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x05, the device index register, has a hexadecimal default value of 0x3F. This means that in Address 0x05, Bits[7:6] = 0, and the remaining Bits[5:0] = 1. This setting is the default channel index setting. The default value results in all ADC channels receiving the next write command. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Register 0x00 to Register 0xFF. The remaining registers are documented in the Memory Map Register Descriptions section. Open Locations All address and bit locations that are not included in Table 19 are not currently supported for this device. Unused bits of a valid address location should be written with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x05). If the entire address location is open or not listed in Table 19 (for example, Address 0x13), this address location should not be written. Logic Levels An explanation of logic level terminology follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Channel-Specific Registers Some channel setup functions can be programmed differently for each channel. In these cases, channel address locations are internally duplicated for each channel. These registers and bits are designated in Table 19 as local. These local registers and bits can be accessed by setting the appropriate data channel bits (A, B, C, or D) and the clock channel DCO bit (Bit 5) and FCO bit (Bit 4) in Register 0x05. If all the bits are set, the subsequent write affects the registers of all channels and the DCO/FCO clock channels. In a read cycle, only one of the channels (A, B, C, or D) should be set to read one of the four registers. If all the bits are set during a SPI read cycle, the part returns the value for Channel A. Registers and bits designated as global in Table 19 affect the entire part or the channel features for which independent settings are not allowed between channels. The settings in Register 0x04 and Register 0x05 do not affect the global registers and bits. Rev. F | Page 33 of 41 AD9653 Data Sheet MEMORY MAP REGISTER TABLE The AD9653 uses a 3-wire interface and 16-bit addressing and, therefore, Bit 0 and Bit 7 in Register 0x00 are set to 0, and Bit 3 and Bit 4 are set to 1. When Bit 5 in Register 0x00 is set high, the SPI enters a soft reset, where all of the user registers revert to their default values and Bit 2 is automatically cleared. Table 19. ADDR (Hex) Parameter Name Chip Configuration Registers SPI port 0x00 configuration 0x01 Chip ID (global) 0x02 Chip grade (global) Bit 7 (MSB) 0= SDO active Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first Soft reset 1= 16-bit address 1= 16-bit address Soft reset LSB first Bit 0 (LSB) 0 = SDO active 8-bit chip ID, Bits[7:0] AD9653 0xB5 = quad, 16-bit, 125 MSPS serial LVDS Open Speed grade ID[6:4] 110 = 125 MSPS Default Value (Hex) 0x18 0xB5 Open Open Open Open Data Channel D Data Channel C Data Channel B Data Channel A 0x0F Device Index and Transfer Registers 0x04 Device index Open Open 0x05 Device index Open Open Clock Channel DCO Clock Channel FCO Data Channel D Data Channel C Data Channel B Data Channel A 0x3F 0xFF Transfer Open Open Open Open Open Open Open Initiate override 0x00 Global ADC Function Registers Power modes 0x08 Open (global) Open Open Open 0x09 Open External powerdown pin function 0 = full powerdown 1= standby Open Open Open Clock (global) Open Rev. F | Page 34 of 41 Open Open Power mode 00 = chip run 01 = full powerdown 10 = standby 11 = reset Open Duty cycle stabilize 0 = on 1 = off Comments The nibbles are mirrored so that LSBfirst or MSBfirst mode registers correctly. The default for ADCs is 16-bit mode. Unique chip ID used to differentiate devices; read only. Unique speed grade ID used to differentiate graded devices; read only. Bits[3:0] must be set to the same value as Register 0x05 Bits[3:0] Bits are set to determine which device on chip receives the next write command. The default is all devices on chip. Set sample rate override. 0x00 Determines various generic modes of chip operation. 0x01 Turns duty cycle stabilizer on or off. Data Sheet ADDR (Hex) 0x0B Parameter Name Clock divide (global) 0x0C Enhancement control 0x0D Test mode (local except for PN sequence resets) 0x10 0x14 Offset adjust (local) Output mode 0x15 Output adjust 0x16 Output phase 0x18 VREF AD9653 Bit 7 (MSB) Open Bit 0 (LSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Clock divide ratio[2:0] Open Open Open Open 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 Chop Open Open Open Open Open Open Open mode 0 = off 1 = on User input test mode Reset Reset PN Output test mode[3:0] (local) 00 = single PN long short 0000 = off (default) 01 = alternate gen gen 0001 = midscale short 10 = single once 0010 = positive FS 11 = alternate once 0011 = negative FS (affects user input test 0100 = alternating checkerboard mode only, 0101 = PN 23 sequence Bits[3:0] = 1000) 0110 = PN 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency 8-bit device offset adjustment [7:0] (local) Offset adjust in LSBs from +127 to −128 (twos complement format) Output LVDS-ANSI/ Output 1 Open Open Open Open format LVDS-IEEE invert 0= option (local) offset 0 = LVDSbinary ANSI 1= 1 = LVDStwos IEEE complereduced ment range link (global) (global) see Table 20 Output Output driver Open Open Open Open Open drive termination[1:0] 0 = 1× 00 = none drive 01 = 200 Ω 1 = 2× 10 = 100 Ω drive 11 = 100 Ω Output clock phase adjust[3:0] Input clock phase adjust[6:4] Open (0000 through 1011) (value is number of input clock see Table 22 cycles of phase delay) see Table 21 Open Open Open Open Open Rev. F | Page 35 of 41 VREF adjustment digital scheme[2:0] 000 = 1.0 V p-p (1.3 V p-p) 001 = 1.14 V p-p (1.48 V p-p) 010 = 1.33 V p-p (1.73 V p-p) 011 = 1.6 V p-p (2.08 V p-p) 100 = 2.0 V p-p (2.6 V p-p) Default Value (Hex) 0x00 Comments 0x00 Enables/ disables chop mode. 0x00 When set, the test data is placed on the output pins in place of normal data. 0x00 Device offset trim. Configures the outputs and the format of the data. 0x03 0x00 Determines LVDS or other output properties. 0x03 On devices that use global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. Selects internal VREF. Values shown are for VREF = 1.0 V (1.3 V). 0x04 AD9653 ADDR (Hex) 0x19 0x1A 0x1B 0x1C 0x21 Parameter Name USER_PATT1_LSB (global) USER_PATT1_MSB (global) USER_PATT2_LSB (global) USER_PATT2_MSB (global) Serial output data control (global) Data Sheet Bit 1 B1 Bit 0 (LSB) B0 Default Value (Hex) 0x00 B10 B9 B8 0x00 B3 B2 B1 B0 0x00 B11 B10 B9 B8 0x00 SDR/DDR one-lane/two-lane, bitwise/bytewise[6:4] 000 = SDR two-lane, bitwise 001 = SDR two-lane, bytewise 010 = DDR two-lane, bitwise 011 = DDR two-lane, bytewise 100 = DDR one-lane, wordwise Open Open Open Open Select 2× frame Open Open 0 Open Bit 7 (MSB) B7 Bit 6 B6 Bit 5 B5 Bit 4 B4 Bit 3 B3 Bit 2 B2 B15 B14 B13 B12 B11 B7 B6 B5 B4 B15 B14 B13 B12 LVDS output LSB first 0x22 Serial channel status (local) Open 0x100 Sample rate override Open Sample rate override enable 0x101 User Input/Output Control 2 Open Open Open Open Open Open 0x102 User Input/Output Control 3 Open Open Open Open Open 0x109 Sync Open Open Open Open VCM powerdown Open 0 Rev. F | Page 36 of 41 Open Serial output number of bits 00 = 16 bits Channel output reset Channel powerdown Sample rate 000 = 20 MSPS 001 = 40 MSPS 010 = 50 MSPS 011 = 65 MSPS 100 = 80 MSPS 101 = 105 MSPS 110 = 125 MSPS SDIO Open pulldown Open Open Sync next only Enable sync 0x30 0x00 0x00 Comments User Defined Pattern 1 LSB. User Defined Pattern 1 MSB. User Defined Pattern 2 LSB. User Defined Pattern 2 MSB. Serial stream control. Default causes MSB first and the native bit stream. Used to power down individual sections of a converter. Sample rate override (requires transfer register, 0xFF). 0x00 Disables SDIO pull-down. 0x00 VCM control. 0x00 Data Sheet AD9653 MEMORY MAP REGISTER DESCRIPTIONS For additional information about functions controlled in Register 0x00 to Register 0xFF, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. Device Index (Register 0x04, Register 0x05) There are certain features in the map that can be set independently for each channel, whereas other features apply globally to all channels (depending on context) regardless of which are selected. The first four bits in Register 0x04 and Register 0x05 are used to select which individual data channels are affected. The output clock channels can be selected in Register 0x05 as well. A smaller subset of the independent feature list can be applied to those devices. Enhancement Control (Register 0x0C) Bits[7:3]—Open Bit 2—Chop Mode For applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the AD9653 is a feature that can be enabled by setting Bit 2. In the frequency domain, chopping translates offsets and other low frequency noise to fCLK/2 where it can be filtered. Bits[1:0]—Open Output Mode (Register 0x14) Bit 7—Open Bit 6—LVDS-ANSI/LVDS-IEEE Option Register 0x04 Bits[3:0] must be set to the same value as Register 0x05 Bits[3:0] Setting this bit chooses LVDS-IEEE (reduced range) option. The default setting is LVDS-ANSI. As described in Table 20, when LVDS-ANSI or LVDS-IEEE reduced range link is selected, the user can select the driver termination. The driver current is automatically selected to give the proper output swing. Transfer (Register 0xFF) All registers except Register 0x100 are updated the moment they are written. Setting Bit 0 of this transfer register high initializes the settings in the sample rate override register (Address 0x100). Table 20. LVDS-ANSI/LVDS-IEEE Options Bit 5—External Power-Down Pin Function Output Mode, Bit 6 0 If set, the external PDWN pin initiates standby mode. If cleared, the external PDWN pin initiates power-down mode. 1 Power Modes (Register 0x08) Bits[7:6]—Open Bits[4:2]—Open Bits[1:0]—Power Mode In standby mode (Bits[1:0] = 10), the digital datapath clocks and the outputs are disabled. During a digital reset (Bits[1:0] = 11), all the digital datapath clocks and the outputs (where applicable) on the chip are reset, except the SPI port. Note that the SPI is always left under control of the user; that is, it is never automatically disabled or in reset (except by power-on reset). The default state is Bit 0 = 1, duty cycle stabilizer off. Note that, when the part is not in SPI mode, the duty cycle stabilizer is on. Refer to the Configuration Without the SPI section for more information. LVDS-IEEE reduced range link User selectable Output Driver Current Automatically selected to give proper swing Automatically selected to give proper swing Bit 2—Output Invert In power-down mode (Bits[1:0] = 01), the digital datapath clocks are disabled while the digital datapath is reset. Outputs are disabled. Bit 0—Duty Cycle Stabilize Output Driver Termination User selectable Bits[5:3]—Open In normal operation (Bits[1:0] = 00), all ADC channels are active. Clock (Register 0x09) Bits[7:1]—Open Output Mode LVDS-ANSI Setting this bit inverts the output bit stream. Bit 1—1 Bit 0—Output Format By default, this bit is set to send the data output in twos complement format. Resetting this bit changes the output mode to offset binary. Output Adjust (Register 0x15) Bits[7:6]—Open Bits[5:4]—Output Driver Termination These bits allow the user to select the internal termination resistor. Bits[3:1]—Open Bit 0—Output Drive Bit 0 of the output adjust register controls the drive strength on the LVDS driver of the FCO and DCO outputs only. The default values set the drive to 1× while the drive can be increased to 2× by setting the appropriate channel bit in Register 0x05 and then setting Bit 0. These features cannot be used with the output driver termination select. The termination selection takes Rev. F | Page 37 of 41 AD9653 Data Sheet precedence over the 2× driver strength on FCO and DCO when both the output driver termination and output drive are selected. Output Phase (Register 0x16) Bit 7—Open Bits[6:4]—Input Clock Phase Adjust When the clock divider (Register 0x0B) is used, the applied clock is at a higher frequency than the internal sampling clock. Register 0x16 Bits[6:4] determine at which phase of the external clock the sampling occurs. This is applicable only when the clock divider is used. It is prohibited to select a value for Bits[6:4] that is greater than the value of Bits[2:0], Register 0x0B. Table 21. Input Clock Phase Adjust Options Input Clock Phase Adjust, Bits[6:4] 000 (Default) 001 010 011 100 101 110 111 Number of Input Clock Cycles of Phase Delay 0 1 2 3 4 5 6 7 Bits[3:0]—Output Clock Phase Adjust Table 22. Output Clock Phase Adjust Options Output Clock (DCO), Phase Adjust, Bits[3:0] 0000 0001 0010 0011 (Default) 0100 0101 0110 0111 1000 1001 1010 1011 DCO Phase Adjustment (Degrees Relative to D0±x/D1±x Edge) 0 60 120 180 240 300 360 420 480 540 600 660 Serial Output Data Control (Register 0x21) The serial output data control register is used to program the AD9653 in various output data modes depending upon the data capture solution. Table 23 describes the various serialization options available in the AD9653. Sample Rate Override (Register 0x100) This register is designed to allow the user to downgrade the device (that is, establish lower power) for applications that do not require a full sample rate. Settings in this register are not initialized until Bit 0 of the transfer register (Register 0xFF) is set to 1. This function does not affect the sample rate; it affects the maximum sample rate capability of the ADC, as well as the resolution. User Input/Output Control 2 (Register 0x101) Bits[7:1]—Open Bit 0—SDIO Pull-Down Bit 0 can be set to disable the internal 30 kΩ pull-down on the SDIO pin, which can be used to limit the loading when many devices are connected to the SPI bus. User Input/Output Control 3 (Register 0x102) Bits[7:4]—Open Bit 3—VCM Power-Down Bit 3 can be set high to power down the internal VCM generator. This feature is used when applying an external reference. Bits[2:0]—Open Table 23. SPI Register Options Register 0x21 Contents 0x30 0x20 0x10 0x00 0x34 0x24 0x14 0x04 0x40 Serialization Options Selected Serial Output Number Frame Mode Serial Data Mode of Bits (SONB) 16-bit 1× DDR two-lane, bytewise 16-bit 1× DDR two-lane, bitwise 16-bit 1× SDR two-lane, bytewise 16-bit 1× SDR two-lane, bitwise 16-bit 2× DDR two-lane, bytewise 16-bit 2× DDR two-lane, bitwise 16-bit 2× SDR two-lane, bytewise 16-bit 2× SDR two-lane, bitwise 16-bit 1× DDR one-lane, wordwise Rev. F | Page 38 of 41 DCO Multiplier 4 × fS 4 × fS 8 × fS 8 × fS 4 × fS 4 × fS 8 × fS 8 × fS 8 × fS Timing Diagram Figure 2 (default setting) Figure 2 Figure 2 Figure 2 Figure 3 Figure 3 Figure 3 Figure 3 Figure 4 Data Sheet AD9653 APPLICATIONS INFORMATION Before starting design and layout of the AD9653 as a system, it is recommended that the designer become familiar with these guidelines, which describes the special circuit connections and layout requirements that are needed for certain pins. POWER AND GROUND RECOMMENDATIONS When connecting power to the AD9653, it is recommended that two separate 1.8 V supplies be used. Use one supply for analog (AVDD); use a separate supply for the digital outputs (DRVDD). For both AVDD and DRVDD, several different decoupling capacitors should be used to cover both high and low frequencies. Place these capacitors close to the point of entry at the PCB level and close to the pins of the part, with minimal trace length. A single PCB ground plane should be sufficient when using the AD9653. With proper decoupling and smart partitioning of the PCB analog, digital, and clock sections, optimum performance is easily achieved. CLOCK STABILITY CONSIDERATIONS When powered on, the AD9653 enters an initialization phase during which an internal state machine sets up the biases and the registers for proper operation. During the initialization process, the AD9653 needs a stable clock. If the ADC clock source is not present or not stable during ADC power-up, it disrupts the state machine and causes the ADC to start up in an unknown state. To correct this, an initialization sequence must be reinvoked after the ADC clock is stable by issuing a digital reset via Register 0x08. In the default configuration (internal VREF, ac-coupled input) where VREF and VCM are supplied by the ADC itself, a stable clock during power-up is sufficient. In the case where VREF and/or VCM are supplied by an external source, these, too, must be stable at power-up; otherwise, a subsequent digital reset via Register 0x08 is needed. The pseudo code sequence for a digital reset is as follows: SPI_Write (0x08, 0x03); SPI_Write (0x08, 0x00); Digital Reset Can be asserted as soon as the next SPI instruction, normal operation resumes after 2.9 million sample clock cycles, ADC outputs 0s until the reset is complete. EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS It is required that the exposed pad on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9653. An exposed continuous copper plane on the PCB should mate to the AD9653 exposed pad, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 76 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. SILKSCREEN PARTITION PIN 1 INDICATOR 10538-074 DESIGN GUIDELINES Figure 76. Typical PCB Layout VCM The VCM pin should be bypassed to ground with a 0.1 μF capacitor. REFERENCE DECOUPLING The VREF pin should be externally bypassed to ground with a low ESR, 1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic capacitor. SPI PORT The SPI port should not be active during periods when the full dynamic performance of the converter is required. Because the SCLK, CSB, and SDIO signals are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9653 to keep these signals from transitioning at the converter inputs during critical sampling periods. Rev. F | Page 39 of 41 AD9653 Data Sheet CROSSTALK PERFORMANCE The AD9653 is available in a 48-lead LFCSP with the input pairs on either corner of the chip. See Figure 6 for the pin configuration. To maximize the crosstalk performance on the board, add grounded filled vias in between the adjacent channels as shown in Figure 77. VIN CHANNEL A VIN CHANNEL B VIN CHANNEL D PIN 1 VIN CHANNEL C Figure 77. Layout Technique to Maximize Crosstalk Performance Rev. F | Page 40 of 41 10538-075 GROUNDED FILLED VIAS FOR ADDED CROSSTALK ISOLATION Data Sheet AD9653 OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 7.10 7.00 SQ 6.90 0.30 0.25 0.18 37 36 48 1 0.50 BSC 5.70 5.60 SQ 5.50 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 END VIEW PKG-004452 SEATING PLANE 0.50 0.40 0.30 24 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF PIN 1 INDIC ATOR AREA OPTIONS (SEE DETAIL A) 0.20 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4. 02-29-2016-A PIN 1 INDICATOR Figure 78. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9653BCPZ-125 AD9653BCPZRL7-125 AD9653-125EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Lead Frame Chip Scale Package [LFCSP] Evaluation Board Z = RoHS Compliant Part. ©2012–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10538-0-11/17(F) Rev. F | Page 41 of 41 Package Option CP-48-13 CP-48-13