AD9661A

a FEATURES < 2 ns Rise/Fall Times Output Current: 120 mA Single +5 V Power Supply Switching Rate: 200 MHz typ Onboard Light Power Control Loop APPLICATIONS Laser Printers and Copiers GENERAL DESCRIPTION Laser Diode Driver with Light Power Control AD9661A and fall times are 2 ns to complement printer applications that use image enhancing techniques such as pulse width modulation to achieve gray scale and resolution enhancement. Control signals are TTL/CMOS compatible. The driver output provides up to 120 mA of current into an infrared N type laser, and the onboard disable circuit turns off the output driver and returns the light power control loop to a safe state. The AD9661A can also be used in closed-loop applications in which the output power level follows an analog POWER LEVEL voltage input. By optimizing the external hold capacitor and the photo detector, the loop can achieve bandwidths as high as 25 MHz. The AD9661A is offered in a 28-pin plastic SOIC for operation over the commercial temperature range (0°C to +70°C). The AD9661A is a highly integrated driver for laser diode applications such as printers and copiers. The AD9661A gets feedback from an external photo detector and includes an analog feedback loop to allow users to set the power level of the laser, and switch the laser on and off at up to 100 MHz. Output rise FUNCTIONAL BLOCK DIAGRAM DISABLE PULSE PULSE2 CAL TTL TTL DISABLE CIRCUIT *13ns DELAY ON RISING EDGE; 0ns ON FALLING HOLD TTL TTL DELAY * VOLT REF VREF +5V PHOTO DETECTOR POWER LEVEL LEVEL SHIFT OUT LEVEL SHIFT IN DAC GAIN CGAIN RGAIN ANALOG VLEVEL SHIFT IN + VREF 5pF LEVEL SHIFT CIRCUIT 0–1.6V 50Ω V1 1:10 REF 3–120mA IOUT LASER DIODE OUTPUT 8 AD9661A ANALOG POWER MONITOR VREF IMONITOR 1:1 SENSE IN IMONITOR 1.0V R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. © Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD9661A–SPECIFICATIONS (+V = +5 V, Temperature = +25 C unless otherwise noted) S Parameter ANALOG INPUT Input Voltage Range, POWER LEVEL Input Bias Current, POWER LEVEL Analog Bandwidth, Control Loop1 Input Voltage Range, LEVEL SHIFT IN Input Bias Current, LEVEL SHIFT IN Analog Bandwidth, Level Shift2 Level Shift Offset Level Shift Gain OUTPUTS Output Current, IOUT Output Compliance Range Idle Current Disable Current SWITCHING PERFORMANCE Maximum Pulse Rate Output Propagation Delay (tPD), Rising3 Output Propagation Delay (tPD), Falling3 Output Current Rise Time4 Output Current Fall Time5 CAL Aperture Delay6 Disable Time7 HOLD NODE Input Bias Current Input Voltage Range Minimum External Hold Cap TTL/CMOS INPUTS Logic “1” Voltage Logic “1” Voltage Logic “0” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current 8 Test Level Temp Min AD9661AKR Typ Max Units Conditions IV I V IV I V I I I IV I IV V IV IV IV IV IV IV I IV V I IV I IV I I I V V I I V I I Full +25°C +25°C Full +25°C Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C Full Full Full Full Full +25°C +25°C Full Full +25°C Full +25°C Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C VREF –50 25 0.1 –10 130 –32 0.95 120 2.50 2 1.0 VREF + 1.6 +50 1.6 0 +32 1.05 V µA MHz V µA MHz mV V/V mA V mA µA MHz ns ns ns ns ns ns nA V pF V V V V µA mA V mV/°C mA mA/mA V Ω V mA CHOLD = 33 pF, RF = 1 kΩ, CF = 2 pF VOUT = 2.5 V PULSE = LOW, DISABLE = LOW PULSE = LOW, DISABLE = HIGH Output Current –3 dB 5.25 5.0 1.0 2.9 3.2 200 3.9 3.7 1.5 1.5 13 3 5.0 4.3 2.0 2.0 5 200 VREF + 1.6 –200 VREF 25 2.0 2.0 VHOLD = 2.5 V Open-Loop Application Only –10 –1.5 1.6 –0.5 0.95 0.7 1 1.0 5 τ = 12.36 µs. Initial calibration time will actually be better than this calculation indicates, as a significant portion of the calibration time will be within 10% of the final value, and the output resistance in the AD9660’s T/H decreases as the hold voltage approaches its final value. Recalibration is functionally identical to initial calibration, but the loop need only correct for droop. Because droop is assumed to be a small percentage of the initial calibration (< 10%), the resistance for the model above will be in the range of 75 Ω to 140 Ω. Again, the higher value should be used to estimate the worst case time needed for recalibration. Continuing with the example above, since the droop error during hold time is < 5%, we meet the criteria for recalibration and τ = RC = 140 Ω × 4.5 nF = 0.64 µs. To get a final error of 1% after recalibration, the 5% droop must be corrected to within a 20% error (20% × 5% = 1%). A 2 τ recalibration time of 1.2 µs is sufficient. Continuous Recalibration Figure 5. Driving the Analog Inputs Using the Level Shift Circuit The AD9661A includes an on board level shift circuit to provide the offset described above. The input, LEVEL SHIFT IN, has an input range from 0.1 V to 1.6 V. The output, LEVEL SHIFT OUT, has a range from VREF to VREF +1.6 V, and can drive POWER MONITOR. The linearity of the level shift circuit is poor for inputs below 100 mV. Between 100 mV and 1.6 V it is about 7 bits accurate. Layout Considerations As in all high speed applications, proper layout is critical; it is particularly important when both analog and digital signals are involved. Analog signal paths should be kept as short as possible, and isolated from digital signals to avoid coupling in noise. In particular, digital lines should be isolated from OUTPUT, SENSE IN, POWER LEVEL, LEVEL SHIFT IN POWER MONITOR, and HOLD traces. Digital signal paths should also be kept short, and run lengths matched to avoid propagation delay mismatch. Layout of the ground and power supply circuits is also critical. A single, low impedance ground plane will reduce noise on the circuit ground. Power supplies should be capacitively coupled to the ground plane to reduce noise in the circuit. 0.1 µF surface mount capacitors, placed as close as possible to the AD9661A +VS connections, and the +VS connection to the laser diode meet this requirement. Multilayer circuit boards allow designers to lay out signal traces without interrupting the ground plane, and provide low impedance power planes to further reduce noise. In applications where the hold capacitor is small (< 500 pF) and the WRITE PULSE signals always have a pulse width > 25 ns, the user may continuously calibrate the feedback loop. In such an application, the CAL signal should be held logic LOW, and the PULSE signal will control loop calibration via the internal AND gate. In such application, it is important to optimize the layout for the TZA (POWER MONITOR, GAIN, RGAIN and CGAIN). REV. 0 –7– AD9661A Minimizing the Impedance of the Output Current Path Optimizing the Feedback Layout Because of the very high current slew that the AD9661A is capable of producing (120+ mA in 1.5 ns), the inductance of the output current path to and from the laser diode is critical. A good layout of the output current path will yield high quality light pulses with rise times of about 1.5 ns and less than 5% overshoot. A poor layout can result in significant overshoot and ringing. The most important guideline for the layout is to minimize the impedance (mostly inductance) of the output current path to the laser. It is important to recognize that the laser current path is a closed loop. The figure illustrates the path that current travels: (1) from the +VS connection at the anode of the laser to the cathode (2) from the cathode to the output pins of the AD9661A (3) through the output drive circuit of the AD9661A, (4) through the return path (GROUND plane in the illustration) (5) through the bypass capacitors back to the +VS connection of the laser diode. The inductance of this loop can be minimized by placing the laser as close to the AD9661A as possible to keep the loop short, and by placing the send and return paths on adjacent layers of the PC board to take advantage of mutual coupling of the path inductances. This mutual coupling effect is the most important factor in reducing inductance in the current path. The trace from the output pins of the AD9661A to the cathode of the laser should be several millimeters wide and should be as direct as possible. The return current will choose the path of least resistance. If the return path is the GROUND plane, it should have an unbroken path, under the output trace, from the laser anode back to a the AD9661A. If the return path is not the ground plane (such as on a two layer board, or on the +VS plane), it should still be on the board plane adjacent to the plane of the output trace. If the current cannot return along a path that follows the output trace, the inductance will be drastically increased and performance will be degraded. In applications where the dynamic performance of the analog feedback loop is important, it is necessary to optimize the layout of the gain resistor, RGAIN, as well as the monitor current path to SENSE IN. Such applications include systems which recalibrate the write loop on pulses as short as 25 ns, and closed-loop applications. The best possible TZA settling will be achieved by using a single carbon surface mount resistor (usually 5% tolerance) for RGAIN and small surface mount capacitor for CGAIN. Because the GAIN pin (Pin 5) is essentially connected to the inverting input of the TZA, it is very sensitive to stray capacitance. RGAIN should be placed between Pin 5 and Pin 6, as close as possible to Pin 5. Small traces should be used, and the ground and +VS planes adjacent to the trace should be removed to further minimize stray capacitance. The trace from SENSE IN to the anode of the PIN photodetector should be thin and routed away from the laser cathode trace. Example Calculations The example below (in addition to the one included in the sections above) should guide users in choosing RGAIN, CGAIN, the hold capacitor values, and worst case calibration times. System Requirements: • Laser power: 4 mW ± 2% • Hold Time: 0.5 ms Laser diode/photo diode characteristics: • Laser efficiency 0.3 mW/mA • Monitor current : 0.2 mA/mW • From the laser power requirements and efficiency we can estimate: ∆IOUT MAX  mW  = 4 mW × (2.0%)/  0.3 = 266.6 µA. mA    +VS PLANE PIN ASSIGNMENTS OUTPUT PIN CONNECTIONS 26 25 1 2 5 BYPASS CAPS AD9661A 24 23 22 MUTUAL COUPLING REDUCES INDUCTANCE 3 21 20 19 GROUND PLANE GROUND PIN CONNECTIONS 4 LASER DIODE CURRENT PATH SEGMENTS (See Text) Figure 6. Laser Diode Current Loop –8– REV. 0 AD9661A • Choosing a hold caps based on this: CHOLD = 18 × 10 –9 × 0.5 ms = 0.034 µF 266.6 µA • From the monitor current specification and the max power specified: I MONITOR MAX = 4 mW and 0.2 mA mW = 800 µA • The initial calibration time for < 0.1% error: 7 τ = 7 × RC = 7 × 550 Ω × 0.034 µF = 130.9 µs • Recalibration for a 0.1% error after 2% droop (need to correct within 5%): 3 τ = 3 RC = 3 × 140 Ω × 0.034 µF = 14.28 µs RGAIN = 1.6 V I MONITOR MAX – 50 Ω = 2.0 kΩ • CGAIN would be chosen from the table as 3 pF for safe compensation. Typical Performance Characteristics PULSE INPUT (TTL) LASER POWER 20mV/DIV 20ns/DIV LASER POWER 20mV/DIV 1ns/DIV Figure 7. Driving 78N20 Laser Diode @ 5 mW REV. 0 –9– AD9661A–Typical Performance Characteristics 180 4.2 160 140 120 IOUT – mA 100 80 60 40 20 10mV 0 1.7 2 2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 20ns VHOLD – V +5V 1kΩ 10Ω TO SCOPE MPSH81 Figure 8. Typical AD9661A V/I Transfer Function AD9661A 2pF 3V 2V LOW HIGH 1kΩ POWER MONITOR GAIN POWER LEVEL PULSEL HOLD 33pF SENSE IN OUTPUT Figure 9. Typical AD9661A Closed-Loop Pulse Response –10– REV. 0 AD9661A AD9661A EVALUATION BOARD The AD9661A Evaluation Board is comprised of two printed circuit boards. The Laser Diode Driver (LDD) Resource Board is both a digital pattern generator and an analog reference generator (see LDD Resource Board Block Diagram.) The board is controlled by an IBM compatible personal computer through a standard printer cable. The resource board interfaces to the AD9661A DUT board, which contains the AD9661A, a level shift circuit for the analog input, and a socket for an N type laser diode. A dummy load circuit for the laser diode is included for evaluation. Power for all the boards is provided through the banana jacks on the AD9661A DUT board. These should be connected to a linear, +5 V power supply. Schematics for the LDD Resource Board, AD9661A DUT, and Dummy Load are included, along with a bill of material and layout information. Please contact Applications for additional information. 40MHz CLOCK OSCILLATOR STANDARD PARALLEL PRINTER CABLE P1 IBM-COMPATIBLE PC WITH WINDOWS PARALLEL PRINTER PORT CENTRONICS CONNECTOR READBACK LATCH 32K x 16 MEMORY PULSE WIDTH MODULATOR (AD9560) ADDRESS COUNTER AND RESOURCE CONTROLLER OUTPUT SMB CONNECTORS J4 J5 J7 J8 J6 J2 PULSE1 (JPUL) CAL (JCALB) DISABLE (JDIS) PULSE2 (JPULB) UNUSED TRIGGER J3 OUTPUT BUFFER DIGITAL PATTERN GENERATOR INTERFACE TO AD9661A EVALUATION BOARD 8 DAC 1 X1 0–2.55V 12 11 EXTERNAL LEVEL SHIFT CIRCUIT R9 AD9661A R8 LEVEL SHIFT IN +5V POWER SUPPLY GROUND 8 DAC 2 X1 0–2.55V 20-PIN HEADER 17–20 1–10 ANALOG REFERENCE LASER DIODE DRIVER RESOURCE BOARD Figure 10. LDD Resource Board Block Diagram INPUT SMB CONNECTORS FOR DIGITAL CONTROLS 5 AD9661A DUMMY LOAD CIRCUIT/ LASER DIODE SOCKET 20 20-PIN HEADER FOR ANALOG CONTROLS OPTIONAL LEVEL SHIFT CIRCUIT AD9661A EVALUATION BOARD Figure 11. Evaluation Board Block Diagram REV. 0 –11– AD9661A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Pin Plastic SOIC (R-28) C2079–6–10/95 0.013 (0.33) 0.009 (0.23) 0.04 (1.02) 0.024 (0.61) 0.712 (18.08) 0.700 (17.78) 28 15 0.300 (7.60) 0.292 (7.40) 1 14 0.419 (10.64) 0.393 (9.98) PIN 1 0.104 (2.64) 0.093 (2.36) 0.0500 (1.27) BSC 0.019 (0.48) 0.014 (0.36) SEATING PLANE 0.012 (0.30) 0.004 (0.10) –12– REV. 0 PRINTED IN U.S.A.