Data Sheet
Octal Ultrasound AFE with JESD204B
AD9675
FEATURES
GENERAL DESCRIPTION
8 channels of LNA, VGA, AAF, ADC, and digital RF decimator
Low power
150 mW per channel, TGC mode, 40 MSPS
62.5 mW per channel, CW mode
10 mm × 10 mm, 144-ball CSP_BGA
TGC channel input referred noise: 0.82 nV/√Hz,
maximum gain
Flexible power-down modes
Fast recovery from low power standby mode: 2 μs
Low noise preamplifier (LNA)
Input referred noise: 0.78 nV/√Hz, gain = 21.6 dB
Programmable gain: 15.6 dB, 17.9 dB, or 21.6 dB
0.1 dB compression: 1000 mV p-p, 750 mV p-p, or 450 mV p-p
Flexible active input impedance matching
Variable gain amplifier (VGA)
Attenuator range: 45 dB, linear in dB gain control
Postamp gain (PGA): 21 dB, 24 dB, 27 dB, or 30 dB
Antialiasing filter (AAF)
Programmable second-order low-pass filter (LPF) from
8 MHz to 18 MHz or 13.5 MHz to 30 MHz and high-pass
filter (HPF)
Analog-to-digital converter (ADC)
SNR: 75 dB, 14 bits up to 125 MSPS
JESD204B Subclass 0 coded serial digital outputs
CW Doppler mode harmonic rejection I/Q demodulator
Individual programmable phase rotation
Dynamic range per channel: 160 dBFS/√Hz
Close-in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS input
RF digital decimation by 2 and high-pass filter
The AD9675 is designed for low cost, low power, small size, and
ease of use for medical ultrasound. It contains eight channels of
a variable gain amplifier (VGA) with a low noise preamplifier
(LNA), a continuous wave (CW) harmonic rejection I/Q
demodulator with programmable phase rotation, an antialiasing
filter (AAF), an analog-to-digital converter (ADC), and a digital
high-pass filter and RF decimation by 2 for data processing and
bandwidth reduction.
Each channel features a maximum gain of up to 52 dB, a fully
differential signal path, and an active input preamplifier termination. The channel is optimized for high dynamic performance
and low power in applications where a small package size is critical.
The LNA has a single-ended to differential gain that is selectable
through the serial port interface (SPI). Assuming a 15 MHz
noise bandwidth (NBW) and a 21.6 dB LNA gain, the LNA
input SNR is 94 dB. In CW Doppler mode, each LNA output
drives an I/Q demodulator that has independently
programmable phase rotation with 16 phase settings.
Power-down of individual channels is supported to increase
battery life for portable applications. Standby mode allows quick
power-up for power cycling. In CW Doppler operation, the
VGA, AAF, and ADC are powered down. The ADC contains
features to maximize flexibility and minimize system cost, such
as a programmable clock, data alignment, and programmable
digital test pattern generation. The digital test patterns include
built-in fixed patterns, built-in pseudorandom patterns, and
custom user-defined test patterns entered via the SPI.
APPLICATIONS
Medical imaging/ultrasound
Nondestructive testing (NDT)
Rev. A
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Technical Support
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AD9675
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Outputs and Timing ..................................................... 29
Applications ....................................................................................... 1
Analog Test Tone Generation ................................................... 38
General Description ......................................................................... 1
CW Doppler Operation............................................................. 39
Revision History ............................................................................... 2
Digital RF Decimator ..................................................................... 40
Functional Block Diagram .............................................................. 3
Vector Profile .............................................................................. 40
Specifications..................................................................................... 4
RF Decimator .............................................................................. 41
AC Specifications.......................................................................... 4
Digital Test Waveforms.............................................................. 41
Digital Specifications ................................................................... 7
Digital Block Power Saving Scheme ........................................ 42
Switching Specifications .............................................................. 9
Serial Port Interface (SPI) .............................................................. 43
Absolute Maximum Ratings.......................................................... 12
Hardware Interface..................................................................... 43
Thermal Impedance ................................................................... 12
Memory Map .................................................................................. 45
ESD Caution ................................................................................ 12
Reading the Memory Map Table .............................................. 45
Pin Configuration and Function Descriptions ........................... 13
Recommended Start-Up Sequence .......................................... 45
Typical Performance Characteristics ........................................... 16
Memory Map Register Table ..................................................... 47
TGC Mode ................................................................................... 16
Memory Map Register Descriptions ........................................ 59
CW Doppler Mode ..................................................................... 20
Outline Dimensions ....................................................................... 60
Theory of Operation ...................................................................... 21
Ordering Guide .......................................................................... 60
TGC Operation ........................................................................... 21
REVISION HISTORY
1/16—Revision A: Initial Version
Rev. A | Page 2 of 60
Data Sheet
AD9675
FUNCTIONAL BLOCK DIAGRAM
PDWN STBY
DVDD
DRVDD
AD9675
LO-A TO LO-H
CWD I/Q
DEMODULATOR
LOSW-A TO LOSW-H
LI-A TO LI-H
LNA
LG-A TO LG-H
VGA
14-BIT
ADC
AAF
RF DECIMATOR
CML
SERIALIZER
SERDOUT1– TO SERDOUT4–
Figure 1.
Rev. A | Page 3 of 60
CLK–
CLK+
TX_TRIG–
TX_TRIG+
DATA
RATE
MULTIPLIER
SDIO
CSB
SCLK
ADDR0 TO
ADDR4
GPO0 TO
GPO3
VREF
RBIAS
GAIN+
GAIN–
MLO–
MLO+
RESET–
RESET+
SERIAL
PORT
INTERFACE
REFERENCE
SERDOUT1+ TO SERDOUT4+
SYSREF+
SYSREF–
SYNCINB+
SYNCINB–
8 CHANNELS
LO
GENERATION
CWQ+
CWQ–
CWI+
CWI–
11381-001
AVDD1 AVDD2
AD9675
Data Sheet
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C),
fIN = 5 MHz, low bandwidth mode, RS = 50 Ω, RFB = ∞ (unterminated), LNA gain = 21.6 dB, LNA bias = mid-high, PGA gain = 27 dB, analog
gain control, VGAIN (V) = (GAIN+) − (GAIN−) = 1.6 V, AAF LPF cutoff = fSAMPLE/3 (Mode I/Mode II) = fSAMPLE/4.5 (Mode III/Mode IV),
HPF cutoff = LPF cutoff/12.00, Mode I = fSAMPLE = 40 MSPS, Mode II = fSAMPLE = 65 MSPS, Mode III = fSAMPLE = 80 MSPS, Mode IV = 125 MSPS,
RF decimator bypassed (Mode I/Mode II), RF decimator enabled (Mode III/Mode IV), digital high-pass filter bypassed, JESD204B link
parameters: M = 8 and L = 2, unless otherwise noted. All gain setting options are listed, which can be configured via SPI registers, and all
power supply currents and power dissipations are listed for the four mode settings (Mode I, Mode II, Mode III, and Mode IV).
Table 1.
Parameter1
LNA CHARACTERISTICS
Gain
Test Conditions/Comments
Min
Typ
Max
Unit
Single-ended input to differential output
Single-ended input to single-ended output
15.6/17.9/21.6
9.6/11.9/15.6
dB
dB
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
1000
750
450
mV p-p
mV p-p
mV p-p
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
1200
900
600
2.2
High-Z
1.5
High-Z
1.5
50
200
6
22
mV p-p
mV p-p
mV p-p
V
Ω
V
Ω
V
Ω
Ω
kΩ
pF
0.83
0.82
0.78
94
2.6
nV/√Hz
nV/√Hz
nV/√Hz
dB
pA/√Hz
0.1 dB Input Compression Point
1 dB Input Compression Point
Input Common Mode (LI-x, LG-x)
Output Common Mode (LO-x)
Output Common Mode (LOSW-x)
Input Resistance (LI-x)
Input Capacitance (LI-x)
Input Referred Noise Voltage
Input Signal-to-Noise Ratio
Input Noise Current
FULL CHANNEL CHARACTERISTICS
AAF Low-Pass Cutoff
In Range AAF Bandwidth
Tolerance
Group Delay Variation
Input Referred Noise Voltage
Noise Figure
Active Termination Matched
Unterminated
Switch off
Switch on
Switch off
Switch on
RFB = 300 Ω, LNA gain = 21.6 dB
RFB = 1350 Ω, LNA gain = 21.6 dB
RS = 0 Ω
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
Noise bandwidth = 15 MHz
Time gain control (TGC)
−3 dB, programmable, low bandwidth mode
−3 dB, programmable, high bandwidth mode
±10
MHz
MHz
%
f = 1 MHz to 18 MHz, VGAIN = −1.6 V to +1.6 V
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
±350
0.96
0.90
0.82
ps
nV/√Hz
nV/√Hz
nV/√Hz
LNA gain = 15.6 dB, RFB = 150 Ω
LNA gain = 17.9 dB, RFB = 200 Ω
LNA gain = 21.6 dB, RFB = 300 Ω
LNA gain = 15.6 dB, RFB = ∞
LNA gain = 17.9 dB, RFB = ∞
LNA gain = 21.6 dB, RFB = ∞
5.6
4.8
3.8
3.2
2.9
2.6
dB
dB
dB
dB
dB
dB
Rev. A | Page 4 of 60
8
13.5
18
30
Data Sheet
Parameter1
Correlated Noise Ratio
Output Offset
Signal-to-Noise Ratio (SNR)
Close-In SNR
Second Harmonic
Third Harmonic
Two-Tone Intermodulation
Distortion (IMD3)
Channel-to-Channel Crosstalk
GAIN ACCURACY
Gain Law Conformance Error
Channel-to-Channel Matching
PGA Gain
GAIN CONTROL INTERFACE
Control Range
Control Common Mode
Input Impedance
Gain Range
Gain Sensitivity
Response Time
CW DOPPLER MODE
LO Frequency
Phase Resolution
Output DC Bias (Single-Ended)
Output AC Current Range
Transconductance (Differential)
Input Referred Noise Voltage
Noise Figure
Input Referred Dynamic Range
AD9675
Test Conditions/Comments
No signal, correlated/uncorrelated
Min
Typ
−30
69
59
−130
Unit
dB
LSB
dBFS
dBFS
dBc/√Hz
−70
−62
−61
−55
−54
dBc
dBc
dBc
dBc
dBc
−60
−55
dB
dB
−125
fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V
fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V
fIN = 3.5 MHz at −0.5 dBFS, VGAIN = 0 V,
1 kHz offset
fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V
fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V
fIN = 5 MHz at −12 dBFS, VGAIN = −1.6 V
fIN = 5 MHz at −1 dBFS, VGAIN = 1.6 V
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, ARF1 =
−1 dBFS, ARF2 = −21 dBFS, VGAIN = 1.6 V, IMD3
relative to ARF2
fIN1 = 5.0 MHz at −1 dBFS
Overrange condition2
TA = 25°C
−1.6 < VGAIN < −1.28 V
−1.28 V < VGAIN < +1.28 V
1.28 V < VGAIN < 1.6 V
VGAIN = 0 V, normalized for ideal AAF loss
−1.28 V < VGAIN < +1.28 V, 1 σ
Differential
GAIN+, GAIN−
GAIN+, GAIN−
0.4
+1.3
−0.5
−0.9
+0.9
0.1
21/24/27/30
Analog
Digital step size
Analog 45 dB change
Rev. A | Page 5 of 60
+125
−1.3
−1.6
0.7
fLO = fMLO/M
Per channel, 4LO mode
Per channel, 8LO mode, 16LO mode
CWI+, CWI−, CWQ+, CWQ−
Per CWI+, CWI−, CWQ+, CWQ−, each channel
enabled (2 fLO and baseband signal)
Demodulated IOUT/VIN, per CWI+, CWI−,
CWQ+, CWQ−
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
RS = 50 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
RS = 0 Ω, RFB = ∞
LNA gain = 15.6 dB
LNA gain = 17.9 dB
LNA gain = 21.6 dB
Max
0.8
10
45
14
3.5
750
1
45
22.5
AVDD2 ÷ 2
±2.2
dB
dB
dB
dB
dB
dB
+1.6
0.9
V
V
MΩ
dB
dB/V
dB
ns
10
MHz
Degrees
Degrees
V
mA
±2.5
3.3
4.3
6.6
mA/V
mA/V
mA/V
1.6
1.3
1.0
nV/√Hz
nV/√Hz
nV/√Hz
5.7
4.5
3.4
dB
dB
dB
164
162
160
dBFS/√Hz
dBFS/√Hz
dBFS/√Hz
AD9675
Parameter1
Close-In SNR
Two-Tone Intermodulation
Distortion (IMD3)
LO Harmonic Rejection
Quadrature Phase Error
I/Q Amplitude Imbalance
Channel to Channel Matching
POWER SUPPLY
AVDD1
AVDD2
DVDD
DRVDD
IAVDD1
IAVDD2
Data Sheet
Test Conditions/Comments
−3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz,
1 kHz offset, 16LO mode, one channel enabled
−3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz,
1 kHz offset, 16LO mode, eight channels enabled
fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, fLO = 80 MHz,
ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative
to ARF2
I to Q, all phases, 1 σ
I to Q, all phases, 1 σ
Phase I to I, Q to Q, 1 σ
Amplitude I to I, Q to Q, 1 σ
Mode I/Mode II/Mode III/Mode IV
TGC mode, low bandwidth mode
CW Doppler mode
TGC mode, no signal, low bandwidth mode
TGC mode, no signal, high bandwidth mode
CW Doppler mode
Total Power Dissipation
(Including Output Drivers)
DVDD = 1.8 V
Four-lane mode, JESD204B lane rates =
1.6 Gbps/2.6 Gbps/1.6 Gbps/2.5 Gbps
Two-lane mode, JESD204B lane rates =
3.2 Gbps/5.0 Gbps/3.2 Gbps/5.0 Gbps
One-lane mode, RF decimator enabled,
JESD204B lane rates = 3.2 Gbps/5.0 Gbps/
not valid/not valid
TGC mode, no signal, two-lane mode
TGC mode, no signal, two-lane mode,
DVDD = 1.8 V
CW Doppler mode, eight channels enabled
Power-Down Dissipation
Standby Power Dissipation
ADC
Resolution
SNR
ADC REFERENCE
Output Voltage Error
Load Regulation at 1.0 mA
Input Resistance
1
2
Typ
156
Max
dBc/√Hz
−58
dBc
−20
dBc
Degrees
dB
Degrees
dB
1.8
3.0
1.4
1.8
148/187/
223/291
4
230
239
140
29/46/40/61
38/60/54/80
121/168/
122/166
127/186/
129/184
73/105/not
valid/not valid
1.9
3.6
1.9
1.9
V
V
V
V
mA
1200/1415/
1365/1615
1230/1460/
1410/1675
500
5
725
1445/1680/
1635/1910
mA
mA
mA
mA
mA
mA
mA
mA
mA
30
mW
mW
mW
Bits
dB
±50
2
7.5
mW
mW
14
75
VREF = 1 V
VREF = 1 V
Unit
dBc/√Hz
161
0.15
0.015
0.5
0.25
1.7
2.85
1.3
1.7
IDVDD
IDRVDD
Min
mV
mV
kΩ
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed.
The overrange condition is specified as 6 dB more than the full-scale input range.
Rev. A | Page 6 of 60
Data Sheet
AD9675
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, full temperature range (0°C to 85°C),
unless otherwise noted.
Table 2.
Parameter1
INPUTS (CLK+, CLK−, TX_TRIG+, TX_TRIG−)
Logic Compliance
Differential Input Voltage2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
INPUTS (MLO+, MLO−, RESET+, RESET−)
Logic Compliance
Differential Input Voltage2
Input Voltage Range
Input Common-Mode Voltage
Input Resistance (Single-Ended)
Input Capacitance
LOGIC INPUTS (PDWN, STBY, SCLK, SDIO, ADDRx)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (SERDOUTx+, SERDOUTx−)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
LOGIC OUTPUT (GPO0, GPO1, GPO2, GPO3)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL INPUT (SYNCINB+, SYNCINB−)
Logic Compliance
Internal Bias
Differential Input Voltage Range
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Temperature
Min
Typ
Max
Unit
3.6
AVDD1 + 0.2
V p-p
V
V
kΩ
pF
AVDD2 × 2
AVDD2 + 0.2
V p-p
V
V
kΩ
pF
DRVDD + 0.3
0.3
V
V
kΩ
pF
DRVDD + 0.3
0.3
V
V
kΩ
pF
CMOS/LVDS/LVPECL
0.2
GND – 0.2
0.9
15
4
25°C
25°C
LVDS/LVPECL
0.250
GND – 0.2
AVDD2/2
20
1.5
25°C
25°C
Full
Full
25°C
25°C
1.2
Full
Full
25°C
25°C
1.2
30 (26 for SDIO)
2 (5 for SDIO)
26
2
Full
Full
1.79
0.05
V
V
750
1.05
mV
V
0.05
V
CML
Full
Full
400
0.75
600
Full
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS
0.9
0.3
GND
0.9
−5
−5
12
Rev. A | Page 7 of 60
3.6
DRVDD
1.4
+5
+5
1
16
20
V
V
V
V
μA
μA
pF
kΩ
AD9675
Parameter1
DIGITAL INPUT (SYSREF+, SYSREF−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Data Sheet
Temperature
Min
Typ
Max
Unit
LVDS
Full
Full
Full
Full
Full
Full
Full
Full
0.9
0.3
GND
0.9
−5
−5
8
1
3.6
DRVDD
1.4
+5
+5
4
10
12
V
V p-p
V
V
μA
μA
pF
kΩ
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2
Specified for LVDS and LVPECL only.
3
Specified for 13 SDIO pins sharing the same connection.
Rev. A | Page 8 of 60
Data Sheet
AD9675
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DVDD = 1.4 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, L = 2, M = 8, fSAMPLE = 40 MHz, lane
data rate = 3.2 Gbps, full temperature range (0°C to 85°C), unless otherwise noted.
Table 3.
Parameter1
CLOCK2
Clock Rate (fSAMPLE)
40 MSPS (Mode I)
65 MSPS (Mode II)
80 MSPS (Mode III)3
125 MSPS (Mode IV)4
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
CLOCK INPUT PARAMETERS
TX_TRIG± to CLK± Setup Time (tSETUP)
TX_TRIG± to CLK± Hold Time (tHOLD)
DATA OUTPUT PARAMETERS
Data Output Period or Unit Interval (UI)
Data Output Duty Cycle
Data Valid Time
PLL Lock Time5
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)6
Device
JESD204B Link
SYNCINB± Falling Edge to First K.28 Characters
Code Group Synchronization (CGS) Phase K.28
Characters Duration
Delay (Latency)
ADC Pipeline
RF Decimator
Digital High-Pass Filter
TX_TRIG± to Start Code (Mode I/Mode II/Mode III/
Mode IV)
Four-Lane Mode
Two-Lane Mode
Data Rate per Lane
Uncorrelated Bounded High Probability (UBHP) Jitter
Random Jitter at 2.5 Gbps Data Rate
Random Jitter at 5 Gbps Data Rate
Output Rise/Fall Time
TERMINATION CHARACTERISTICS
Differential Termination Resistance
APERTURE
Aperture Uncertainty (Jitter)
Temperature
Min
Full
Full
Full
Full
Full
Full
20.5
20.5
20.5
20.5
25°C
25°C
1
1
Typ
Max
Unit
40
65
80
125
MHz
MHz
MHz
MHz
ns
ns
3.75
3.75
ns
ns
Full
25°C
25°C
25°C
25°C
L/(20 × M × fSAMPLE)
50
0.76
26
2
Seconds
%
UI
μs
μs
25°C
25°C
Full
Full
375
250
μs
μs
Multiframes
Multiframe
16
11
100
Cycles
Cycles
Cycles
Full
Full
25°C
25°C
25°C
25°C
25°C
31/42/30/36
31/33/30/30
11
80
46
64
Cycles
Cycles
Gbps
ps
ps rms
ps rms
ps
Full
100
Ω
25°C
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