AD9680BCPZ-820

14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter AD9680 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM 14 VIN+B VIN–B Rev. E DDC ADC CORE BUFFER CONTROL REGISTERS V_1P0 SIGNAL MONITOR CLOCK GENERATION CLK+ CLK– ÷2 ÷4 ÷8 AGND DRGND DGND 4 FAST DETECT JESD204B SUBCLASS 1 CONTROL SPI CONTROL AD9680 SDIO SCLK CSB SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SYNCINB± SYSREF± PDWN/ STBY Figure 1. PRODUCT HIGHLIGHTS 1. 2. 3. APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receivers Instrumentation Radars Signals intelligence (SIGINT) DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers SIGNAL MONITOR 11752-001 FD_B DDC Tx OUTPUTS FD_A ADC CORE 14 JESD204B HIGH SPEED SERIALIZER BUFFER VIN+A VIN–A FAST DETECT JESD204B (Subclass 1) coded serial digital outputs 1.65 W total power per channel at 1 GSPS (default settings) SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 1 GHz (AIN = −1.0 dBFS) ENOB = 10.8 bits at 10 MHz DNL = ±0.5 LSB INL = ±2.5 LSB Noise density = −154 dBFS/Hz at 1 GSPS 1.25 V, 2.5 V, and 3.3 V dc supply operation No missing codes Internal ADC voltage reference Flexible input range: 1.46 V p-p to 1.94 V p-p AD9680-1250: 1.58 V p-p nominal AD9680-1000 and AD9680-820: 1.70 V p-p nominal AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) Programmable termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 2 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation 2 integrated wideband digital processors per channel 12-bit NCO, up to 4 half-band filters Differential clock input Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Small signal dither SPIVDD AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD (1.25V) (1.25V) (1.8V TO 3.3V) (1.25V) (1.25V) (2.5V) (3.3V) 4. 5. 6. Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm × 9 mm, 64-lead LFCSP. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 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Technical Support www.analog.com AD9680 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 FIR Filters General Description ............................................... 58 Applications ....................................................................................... 1 Half-Band Filters ........................................................................ 59 Functional Block Diagram .............................................................. 1 DDC Gain Stage ......................................................................... 61 Product Highlights ........................................................................... 1 DDC Complex to Real Conversion ......................................... 61 Revision History ............................................................................... 3 DDC Example Configurations ................................................. 62 General Description ......................................................................... 5 Digital Outputs ............................................................................... 65 Specifications..................................................................................... 6 Introduction to the JESD204B Interface ................................. 65 DC Specifications ......................................................................... 6 JESD204B Overview .................................................................. 65 AC Specifications.......................................................................... 7 Functional Overview ................................................................. 66 Digital Specifications ................................................................... 9 JESD204B Link Establishment ................................................. 67 Switching Specifications ............................................................ 10 Physical Layer (Driver) Outputs .............................................. 68 Timing Specifications ................................................................ 11 JESD204B Tx Converter Mapping ........................................... 71 Absolute Maximum Ratings.......................................................... 13 Configuring the JESD204B Link .............................................. 73 Thermal Characteristics ............................................................ 13 Deterministic Latency.................................................................... 76 ESD Caution ................................................................................ 13 Subclass 0 Operation.................................................................. 76 Pin Configuration and Function Descriptions ........................... 14 Subclass 1 Operation.................................................................. 76 Typical Performance Characteristics ........................................... 16 Multichip Synchronization............................................................ 78 AD9680-1250 .............................................................................. 16 Normal Mode .............................................................................. 78 AD9680-1000 .............................................................................. 20 Timestamp Mode ....................................................................... 78 AD9680-820 ................................................................................ 25 SYSREF± Input ........................................................................... 80 AD9680-500 ................................................................................ 30 SYSREF± Setup/Hold Window Monitor ................................. 82 Equivalent Circuits ......................................................................... 34 Latency ............................................................................................. 84 Theory of Operation ...................................................................... 36 End to End Total Latency .......................................................... 84 ADC Architecture....................................................................... 36 Example Latency Calculation ................................................... 84 Analog Input Considerations.................................................... 36 Test Modes ....................................................................................... 85 Voltage Reference ....................................................................... 42 ADC Test Modes ........................................................................ 85 Clock Input Considerations ...................................................... 43 JESD204B Block Test Modes..................................................... 86 ADC Overrange and Fast Detect.................................................. 45 Serial Port Interface ........................................................................ 88 ADC Overrange .......................................................................... 45 Configuration Using the SPI ..................................................... 88 Fast Threshold Detection (FD_A and FD_B) ......................... 45 Hardware Interface ..................................................................... 88 Signal Monitor ................................................................................ 46 SPI Accessible Features .............................................................. 88 SPORT Over JESD204B ............................................................. 47 Memory Map .................................................................................. 89 Digital Downconverter (DDC) ..................................................... 49 Reading the Memory Map Register Table............................... 89 DDC I/Q Input Selection .......................................................... 49 Memory Map Register Table ..................................................... 90 DDC I/Q Output Selection ....................................................... 49 Applications Information ............................................................ 104 DDC General Description ........................................................ 49 Power Supply Recommendations........................................... 104 Frequency Translation.................................................................... 55 Exposed Pad Thermal Heat Slug Recommendations .......... 104 Frequency Translation General Description .............................. 55 AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) ............ 104 DDC NCO Plus Mixer Loss and SFDR ................................... 56 Outline Dimensions ..................................................................... 105 Numerically Controlled Oscillator........................................... 56 Ordering Guide ........................................................................ 105 FIR Filters ........................................................................................ 58 Rev. E | Page 2 of 105 Data Sheet AD9680 REVISION HISTORY 3/2019—Rev. D to Rev. E Changes to Figure 146 ....................................................................50 11/2017—Rev. C to Rev. D Changes to Table 2............................................................................. 7 Change to Junction Temperature Range, Table 6 ........................13 Changes to Figure 17 ......................................................................17 Changes to Figure 18 ......................................................................18 Changes to Figure 34 ......................................................................20 Changes to Figure 65 and Figure 66 .............................................26 Changes to Figure 67 and Figure 68 .............................................27 Changes to Figure 118 to Figure 120 ............................................38 Added Deterministic Latency Section, Subclass 0 Operation Section, Subclass 1 Operation Section, Deterministic Latency Requirements Section, Setting Deterministic Latency Registers Section, and Figure 171; Renumbered Sequentially ...................75 Added Figure 172 and Figure 173 .................................................76 Changes to Multichip Synchronization Section ..........................77 Added Normal Mode Section, Timestamp Mode Section, and Figure 174 .........................................................................................77 Added Figure 175 ............................................................................78 Added SYSREF± Input Section, SYSREF± Control Features Section, and Figure 176 to Figure 179 ..........................................79 Added Figure 180 and Figure 181 .................................................80 Added Latency Section, End to End Total Latency Section, Example Latency Calculation Section, and Table 29 to Table 31 .............................................................................................83 Updated Outline Dimensions ......................................................103 Changes to Ordering Guide .........................................................103 11/2015—Rev. B to Rev. C Added AD9680-1250 ......................................................... Universal Changes to Features Section ............................................................ 1 Change to General Description Section ......................................... 4 Changes to Table 1............................................................................. 5 Changes to Table 2............................................................................. 6 Changes to Table 4............................................................................. 9 Changes to Table 5...........................................................................10 Changes to Figure 4......................................................................... 11 Changes to Pin 14 Description, Table 8 .......................................14 Added AD9680-1250 Section and Figure 6 to Figure 29; Renumbered Sequentially ..............................................................15 Changes to Figure 113 ....................................................................34 Changes to Analog Input Considerations Section ......................35 Changes to Table 9...........................................................................36 Changes to Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Section ..........................................37 Added Figure 118 to Figure 120 ....................................................37 Changes to Table 10 ........................................................................40 Changes to Table 17 ........................................................................57 Changes to ADC Test Modes Section ........................................... 78 Changes to Table 36 ........................................................................ 83 Changes to Ordering Guide ........................................................... 97 3/2015—Rev. A to Rev. B Added AD9680-820 ........................................................... Universal Changes to Features Section ............................................................ 1 Changes to Table 1 ............................................................................ 5 Changes to Table 2 ............................................................................ 6 Changes to Table 3 ............................................................................ 8 Changes to Table 4 ............................................................................ 9 Added Figure 14; Renumbered Sequentially ............................... 15 Added AD9680-820 Section and Figure 31 Through Figure 36.... 19 Added Figure 37 Through Figure 42 ............................................ 20 Added Figure 43 Through Figure 48 ............................................ 21 Added Figure 49 Through Figure 54 ............................................ 22 Added Figure 55 .............................................................................. 23 Changes to Figure 69 and Figure 70 ............................................. 26 Changes to Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Section, Table 9, and Figure 93 .................... 31 Added Figure 99 Through Figure 100 .......................................... 33 Changes to Table 10 ........................................................................ 34 Changes to Clock Jitter Considerations Section ......................... 37 Added Figure 112 ............................................................................ 37 Changes to Digital Downconverter (DDC) Section ................... 42 Changes to Table 17 ........................................................................ 51 Changes to Table 36 ........................................................................ 77 Changes to Ordering Guide ........................................................... 91 12/2014—Rev. 0 to Rev. A Added AD9680-500 ........................................................... Universal Changes to Features Section and Figure 1 ..................................... 1 Changes to General Description Section ....................................... 4 Changes to Specifications Section and Table 1 ............................. 5 Changes to AC Specifications Section and Table 2 ....................... 6 Changes to Digital Specifications Section ..................................... 8 Changes to Switching Specifications Section and Table 4 ........... 9 Changes to Table 6, Thermal Characteristics Section, and Table 7 ............................................................................................... 11 Change to Digital Inputs Description, Table 8 ............................ 13 Added AD9680-1000 Section, Figure 10, and Figure 11; Renumbered Sequentially .............................................................. 14 Changes to Figure 6 to Figure 9 .................................................... 14 Added Figure 12 to Figure 14 ........................................................ 15 Changes to Figure 15 to Figure 17 ................................................ 15 Changes to Figure 18 to Figure 21 ................................................ 16 Changes to Figure 25 and Figure 29 ............................................. 17 Changes to Figure 30 ...................................................................... 18 Deleted Figure 35, Figure 36, and Figure 38................................ 19 Added AD9680-500 Section and Figure 31 to Figure 54 ............. 19 Rev. E | Page 3 of 105 AD9680 Data Sheet Changes to Analog Input Considerations Section and Differential Input Configurations Section .................................. 25 Added Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Section, Figure 66, Figure 68, and Table 9; Renumbered Sequentially.............................................................. 26 Changes to Analog Input Buffer Controls and SFDR Optimization Section and Figure 67 ............................................ 26 Added Figure 69 to Figure 72........................................................ 27 Added Figure 73 to Figure 75........................................................ 28 Changes to Table 10 ........................................................................ 28 Added Input Clock Divider ½ Period Delay Adjust Section and Clock Fine Delay Adjust Section .................................................. 30 Changes to Figure 83 and Temperature Diode Section ............. 31 Added Signal Monitor Section and Figure 86 to Figure 89 ...... 33 Changes to Table 11 ........................................................................ 39 Changes to Table 12 to Table 14.................................................... 40 Changes to Table 16 ........................................................................ 41 Deleted Figure 65 and Figure 66................................................... 45 Changes to Table 17........................................................................ 45 Changes to Table 19 to Table 20 ................................................... 46 Changes to Table 22........................................................................ 47 Changes to Table 23........................................................................ 49 Changes to JESD204B Link Establishment Section ................... 53 Added Figure 105 to Figure 110 ................................................... 56 Changes to Example 1: Full Bandwidth Mode Section ............. 60 Added Multichip Synchronization Section, Figure 115 to Figure 117, and Table 28 ................................................................ 62 Added Test Modes Section and Table 29 to Table 33 ................. 66 Changes to Reading the Memory Map Register Table Section ...... 70 Changes to Table 36........................................................................ 71 Changes to Power Supply Recommendations Section, Figure 118, and Exposed Pad Thermal Heat Slug Recommendations Section............................................................ 83 Changes to Ordering Guide .......................................................... 84 5/2014—Revision 0: Initial Version Rev. E | Page 4 of 105 Data Sheet AD9680 GENERAL DESCRIPTION The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/ 500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins. The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default. In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI. The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent. Rev. E | Page 5 of 105 AD9680 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Voltage INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage Range (Programmable) Common-Mode Voltage (VCM) Differential Input Capacitance 1 Analog Input Full Power Bandwidth POWER SUPPLY AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD IAVDD1 IAVDD2 IAVDD3 IAVDD1_SR IDVDD 2 IDRVDD1 IDRVDD (L = 2 Mode) ISPIVDD Temp Full AD9680-500 Min Typ Max 14 AD9680-820 Min Typ Max 14 Min 14 Full Full Full Full Full Full Guaranteed −0.3 0 +0.3 0 0.3 −6 0 +6 1 5.1 −0.6 ±0.5 +0.7 Guaranteed −0.3 0 +0.3 0 0.23 −6 0 +6 1 5.5 −0.7 ±0.5 +0.8 Full −4.5 −3.3 ±2.5 +5.0 ±2.5 +4.3 AD9680-1000 Typ Max AD9680-1250 Min Typ Max 14 Unit Bits Guaranteed −0.31 0 +0.31 0 0.23 −6 0 +6 1 4.5 −0.7 ±0.5 +0.8 Guaranteed −0.31 0 +0.31 0 0.3 −6 0 +6 1 4.5 −0.8 ±0.5 +0.8 % FSR % FSR % FSR % FSR LSB −5.7 −6 LSB ±2.5 +6.9 ±3 +6 Full Full −3 ±25 −10 ±54 −12 ±13.8 −15 92 ppm/°C ppm/°C Full 1.0 1.0 1.0 1.0 V 25°C 2.06 2.46 2.63 3.45 LSB rms Full 1.46 2.06 2.06 1.46 1.70 1.94 1.46 1.70 1.94 1.46 1.58 1.94 V p-p 25°C 2.05 2.05 2.05 2.05 V 25°C 1.5 1.5 1.5 1.5 pF 25°C 2 2 2 2 GHz Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C Full 1.22 2.44 3.2 1.22 1.22 1.22 1.7 1.25 2.50 3.3 1.25 1.25 1.25 1.8 435 395 87 15 145 190 140 5 1.28 2.56 3.4 1.28 1.28 1.28 3.4 467 463 101 22 152 237 6 1.22 2.44 3.2 1.22 1.22 1.22 1.7 1.25 2.50 3.3 1.25 1.25 1.25 1.8 605 490 125 15 205 200 N/A 3 5 1.28 2.56 3.4 1.28 1.28 1.28 3.4 660 545 140 18 246 240 6 Rev. E | Page 6 of 105 1.22 2.44 3.2 1.22 1.22 1.22 1.7 1.25 2.50 3.3 1.25 1.25 1.25 1.8 685 595 125 16 208 200 N/A3 5 1.28 2.56 3.4 1.28 1.28 1.28 3.4 720 680 142 18 269 225 6 1.22 2.44 3.2 1.22 1.22 1.22 1.7 1.25 2.50 3.3 1.25 1.25 1.25 1.8 785 675 125 17 250 220 N/A3 5 1.28 2.56 3.4 1.28 1.28 1.28 3.4 880 780 142 20 325 300 6 V V V V V V V mA mA mA mA mA mA mA mA Data Sheet Parameter POWER CONSUMPTION Total Power Dissipation (Including Output Drivers)2 Total Power Dissipation (L = 2 Mode) Power-Down Dissipation Standby 4 AD9680 Temp AD9680-500 Min Typ Max AD9680-820 Min Typ Max Min AD9680-1000 Typ Max AD9680-1250 Min Typ Max Unit Full 2.2 2.9 3.3 3.7 W 25°C 2.1 N/A3 N/A3 N/A3 W Full Full 700 1.2 820 1.3 835 1.4 1030 1.66 mW W All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used. Default mode. No DDCs used. L = 4, M = 2, F = 1. 3 N/A means not applicable. At the maximum sample rate, it is not applicable to use L = 2 mode on the JESD204B output interface because this exceeds the maximum lane rate of 12.5 Gbps. L = 2 mode is supported when the equation ((M × N΄ × (10/8) × fOUT)/L) results in a line rate that is ≤12.5 Gbps. fOUT is the output sample rate and is denoted by fS/DCM, where DCM is the decimation ratio. 4 Can be controlled by the SPI. 1 2 AC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 2. Parameter 1 ANALOG INPUT FULL SCALE NOISE DENSITY 2 SIGNAL-TO-NOISE RATIO (SNR) 3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz SNR AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz Temp Full Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C AD9680-500 Min Typ Max 2.06 −153 67.8 67.6 10.9 69.2 69.0 68.6 68.0 64.4 63.8 60.5 69.0 68.8 68.4 67.9 64.2 63.6 60.3 11.2 11.1 11.1 11.0 10.4 10.3 9.7 AD9680-820 Min Typ Max 1.7 −153 65.6 65.2 10.5 67.2 67.0 66.5 65.1 64.0 63.4 59.7 67.1 66.8 66.3 64.7 63.5 62.7 58.7 10.9 10.8 10.7 10.5 10.3 10.1 9.5 Rev. E | Page 7 of 105 AD9680-1000 Min Typ Max 1.7 −154 65.1 65.0 10.5 67.2 66.6 65.3 64.0 62.6 61.5 57.0 67.1 66.4 65.2 63.8 62.5 61.4 56.4 10.8 10.7 10.5 10.3 10.1 9.9 9.1 AD9680-1250 Min Typ Max 1.58 −151.5 61.5 61.4 9.9 Unit V p-p dBFS/Hz 63.6 63.2 62.8 62.2 61.1 59.2 55.5 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 63.5 62.8 62.6 61.8 60.8 58.2 51.5 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 10.3 10.1 10.1 10.0 9.8 9.4 8.3 Bits Bits Bits Bits Bits Bits Bits AD9680 Parameter 1 SPURIOUS-FREE DYNAMIC RANGE (SFDR)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz fIN1 = 338 MHz, fIN2 = 341 MHz CROSSTALK 5 FULL POWER BANDWIDTH 6 Data Sheet Temp 25°C Full 25°C 25°C 25°C 25°C 25°C AD9680-500 Min Typ Max 80 83 88 83 81 80 75 70 AD9680-820 Min Typ Max 75 91 83 81 78 78 74 70 75 88 85 85 82 82 80 69 74 84 77 78 76 77 71 61 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 25°C Full 25°C 25°C 25°C 25°C 25°C −95 −95 −93 −93 −88 −89 −84 25°C −88 −90 −87 −82 dBFS 25°C −88 −87 −88 −78 4 dBFS 25°C 25°C 95 2 95 2 95 2 95 2 dB GHz −82 −97 −93 −91 −90 −83 −84 −74 −80 −95 −94 −88 −86 −83 −82 −79 −75 −81 −84 −77 −78 −76 −77 −71 −61 Unit −83 −88 −83 −81 −80 −75 −70 −75 −88 −85 −85 −82 −82 −80 −69 AD9680-1250 Min Typ Max 25°C Full 25°C 25°C 25°C 25°C 25°C −80 −91 −83 −81 −78 −78 −74 −70 AD9680-1000 Min Typ Max −87 −79 −81 −79 −79 −77 −69 −74 −74 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 10 for the recommended settings for full-scale voltage and buffer current settings. 4 Measurement taken with 449 MHz and 452 MHz inputs for two-tone. 5 Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel. 6 Measured with the circuit shown in Figure 115. 1 2 Rev. E | Page 8 of 105 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Data Sheet AD9680 DIGITAL SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 3. Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance SYSREF INPUTS (SYSREF+, SYSREF−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) LOGIC INPUTS (SDI, SCLK, CSB, PDWN/STBY) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUT (SDIO) Logic Compliance Logic 1 Voltage (IOH = 800 µA) Logic 0 Voltage (IOL = 50 µA) SYNCIN INPUT (SYNCINB+/SYNCINB−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC OUTPUTS (FD_A, FD_B) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3) Logic Compliance Differential Output Voltage Output Common-Mode Voltage (VCM) AC-Coupled Short-Circuit Current (IDSHORT) Differential Return Loss (RLDIFF) 1 Common-Mode Return Loss (RLCM)1 Differential Termination Impedance 1 Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min 600 Typ LVDS/LVPECL 1200 0.85 35 Max Unit 1800 mV p-p V kΩ pF 2.5 400 0.6 LVDS/LVPECL 1200 0.85 35 1800 2.0 2.5 mV p-p V kΩ pF CMOS 0.8 × SPIVDD 0 0.5 30 V V kΩ CMOS 0.8 × SPIVDD 0 400 0.6 0.5 LVDS/LVPECL/CMOS 1200 0.85 35 1800 2.0 2.5 V V mV p-p V kΩ pF CMOS 0.8 × SPIVDD 0 0.5 V V kΩ 30 Full Full 360 770 mV p-p 25°C 25°C 25°C 25°C Full 0 −100 8 6 80 1.8 +100 V mA dB dB Ω Differential and common-mode return loss are measured from 100 MHz to 0.75 × baud rate. Rev. E | Page 9 of 105 CML 100 120 AD9680 Data Sheet SWITCHING SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate for each speed grade, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 4. Parameter CLOCK Clock Rate (at CLK+/CLK− Pins) Maximum Sample Rate 1 Minimum Sample Rate 2 Clock Pulse Width High Clock Pulse Width Low OUTPUT PARAMETERS Unit Interval (UI) 3 Rise Time (tR) (20% to 80% into 100 Ω Load) Fall Time (tF) (20% to 80% into 100 Ω Load) PLL Lock Time Data Rate per Channel (NRZ) 4 LATENCY 5 Pipeline Latency Fast Detect Latency Wake-Up Time 6 Standby Power-Down APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out-of-Range Recovery Time Temp AD9680-500 Min Typ Max Min Full 0.3 0.3 Full Full Full Full 500 300 1000 1000 Full 25°C 80 24 200 32 80 24 121.95 32 80 24 100 32 80 24 80 32 ps ps 25°C 24 32 24 32 24 32 24 32 ps 25°C 25°C 3.125 2 5 3.125 2 8.2 3.125 2 10 3.1215 2 12.5 Full 4 AD9680-820 Typ Max 4 820 300 609.7 609.7 12.5 55 Full AD9680-1000 Min Typ Max AD9680-1250 Min Typ Max Unit 0.3 0.3 GHz 4 1000 300 500 500 12.5 55 28 1250 300 400 400 12.5 55 28 1 4 MSPS MSPS ps ps 12.5 55 28 1 Full Full 530 55 530 55 530 55 530 55 ps fS rms Full 1 1 1 1 Clock cycles 4 The maximum sample rate is the clock rate after the divider. The minimum sample rate operates at 300 MSPS with L = 2 or L = 1. 3 Baud rate = 1/UI. A subset of this range can be supported. 4 Default L = 4. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 4, M = 2, F = 1. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. 1 2 Rev. E | Page 10 of 105 1 Clock cycles Clock cycles 25°C 25°C 4 1 28 ms Gbps 4 4 ms ms Data Sheet AD9680 TIMING SPECIFICATIONS Table 5. Parameter CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tACCESS Test Conditions/Comments See Figure 3 Device clock to SYSREF+ setup time Device clock to SYSREF+ hold time See Figure 4 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Maximum time delay between falling edge of SCLK and output data valid for a read operation Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 4) tDIS_SDIO Min Typ Max Unit 117 −96 ps ps 6 ns ns ns ns ns ns ns ns 2 2 40 2 2 10 10 10 10 ns Timing Diagrams APERTURE DELAY ANALOG INPUT SIGNAL SAMPLE N N – 54 N+1 N – 55 N – 53 N – 52 N–1 N – 51 CLK– CLK+ CLK– CLK+ SERDOUT0– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 LSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 LSB SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SAMPLE N – 55 ENCODED INTO 1 8-BIT/10-BIT SYMBOL SAMPLE N – 54 ENCODED INTO 1 8-BIT/10-BIT SYMBOL SAMPLE N – 53 ENCODED INTO 1 8-BIT/10-BIT SYMBOL Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4; M = 2; F = 1) Rev. E | Page 11 of 105 11752-002 SERDOUT3+ AD9680 Data Sheet CLK– CLK+ tH_SR tSU_SR 11752-003 SYSREF– SYSREF+ Figure 3. SYSREF± Setup and Hold Timing tHIGH tDS tS tCLK tDH tACCESS tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D7 Figure 4. Serial Port Interface Timing Diagram Rev. E | Page 12 of 105 D6 D3 D2 D1 D0 DON’T CARE 11752-004 SCLK DON’T CARE Data Sheet AD9680 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD1 to AGND AVDD1_SR to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD to DRGND SPIVDD to AGND AGND to DRGND VIN±x to AGND SCLK, SDIO, CSB to AGND PDWN/STBY to AGND Operating Temperature Range Junction Temperature Range Storage Temperature Range (Ambient) Rating 1.32 V 1.32 V 2.75 V 3.63 V 1.32 V 1.32 V 3.63 V −0.3 V to +0.3 V 3.2 V −0.3 V to SPIVDD + 0.3 V −0.3 V to SPIVDD + 0.3 V −40°C to +85°C −40°C to +125°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Typical θJA, θJB, and θJC are specified vs. the number of printed circuit board (PCB) layers in different airflow velocities (in m/sec). Airflow increases heat dissipation effectively reducing θJA and θJB. In addition, metal in direct contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes, reduces θJA. Thermal performance for actual applications requires careful inspection of the conditions in an application. The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 6. Table 7. Thermal Resistance Values PCB Type JEDEC 2s2p Board Airflow Velocity (m/sec) 0.0 1.0 2.5 θJA 17.81, 2 15.61, 2 15.01, 2 ΨJB 6.31, 3 5.91, 3 5.71, 3 θJC_TOP 4.71, 4 N/A5 N/A5 θJC_BOT 1.21, 4 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per JEDEC JESD51-8 (still air). 4 Per MIL-STD 883, Method 1012.1. 5 N/A means not applicable. 1 2 ESD CAUTION Rev. E | Page 13 of 105 Unit °C/W °C/W °C/W AD9680 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD1 AVDD2 AVDD2 AVDD1 AGND SYSREF– SYSREF+ AVDD1_SR AGND AVDD1 CLK– CLK+ AVDD1 AVDD2 AVDD2 AVDD1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AD9680 TOP VIEW (Not to Scale) AVDD1 AVDD1 AVDD2 AVDD3 VIN–B VIN+B AVDD3 AVDD2 AVDD2 AVDD2 SPIVDD CSB SCLK SDIO DVDD DGND NOTES 1. EXPOSED PAD. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE GROUND REFENCE FOR AVDDx. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 11752-005 FD_A DRGND DRVDD SYNCINB– SYNCINB+ SERDOUT0– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ DRVDD DRGND FD_B 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD1 AVDD1 AVDD2 AVDD3 VIN–A VIN+A AVDD3 AVDD2 AVDD2 AVDD2 AVDD2 V_1P0 SPIVDD PDWN/STBY DVDD DGND Figure 5. Pin Configuration (Top View) Table 8. Pin Function Descriptions Pin No. Power Supplies 0 Mnemonic Type Description EPAD Ground 1, 2, 47, 48, 49, 52, 55, 61, 64 3, 8, 9, 10, 11, 39, 40, 41, 46, 50, 51, 62, 63 4, 7, 42, 45 13, 38 15, 34 16, 33 18, 31 19, 30 56, 60 57 Analog 5, 6 12 AVDD1 AVDD2 Supply Supply Exposed Pad. The exposed thermal pad on the bottom of the package provides the ground reference for AVDDx. This exposed pad must be connected to ground for proper operation. Analog Power Supply (1.25 V Nominal). Analog Power Supply (2.5 V Nominal). AVDD3 SPIVDD DVDD DGND DRGND DRVDD AGND1 AVDD1_SR 1 Supply Supply Supply Ground Ground Supply Ground Supply Analog Power Supply (3.3 V Nominal). Digital Power Supply for SPI (1.8 V to 3.3 V). Digital Power Supply (1.25 V Nominal). Ground Reference for DVDD. Ground Reference for DRVDD. Digital Driver Power Supply (1.25 V Nominal). Ground Reference for SYSREF±. Analog Power Supply for SYSREF± (1.25 V Nominal). VIN−A, VIN+A V_1P0 Input Input/DNC VIN−B, VIN+B CLK+, CLK− Input Input ADC A Analog Input Complement/True. 1.0 V Reference Voltage Input/Do Not Connect. This pin is configurable through the SPI as a no connect or an input. Do not connect this pin if using the internal reference. Requires a 1.0 V reference voltage input if using an external voltage reference source. ADC B Analog Input Complement/True. Clock Input True/Complement. 44, 43 53, 54 Rev. E | Page 14 of 105 Data Sheet Pin No. CMOS Outputs 17, 32 Digital Inputs 20, 21 58, 59 Data Outputs 22, 23 24, 25 26, 27 28, 29 Device Under Test (DUT) Controls 14 35 36 37 1 AD9680 Mnemonic Type Description FD_A, FD_B Output Fast Detect Outputs for Channel A and Channel B. SYNCINB−, SYNCINB+ SYSREF+, SYSREF− Input Input Active Low JESD204B LVDS Sync Input True/Complement. Active High JESD204B LVDS System Reference Input True/Complement. SERDOUT0−, SERDOUT0+ SERDOUT1−, SERDOUT1+ SERDOUT2−, SERDOUT2+ SERDOUT3−, SERDOUT3+ Output Output Output Output Lane 0 Output Data Complement/True. Lane 1 Output Data Complement/True. Lane 2 Output Data Complement/True. Lane 3 Output Data Complement/True. PDWN/STBY Input SDIO SCLK CSB Input/Output Input Input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as powerdown or standby. Requires an external 10 kΩ pull-down resistor. SPI Serial Data Input/Output. SPI Serial Clock. SPI Chip Select (Active Low). To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, see the Applications Information section. Rev. E | Page 15 of 105 AD9680 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AD9680-1250 AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted. See Table 10 for recommended settings. AIN = –1dBFS SNR = 64dBFS ENOB = 10.3 BITS SFDR = 82dBFS BUFFER CURRENT = 3.5× –10 –30 AMPLITUDE (dBFS) –50 –70 –90 –50 –70 –90 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) –130 11752-606 –130 0 AIN = –1dBFS SNR = 60.9dBFS ENOB = 9.8 BITS SFDR = 74dBFS BUFFER CURRENT = 5.5× –10 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) Figure 9. Single-Tone FFT with fIN = 450.3 MHz AIN = –1dBFS SNR = 63.4dBFS ENOB = 10.2 BITS SFDR = 79dBFS BUFFER CURRENT = 3.5× –30 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) Figure 6. Single-Tone FFT with fIN = 10.3 MHz –10 78.125 11752-609 –110 –110 –50 –70 –90 –110 –50 –70 –90 –110 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) –130 11752-607 –130 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) Figure 7. Single-Tone FFT with fIN = 170.3 MHz 11752-610 AMPLITUDE (dBFS) –30 AIN = –1dBFS SNR = 62.5dBFS ENOB = 9.9 BITS SFDR = 70dBFS BUFFER CURRENT = 3.5× –10 Figure 10. Single-Tone FFT with fIN = 765.3 MHz 0 AIN = –1dBFS SNR = 62.8dBFS ENOB = 10.1 BITS SFDR = 76dBFS BUFFER CURRENT = 3.5× –10 AMPLITUDE (dBFS) –20 –50 –70 –90 –40 –60 –80 –130 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) –120 Figure 8. Single-Tone FFT with fIN = 340.3 MHz 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) Figure 11. Single-Tone FFT with fIN = 985.3 MHz Rev. E | Page 16 of 105 11752-611 –100 –110 11752-608 AMPLITUDE (dBFS) –30 AIN = –1dBFS SNR = 59.7dBFS ENOB = 9.6 BITS SFDR = 74dBFS BUFFER CURRENT = 5.5× Data Sheet AD9680 0 85 AIN = –1dBFS SNR = 58.5dBFS ENOB = 9.3 BITS SFDR = 68dBFS BUFFER CURRENT = 5.5× 80 –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) –20 –60 –80 SFDR 75 70 65 –100 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) 60 11752-612 –120 Figure 12. Single-Tone FFT with fIN = 1205.3 MHz 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260 SAMPLE RATE (MHz) Figure 15. SNR/SFDR vs. fS, fIN = 170.3 MHz; Buffer Control 1 (0x018) = 3.5× 85 0 AIN = –1dBFS SNR = 56.6dBFS ENOB = 9.0 BITS SFDR = 67dBFS BUFFER CURRENT = 7.5× 3.5× SNR (dBFS) 3.5× SFDR (dBFS) 4.5× SNR (dBFS) 4.5× SFDR (dBFS) 80 SNR/SFDR (dBFS) –40 –60 –80 75 70 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) 60 10.3 11752-613 –120 147.3 212.3 290.3 355.3 433.3 511.3 589.3 667.3 INPUT FREQUENCY (MHz) Figure 13. Single-Tone FFT with fIN = 1602.3 MHz 11752-616 65 –100 Figure 16. SNR/SFDR vs. fIN; fIN < 700 MHz; Buffer Control 1 (0x018) = 3.5× and 4.5× 80 0 AIN = –1dBFS SNR = 55.4dBFS ENOB = 8.8 BITS SFDR = 63dBFS BUFFER CURRENT = 8.5× –20 75 SNR/SFDR (dBFS) –40 –60 –80 SFDR 70 65 SNR 60 –120 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) 11752-614 –100 55 628.3 706.6 784.3 862.3 940.3 1018.3 1096.3 1174.3 1252.3 INPUT FREQUENCY (MHz) Figure 17. SNR/SFDR vs. fIN; 650 MHz < fIN < 1.3 GHz; Buffer Control 1 (0x018) = 6.5× Figure 14. Single-Tone FFT with fIN = 1954.3 MHz Rev. E | Page 17 of 105 11752-617 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 11752-615 SNR AD9680 Data Sheet 0 80 –20 SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBFS) 75 IMD3 (dBc) IMD3 (dBFS) SFDR (dBFS) SFDR (dBc) 70 SFDR 65 60 SNR 55 –40 –60 –80 1356.3 1460.3 1564.3 1668.3 177.23 1876.3 1980.3 INPUT FREQUENCY (MHz) –120 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 INPUT AMPLITUDE (dBFS) Figure 21. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz Figure 18. SNR/SFDR vs. fIN; 1.3 GHz < fIN < 2GHz; Buffer Control 1 (0x018) = 8.5× 0 0 AIN1 AND AIN2 = –7dBFS SFDR = 82dBFS IMD2 = 84dBFS IMD3 = 82dBFS BUFFER CURRENT = 3.5× IMD3 (dBc) IMD3 (dBFS) SFDR (dBFS) SFDR (dBc) –20 SFDR/IMD3 (dBc AND dBFS) –40 –60 –80 –100 –40 –60 –80 –100 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) –140 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 11752-095 –120 0 INPUT AMPLITUDE (dBFS) 11752-623 –120 Figure 22. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with fIN1 = 449 MHz and fIN2 = 452 MHz Figure 19. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz 120 0 AIN1 AND AIN2 = –7dBFS SFDR = 78dBFS IMD2 = 78dBFS IMD3 = 78dBFS BUFFER CURRENT = 5.5× –20 100 80 SNR/SFDR (dB) –40 –60 60 40 20 –80 0 –100 SNR (dBFS) SNR (dBc) SFDR (dBc) SFDR (dBFS) –120 0 78.125 156.250 234.375 312.500 390.625 468.750 546.875 625.000 FREQUENCY (MHz) 11752-096 –20 Figure 20. Two-Tone FFT; fIN1 = 449 MHz, fIN2 = 452 MHz –40 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 INPUT AMPLITUDE (dBFS) Figure 23. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz Rev. E | Page 18 of 105 11752-624 AMPLITUDE (dBFS) –20 AMPLITUDE (dBFS) 11752-622 50 1252.3 11752-618 –100 Data Sheet AD9680 1200000 85 3.45 LSB rms SFDR 1000000 NUMBER OF HITS SNR/SFDR (dBFS) 80 75 70 65 800000 600000 400000 SNR 60 12 22 32 42 52 62 72 82 92 102 112 TEMPERATURE (°C) 0 11752-628 2 11752-625 55 –48 –38 –28 –18 –8 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 200000 CODE Figure 24. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Figure 27. Input-Referred Noise Histogram 4 4.00 3 3.95 3.90 2 3.85 POWER (W) INL (LSB) 1 0 –1 3.80 3.75 3.70 –2 3.65 –3 0 2000 4000 6000 8000 10000 12000 14000 16000 OUTPUT CODE 3.55 –48 –38 –28 –18 –8 11752-626 –4 Figure 25. INL, fIN = 10.3 MHz 12 22 32 42 52 62 72 82 Figure 28. Power Dissipation vs. Temperature 0.4 4.0 0.3 3.9 POWER DISSIPATION (W) 0.2 0.1 0 –0.1 –0.2 3.8 3.7 3.6 3.5 –0.4 0 2000 4000 6000 8000 10000 12000 OUTPUT CODE 14000 16000 Figure 26. DNL, fIN = 15 MHz 3.3 1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260 SAMPLE RATE (MHz) Figure 29. Power Dissipation vs. fS Rev. E | Page 19 of 105 11752-630 3.4 –0.3 11752-627 DNL (LSB) 2 TEMPERATURE (°C) 11752-629 3.60 AD9680 Data Sheet AD9680-1000 AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.7 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted. See Table 10 for recommended settings. AIN = –1dBFS SNR = 67.2dBFS ENOB = 10.8 BITS SFDR = 88dBFS BUFFER CONTROL 1 = 1.5× –10 –30 AMPLITUDE (dBFS) –50 –70 –90 –50 –70 –90 –110 –110 0 100 200 300 400 500 FREQUENCY (MHz) –130 11752-100 –130 100 0 Figure 30. Single-Tone FFT with fIN = 10.3 MHz 400 500 AIN = –1dBFS SNR = 62.6dBFS ENOB = 10.1 BITS SFDR = 82dBFS BUFFER CONTROL 1 = 6.0× AMPLITUDE (dBFS) AMPLITUDE (dBFS) –30 300 Figure 33. Single-Tone FFT with fIN = 450.3 MHz AIN = –1dBFS SNR = 66.6dBFS ENOB = 10.7 BITS SFDR = 85dBFS BUFFER CONTROL 1 = 3.0× –10 200 FREQUENCY (MHz) 11752-103 AMPLITUDE (dBFS) –30 AIN = –1dBFS SNR = 64.0dBFS ENOB = 10.3 BITS SFDR = 82dBFS BUFFER CONTROL 1 = 3.0× –10 –50 –70 –90 0 100 200 300 400 500 FREQUENCY (MHz) 0 0 400 500 AIN = –1dBFS SNR = 60.5dBFS ENOB = 9.9 BITS SFDR = 80dBFS BUFFER CONTROL 1 = 6.0× AMPLITUDE (dBFS) –20 –50 –70 –90 –40 –60 –80 –130 0 100 200 300 400 FREQUENCY (MHz) 500 Figure 32. Single-Tone FFT with fIN = 340.3 MHz –120 0 100 200 300 400 FREQUENCY (MHz) Figure 35. Single-Tone FFT with fIN = 985.3 MHz Rev. E | Page 20 of 105 500 11752-105 –100 –110 11752-102 AMPLITUDE (dBFS) 300 Figure 34. Single-Tone FFT with fIN = 765.3 MHz AIN = –1dBFS SNR = 65.3dBFS ENOB = 10.5 BITS SFDR = 85dBFS BUFFER CONTROL 1 = 3.0× –30 200 FREQUENCY (MHz) Figure 31. Single-Tone FFT with fIN = 170.3 MHz –10 100 11752-104 –130 11752-101 –110 Data Sheet AD9680 90 0 85 SFDR (dBFS) –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) AIN = –1dBFS SNR = 59.8BFS ENOB = 9.6 BITS –20 SFDR = 79dBFS BUFFER CONTROL 1 = 8.0× –60 –80 80 75 70 SNR (dBFS) –100 0 100 200 300 400 500 FREQUENCY (MHz) 60 700 750 800 850 900 950 1000 1050 11752-201 –120 11752-107 65 1100 SAMPLE RATE (MHz) Figure 36. Single-Tone FFT with fIN = 1293.3 MHz Figure 39. SNR/SFDR vs. fS, fIN = 170.3 MHz; Buffer Control 1 (0x018) = 3.0× 0 90 85 80 –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) AIN = –1dBFS SNR = 57.7dBFS ENOB = 9.2 BITS –20 SFDR = 70dBFS BUFFER CONTROL 1 = 8.0× –60 –80 75 70 65 55 1.5× SFDR (dBFS) 1.5× SNR (dBFS) 3.0× SFDR (dBFS) 3.0× SNR (dBFS) 0 100 200 300 400 500 FREQUENCY (MHz) 11752-108 –120 50 10.3 63.3 ANALOG INPUT FREQUENCY (MHz) Figure 40. SNR/SFDR vs. fIN; fIN < 500 MHz; Buffer Control 1 (0x018) = 1.5× and 3.0× Figure 37. Single-Tone FFT with fIN = 1725.3 MHz 100 0 AIN = –1dBFS SNR = 57.0dBFS ENOB = 9.1 BITS SFDR = 69dBFS BUFFER CURRENT = 6.0× 90 SNR/SFDR (dBFS) –20 –40 –60 –80 80 70 60 –120 0 100 200 300 FREQUENCY (MHz) 400 500 50 476.8 4.0× SFDR 4.0× SNRFS 6.0× SFDR 6.0× SNRFS 554.4 593.2 670.8 748.4 826.0 903.6 981.2 ANALOG INPUT FREQUENCY (MHz) Figure 41. SNR/SFDR vs. fIN; 500 MHz < fIN < 1 GHz; Buffer Control 1 (0x018) = 4.0× and 6.0× Figure 38. Single-Tone FFT with fIN = 1950.3 MHz Rev. E | Page 21 of 105 11752-218 –100 11752-506 AMPLITUDE (dBFS) 100.3 170.3 225.3 302.3 341.3 403.3 453.3 502.3 11752-216 60 –100 AD9680 Data Sheet 100 0 –20 AMPLITUDE (dBFS) 90 80 SFDR 70 –40 –60 –80 SNR 60 50 978.5 1142.4 1065.0 1220.0 1297.3 1452.2 1374.8 –120 ANALOG INPUT FREQUENCY (MHz) 0 100 200 300 Figure 42. SNR/SFDR vs. fIN; 1 GHz < fIN < 1.5 GHz; Buffer Control 1 (0x018) = 6.0× 500 Figure 45. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz 100 20 SFDR (dBc) SFDR (dBFS) IMD3 (dBc) IMD3 (dBFS) 0 SFDR/IMD3 (dBc AND dBFS) 90 80 SFDR 70 60 SNR 1607.4 1701.6 –40 –60 –80 –100 –120 11752-220 50 1513.3 –20 1889.7 1795.6 ANALOG INPUT FREQUENCY (MHz) –140 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 INPUT AMPLITUDE (dBFS) Figure 43. SNR/SFDR vs. fIN; 1.5 GHz < fIN < 2 GHz; Buffer Control 1 (0x018) = 7.5× Figure 46. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz 0 SFDR (dBc) SFDR (dBFS) IMD3 (dBc) IMD3 (dBFS) SNR/SFDR (dBc AND dBFS) 0 –40 –60 –80 –20 –40 –60 –80 –100 –100 0 100 200 300 400 FREQUENCY (MHz) 500 –140 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 INPUT AMPLITUDE (dBFS) Figure 44. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz Figure 47. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with fIN1 = 338 MHz and fIN2 = 341 MHz Rev. E | Page 22 of 105 11752-208 –120 –120 11752-205 AMPLITUDE (dBFS) 20 AIN1 AND AIN2 = –7dBFS SFDR = 87dBFS IMD2 = 93dBFS IMD3 = 87dBFS BUFFER CONTROL 1 = 3.0× –20 11752-207 SNR/SFDR (dBFS) 400 FREQUENCY (MHz) 11752-206 –100 11752-219 SNR/SFDR (dBFS) AIN1 AND AIN2 = –7dBFS SFDR = 88dBFS IMD2 = 93dBFS IMD3 = 88dBFS BUFFER CONTROL 1 = 4.5× Data Sheet AD9680 3 110 100 90 2 80 1 60 INL (LSB) SNR/SFDR (dB) 70 50 40 0 30 –1 20 10 0 INPUT AMPLITUDE (dBFS) –3 11752-209 –20 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 0 2000 6000 8000 10000 12000 14000 16000 OUTPUT CODE Figure 48. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz Figure 50. INL, fIN = 10.3 MHz 0.6 100 0.4 90 SFDR 0.2 70 DNL (LSB) 80 SNR 0 –0.2 60 50 –50 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 90 –0.6 0 2000 4000 6000 8000 10000 12000 14000 16000 OUTPUT CODE Figure 49. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Figure 51. DNL, fIN = 15 MHz Rev. E | Page 23 of 105 11752-212 –0.4 11752-210 SNR/SFDR (dBFS) 4000 11752-211 –2 SFDR (dBFS) SFDR (dBc) SNR (dBFS) SNR (dBc) 0 –10 AD9680 Data Sheet 3.40 25000 L = 4, M = 2, F = 1 2.63 LSB rms 3.35 3.30 POWER DISSIPATION (W) NUMBER OF HITS 20000 15000 10000 3.25 3.20 3.15 3.10 3.05 3.00 5000 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 CODE Figure 52. Input-Referred Noise Histogram L=4 M=2 F=1 3.30 3.25 3.20 10 20 30 40 50 60 70 TEMPERATURE (°C) 80 90 11752-214 POWER DISSIPATION (W) 3.35 0 750 800 850 900 950 1000 SAMPLE RATE (MHz) Figure 54. Power Dissipation vs. fS 3.40 3.15 –50 –40 –30 –20 –10 2.90 700 Figure 53. Power Dissipation vs. Temperature Rev. E | Page 24 of 105 1050 1100 11752-215 0 11752-213 2.95 Data Sheet AD9680 AD9680-820 AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.7 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted. See Table 10 for recommended settings. 0 0 AIN = –1dBFS SNR = 67.2dBFS ENOB = 10.9BITS SFDR = 89dBFS BUFFER CONTROL 1 = 1.5× AIN = –1dBFS SNR = 65.1dBFS ENOB = 10.5 BITS SFDR = 79dBFS BUFFER CONTROL 1 = 6.5× –20 AMPLITUDE (dBFS) –40 –60 –80 –40 –60 –80 0 82 164 246 FREQUENCY (MHz) 328 410 –120 11752-507 –120 0 246 328 410 Figure 58. Single-Tone FFT with fIN = 450.3 MHz 0 0 AIN = –1dBFS SNR = 67.0dBFS ENOB = 10.8 BITS SFDR = 83dBFS BUFFER CONTROL 1 = 2.0× AIN = –1dBFS SNR = 64.0dBFS ENOB = 10.3 BITS SFDR = 79dBFS BUFFER CONTROL 1 = 6.5× –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –40 –60 –80 –100 –100 0 82 164 246 328 410 FREQUENCY (MHz) –120 11752-508 –120 0 82 164 246 328 410 11752-511 AMPLITUDE (dBFS) 164 FREQUENCY (MHz) Figure 55. Single-Tone FFT with fIN = 10.3 MHz 410 FREQUENCY (MHz) Figure 59. Single-Tone FFT with fIN = 765.3 MHz Figure 56. Single-Tone FFT with fIN = 170.3 MHz 0 0 AIN = –1dBFS SNR = 66.5dBFS ENOB = 10.7 BITS SFDR = 86dBFS BUFFER CONTROL 1 = 3.0× AIN = –1dBFS SNR = 63.4dBFS ENOB = 10.1 BITS SFDR = 74dBFS BUFFER CONTROL 1 = 8.5× –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –40 –60 –80 –100 –100 –120 0 82 164 246 FREQUENCY (MHz) 328 410 11752-509 AMPLITUDE (dBFS) 82 11752-510 –100 –100 11752-512 AMPLITUDE (dBFS) –20 Figure 57. Single-Tone FFT with fIN = 340.3 MHz –120 0 82 164 246 328 FREQUENCY (MHz) Figure 60. Single-Tone FFT with fIN = 985.3 MHz Rev. E | Page 25 of 105 AD9680 Data Sheet 0 90 AIN = –1dBFS SNR = 62.0dBFS ENOB = 9.9 BITS SFDR = 76dBFS BUFFER CONTROL 1 = 6.5× 85 SFDR 80 –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) –20 –60 –80 75 70 SNR 65 60 –100 0 82 164 246 FREQUENCY (MHz) 328 410 50 500 550 Figure 61. Single-Tone FFT with fIN = 1205.3 MHz 650 700 750 SAMPLE RATE (MHz) 800 850 900 Figure 64. SNR/SFDR vs. fS, fIN = 170.3 MHz; Buffer Control 1 (0x018) = 3.0× 0 95 AIN = –1dBFS SNR = 60.5dBFS ENOB = 9.5 BITS SFDR = 68dBFS BUFFER CONTROL 1 = 7.5× –20 90 85 –40 SNR/SFDR (dBFS) –60 –80 80 75 70 65 60 450.3 11752-517 985.3 11752-518 420.3 390.3 360.3 340.7 330.3 301.3 270.3 240.3 50 210.5 410 180.3 328 170.3 246 65.5 164 FREQUENCY (MHz) 10.3 82 11752-514 0 150.3 SFDR SNR 55 –120 95.3 –100 125.4 AMPLITUDE (dBFS) 600 11752-516 –120 11752-513 55 ANALOG INPUT FREQUENCY (MHz) Figure 65. SNR/SFDR vs. fIN; fIN < 450 MHz; Buffer Control 1 (0x018) = 3.0× Figure 62. Single-Tone FFT with fIN = 1720.3 MHz 85 0 AIN = –1dBFS SNR = 59.7dBFS ENOB = 9.5 BITS SFDR = 69dBFS BUFFER CONTROL 1 = 8.5× 80 SNR/SFDR (dBFS) 75 –40 –60 –80 70 SNR 65 60 –100 55 –120 0 82 164 246 328 FREQUENCY (MHz) 410 11752-515 AMPLITUDE (dBFS) –20 SFDR 50 450.3 480.3 510.3 515.3 610.3 766.3 810.3 ANALOG INPUT FREQUENCY (MHz) Figure 66. SNR/SFDR vs. fIN; 450 MHz < fIN < 1 GHz; Buffer Control 1 (0x018) = 6.5× Figure 63. Single-Tone FFT with fIN = 1950.3 MHz Rev. E | Page 26 of 105 Data Sheet AD9680 0 80 SFDR AMPLITUDE (dBFS) 70 65 SNR 60 –40 –60 –80 –100 55 –120 1022.3 1110.3 1205.3 1315.3 1420.3 1510.3 ANALOG INPUT FREQUENCY (MHz) 11752-519 50 985.3 0 164 246 328 410 FREQUENCY (MHz) Figure 67. SNR/SFDR vs. fIN; 1 GHz < fIN < 1.5 GHz; Buffer Control 1 (0x018) = 6.5× Figure 70. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz 75 0 –20 SFDR/IMD3 (dBc AND dBFS) 70 SFDR SNR/SFDR (dBFS) 82 11752-527 SNR/SFDR (dBFS) AIN1 AND AIN2 = –7dBFS SFDR = 87dBFS IMD2 = 92dBFS IMD3 = 87dBFS BUFFER CURRENT = 3.0× –20 75 65 SNR 60 55 IMD3 (dBc) IMD3 (dBFS) SFDR (dBc) SFDR (dBFS) –40 –60 –80 1600.3 1720.3 1810.3 1920.3 ANALOG INPUT FREQUENCY (MHz) 1950.3 –120 –87 –81 –75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9 INPUT AMPLITUDE (dBFS) Figure 68. SNR/SFDR vs. fIN; 1.5 GHz < fIN < 2 GHz; Buffer Control 1 (0x018) = 8.5× Figure 71. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz 0 0 AIN1 AND AIN2 = –7dBFS SFDR = 90dBFS IMD2 = 90dBFS IMD3 = 91dBFS BUFFER CURRENT = 3.0× –20 SFDR/IMD3 (dBc AND dBFS) –20 –40 –60 –80 –100 IMD3 (dBc) IMD3 (dBFS) SFDR (dBc) SFDR (dBFS) –40 –60 –80 –120 0 82 164 246 FREQUENCY (MHz) 328 410 –120 –87 –81 –75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9 INPUT AMPLITUDE (dBFS) Figure 72. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with fIN1 = 338 MHz and fIN2 = 341 MHz Figure 69. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz Rev. E | Page 27 of 105 11752-535 –100 11752-529 AMPLITUDE (dBFS) 11752-528 50 1510.3 11752-520 –100 Data Sheet 120 2.5 105 2.0 90 1.5 75 1.0 INL (LSB) 60 45 30 0.5 0 –0.5 15 –1.0 SNR (dBc) SNR (dBFS) SFDR (dBc) SFDR (dBFS) –15 –1.5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 –55 –50 –60 –65 –70 –75 –80 –85 –90 –95 –30 –2.0 0 2000 4000 6000 8000 10000 OUTPUT CODE 12000 14000 16000 11752-534 0 11752-521 SNR/SFDR (dBc AND dBFS) AD9680 INPUT AMPLITUDE (dBFS) Figure 73. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz Figure 75. INL, fIN = 10.3 MHz 0.25 90 SNR (dBFS) SFDR (dBFS) 0.20 85 0.15 DNL (LSB) 0.05 75 0 –0.05 –0.10 70 –0.15 –0.20 65 –30 –15 –5 5 15 25 TEMPERATURE (°C) 45 65 85 –0.30 0 2000 4000 6000 8000 10000 OUTPUT CODE 12000 Figure 76. DNL, fIN = 15 MHz Figure 74. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Rev. E | Page 28 of 105 14000 16000 11752-530 –0.25 60 –45 11752-533 SNR/SFDR (dBFS) 0.10 80 Data Sheet AD9680 3.1 1600000 2.46 LSB rms 1400000 3.0 2.9 POWER (W) 1000000 800000 600000 2.8 2.7 400000 11752-531 CODE 2.90 2.88 2.86 2.84 2.82 2.80 –15 –5 5 15 25 TEMPERATURE (°C) 45 65 85 11752-532 2.78 –30 900 875 850 825 800 775 750 725 700 650 675 625 600 575 550 SAMPLE RATE (MHz) Figure 79. Power Dissipation vs. fS ; L = 4, M = 2, F = 1 for fS ≥ 625 MSPS and L = 2, M = 2, F = 2 for fS < 625 MSPS (Default SPI) Figure 77. Input-Referred Noise Histogram 2.76 –45 525 2.5 500 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 0 11752-522 2.6 200000 POWER (W) NUMBER OF HITS 1200000 Figure 78. Power Dissipation vs. Temperature Rev. E | Page 29 of 105 AD9680 Data Sheet AD9680-500 AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 2.06 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted. See Table 10 for recommended settings. 0 0 AIN = −1dBFS SNR = 68.9dBFS ENOB = 10.9 BITS SFDR = 83dBFS BUFFER CONTROL 1 = 2.0× –20 –40 AMPLITUDE (dBFS) –40 –60 –80 –60 –80 –100 –100 0 25 50 75 100 125 150 175 200 225 –140 11752-132 –140 250 FREQUENCY (MHz) 0 25 175 200 225 250 –40 AMPLITUDE (dBFS) –60 –80 –120 –60 –80 –100 –140 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) 11752-133 –120 –140 0 75 100 125 150 175 200 225 250 Figure 84. Single-Tone FFT with fIN = 765.3 MHz 0 AIN = −1dBFS SNR = 68.5dBFS ENOB = 10.9 BITS SFDR = 83dBFS BUFFER CONTROL 1 = 4.5× –20 50 FREQUENCY (MHz) Figure 81. Single-Tone FFT with fIN = 170.3 MHz 0 25 11752-136 AMPLITUDE (dBFS) 150 AIN = −1dBFS SNR = 64.7dBFS ENOB = 10.4 BITS SFDR = 80dBFS BUFFER CONTROL 1 = 5.0× –20 –100 AIN = −1dBFS SNR = 64.0dBFS ENOB = 10.3 BITS SFDR = 76dBFS BUFFER CONTROL 1 = 5.0× –20 –40 –40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 125 0 –40 –60 –80 –100 –120 –60 –80 –100 –120 0 25 50 75 100 125 150 175 200 225 FREQUENCY (MHz) 250 –140 11752-134 –140 100 Figure 83. Single-Tone FFT with fIN = 450.3 MHz AIN = −1dBFS SNR = 68.9dBFS ENOB = 11 BITS SFDR = 88dBFS BUFFER CONTROL 1 = 2.0× –20 75 FREQUENCY (MHz) Figure 80. Single-Tone FFT with fIN = 10.3 MHz 0 50 11752-135 –120 –120 0 25 50 75 100 125 150 175 200 225 FREQUENCY (MHz) Figure 82. Single-Tone FFT with fIN = 340.3 MHz Figure 85. Single-Tone FFT with fIN = 985.3 MHz Rev. E | Page 30 of 105 250 11752-137 AMPLITUDE (dBFS) AIN = −1dBFS SNR = 67.8dBFS ENOB = 10.8 BITS SFDR = 83dBFS BUFFER CONTROL 1 = 4.5× –20 Data Sheet AD9680 95 0 AIN = −1dBFS SNR = 63.0dBFS ENOB = 10.0 BITS SFDR = 69dBFS BUFFER CONTROL 1 = 8.0× 90 SNR/SFDR (dBFS) –60 –80 80 75 –100 70 –120 65 –140 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) SNR 60 300 320 340 360 380 400 420 440 460 480 500 530 550 11752-138 AMPLITUDE (dBFS) SFDR 85 –40 SAMPLE FREQUENCY (MHz) Figure 86. Single-Tone FFT with fIN = 1310.3 MHz 11752-141 –20 Figure 89. SNR/SFDR vs. fS, fIN = 170.3 MHz; Buffer Control 1 = 2.0× 100 0 AIN = −1dBFS SNR = 61.5dBFS ENOB = 9.8 BITS SFDR = 69dBFS BUFFER CONTROL 1 = 8.0× –20 90 SNR/SFDR (dBFS) AMPLITUDE (dBFS) –40 –60 –80 80 70 –100 60 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) 50 10.3 11752-139 –140 2.0× SNR 2.0× SFDR 4.5× SNR 4.5× SFDR 95.3 150.3 180.3 240.3 301.3 340.7 390.3 450.3 ANALOG INPUT FREQUENCY (MHz) Figure 87. Single-Tone FFT with fIN = 1710.3 MHz 11752-142 –120 Figure 90. SNR/SFDR vs. fIN; fIN < 500 MHz; Buffer Control 1 (0x018) = 2.0× and 4.5× 0 100 AIN = −1dBFS SNR = 60.8dBFS ENOB = 9.6 BITS SFDR = 68dBFS BUFFER CONTROL 1 = 8.0× –20 90 SNR/SFDR (dBFS) –60 –80 80 70 –100 60 –140 0 25 50 75 100 125 150 175 200 225 FREQUENCY (MHz) 250 50 450.3 4.0× SNR 4.0× SFDR 8.0× SNR 8.0× SFDR 480.3 510.3 515.3 610.3 765.3 810.3 985.3 ANALOG INPUT FREQUENCY (MHz) Figure 91. SNR/SFDR vs. fIN; 500 MHz < fIN < 1 GHz; Buffer Control 1 (0x018) = 4.0× and 8.0× Figure 88. Single-Tone FFT with fIN = 1950.3 MHz Rev. E | Page 31 of 105 1010.3 11752-143 –120 11752-140 AMPLITUDE (dBFS) –40 AD9680 80 0 7.0× SNR 7.0× SFDR 8.0× SNR 8.0× SFDR 70 65 60 –40 –60 –80 –100 1205.3 1410.3 1600.3 1810.3 ANALOG INPUT FREQUENCY (MHz) 1950.3 –120 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 INPUT AMPLITUDE (dBFS) Figure 92. SNR/SFDR vs. fIN; 1 GHz < fIN < 2 GHz; Buffer Control 1 (0x018) = 7.0× and 8.0× Figure 95. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz 0 0 AIN1 AND AIN2 = –7dBFS SFDR = 88dBFS IMD2 = 94dBFS IMD3 = 88dBFS BUFFER CONTROL 1 = 2.0× SFDR (dBc) SFDR (dBFS) IMD3 (dBc) IMD3 (dBFS) –20 SFDR/IMD3 (dBc AND dBFS) –20 –40 –60 –80 –40 –60 –80 0 50 100 150 FREQUENCY (MHz) 200 250 11752-146 –120 –120 –90 –72 –63 –54 –45 –36 100 90 80 SNR/SFDR (dBc AND dBFS) –40 –60 –80 70 60 50 40 30 20 10 –100 SFDR (dBFS) SNR (dBFS) SFDR (dBc) SNR (dBc) 0 –120 200 250 11752-147 –10 100 150 FREQUENCY (MHz) –9 110 AIN1 AND AIN2 = –7dBFS SFDR = 88dBFS IMD2 = 88dBFS IMD3 = 89dBFS BUFFER CONTROL 1 = 4.5× 50 –18 Figure 96. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with fIN1 = 338 MHz and fIN2 = 341 MHz 0 0 –27 AMPLITUDE (dBFS) Figure 93. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz –20 –81 11752-149 –100 –100 –20 –90 –80 –70 –60 –50 –40 –30 –20 –10 INPUT AMPLITUDE (dBFS) Figure 94. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz Figure 97. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz Rev. E | Page 32 of 105 0 11752-150 AMPLITUDE (dBFS) 11752-148 50 1010.3 11752-144 55 AMPLITUDE (dBFS) SFDR (dBc) SFDR (dBFS) IMD3 (dBc) IMD3 (dBFS) –20 SFDR/IMD3 (dBc AND dBFS) 75 SNR/SFDR (dBFS) Data Sheet Data Sheet AD9680 95 900000 2.06 LSB RMS 800000 SFDR 700000 NUMBER OF HITS SNR/SFDR (dBFS) 90 85 80 75 600000 500000 400000 300000 200000 SNR 70 10 35 60 85 TEMPERATURE (°C) 0 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 –15 11752-151 65 –40 OUTPUT CODE Figure 98. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Figure 101. Input-Referred Noise Histogram 2.32 3.0 L=4 M=2 F=1 2.5 2.30 2.0 1.5 2.28 POWER (W) INL (LSB) 11752-154 100000 1.0 0.5 0 2.26 2.24 –0.5 –1.0 2.22 0 2000 4000 6000 8000 10000 12000 14000 16000 OUTPUT CODE 2.20 –45 11752-152 –2.0 –35 –5 15 25 45 65 11752-155 –1.5 85 TEMPERATURE (°C) Figure 99. INL, fIN = 10.3 MHz Figure 102. Power Dissipation vs. Temperature 0.8 2.37 0.6 2.32 L = 4, M = 2, F = 1 L = 2, M = 2, F = 2 2.27 0.4 POWER (W) DNL (LSB) 2.22 0.2 0 –0.2 2.17 2.12 2.07 2.02 –0.4 1.97 –0.6 2000 4000 6000 8000 10000 12000 OUTPUT CODE 14000 16000 1.87 300 320 340 360 380 400 420 440 460 480 500 520 540 SAMPLE RATE (MHz) Figure 103. Power Dissipation vs. fS Figure 100. DNL, fIN = 15 MHz Rev. E | Page 33 of 105 11752-156 0 11752-153 1.92 –0.8 AD9680 Data Sheet EQUIVALENT CIRCUITS AVDD3 AVDD3 AVDD3 3pF 1.5pF 200Ω EMPHASIS/SWING CONTROL (SPI) VCM BUFFER 200Ω 67Ω 28Ω 10pF 200Ω 400Ω DRVDD AVDD3 AVDD3 DATA+ SERDOUTx+ x = 0, 1, 2, 3 VIN–x DRGND OUTPUT DRIVER DATA– SERDOUTx– x = 0, 1, 2, 3 11752-011 AIN CONTROL (SPI) 3pF 1.5pF DRVDD DRGND 11752-014 67Ω 200Ω 28Ω VIN+x Figure 107. Digital Outputs Figure 104. Analog Inputs DVDD 1kΩ 25Ω CLK+ DGND 20kΩ LEVEL TRANSLATOR 25Ω SYNCINB– 20kΩ 20kΩ VCM = 0.85V VCM 1kΩ SYNCINB± PIN CONTROL (SPI) 11752-012 CLK– 20kΩ DVDD AVDD1 VCM = 0.85V 11752-015 SYNCINB+ AVDD1 DGND Figure 105. Clock Inputs Figure 108. SYNCINB± Inputs AVDD1_SR 1kΩ SPIVDD ESD PROTECTED 20kΩ LEVEL TRANSLATOR AVDD1_SR SCLK 20kΩ SPIVDD 1kΩ 30kΩ 1kΩ ESD PROTECTED 11752-013 SYSREF– VCM = 0.85V 11752-016 SYSREF+ Figure 109. SCLK Input Figure 106. SYSREF± Inputs Rev. E | Page 34 of 105 Data Sheet AD9680 SPIVDD ESD PROTECTED 30kΩ 1kΩ CSB 1kΩ PDWN/ STBY ESD PROTECTED 11752-017 ESD PROTECTED Figure 110. CSB Input Figure 113. PDWN/STBY Input SPIVDD ESD PROTECTED AVDD2 SDO ESD PROTECTED SPIVDD 1kΩ SDIO PDWN CONTROL (SPI) 11752-020 ESD PROTECTED SPIVDD SDI V_1P0 30kΩ 11752-018 V_1P0 PIN CONTROL (SPI) Figure 111. SDIO Input Figure 114. V_1P0 Input/Output SPIVDD ESD PROTECTED FD JESD LMFC FD_A/FD_B JESD SYNC~ TEMPERATURE DIODE (FD_A ONLY) FD_x PIN CONTROL (SPI) 11752-019 ESD PROTECTED Figure 112. FD_A/FD_B Outputs Rev. E | Page 35 of 105 11752-021 ESD PROTECTED ESD PROTECTED AD9680 Data Sheet THEORY OF OPERATION The AD9680 has two analog input channels and four JESD204B output lane pairs. The ADC is designed to sample wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD9680 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. The Subclass 1 JESD204B-based high speed serialized output data lanes can be configured in one-lane (L = 1), two-lane (L = 2), and four-lane (L = 4) configurations, depending on the sample rate and the decimation ratio. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins. ADC ARCHITECTURE The architecture of the AD9680 consists of an input buffered pipelined ADC. The input buffer is designed to provide a termination impedance to the analog input signal. This termination impedance can be changed using the SPI to meet the termination needs of the driver/amplifier. The default termination value is set to 400 Ω. The equivalent circuit diagram of the analog input termination is shown in Figure 104. The input buffer is optimized for high linearity, low noise, and low power. The input buffer provides a linear high input impedance (for ease of drive) and reduces kickback from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample; at the same time, the remaining stages operate with the preceding samples. Sampling occurs on the rising edge of the clock. ANALOG INPUT CONSIDERATIONS The analog input to the AD9680 is a differential buffer. The internal common-mode voltage of the buffer is 2.05 V. The clock signal alternately switches the input circuit between sample mode and hold mode. When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor, in series with each input, can help reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, thus, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a differential capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input, which limits unwanted broadband noise. For more information, refer to the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005). In general, the precise values depend on the application. For best dynamic performance, the source impedances driving VIN+x and VIN−x must be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9680, the available span is programmable through the SPI port from 1.46 V p-p to 2.06 V p-p differential, with 1.58 V p-p differential being the default for the AD9680-1250, 1.70 V p-p differential being the default for the AD9680-1000 and AD9680-820, and 2.06 V p-p differential being the default for the AD9680-500. Differential Input Configurations There are several ways to drive the AD9680, either actively or passively. However, optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 115 and Table 9) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9680. For low to midrange frequencies, a double balun or double transformer network (see Figure 115 and Table 9) is recommended for optimum performance of the AD9680. For higher frequencies in the second or third Nyquist zones, it is better to remove some of the front-end passive components to ensure wideband operation (see Figure 115 and Table 9). Rev. E | Page 36 of 105 Data Sheet AD9680 0.1µF R1 R3 R2 C1 ADC C2 R2 R1 0.1µF 0.1µF R3 C1 11752-168 BALUN NOTES 1. SEE TABLE 9 FOR COMPONENT VALUES. Figure 115. Differential Transformer-Coupled Configuration for AD9680 Table 9. Differential Transformer-Coupled Input Configuration Component Values Device AD9680-500 Frequency Range DC to 250 MHz 250 MHz to 2 GHz DC to 410 MHz 410 MHz to 2 GHz DC to 500 MHz 500 MHz to 2 GHz DC to 625 MHz 625 MHz to 2 GHz AD9680-820 AD9680-1000 AD9680-1250 Transformer ETC1-1-13 BAL-0006/BAL-0006SMG ETC1-1-13 BAL-0006/BAL-0006SMG ETC1-1-13/BAL-0006SMG BAL-0006/BAL-0006SMG BAL-0006SMG BAL-0006SMG Input Common Mode The analog inputs of the AD9680 are internally biased to the common mode as shown in Figure 116. The common-mode buffer has a limited range in that the performance suffers greatly if the common-mode voltage drops by more than 100 mV. Therefore, in dc-coupled applications, set the common-mode voltage to 2.05 V, ±100 mV to ensure proper ADC operation. The full-scale voltage setting must be at a 1.7 V p-p differential if running in a dc-coupled application. Analog Input Buffer Controls and SFDR Optimization The AD9680 input buffer offers flexible controls for the analog inputs, such as input termination, buffer current, and input fullscale adjustment. All the available controls are shown in Figure 116. AVDD3 AVDD3 200Ω 67Ω 200Ω 28Ω VIN+x AVDD3 3pF 1.5pF VCM BUFFER 11752-169 AIN CONTROL SPI REGISTERS (0x008, 0x015, 0x016, 0x018, 0x019, 0x01A, 0x11A, 0x934, 0x935) C1 (pF) 4 4 4 4 4 Open 4 Open C2 (pF) 2 2 2 2 2 Open 2 Open The input buffer has many registers that set the bias currents and other settings for operation at different frequencies. These bias currents and settings can be changed to suit the input frequency range of operation. Register 0x018 controls the buffer bias current to help with the kickback from the ADC core. This setting can be scaled from a low setting of 1.0× to a high setting of 8.5×. The default setting is 3.0× for the AD9680-1000 and AD9680-820, and 2.0× for the AD9680-500. These settings are sufficient for operation in the first Nyquist zone for the products. When the input buffer current in Register 0x018 is set, the amount of current required by the AVDD3 supply changes. This relationship is shown in Figure 117. For a complete list of buffer current settings, see Table 39. VIN–x 3pF 1.5pF R3 (Ω) 10 10 10 10 10 0 15 0 Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) AVDD3 AVDD3 R2 (Ω) 50 50 50 50 25 25 50 50 Using the 0x018, 0x019, 0x01A, 0x11A, 0x934, and 0x935 registers, the buffer behavior on each channel can be adjusted to optimize the SFDR over various input frequencies and bandwidths of interest. 200Ω 67Ω 28Ω 10pF 200Ω 400Ω R1 (Ω) 10 10 10 10 25 25 10 10 Figure 116. Analog Input Controls Rev. E | Page 37 of 105 AD9680 Data Sheet 300 80 75 AD9680-500 150 70 65 100 3.5× 4.5× 5.5× 6.5× 7.5× 8.5× BUFFER CONTROL 1 SETTING Figure 117. IAVDD3 vs. Buffer Control 1 Setting in Register 0x018 The 0x019, 0x01A, 0x11A, and 0x935 registers offer secondary bias controls for the input buffer for frequencies >500 MHz. Register 0x934 can be used to reduce input capacitance to achieve wider signal bandwidth but may result in slightly lower linearity and noise performance. These register settings do not impact the AVDD3 power as much as Register 0x018 does. For frequencies 500 MHz for the AD9680-1000). This setting enables the ADC sampling network to optimize the sampling and settling times internal to the ADC for high frequency operation. For frequencies greater than 500 MHz, it is recommended to operate the ADC core at a 1.46 V full-scale setting irrespective of the speed grade. This setting offers better SFDR without any significant penalty in SNR. Figure 118, Figure 119, and Figure 120 show the SFDR vs. analog input frequency for various buffer settings for the AD9680-1250. The recommended settings shown in Table 10 were used to take the data while changing the contents of Register 0x018 only. 3.5× 4.5× 5.5× 6.5× 55 602.3 680.3 758.3 836.3 914.3 992.3 1070.3 1148.3 1226.3 INPUT FREQUENCY (MHz) Figure 119. Buffer Current Sweeps, AD9680-1250 (SFDR vs. IBUFF); 600 MHz < fIN < 1300 MHz; Front-End Network Shown in Figure 115 76 74 72 70 SFDR (dBFS) 2.5× 11752-341 50 1.5× 60 11752-632 200 68 66 64 62 6.5× 7.5× 8.5× 60 58 1304.3 1408.3 1512.3 1616.3 1720.3 1824.3 1928.3 INPUT FREQUENCY (MHz) 11752-633 AD9680-1250, AD9680-1000, AND AD9680-820 SFDR (dBFS) IAVDD3 (mA) 250 Figure 120. Buffer Current Sweeps, AD9680-1250 (SFDR vs. IBUFF); 1300 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 115 Figure 121, Figure 122, and Figure 123 show the SFDR vs. analog input frequency for various buffer settings for the AD9680-1000. The recommended settings shown in Table 10 were used to take the data while changing the contents of Register 0x018 only. 90 85 2.5× 3.5× 4.5× 5.5× SFDR (dBFS) 80 75 75 70 65 70 60 60 10.3 55 50 10 147.3 212.3 290.3 355.3 433.3 511.3 589.3 667.3 INPUT FREQUENCY (MHz) Figure 118. Buffer Current Sweeps, AD9680-1250 (SFDR vs. IBUFF); fIN < 500 MHz; Front-End Network Shown in Figure 115 Rev. E | Page 38 of 105 1.5× 3.0× 4.5× 60 110 160 210 260 310 360 410 460 ANALOG INPUT FREQUENCY (MHz) Figure 121. Buffer Current Sweeps, AD9680-1000 (SFDR vs. IBUFF); fIN < 500 MHz; Front-End Network Shown in Figure 115 11752-170 65 11752-631 SFDR (dBFS) 80 85 Data Sheet AD9680 85 Figure 125, Figure 126, and Figure 127 show the SFDR vs. analog input frequency for various buffer settings for the AD9680-820. The recommended settings shown in Table 10 were used to take the data while changing the contents of Register 0x018 only. 4.0× 5.0× 6.0× 80 75 SFDR (dBFS) 70 65 95 60 90 55 85 50 SFDR (dBFS) 80 677.6 851.9 1200.5 1026.2 1374.8 ANALOG INPUT FREQUENCY (MHz) 75 70 65 Figure 122. Buffer Current Sweeps, AD9680-1000 (SFDR vs. IBUFF); 500 MHz < fIN < 1500 MHz; Front-End Network Shown in Figure 115 1.5× 2.0× 3.0× 4.5× 60 80 55 75 450.3 420.3 390.3 360.3 340.7 330.3 301.3 270.3 240.3 210.5 180.3 170.3 150.3 95.3 125.4 70 65.5 10.3 50 11752-523 40 503.4 11752-172 45 Figure 125. Buffer Current Sweeps, AD9680-820 (SFDR vs. IBUFF); fIN < 500 MHz; Front-End Network Shown in Figure 115 60 85 55 80 50 1.65GHz 1.52GHz 1.76GHz 1.95GHz 1.9GHz 70 65 65 55 –3 1.52GHz 1.65GHz 1.76GHz 1.9GHz 1.95GHz INPUT LEVEL (dBFS) 55 –1 11752-524 1022.3 985.3 Figure 126. Buffer Current Sweeps, AD9680-820 (SFDR vs. IBUFF); 500 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 115 60 –2 810.3 ANALOG INPUT FREQUENCY (MHz) 75 70 60 50 11752-174 SFDR (dBFS) 75 80 55 SNR (dBc) 80 3.5× 4.5× 5.5× 6.5× 7.5× 60 766.3 In certain high frequency applications, the SFDR can be improved by reducing the full-scale setting, as shown in Table 10. At high frequencies, the performance of the ADC core is limited by jitter. The SFDR can be improved by backing off of the full scale level. Figure 124 shows the SFDR and SNR vs. full-scale input level at different high frequencies for the AD9680-1000. 65 610.3 Figure 123. Buffer Current Sweeps, AD9680-1000 (SFDR vs. IBUFF); 1500 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 115 70 515.3 1889.8 510.3 1795.6 480.3 1701.5 ANALOG INPUT FREQUENCY (MHz) 420.3 1607.4 SFDR (dBFS) 40 1513.4 75 11752-173 45 4.5× 5.5× 6.5× 7.5× 8.5× 450.3 SFDR (dBFS) ANALOG INPUT FREQUENCY (MHz) 65 Figure 124. SNR/SFDR vs. Analog Input Level vs. Input Frequencies, AD9680-1000 Rev. E | Page 39 of 105 AD9680 Data Sheet 95 80 6.5× 7.5× 8.5× 75 90 85 SFDR (dBFS) 65 75 60 11752-525 1950.3 1920.3 1810.3 1720.3 1600.3 1510.3 1420.3 1315.3 1205.3 1110.3 1022.3 65 450.3 ANALOG INPUT FREQUENCY (MHz) Figure 127. Buffer Current Sweeps, AD9680-820 (SFDR vs. IBUFF); 1000 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 115 Figure 128, Figure 129, and Figure 130 show the SFDR vs. analog input frequency for various buffer settings for the AD9680-500. The recommended settings shown in Table 10 were used to take the data while changing the contents of Register 0x018 only. 480.3 510.3 515.3 610.3 765.3 810.3 985.3 ANALOG INPUT FREQUENCY (MHz) Figure 129. Buffer Current Sweeps, AD9680-500 (SFDR vs. IBUFF); 450 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 115 80 75 SFDR (dBFS) 70 100 90 65 60 55 50 80 45 70 40 1010.3 4.0× 5.0× 6.0× 7.0× 8.0× 1205.3 1410.3 1600.3 1810.3 1950.3 ANALOG INPUT FREQUENCY (MHz) 60 Figure 130. Buffer Current Sweeps, AD9680-500 (SFDR vs. IBUFF); 1 GHz < fIN < 2 GHz; Front-End Network Shown in Figure 115 50 30 10.3 1.0× 1.5× 2.0× 3.0× 4.5× 95.3 150.3 180.3 240.3 301.3 340.7 390.3 ANALOG INPUT FREQUENCY (MHz) 450.3 11752-145 40 11752-175 70 55 SFDR (dBFS) 80 Figure 128. Buffer Current Sweeps, AD9680-500 (SFDR vs. IBUFF); fIN < 500 MHz; Front-End Network Shown in Figure 115 Buffer Control 1 (0x018) = 1.0×, 1.5×, 2.0×, 3.0×, or 4.5× Rev. E | Page 40 of 105 11752-176 SFDR (dBFS) 70 50 4.0× 5.0× 6.0× 7.0× 8.0× Data Sheet AD9680 Table 10. Recommended Register Settings for SFDR Optimization at Different Input Frequencies Product AD9680500 AD9680820 AD96801000 AD96801250 Buffer Control 1 (0x018)— Buffer Current Control Buffer Control 2 (0x019)— Buffer Bias Setting Buffer Control 3 (0x01A)— Buffer Bias Setting Buffer Control 4 (0x11A)— High Frequency Setting Buffer Control 5 (0x935)— Low Frequency Setting 0x20 (2.0×) 0x70 (4.5×) 0x80 (5.0×) 0xF0 (8.5×) 0x60 (Setting 3) 0x60 (Setting 3) 0x40 (Setting 1) 0x40 (Setting 1) 0x0A (Setting 3) 0x0A (Setting 3) 0x08 (Setting 1) 0x08 (Setting 1) 0x00 (off) 0x04 (on) 0x00 (off) 0x04 (on) 0x00 (off) 0x00 (off) 0x00 (off) 0x00 (off) DC to 200 MHz DC to 410 MHz 500 MHz to 1 GHz 1 GHz to 2 GHz 0x10 (1.5×) 0x40 (3.0×) 0x80 (5.0×) 0xF0 (8.5×) 0x40 (Setting 1) 0x40 (Setting 1) 0x40 (Setting 1) 0x40 (Setting 1) 0x09 (Setting 2) 0x09 (Setting 2) 0x08 (Setting 1) 0x08 (Setting 1) 0x00 (off) 0x04 (on) 0x00 (off) 0x04 (on) 0x00 (off) 0x00 (off) 0x00 (off) 0x00 (off) DC to 150 MHz 0x10 (1.5×) 0x50 (Setting 2) 0x09 (Setting 2) 0x00 (off) 0x04 (on) DC to 500 MHz 0x40 (3.0×) 0x50 (Setting 2) 0x09 (Setting 2) 0x00 (off) 500 MHz to 1 GHz 1 GHz to 2 GHz DC to 625 MHz >625 MHz 0xA0 (6.0×) 0xD0 (7.5×) 0x50 (3.5×) 0xA0 (6.0×) 0x60 (Setting 3) 0x70 (Setting 4) 0x50 (Setting 2) 0x50 (Setting 2) 0x09 (Setting 2) 0x09 (Setting 2) 0x09 (Setting 2) 0x09 (Setting 2) Frequency DC to 250 MHz 250 MHz to 500 MHz 500 MHz to 1 GHz 1 GHz to 2 GHz Input FullScale Control (0x030) Input Termination (0x016) 1 Input Capacitance (0x934) 0x0C (2.06 V p-p) 0x0C (2.06 V p-p) 0x08 (1.46 V p-p) 0x08 (1.46 V p-p) 0x04 0x0C/0x1C/… 0x1F 0x04 0x0C/0x1C/… 0x1F 0x18 0x0C/0x1C/… 0x18 0x0C/0x1C/… 0x1F or 0x00 2 0x1F or 0x001 0x0A (1.70 V p-p) 0x0A (1.70 V p-p) 0x08 (1.46 V p-p) 0x08 (1.46 V p-p) 0x14 0x0C/0x1C/… 0x1F 0x14 0x0C/0x1C/… 0x1F 0x18 0x0C/0x1C/… 0x1F or 0x002 0x18 0x0C/0x1C/… 0x1F or 0x001 0x0A (1.70 V p-p) 0x18 0x0E/0x1E/… 0x1F 0x04 (on) 0x0A (1.70 V p-p) 0x18 0x0E/0x1E/… 0x1F 0x20 (on) 0x00 (off) 0x18 0x0E/0x1E/… 0x1F or 0x001 0x20 (on) 0x00 (off) 0x18 0x0E/0x1E/… 0x1F or 0x001 0x00 (off) 0x04 (on) 0x18 0x0E/0x1E/… 0x1F N/A 3 0x00 (off) 0x08 (1.46 V p-p) 0x08 (1.46 V p-p) 0x0A (1.58 V p-p) 0x08 (1.46 V p-p) 0x18 0x0E/0x1E/… 0x1F or 0x001 Input Full-Scale Range (0x025) The input termination can be changed to accommodate the application with little or no impact to ac performance. The input capacitance can be set to 1.5 pF to achieve wider input bandwidth but results in slightly lower ac performance. 3 N/A means not applicable. 1 2 Rev. E | Page 41 of 105 AD9680 Data Sheet The absolute maximum input swing allowed at the inputs of the AD9680 is 4.3 V p-p differential. Signals operating near or at this level can cause permanent damage to the ADC. VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9680. This internal 1.0 V reference is used to set the fullscale input range of the ADC. The full-scale input range can be adjusted via the ADC Function Register 0x025. For more information on adjusting the input swing, see Table 39. Figure 131 shows the block diagram of the internal 1.0 V reference controls. the reference voltage. For more information on adjusting the full-scale level of the AD9680, refer to the Memory Map Register Table section. The use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 132 shows the typical drift characteristics of the internal 1.0 V reference. 1.0010 1.0009 1.0008 1.0007 V_1P0 VOLTAGE (V) Absolute Maximum Input Swing VIN+A/ VIN+B VIN–A/ VIN–B ADC CORE FULL-SCALE VOLTAGE ADJUST 1.0004 1.0003 1.0002 1.0001 1.0000 V_1P0 0.9998 –50 25 90 Figure 132. Typical V_1P0 Drift 11752-031 V_1P0 PIN CONTROL SPI REGISTER (0x025, 0x02, AND 0x024) Figure 131. Internal Reference Configuration and Controls The SPI Register 0x024 enables the user to either use this internal 1.0 V reference, or to provide an external 1.0 V reference. When using an external voltage reference, provide a 1.0 V reference. The full-scale adjustment is made using the SPI, irrespective of The external reference must be a stable 1.0 V reference. The ADR130 is a good option for providing the 1.0 V reference. Figure 133 shows how the ADR130 can be used to provide the external 1.0 V reference to the AD9680. The grayed out areas show unused blocks within the AD9680 while using the ADR130 to provide the external reference. INTERNAL V_1P0 GENERATOR ADR130 FULL-SCALE VOLTAGE ADJUST NC 6 1 NC 2 GND SET 5 3 VIN 0.1µF 0 TEMPERATURE (°C) 11752-106 0.9999 INPUT FULL-SCALE RANGE ADJUST SPI REGISTER (0x025, 0x02, AND 0x024) INPUT 1.0005 VOUT 4 V_1P0 0.1µF FULL-SCALE CONTROL Figure 133. External Reference Using ADR130 Rev. E | Page 42 of 105 11752-032 INTERNAL V_1P0 GENERATOR 1.0006 Data Sheet AD9680 CLOCK INPUT CONSIDERATIONS Input Clock Divider For optimum performance, drive the AD9680 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or clock drivers. These pins are biased internally and require no additional biasing. The AD9680 contains an input clock divider with the ability to divide the Nyquist input clock by 1, 2, 4, and 8. The divider ratios can be selected using Register 0x10B. This is shown in Figure 137. Figure 134 shows a preferred method for clocking the AD9680. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. 0.1µF 1:1Z CLK+ 100Ω 50Ω CLK+ ADC CLK– CLK– 11752-035 0.1µF ÷2 ÷4 ÷8 Figure 134. Transformer-Coupled Differential Clock Another option is to ac couple a differential CML or LVDS signal to the sample clock input pins, as shown in Figure 135 and Figure 136. REG 0x10B Figure 137. Clock Divider Circuit The AD9680 clock divider can be synchronized using the external SYSREF± input. A valid SYSREF± causes the clock divider to reset to a programmable state. This synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. See the Memory Map section for more information. 3.3V 71Ω 10pF 33Ω 33Ω Z0 = 50Ω 0.1µF ADC Z0 = 50Ω 0.1µF 11752-036 CLK+ CLK– Input Clock Divider ½ Period Delay Adjust Figure 135. Differential CML Sample Clock LVDS DRIVER 100Ω 50Ω1 50Ω1 ADC CLK– CLK– Clock Fine Delay Adjust 0.1µF RESISTORS ARE OPTIONAL. 11752-037 0.1µF 150Ω CLK+ CLK+ CLOCK INPUT The input clock divider inside the AD9680 provides phase delay in increments of ½ the input clock cycle. Register 0x10C can be programmed to enable this delay independently for each channel. Changing this register does not affect the stability of the JESD204B link. 0.1µF 0.1µF CLOCK INPUT 11752-038 CLOCK INPUT The maximum frequency at the CLK± inputs is 4 GHz. This is the limit of the divider. In applications where the clock input is a multiple of the sample clock, care must be taken to program the appropriate divider ratio into the clock divider before applying the clock signal. This ensures that the current transients during device startup are controlled. Figure 136. Differential LVDS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. In applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock can be supplied to the device. The AD9680 can be clocked at 2 GHz with the internal clock divider set to 2. The output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal ADC. See the Memory Map section for more details on using this feature. The AD9680 sampling edge instant can be adjusted by writing to Register 0x117 and Register 0x118. Setting Bit 0 of Register 0x117 enables the feature, and Bits[7:0] of Register 0x118 set the value of the delay. This value can be programmed individually for each channel. The clock delay can be adjusted from −151.7 ps to +150 ps in ~1.7 ps increments. The clock delay adjust takes effect immediately when it is enabled via SPI writes. Enabling the clock fine delay adjust in Register 0x117 causes a datapath reset. However, the contents of Register 0x118 can be changed without affecting the stability of the JESD204B link. Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by Rev. E | Page 43 of 105 SNR = 20 × log 10 (2 × π × fA × tJ) AD9680 Data Sheet In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. Power-Down/Standby Mode IF undersampling applications are particularly sensitive to jitter (see Figure 138). 130 12.5fS 25fS 50fS 100fS 200fS 400fS 800fS 120 110 100 In standby mode, the JESD204B link is not disrupted and transmits zeros for all converter samples. This can be changed using Register 0x571, Bit 7 to select /K/ characters. 80 Temperature Diode 70 The AD9680 contains a diode-based temperature sensor for measuring the temperature of the die. This diode can output a voltage and serve as a coarse temperature sensor to monitor the internal die temperature. 60 50 30 10 100 1000 10000 ANALOG INPUT FREQUENCY (MHz) 11752-039 40 Figure 138. Ideal SNR vs. Input Frequency and Jitter Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9680. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. If the clock is generated from another type of source (by gating, dividing, or other methods), retime the clock by the original clock at the last step. Refer to the AN-501 Application Note and the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs. Figure 139 shows the estimated SNR of the AD9680-1000 across input frequency for different clock induced jitter values. The SNR can be estimated by using the following equation:  − SNR JITTER     − SNR ADC    SNR (dBFS) = 10log 10 10  + 10 10       The temperature diode voltage can be output to the FD_A pin using the SPI. Use Register 0x028, Bit 0 to enable or disable the diode. Register 0x028 is a local register. Channel A must be selected in the device index register (0x008) to enable the temperature diode readout. Configure the FD_A pin to output the diode voltage by programming Register 0x040[2:0]. See Table 39 for more information. The voltage response of the temperature diode (SPIVDD = 1.8 V) is shown in Figure 140. 0.90 0.85 DIODE VOLTAGE (V) SNR (dB) 90 The AD9680 has a PDWN/STBY pin that can be used to configure the device in power-down or standby mode. The default operation is PDWN. The PDWN/STBY pin is a logic high pin. When in power-down mode, the JESD204B link is disrupted. The power-down option can also be set via Register 0x03F and Register 0x040. 0.80 0.75 0.70 0.65 0.60 –55 –45 –35 –25 –15 –5 65 5 15 25 35 45 55 65 75 85 95 105 115 125 TEMPERATURE (°C) 55 50 45 10 25fs 50fs 75fs 100f s 125f s 150f s 175f s 200f s 100 1K INPUT FREQUENCY (MHz) 10K 11752-526 SNR (dBFS) Figure 140. Temperature Diode Voltage vs. Temperature 60 Figure 139. Estimated SNR Degradation for the AD9680-1000 vs. Input Frequency and RMS Jitter Rev. E | Page 44 of 105 11752-353 70 Data Sheet AD9680 ADC OVERRANGE AND FAST DETECT The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 141. In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overrange bit in the JESD204B outputs provides information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, the latency of this function is of major concern. Highly pipelined converters can have significant latency. The AD9680 contains fast detect circuitry for individual channels to monitor the threshold and assert the FD_A and FD_B pins. The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located at Register 0x247 and Register 0x248. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 28 clock cycles (maximum). The approximate upper threshold magnitude is defined by Upper Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) ADC OVERRANGE The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, located at Register 0x249 and Register 0x24A. The fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency, but is accurate in terms of converter resolution. The lower threshold magnitude is defined by The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange indicator can be embedded within the JESD204B link as a control bit (when CSB > 0). The latency of this overrange indicator matches the sample latency. The AD9680 also records any overrange condition in any of the eight virtual converters. For more information on the virtual converters, refer to Figure 146. The overrange status of each virtual converter is registered as a sticky bit in Register 0x563. The contents of Register 0x563 can be cleared using Register 0x562, by toggling the bits corresponding to the virtual converter to set and reset position. Lower Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) For example, to set an upper threshold of −6 dBFS, write 0xFFF to Register 0x247 and Register 0x248. To set a lower threshold of −10 dBFS, write 0xA1D to Register 0x249 and Register 0x24A. FAST THRESHOLD DETECTION (FD_A AND FD_B) The FD bit is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit is only cleared when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. This feature provides hysteresis and prevents the FD bit from excessively toggling. The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located at Register 0x24B and Register 0x24C. See the Memory Map section (Register 0x040, and Register 0x245 to Register 0x24C in Table 39) for more details. UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD DWELL TIME FD_A OR FD_B Figure 141. Threshold Settings for FD_A and FD_B Signals Rev. E | Page 45 of 105 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 11752-040 MIDSCALE LOWER THRESHOLD AD9680 Data Sheet SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The results of the signal monitor block can be obtained either by reading back the internal values from the SPI port or by embedding the signal monitoring information into the JESD204B interface as special control bits. A global, 24-bit programmable period controls the duration of the measurement. Figure 142 shows the simplified block diagram of the signal monitor block. FROM MEMORY MAP SIGNAL MONITOR PERIOD REGISTER (SMPR) 0x271, 0x272, 0x273 DOWN COUNTER IS COUNT = 1? FROM INPUT LOAD LOAD SIGNAL MONITOR HOLDING REGISTER TO SPORT OVER JESD204B AND MEMORY MAP 11752-087 CLEAR COMPARE A>B Figure 142. Signal Monitor Block The peak detector captures the largest signal within the observation period. The detector only observes the magnitude of the signal. The resolution of the peak detector is a 13-bit value, and the observation period is 24 bits and represents converter output samples. The peak magnitude can be derived by using the following equation: The magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal monitor period register (SMPR). The peak detector function is enabled by setting Bit 1 of Register 0x270 in the signal monitor control register. The 24-bit SMPR must be programmed before activating this mode. After enabling peak detection mode, the value in the SMPR is loaded into a monitor period timer, which decrements at the decimated clock rate. The magnitude of the input signal is compared with the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. LOAD MAGNITUDE STORAGE REGISTER Peak Magnitude (dBFS) = 20log(Peak Detector Value/213) When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the SPORT over the JESD204B interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown restarts. In addition, the magnitude of the first input sample is updated in the magnitude storage register, and the comparison and update procedure, as explained previously, continues. Rev. E | Page 46 of 105 Data Sheet AD9680 SPORT OVER JESD204B is to be inserted (CS = 1), only the most significant control bit is used (see Example Configuration 1 and Example Configuration 2 in Figure 143). To select the SPORT over JESD204B option, program Register 0x559, Register 0x55A, and Register 0x58F. See Table 39 for more information on setting these bits. The signal monitor data can also be serialized and sent over the JESD204B interface as control bits. These control bits must be deserialized from the samples to reconstruct the statistical data. The signal control monitor function is enabled by setting Bits[1:0] of Register 0x279 and Bit 1 of Register 0x27A. Figure 143 shows two different example configurations for the signal monitor control bit locations inside the JESD204B samples. A maximum of three control bits can be inserted into the JESD204B samples; however, only one control bit is required for the signal monitor. Control bits are inserted from MSB to LSB. If only one control bit Figure 144 shows the 25-bit frame data that encapsulates the peak detector value. The frame data is transmitted MSB first with five 5-bit subframes. Each subframe contains a start bit that can be used by a receiver to validate the deserialized data. Figure 145 shows the SPORT over JESD204B signal monitor data with a monitor period timer set to 80 samples. 16-BIT JESD204B SAMPLE SIZE (N' = 16) EXAMPLE CONFIGURATION 1 (N' = 16, N = 15, CS = 1) 1-BIT CONTROL BIT (CS = 1) 15-BIT CONVERTER RESOLUTION (N = 15) 15 S[14] X 14 S[13] X 13 S[12] X 12 S[11] X 11 10 S[10] X 9 S[9] X 8 S[8] X 7 S[7] X 6 S[6] X 5 S[5] X 4 S[4] X S[3] X 3 S[2] X 2 S[1] X 1 0 S[0] X CTRL [BIT 2] X SERIALIZED SIGNAL MONITOR FRAME DATA 16-BIT JESD204B SAMPLE SIZE (N' = 16) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S[13] X S[12] X S[11] X S[10] X S[9] X S[8] X S[7] X S[6] X S[5] X S[4] X S[3] X S[2] X S[1] X S[0] X CTRL [BIT 2] X TAIL X SERIALIZED SIGNAL MONITOR FRAME DATA Figure 143. Signal Monitor Control Bit Locations 5-BIT SUB-FRAMES 5-BIT IDLE SUB-FRAME (OPTIONAL) 25-BIT FRAME IDLE 1 IDLE 1 IDLE 1 IDLE 1 IDLE 1 5-BIT IDENTIFIER START 0 SUB-FRAME ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 5-BIT DATA MSB SUB-FRAME START 0 P[12] P[11] P[10] P[9] 5-BIT DATA SUB-FRAME START 0 P[8] P[7] P[6] P5] 5-BIT DATA SUB-FRAME START 0 P[4] P[3] P[2] P1] 5-BIT DATA LSB SUB-FRAME START 0 P[0] 0 0 0 P[] = PEAK MAGNITUDE VALUE 11752-089 EXAMPLE CONFIGURATION 2 (N' = 16, N = 14, CS = 1) Figure 144. SPORT over JESD204B Signal Monitor Frame Data Rev. E | Page 47 of 105 11752-088 1 CONTROL 1 TAIL BIT BIT (CS = 1) 14-BIT CONVERTER RESOLUTION (N = 14) AD9680 Data Sheet SMPR = 80 SAMPLES (0x271 = 0x50; 0x272 = 0x00; 0x273 = 0x00) 80 SAMPLE PERIOD PAYLOAD #3 25-BIT FRAME (N) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD PAYLOAD #3 25-BIT FRAME (N + 1) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE Figure 145. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples Rev. E | Page 48 of 105 11752-090 PAYLOAD #3 25-BIT FRAME (N + 2) Data Sheet AD9680 DIGITAL DOWNCONVERTER (DDC) The AD9680 includes four digital downconverters (DDC 0 to DDC 3) that provide filtering and reduce the output data rate. This digital processing section includes an NCO, a half-band decimating filter, an FIR filter, a gain stage, and a complex-real conversion stage. Each of these processing blocks has control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverter can be configured to output either real data or complex output data. The Chip Q ignore bit (Bit 5) in the chip application mode register (Register 0x200) controls the chip output muxing of all the DDC channels. When all DDC channels use real outputs, this bit must be set high to ignore all DDC Q output ports. When any of the DDC channels are set to use complex I/Q outputs, the user must clear this bit to use both DDC Output Port I and DDC Output Port Q. For more information, see Figure 154. The DDCs output a 16-bit stream. To enable this operation, the converter number of bits, N, is set to a default value of 16, even though the analog core only outputs 14 bits. In full bandwidth operation, the ADC outputs are the 14-bit word followed by two zeros, unless the tail bits are enabled. DDC GENERAL DESCRIPTION DDC I/Q INPUT SELECTION The AD9680 has two ADC channels and four DDC channels. Each DDC channel has two input ports that can be paired to support both real or complex inputs through the I/Q crossbar mux. For real signals, both DDC input ports must select the same ADC channel (for example, DDC Input Port I = ADC Channel A, and Input Port Q = ADC Channel A). For complex signals, each DDC input port must select different ADC channels (for example, DDC Input Port I = ADC Channel A, and Input Port Q = ADC Channel B). The inputs to each DDC are controlled by the DDC input selection registers (Register 0x311, Register 0x331, Register 0x351, and Register 0x371). See Table 39 for information on how to configure the DDCs. DDC I/Q OUTPUT SELECTION Each DDC channel has two output ports that can be paired to support both real or complex outputs. For real output signals, only the DDC Output Port I is used (the DDC Output Port Q is invalid). For complex I/Q output signals, both DDC Output Port I and DDC Output Port Q are used. The I/Q outputs to each DDC channel are controlled by the DDC complex to real enable bit (Bit 3) in the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). The four DDC blocks are used to extract a portion of the full digital spectrum captured by the ADC(s). They are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. Each DDC block contains the following signal processing stages. Frequency Translation Stage (Optional) The frequency translation stage consists of a 12-bit complex NCO and quadrature mixers that can be used for frequency translation of both real or complex input signals. This stage shifts a portion of the available digital spectrum down to baseband. Filtering Stage After shifting down to baseband, the filtering stage decimates the frequency spectrum using a chain of up to four half-band low-pass filters for rate conversion. The decimation process lowers the output data rate, which in turn reduces the output interface rate. Gain Stage (Optional) Due to losses associated with mixing a real input signal down to baseband, the gain stage compensates by adding an additional 0 dB or 6 dB of gain. Complex to Real Conversion Stage (Optional) When real outputs are necessary, the complex to real conversion stage converts the complex outputs back to real by performing an fS/4 mixing operation plus a filter to remove the complex component of the signal. Figure 146 shows the detailed block diagram of the DDCs implemented in the AD9680. Rev. E | Page 49 of 105 AD9680 Data Sheet REAL/I ADC SAMPLING AT fS COMPLEX TO REAL CONVERSION (OPTIONAL) HB1 FIR DCM = 2 GAIN = 0dB OR 6dB REAL/Q Q HB2 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 I HB4 FIR DCM = BYPASS OR 2 DDC 0 REAL/I REAL/I CONVERTER 0 Q CONVERTER 1 SYSREF± COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) Q CONVERTER 3 REAL/Q Q ADC SAMPLING AT fS HB1 FIR DCM = 2 I HB2 FIR DCM = BYPASS OR 2 REAL/I HB3 FIR DCM = BYPASS OR 2 DDC 2 REAL/I CONVERTER 4 OUTPUT INTERFACE GAIN = 0dB OR 6dB GAIN = 0dB OR 6dB GAIN = 0dB OR 6dB HB1 FIR DCM = 2 REAL/I CONVERTER 2 SYSREF± NCO + MIXER (OPTIONAL) REAL/Q HB2 FIR DCM = BYPASS OR 2 REAL/Q Q HB3 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB4 FIR DCM = BYPASS OR 2 I/Q CROSSBAR MUX I HB4 FIR DCM = BYPASS OR 2 DDC 1 REAL/I Q CONVERTER 5 SYSREF± SYSREF SYNCHRONIZATION CONTROL CIRCUITS HB1 FIR DCM = 2 REAL/I CONVERTER 6 Q CONVERTER 7 11752-041 REAL/Q Q HB2 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 I HB4 FIR DCM = BYPASS OR 2 DDC 3 REAL/I SYSREF± Figure 146. DDC Detailed Block Diagram Figure 147 shows an example usage of one of the four DDC blocks with a real input signal and four half-band filters (HB4, HB3, HB2, and HB1). It shows both complex (decimate by 16) and real (decimate by 8) output options. the chip decimation ratio sample rate. Whenever the NCO frequency is set or changed, the DDC soft reset must be issued. If the DDC soft reset is not issued, the output may potentially show amplitude variations. When DDCs have different decimation ratios, the chip decimation ratio (Register 0x201) must be set to the lowest decimation ratio of all the DDC blocks. In this scenario, samples of higher decimation ratio DDCs are repeated to match Table 11, Table 12, Table 13, Table 14, and Table 15 show the DDC samples when the chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively. Rev. E | Page 50 of 105 Data Sheet AD9680 ADC ADC SAMPLING AT fS REAL REAL INPUT—SAMPLED AT fS BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 REAL BANDWIDTH OF INTEREST fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 FREQUENCY TRANSLATION STAGE (OPTIONAL) DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) fS/2 fS/3 fS/4 fS/8 I NCO TUNES CENTER OF BANDWIDTH OF INTEREST TO BASEBAND cos(ωt) REAL 12-BIT NCO 90° 0° –sin(ωt) Q DIGITAL FILTER RESPONSE –fS/2 –fS/3 –fS/4 fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 BANDWIDTH OF INTEREST IMAGE (–6dB LOSS DUE TO NCO + MIXER) BANDWIDTH OF INTEREST (–6dB LOSS DUE TO NCO + MIXER) fS/8 fS/4 fS/3 fS/2 FILTERING STAGE HB4 FIR 4 DIGITAL HALF-BAND FILTERS (HB4 + HB3 + HB2 + HB1) I HALFBAND FILTER Q HALFBAND FILTER HB3 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB4 FIR HB2 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB3 FIR HB1 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB2 FIR I HB1 FIR Q 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS COMPLEX (I/Q) OUTPUTS GAIN STAGE (OPTIONAL) DIGITAL FILTER RESPONSE I GAIN STAGE (OPTIONAL) Q 0dB OR 6dB GAIN COMPLEX TO REAL CONVERSION STAGE (OPTIONAL) fS/4 MIXING + COMPLEX FILTER TO REMOVE Q –fS/32 fS/32 DC –fS/16 fS/16 –fS/8 I REAL (I) OUTPUTS +6dB +6dB fS/8 2 +6dB 2 +6dB I Q fS/32 –fS/32 DC –fS/16 fS/16 DOWNSAMPLE BY 2 I DECIMATE BY 8 Q DECIMATE BY 16 0dB OR 6dB GAIN Q COMPLEX REAL/I TO REAL –fS/8 fS/32 –fS/32 DC –fS/16 fS/16 fS/8 Figure 147. DDC Theory of Operation Example (Real Input—Decimate by 16) Rev. E | Page 51 of 105 11752-042 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS AD9680 Data Sheet Table 11. DDC Samples, Chip Decimation Ratio = 1 Real (I) Output (Complex to Real Enabled) HB1 FIR (DCM 1 = 1) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 N + 24 N + 25 N + 26 N + 27 N + 28 N + 29 N + 30 N + 31 1 HB2 FIR + HB1 FIR (DCM1 = 2) N N+1 N N+1 N+2 N+3 N+2 N+3 N+4 N+5 N+4 N+5 N+6 N+7 N+6 N+7 N+8 N+9 N+8 N+9 N + 10 N + 11 N + 10 N + 11 N + 12 N + 13 N + 12 N + 13 N + 14 N + 15 N + 14 N + 15 HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 4) N N+1 N N+1 N N+1 N N+1 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+4 N+5 N+4 N+5 N+4 N+5 N+4 N+5 N+6 N+7 N+6 N+7 N+6 N+7 N+6 N+7 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 HB1 FIR (DCM1 = 2) N N+1 N N+1 N+2 N+3 N+2 N+3 N+4 N+5 N+4 N+5 N+6 N+7 N+6 N+7 N+8 N+9 N+8 N+9 N + 10 N + 11 N + 10 N + 11 N + 12 N + 13 N + 12 N + 13 N + 14 N + 15 N + 14 N + 15 DCM means decimation. Rev. E | Page 52 of 105 HB2 FIR + HB1 FIR (DCM1 = 4) N N+1 N N+1 N N+1 N N+1 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+4 N+5 N+4 N+5 N+4 N+5 N+4 N+5 N+6 N+7 N+6 N+7 N+6 N+7 N+6 N+7 HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 Data Sheet AD9680 Table 12. DDC Samples, Chip Decimation Ratio = 2 Real (I) Output (Complex to Real Enabled) HB2 FIR + HB1 FIR (DCM 1 = 2) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 1 HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 4) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) N N+1 N N+1 N N N+1 N+1 N+2 N N+3 N+2 N+1 N N+3 N+1 N+4 N+2 N+5 N+3 N+4 N+2 N+5 N+6 N+3 N+2 N+7 N+3 N+6 N+2 N+7 N+3 Complex (I/Q) Outputs (Complex to Real Disabled) HB1 FIR (DCM1 = 2) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 HB2 FIR + HB1 FIR (DCM1 = 4) HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N+1 N N+1 N N+1 N N N N+1 N+1 N+1 N+2 N N N+3 N+2 N+1 N N+1 N N+3 N+1 N+1 N+4 N+2 N N+5 N+3 N+1 N+4 N+2 N N+5 N+6 N+3 N+2 N+1 N N+7 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 DCM means decimation. Table 13. DDC Samples, Chip Decimation Ratio = 4 Real (I) Output (Complex to Real Enabled) HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 4) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 1 HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) N N+1 N N+1 N+2 N+3 N+2 N+3 Complex (I/Q) Outputs (Complex to Real Disabled) HB2 FIR + HB1 FIR (DCM1 = 4) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N N+1 N+1 N N N+1 N+1 N+2 N+3 N N+1 N+2 N N+3 N+1 DCM means decimation. Table 14. DDC Samples, Chip Decimation Ratio = 8 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8) N N+1 N+2 N+3 N+4 Complex (I/Q) Outputs (Complex to Real Disabled) HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) N N+1 N+2 N+3 N+4 Rev. E | Page 53 of 105 HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N+1 N N+1 N+2 AD9680 Data Sheet Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled) HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) N+5 N+6 N+7 HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8) N+5 N+6 N+7 1 HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N+3 N+2 N+3 DCM means decimation. Table 15. DDC Samples, Chip Decimation Ratio = 16 Real (I) Output (Complex to Real Enabled) Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 16) Not applicable Not applicable Not applicable Not applicable HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N+1 N+2 N+3 1 DCM means decimation. If the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs decimate by 4), and DDC 1 is set to use HB4 + HB3 + HB2 + HB1 filters (real outputs decimate by 8), then DDC 1 repeats its output data two times for every one DDC 0 output. The resulting output samples are shown in Table 16. Table 16. DDC Output Samples when Chip DCM 1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real) DDC 0 DDC Input Samples N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 1 Output Port I I0 [N] DDC 1 Output Port Q Q0 [N] Output Port I I1 [N] Output Port Q Not applicable I0 [N + 1] Q0 [N + 1] I1 [N + 1] Not applicable I0 [N + 2] Q0 [N + 2] I1 [N] Not applicable I0 [N + 3] Q0 [N + 3] I1 [N + 1] Not applicable DCM means decimation. Rev. E | Page 54 of 105 Data Sheet AD9680 FREQUENCY TRANSLATION FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode Frequency translation is accomplished by using a 12-bit complex NCO along with a digital quadrature mixer. The frequency translation translates either a real or complex input signal from an intermediate frequency (IF) to a baseband complex digital output (carrier frequency = 0 Hz). NCO and mixers are enabled. NCO output frequency can be used to digitally tune the IF frequency. 0 Hz IF (ZIF) Mode Mixers are bypassed and the NCO is disabled. fS/4 Hz IF Mode The frequency translation stage of each DDC can be controlled individually and supports four different IF modes using Bits[5:4] of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). These IF modes are Test Mode Variable IF mode 0 Hz IF (ZIF) mode fS/4 Hz IF mode Test mode Input samples are forced to 0.999 to positive full scale. NCO is enabled. This test mode allows the NCOs to directly drive the decimation filters. Figure 148 and Figure 149 show examples of the frequency translation stage for both real and complex inputs. NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 I ADC + DIGITAL MIXER + NCO REAL INPUT—SAMPLED AT fS REAL cos(ωt) ADC SAMPLING AT fS REAL 12-BIT NCO 90° 0° COMPLEX –sin(ωt) Q BANDWIDTH OF INTEREST BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 –fS/8 fS/32 –fS/32 DC –fS/16 fS/16 fS/8 fS/4 fS/3 fS/2 –6dB LOSS DUE TO NCO + MIXER 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 DC fS/32 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = –1365 (0xAAB) –fS/32 NEGATIVE FTW VALUES DC fS/32 Figure 148. DDC NCO Frequency Tuning Word Selection—Real Inputs Rev. E | Page 55 of 105 11752-043 • • • • Mixers and NCO are enabled in special down mixing by fS/4 mode to save power. AD9680 Data Sheet NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 QUADRATURE ANALOG MIXER + 2 ADCs + QUADRATURE DIGITAL REAL MIXER + NCO COMPLEX INPUT—SAMPLED AT fS QUADRATURE MIXER ADC SAMPLING AT fS I + I I Q Q 90° PHASE 12-BIT NCO 90° 0° Q Q ADC SAMPLING AT fS Q Q I I – –sin(ωt) I I + COMPLEX Q + BANDWIDTH OF INTEREST IMAGE DUE TO ANALOG I/Q MISMATCH –fS/3 –fS/4 –fS/32 fS/32 fS/16 –fS/16 DC –fS/8 fS/8 fS/4 fS/3 fS/2 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 fS/32 11752-044 –fS/2 DC Figure 149. DDC NCO Frequency Tuning Word Selection—Complex Inputs DDC NCO PLUS MIXER LOSS AND SFDR When mixing a real input signal down to baseband, 6 dB of loss is introduced in the signal due to filtering of the negative image. An additional 0.05 dB of loss is introduced by the NCO. The total loss of a real input signal mixed down to baseband is 6.05 dB. For this reason, it is recommended that the user compensate for this loss by enabling the additional 6 dB of gain in the gain stage of the DDC to recenter the dynamic range of the signal within the full scale of the output bits. When mixing a complex input signal down to baseband, the maximum value each I/Q sample can reach is 1.414 × full scale after it passes through the complex mixer. To avoid overrange of the I/Q samples and to keep the data bit widths aligned with real mixing, 3.06 dB of loss (0.707 × full scale) is introduced in the mixer for complex signals. An additional 0.05 dB of loss is introduced by the NCO. The total loss of a complex input signal mixed down to baseband is −3.11 dB. The worst case spurious signal from the NCO is greater than 102 dBc SFDR for all output frequencies. NUMERICALLY CONTROLLED OSCILLATOR The AD9680 has a 12-bit NCO for each DDC that enables the frequency translation process. The NCO allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. The NCO can be set up by providing a frequency tuning word (FTW) and a phase offset word (POW). Setting Up the NCO FTW and POW The NCO frequency value is given by the 12-bit twos complement number entered in the NCO FTW. Frequencies between −fS/2 and fS/2 (fS/2 excluded) are represented using the following frequency words: • • • 0x800 represents a frequency of –fS/2. 0x000 represents dc (frequency is 0 Hz). 0x7FF represents a frequency of +fS/2 – fS/212. The NCO frequency tuning word can be calculated using the following equation:  Mod( fC , f S )   NCO _ FTW = round 212  fS   where: NCO_FTW is a 12-bit twos complement number representing the NCO FTW. fS is the AD9680 sampling frequency (clock rate) in Hz. fC is the desired carrier frequency in Hz. Mod( ) is a remainder function. For example, Mod(110,100) = 10, and for negative numbers, Mod(–32, 10) = –2. round( ) is a rounding function. For example, round(3.6) = 4, and for negative numbers, round(–3.4)= –3. Rev. E | Page 56 of 105 Data Sheet AD9680 Note that this equation applies to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). For example, if the ADC sampling frequency (fS) is 1250 MSPS and the carrier frequency (fC) is 416.667 MHz, in the Setting Up the NCO FTW and POW section. The phase increment value of each PAW is determined by the FTW. Two methods can be used to synchronize multiple PAWs within the chip: •  Mod(416.667,1250  NCO _ FTW = round 212  = 1365 MHz 1250   This, in turn, converts to 0x555 in the 12-bit twos complement representation for NCO_FTW. The actual carrier frequency can be calculated based on the following equation: NCO _ FTW × f S fC − actual = = 416.56 MHz 212 • A 12-bit POW is available for each NCO to create a known phase relationship between multiple AD9680 chips or individual DDC channels inside one AD9680. The following procedure must be followed to update the FTW and/or POW registers to ensure proper operation of the NCO: • • • Write to the FTW registers for all the DDCs. Write to the POW registers for all the DDCs. Synchronize the NCOs either through the DDC soft reset bit accessible through the SPI, or through the assertion of the SYSREF± pin. Note that the NCOs must be synchronized either through SPI or through the SYSREF± pin after all writes to the FTW or POW registers have completed. This synchronization is necessary to ensure the proper operation of the NCO. NCO Synchronization Each NCO contains a separate phase accumulator word (PAW) that determines the instantaneous phase of the NCO. The initial reset value of each PAW is determined by the POW described Using the SPI. The DDC NCO soft reset bit in the DDC synchronization control register (Register 0x300, Bit 4) can be used to reset all the PAWs in the chip. This is accomplished by toggling the DDC NCO soft reset bit. This method can only be used to synchronize DDC channels within the same AD9680 chip. Using the SYSREF± pin. When the SYSREF± pin is enabled in the SYSREF± control registers (Register 0x120 and Register 0x121), and the DDC synchronization is enabled in Bits[1:0] in the DDC synchronization control register (Register 0x300), any subsequent SYSREF± event resets all the PAWs in the chip. This method can be used to synchronize DDC channels within the same AD9680 chip, or DDC channels within separate AD9680 chips. Mixer The NCO is accompanied by a mixer, whose operation is similar to an analog quadrature mixer. The mixer performs the downconversion of input signals (real or complex) by using the NCO frequency as a local oscillator. For real input signals, this mixer performs a real mixer operation (with two multipliers). For complex input signals, the mixer performs a complex mixer operation (with four multipliers and two adders). The mixer adjusts its operation based on the input signal (real or complex) provided to each individual channel. The selection of real or complex inputs can be controlled individually for each DDC block by using Bit 7 of the DDC control register (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). Rev. E | Page 57 of 105 AD9680 Data Sheet FIR FILTERS FIR FILTERS GENERAL DESCRIPTION Table 17 shows the different bandwidth options by including different half-band filters. In all cases, the DDC filtering stage of the AD9680 provides less than −0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection. There are four sets of decimate-by-2, low-pass, half-band, finite impulse response (FIR) filters (HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR, shown in Figure 146). These filters follow the frequency translation stage. After the carrier of interest is tuned down to dc (carrier frequency = 0 Hz), these filters efficiently lower the sample rate while providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. Table 18 shows the amount of stop-band alias rejection for multiple pass-band ripple/cutoff points. The decimation ratio of the filtering stage of each DDC can be controlled individually through Bits[1:0] of the DDC control registers (0x310, 0x330, 0x350, and 0x370). HB1 FIR is always enabled and cannot be bypassed. The HB2, HB3, and HB4 FIR filters are optional and can be bypassed for higher output sample rates. Table 17. DDC Filter Characteristics Real Output ADC Sample Rate (MSPS) 1250 1000 820 500 1 Complex (I/Q) Output Decimation Ratio 1 Output Sample Rate (MSPS) 1250 Decimation Ratio 2 HB1 + HB2 2 625 4 HB1 + HB2 + HB3 HB1 + HB2 + HB3 + HB4 HB1 4 312.5 8 8 156.25 16 1 1000 2 HB1 + HB2 2 500 4 HB1 + HB2 + HB3 HB1 + HB2 + HB3 + HB4 HB1 4 250 8 8 125 16 1 820 2 HB1 + HB2 2 410 4 HB1 + HB2 + HB3 HB1 + HB2 + HB3 + HB4 HB1 4 205 8 8 102.5 16 1 500 2 HB1 + HB2 2 250 4 HB1 + HB2 + HB3 HB1 + HB2 + HB3 + HB4 4 125 8 8 62.5 16 Half Band Filter Selection HB1 Output Sample Rate (MSPS) 625 (I) + 625 (Q) 312.5 (I) + 312.5 (Q) 156.25 (I) + 156.25 (Q) 78.125 (I) + 78.125 (Q) 500 (I) + 500 (Q) 250 (I) + 250 (Q) 125 (I) + 125 (Q) 62.5 (I) + 62.5 (Q) 410 (I) + 410 (Q) 205 (I) + 205 (Q) 102.5 (I) + 102.5 (Q) 51.25 (I) + 51.25 (Q) 250 (I) + 250 (Q) 125 (I) + 125 (Q) 62.5 (I) + 62.5 (Q) 31.25 (I) + 31.25 (Q) Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)). Rev. E | Page 58 of 105 Alias Protected Bandwidth (MHz) 481.25 Ideal SNR Improvement (dB) 1 1 240.62 4 120.31 7 60.15 10 385.0 1 192.5 4 96.3 7 48.1 10 315.7 1 157.8 4 78.9 7 39.4 10 192.5 1 96.3 4 48.1 7 24.1 10 PassBand Ripple (dB) 100 Data Sheet AD9680 Table 18. DDC Filter Alias Rejection Alias Rejection (dB) >100 90 85 63.3 25 19.3 10.7 1 Pass-Band Ripple/ Cutoff Point (dB)