AD9683BCPZRL7-250

FEATURES FUNCTIONAL BLOCK DIAGRAM JESD204B Subclass 0 or Subclass 1 coded serial digital outputs Signal-to-noise ratio (SNR) = 70.6 dBFS at 185 MHz AIN and 250 MSPS Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS Total power consumption: 434 mW at 250 MSPS 1.8 V supply voltages Integer 1-to-8 input clock divider Sample rates of up to 250 MSPS Intermediate frequency (IF) sampling frequencies of up to 400 MHz Internal analog-to-digital converter (ADC) voltage reference Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal) ADC clock duty cycle stabilizer (DCS) Serial port control Energy saving power-down modes AVDD DRVDD DVDD AGND DGND DRGND AD9683 JESD204B INTERFACE VIN+ VIN– PIPELINE 14-BIT ADC HIGH SPEED SERIALIZERS CML, TX OUTPUTS SERDOUT0± VCM CMOS DIGITAL INPUT CONTROL REGISTERS SYSREF± SYNCINB± CLK± RFCLK PDWN CLOCK GENERATION CMOS DIGITAL INPUT/OUTPUT RST FAST DETECT SDIO SCLK CS CMOS DIGITAL OUTPUT FD 11410-001 Data Sheet 14-Bit, 170 MSPS/250 MSPS, JESD204B, Analog-to-Digital Converter AD9683 Figure 1. GENERAL DESCRIPTION APPLICATIONS Communications Diversity radio systems Multimode digital receivers (3G) TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Smart antenna systems Electronic test and measurement equipment Radar receivers COMSEC radio architectures IED detection/jamming systems General-purpose software radios Broadband data applications Ultrasound equipment Rev. D The AD9683 is a 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9683 supports communications applications where low cost, small size, wide bandwidth, and versatility are desired. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC core features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device. The ADC output data is routed directly to the JESD204B serial output lane. These outputs are at CML voltage levels. Data can be sent through the lane at the maximum sampling rate of 250 MSPS, which results in a lane rate of 5 Gbps. Synchronization inputs (SYNCINB± and SYSREF±) are provided. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9683 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation and Standby Mode .................................... 23 Applications ....................................................................................... 1 Digital Outputs ............................................................................... 24 Functional Block Diagram .............................................................. 1 JESD204B Transmit Top Level Description............................ 24 General Description ......................................................................... 1 ADC Overrange and Gain Control.......................................... 29 Revision History ............................................................................... 2 DC Correction (DCC) ................................................................... 31 Product Highlights ........................................................................... 3 DC Correction Bandwidth........................................................ 31 Specifications..................................................................................... 4 DC Correction Readback .......................................................... 31 ADC DC Specifications ............................................................... 4 DC Correction Freeze ................................................................ 31 ADC AC Specifications ............................................................... 5 DC Correction Enable Bits ....................................................... 31 Digital Specifications ................................................................... 6 Serial Port Interface (SPI) .............................................................. 32 Switching Specifications .............................................................. 8 Configuration Using the SPI ..................................................... 32 Timing Specifications .................................................................. 9 Hardware Interface..................................................................... 32 Absolute Maximum Ratings.......................................................... 10 SPI Accessible Features .............................................................. 33 Thermal Characteristics ............................................................ 10 Memory Map .................................................................................. 34 ESD Caution ................................................................................ 10 Reading the Memory Map Register Table............................... 34 Pin Configuration and Function Descriptions ........................... 11 Memory Map Register Table ..................................................... 35 Typical Performance Characteristics ........................................... 13 Memory Map Register Descriptions ........................................ 39 Equivalent Circuits ......................................................................... 18 Applications Information .............................................................. 43 Theory of Operation ...................................................................... 19 Design Guidelines ...................................................................... 43 ADC Architecture ...................................................................... 19 Outline Dimensions ....................................................................... 44 Analog Input Considerations.................................................... 19 Ordering Guide .......................................................................... 44 Voltage Reference ....................................................................... 20 Clock Input Considerations ...................................................... 21 REVISION HISTORY 6/2016—Rev. C to Rev.D Changes to Table 17 ........................................................................ 37 Change to JESD204B Link Control 1 (Address 0x5F) Section ....... 40 9/2015—Rev. B to Rev. C Changes to General Description Section ...................................... 3 Changes to Nyquist Clock Input Options Section ..................... 21 Changes to JESD204B Overview Section .................................... 24 Changes to Figure 60 ...................................................................... 27 Change to Table 17 ......................................................................... 37 5/2014—Rev. A to Rev. B Changed Minimum RF Clock Rate from 625 MHz to 500 MHz (Throughout) .................................................................................... 6 Changes to SYNCINB+ Pin Description .................................... 11 Changes to Transfer Register Map Section ................................. 34 Changes to Register 0x3A ............................................................. 36 Changes to Register 0x6F, Register 0x70, Register 0x72, Register 0x73, Register 0x74, Register 0x75 ................................ 38 Changes to JESD204B Link Control 2 (Address 0x60) Section..... 40 2/2014—Rev. 0 to Rev. A Changes to Data Output Parameters, Table 4 ................................8 Changes to Figure 3 ...........................................................................9 4/2013—Revision 0: Initial Version Rev. D | Page 2 of 44 Data Sheet AD9683 Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported via the dedicated fast detect pins. Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. The AD9683 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. Integrated 14-bit, 170 MSPS/250 MSPS ADC. 2. The configurable JESD204B output block supports lane rates up to 5 Gbps. 3. An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock. 4. Support for an optional radio frequency (RF) clock input to ease system board design. 5. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz. 6. Operation from a single 1.8 V power supply. 7. Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, overrange fast detection, and serial output configuration. Rev. D | Page 3 of 44 AD9683 Data Sheet SPECIFICATIONS ADC DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, duty cycle stabilizer enabled, default SPI, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL)1 TEMPERATURE DRIFT Offset Error Gain Error INPUT REFERRED NOISE VREF = 1.75 V ANALOG INPUT Input Span Input Capacitance2 Input Resistance3 Input Common-Mode Voltage POWER SUPPLIES Supply Voltage AVDD DRVDD DVDD Supply Current IAVDD IDRVDD + IDVDD POWER CONSUMPTION Sine Wave Input Standby Power4 Power-Down Power5 Temperature Full Min 14 Full Full Full Full 25°C Full 25°C AD9683-170 Typ Max Min 14 Guaranteed AD9683-250 Typ Max Unit Bits Guaranteed ±0.8 ±1.5 mV %FSR LSB LSB LSB LSB Full Full ±7 ±13 ±7 ±39 ppm/°C ppm/°C 25°C 1.38 1.42 LSB rms Full Full Full Full 1.75 2.5 20 0.9 1.75 2.5 20 0.9 V p-p pF kΩ V Full Full Full ±9 −6.6/−0.3 ±0.8 ±9 −5.3/+1.2 ±0.75 ±0.5 ±0.5 ±1.6 1.7 1.7 1.7 1.8 1.8 1.8 1.9 1.9 1.9 Full Full 135 68 Full Full Full 365 221 9 ±2.7 1.7 1.7 1.7 1.8 1.8 1.8 1.9 1.9 1.9 V V V 151 73 149 92 163 97 mA mA 403 434 266 9 468 mW mW mW Measured with a low input frequency, full-scale sine wave. Input capacitance refers to the effective capacitance between one differential input pin and its complement. 3 Input resistance refers to the effective resistance between one differential input pin and its complement. 4 Standby power is measured with a low input frequency, full-scale sine wave, and the CLK± pins active. Address 0x08 is set to 0x20, and the PDWN pin is asserted. 5 Power-down power is measured with a low input frequency, a full-scale sine wave, RFCLK pulled high, and the CLK± pins active. Address 0x08 is set to 0x00, and the PDWN pin is asserted. 1 2 Rev. D | Page 4 of 44 Data Sheet AD9683 ADC AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, default SPI, unless otherwise noted. Table 2. Parameter1 SIGNAL-TO-NOISE-RATIO (SNR) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz WORST SECOND OR THIRD HARMONIC fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 30 MHz fIN = 90 MHz fIN = 140 MHz fIN = 185 MHz fIN = 220 MHz Temperature 25°C 25°C Full 25°C 25°C Full 25°C 25°C 25°C Full 25°C 25°C Full 25°C Min AD9683-170 Typ Max Min AD9683-250 Typ Max 72.3 72.0 72.1 71.7 71.3 70.5 71.3 70.6 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 71 70.0 70.0 70.0 71.3 70.8 70.9 70.6 70.2 69.5 70.1 69.5 Unit 68.8 68.7 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 25°C 25°C 25°C 25°C 25°C 11.5 11.5 11.4 11.3 11.1 11.5 11.4 11.4 11.3 11.1 Bits Bits Bits Bits Bits 25°C 25°C Full 25°C 25°C Full 25°C 94 89 87 86 94 89 87 88 dBc dBc dBc dBc dBc dBc dBc 69.9 68.7 81 80 87 86 25°C 25°C Full 25°C 25°C Full 25°C −94 −89 −87 −86 25°C 25°C Full 25°C 25°C Full 25°C Rev. D | Page 5 of 44 −81 −94 −89 −87 −88 −87 −86 −99 −92 −95 −94 −80 −83 −96 −94 −94 −93 −82 −95 −92 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc AD9683 Parameter1 TWO-TONE SFDR fIN1 = 184.12 MHz (−7 dBFS), fIN2 = 187.12 MHz (−7 dBFS) FULL POWER BANDWIDTH2 1 2 Data Sheet Temperature 25°C 25°C Min AD9683-170 Typ Max Min AD9683-250 Typ Max 87 1000 87 1000 Unit dBc MHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation for a complete set of definitions. Full power bandwidth is the bandwidth of operation determined by where the spectral power of the fundamental frequency is reduced by 3 dB. DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, default SPI, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Input CLK± Clock Rate Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current Low Level Input Current Input Capacitance Input Resistance RF CLOCK INPUT (RFCLK) RF Clock Rate Logic Compliance Internal Bias Input Voltage Range High Input Voltage Level Low Input Voltage Level High Level Input Current Low Level Input Current Input Capacitance Input Resistance (AC-Coupled) SYNCIN INPUTS (SYNCINB+/SYNCINB−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Range Input Voltage Range Input Common-Mode Range High Level Input Current Low Level Input Current Input Capacitance Input Resistance Temperature Min Full 40 Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Rev. D | Page 6 of 44 Typ Max Unit 625 MHz CMOS/LVDS/LVPECL 0.9 0.3 AGND 0.9 0 −60 8 12 V V p-p V V µA µA pF kΩ 1500 MHz 3.6 AVDD 1.4 +60 0 4 10 500 CMOS/LVDS/LVPECL 0.9 AGND 1.2 AGND 0 −150 8 AVDD AVDD 0.6 +150 0 1 10 12 CMOS/LVDS 0.9 0.3 DGND 0.9 −5 −10 12 3.6 DVDD 1.4 +5 +10 1 16 20 V V V V µA µA pF kΩ V V p-p V V µA µA pF kΩ Data Sheet Parameter SYSREF INPUTS (SYSREF+/SYSREF−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Range Input Voltage Range Input Common-Mode Range High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (RST)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (SCLK, PDWN, CS2)3 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SDIO)3 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS (SERDOUT0+/SERDOUT0−) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) DIGITAL OUTPUTS (SDIO/FD4) High Level Output Voltage (VOH) IOH = 50 µA IOH = 0.5 mA IOH = 2.0 mA Low Level Output Voltage (VOL) IOL = 2.0 mA IOL = 1.6 mA IOL = 50 µA AD9683 Temperature Min Typ Max Unit LVDS Full Full Full Full Full Full Full Full 0.9 0.3 AGND 0.9 −5 −10 8 Full Full Full Full Full Full 1.22 0 −5 −100 Full Full Full Full Full Full 1.22 0 45 −10 Full Full Full Full Full Full 1.22 0 45 −10 Full Full 400 0.75 Full Full Full 1.79 1.75 1.6 Full Full Full Pull-up. Needs an external pull-up. Pull-down. 4 Compatible with JEDEC standard JESD8-7A. 1 2 3 Rev. D | Page 7 of 44 3.6 AVDD 1.4 +5 +10 4 10 12 2.1 0.6 +5 −45 V V µA µA kΩ pF 2.1 0.6 100 +10 V V µA µA kΩ pF 2.1 0.6 100 +10 V V µA µA kΩ pF 750 1.05 mV V 26 2 26 2 26 5 CML 600 DRVDD/2 V V p-p V V µA µA pF kΩ V V V 0.25 0.2 0.05 V V V AD9683 Data Sheet SWITCHING SPECIFICATIONS Table 4. Parameter CLOCK INPUT PARAMETERS Conversion Rate1 SYSREF± Setup Time to Rising Edge CLK±2 SYSREF± Hold Time from Rising Edge CLK±2 SYSREF± Setup Time to Rising Edge RFCLK±2 SYSREF± Hold Time from Rising Edge RFCLK±2 CLK± Pulse Width High Divide-by-1 Mode, DCS Enabled Divide-by-1 Mode, DCS Disabled Divide-by-2 Mode Through Divide-by-8 Mode Aperture Delay Aperture Uncertainty (Jitter) DATA OUTPUT PARAMETERS Data Output Period or Unit Interval (UI) Data Output Duty Cycle Data Valid Time PLL Lock Time Wake-Up Time Standby ADC (Power-Down)3 Output (Power-Down)4 Subclass 0: SYNCINB± Falling Edge to First Valid K.28 Characters (Delay Required for Rx CGS Start) Subclass 1: SYSREF± Rising Edge to First Valid K.28 Characters (Delay Required for SYNCINB± Rising Edge/Rx CGS Start) CGS Phase K.28 Characters Duration Pipeline Delay JESD204B (Latency) Fast Detect (Latency) Lane Rate Uncorrelated Bounded High Probability (UBHP) Jitter Random Jitter At 3.4 Gbps At 5 Gbps Output Rise/Fall Time Differential Termination Resistance Out-of-Range Recovery Time AD9683-170 Min Typ Max AD9683-250 Min Typ Max Full Full Full Full Full 40 40 2.61 2.76 0.8 tA tJ Full Full Full Full Full tLOCK Symbol Temperature fS tREFS tREFH tREFSRF tREFHRF tCH 170 300 40 400 0 2.9 2.9 250 MSPS ps ps ps ps 2.2 2.1 300 40 400 0 1.0 0.16 1.0 0.16 ns ns ns ns ps rms Full 25°C 25°C 25°C 20 × fS 50 0.82 25 20 × fS 50 0.78 25 Seconds % UI µs 25°C 25°C 25°C Full 10 250 50 10 250 50 5 5 µs µs µs Multiframes Full 6 6 Multiframes Full 1 1 Multiframe Full Full Full Full 36 7 3.4 10 Full Full Full 25°C Full 2.4 3.19 3.05 1.8 1.9 0.8 36 7 2 Rev. D | Page 8 of 44 12 Cycles5 Cycles5 Gbps ps 1.7 60 100 3 ps rms ps rms ps Ω Cycles5 5 60 100 3 Conversion rate is the clock rate after the divider. Refer to Figure 3 for timing diagram. 3 Wake-up time ADC is defined as the time required for the ADC to return to normal operation from power-down mode. 4 Wake-up time output is defined as the time required for JESD204B output to return to normal operation from power-down mode. 5 Cycles refers to ADC conversion rate cycles. 1 2.0 2.0 Unit 5 Data Sheet AD9683 TIMING SPECIFICATIONS Table 5. Parameter SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO Test Conditions/Comments See Figure 67 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CS and SCLK Hold time between CS and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in figures) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in figures) Time required after hard or soft reset until SPI access is available (not shown in figures) tDIS_SDIO tSPI_RST Min Typ Max Unit 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns 500 µs Timing Diagrams SAMPLE N N – 36 N+1 N – 35 ANALOG INPUT SIGNAL N – 34 N–1 N – 33 CLK– CLK+ CLK– CLK+ SAMPLE N – 36 ENCODED INTO 2 8B/10B SYMBOLS 11410-002 SERDOUT0± SAMPLE N – 34 ENCODED INTO 2 8B/10B SYMBOLS SAMPLE N – 35 ENCODED INTO 2 8B/10B SYMBOLS Figure 2. Data Output Timing RFCLK CLK– CLK+ SYSREF– tREFS tREFSRF tREFH tREFHRF 11410-003 SYSREF+ NOTES 1. CLOCK INPUT IS EITHER RFCLK OR CLK±, NOT BOTH. Figure 3. SYSREF± Setup and Hold Timing (Clock Input Either RFCLK or CLK±, Not Both) Rev. D | Page 9 of 44 AD9683 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD to AGND DRVDD to DRGND DVDD to DGND VIN+, VIN− to AGND CLK+, CLK− to AGND RFCLK to AGND VCM to AGND CS, PDWN to DGND SCLK to DGND SDIO to DGND RST to DGND FD to DGND SERDOUT0+, SERDOUT0− to AGND SYNCINB+, SYNCINB− to DGND SYSREF+, SYSREF− to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to AVDD + 0.3 V −40°C to +85°C The exposed pad must be soldered to the ground plane of the LFCSP. This increases the reliability of the solder joints, maximizing the thermal capability of the package. Table 7. Thermal Resistance Package Type 32-Lead LFCSP 5 mm × 5 mm (CP-32-12) θJA1, 2 37.1 32.4 29.1 θJC1, 3, 4 3.1 N/A N/A θJB1, 4, 5 20.7 N/A N/A Unit °C/W °C/W °C/W Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-STD-883, Method 1012.1. 4 N/A = not applicable. 5 Per JEDEC JESD51-8 (still air). 1 2 Typical θJA is specified for a 4-layer printed circuit board (PCB) with a solid ground plane. As shown in Table 7, airflow increases heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. ESD CAUTION 150°C Airflow Velocity (m/sec) 0 1.0 2.5 −65°C to +125°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. D | Page 10 of 44 Data Sheet AD9683 32 31 30 29 28 27 26 25 AVDD AVDD AVDD VIN+ VIN– AVDD AVDD VCM PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD9683 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 DNC PDWN CS SCLK SDIO FD DGND DVDD NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE GROUND REFERENCE FOR AVDD. THIS EXPOSED PAD MUST BE CONNECTED TO AGND FOR PROPER OPERATION. 11410-004 DGND DVDD SYNCINB+ SYNCINB– DRGND DRVDD SERDOUT0– SERDOUT0+ 9 10 11 12 13 14 15 16 RFCLK CLK– CLK+ AVDD SYSREF+ SYSREF– AVDD RST Figure 4. Pin Configuration (Top View) Table 8. Pin Function Descriptions Pin No. ADC Power Supplies 4, 7, 26, 27, 30, 31, 32 10, 17 9, 18 13 14 24 ADC Analog 1 2 3 25 28 29 ADC Fast Detect Output 19 Digital Inputs 5 6 11 12 Data Outputs 15 16 Mnemonic Type Description AVDD DVDD DGND DRGND DRVDD Supply Supply Ground Ground Supply DNC EPAD (AGND) Ground Analog Power Supply (1.8 V Nominal). Digital Power Supply (1.8 V Nominal). Ground Reference for DVDD. Ground Reference for DRVDD. JESD204B PHY Serial Output Driver Supply (1.8 V Nominal). Note that the DRVDD power is referenced to the AGND plane. Do Not Connect. Exposed Pad. The exposed thermal pad on the bottom of the package provides the ground reference for AVDD. This exposed pad must be connected to AGND for proper operation. RFCLK CLK− CLK+ VCM Input Input Input Output VIN− VIN+ Input Input ADC RF Clock Input. ADC Nyquist Clock Input—Complement. ADC Nyquist Clock Input—True. Common-Mode Level Bias Output for Analog Inputs. Decouple this pin to ground using a 0.1 µF capacitor. Differential Analog Input (−). Differential Analog Input (+). FD Output Fast Detect Indicator (CMOS Levels). SYSREF+ SYSREF− SYNCINB+ SYNCINB− Input Input Input Input JESD204B LVDS SYSREF Input—True. JESD204B LVDS SYSREF Input—Complement. JESD204B LVDS Sync Input—True/JESD204B CMOS Sync Input. JESD204B LVDS Sync Input—Complement. SERDOUT0− SERDOUT0+ Output Output CML Output Data—Complement. CML Output Data—True. Rev. D | Page 11 of 44 AD9683 Pin No. Device Under Test (DUT) Controls 8 20 21 22 23 Data Sheet Mnemonic Type Description RST SDIO SCLK CS PDWN Input Input/output Input Input Input Digital Reset (Active Low). SPI Serial Data Input/Output. SPI Serial Clock. SPI Chip Select (Active Low). This pin needs an external pull-up. Power-Down Input (Active High). The operation of this pin depends on SPI mode and can be configured as power-down or standby (see Table 17). Rev. D | Page 12 of 44 Data Sheet AD9683 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DRVDD = 1.8 V, DVDD = 1.8 V, maximum sample rate for speed grade, VIN = −1.0 dBFS, 1.75 V p-p differential input, DCS enabled, 16k sample, TA = 25°C, default SPI, unless otherwise noted. 0 0 170MSPS 90.1MHz AT –1.0dBFS SNR = 70.7dB (71.7dBFS) SFDR = 89dBc –20 –20 –40 AMPLITUDE (dBFS) –60 THIRD HARMONIC –80 SECOND HARMONIC –100 20 30 40 50 60 70 80 –100 –140 30 40 0 –20 –40 –40 AMPLITUDE (dBFS) 170MSPS 90.1MHz AT –1.0dBFS SNR = 71.1dB (72.1dBFS) –20 SFDR = 88dBc –60 THIRD HARMONIC SECOND HARMONIC –100 –120 50 60 70 80 170MSPS 305.1MHz AT –1.0dBFS SNR = 67.6dB (68.6dBFS) SFDR = 85dBc –60 THIRD HARMONIC SECOND HARMONIC –80 –100 10 20 30 40 50 60 70 80 –140 11410-006 0 40 50 60 70 80 SFDR (dBFS) SNR/SFDR (dBc AND dBFS) 100 –60 SECOND HARMONIC 30 120 –40 –80 20 Figure 9. AD9683-170 Single-Tone FFT with fIN = 305.1 MHz 170MSPS 185.1MHz AT –1.0dBFS SNR = 69.6dB (70.6 dBFS) SFDR = 90dBc –20 10 FREQUENCY (MHz) Figure 6. AD9683-170 Single-Tone FFT with fIN = 90.1 MHz, RFCLK = 680 MHz with Divide by 4 (Address 0x09 = 0x21) 0 0 11410-009 –120 FREQUENCY (MHz) THIRD HARMONIC –100 80 SNR (dBFS) 60 SFDR (dBc) 40 SNR (dBc) 20 –120 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) Figure 7. AD9683-170 Single-Tone FFT with fIN = 185.1 MHz 0 –100 11410-007 –140 20 10 Figure 8. AD9683-170 Single-Tone FFT with fIN = 185.1 MHz, RFCLK = 680 MHz with Divide by 4 (Address 0x09 = 0x21) 0 –80 0 FREQUENCY (MHz) Figure 5. AD9683-170 Single-Tone FFT with fIN = 90.1 MHz –140 SECOND HARMONIC 11410-008 10 11410-005 0 FREQUENCY (MHz) AMPLITUDE (dBFS) THIRD HARMONIC –80 –120 –120 AMPLITUDE (dBFS) –60 –90 –80 –70 –60 –50 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 0 11410-010 AMPLITUDE (dBFS) –40 –140 170MSPS 185.1MHz AT –1dBFS SNR = 70.1dB (71.1dBFS) SFDR = 84dBc Figure 10. AD9683-170 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 185.1 MHz Rev. D | Page 13 of 44 AD9683 Data Sheet 100 0 95 –20 SFDR/IMD3 (dBc AND dBFS) SNR (dBFS)/SFDR (dBc) SFDR (dBc) 90 85 80 75 SNR (dBFS) 70 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 65 80 115 150 185 220 255 290 325 360 395 430 465 500 FREQUENCY (MHz) 11410-011 45 –120 –90.0 –81.7 –73.4 –65.1 –56.8 –48.5 –40.2 –31.9 –23.6 –15.3 –7.0 Figure 11. AD9683-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN) INPUT AMPLITUDE (dBFS) Figure 14. AD9683-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 170 MSPS 0 100 170MSPS 89.12MHz AT –7dBFS 92.12MHz AT –7dBFS SFDR = 90dBc (97dBFS) –20 90 –40 SFDR (dBc) AMPLITUDE (dBFS) 85 80 75 SNR (dBFS) –60 –80 –100 70 –120 65 45 80 115 150 185 220 255 290 325 360 395 430 465 500 FREQUENCY (MHz) –140 11410-012 60 10 Figure 12. AD9683-170 Single-Tone SNR/SFDR vs. Input Frequency (fIN), RFCLK = 680 MHz with Divide by 4 (Address 0x09 = 0x21) 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) 11410-015 SNR (dBFS)/SFDR (dBc) 95 Figure 15. AD9683-170 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 170 MSPS 0 0 170MSPS 184.12MHz AT –7dBFS 187.12MHz AT –7dBFS SFDR = 87dBc (94dBFS) –20 –20 SFDR (dBc) –40 AMPLITUDE (dBFS) SFDR/IMD3 (dBc AND dBFS) 11410-014 IMD3 (dBFS) 60 10 –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 –60 –80 –100 –120 –78.5 –67.0 –55.5 –44.0 –32.5 INPUT AMPLITUDE (dBFS) –21.0 –9.5 Figure 13. AD9683-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 170 MSPS Rev. D | Page 14 of 44 –140 0 10 20 30 40 50 60 70 80 FREQUENCY (MHz) Figure 16. AD9683-170 Two-Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 170 MSPS 11410-016 –120 –90.0 11410-013 IMD3 (dBFS) Data Sheet AD9683 100 0 SFDR (dBc) 95 –40 AMPLITUDE (dBFS) 90 85 80 –60 THIRD HARMONIC –80 –100 75 –120 SNR (dBFS) 50 60 70 80 90 100 110 120 130 140 150 160 170 SAMPLE RATE (MSPS) –140 11410-017 70 40 SECOND HARMONIC 0 25 50 75 100 125 FREQUENCY (MHz) 11410-020 SNR (dBFS)/SFDR (dBc) 250MSPS 90.1MHz AT –1dBFS SNR = 71dB (72dBFS) SFDR = 89dBc –20 Figure 20. AD9683-250 Single-Tone FFT with fIN = 90.1 MHz, RFCLK = 1.0 GHz with Divide by 4 (Address 0x09 = 0x21) Figure 17. AD9683-170 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 90.1 MHz 0 700000 250MSPS 185.1MHz AT –1dBFS SNR = 69.5dB (70.5dBFS) –20 SFDR = 88dBc 2,097,152 TOTAL HITS 1.375 LSB rms 598772 600000 521038 –40 400000 AMPLITUDE (dBFS) NUMBER OF HITS 500000 384443 300000 278480 200000 –60 –80 THIRD HARMONIC SECOND HARMONIC –100 138113 100153 100000 –120 41248 638 N–5 24088 7601 2363 N–3 N–1 N+1 N+3 182 N+5 –140 OUTPUT CODE 0 100 125 0 250MSPS 185.1MHz AT –1dBFS SNR = 70dB (71dBFS) –20 SFDR = 85dBc –40 AMPLITUDE (dBFS) –40 –60 THIRD HARMONIC –80 SECOND HARMONIC –100 –60 THIRD HARMONIC –80 SECOND HARMONIC –100 –120 –140 0 25 50 75 100 125 FREQUENCY (MHz) –140 0 25 50 75 100 125 FREQUENCY (MHz) Figure 22. AD9683-250 Single-Tone FFT with fIN = 185.1 MHz, RFCLK = 1.0 GHz with Divide by 4 (Address 0x09 = 0x21) Figure 19. AD9683-250 Single-Tone FFT with fIN = 90.1 MHz Rev. D | Page 15 of 44 11410-022 –120 11410-019 AMPLITUDE (dBFS) 75 Figure 21. AD9683-250 Single-Tone FFT with fIN = 185.1 MHz 250MSPS 90.1MHz AT –1dBFS SNR = 71dB (72dBFS) SFDR = 89dBc –20 50 FREQUENCY (MHz) Figure 18. AD9683-170 Grounded Input Histogram 0 25 11410-021 N–7 28 11410-018 0 1 AD9683 Data Sheet 100 0 250MSPS 305.1MHz AT –1dBFS SNR = 67.5dB (68.5dBFS) SFDR = 85dBc 95 SFDR (dBc) SNR (dBFS)/SFDR (dBc) –20 –60 SECOND HARMONIC THIRD HARMONIC –80 –100 –120 85 80 75 SNR (dBFS) 70 65 0 25 50 75 100 125 FREQUENCY (MHz) 60 10 11410-023 –140 Figure 23. AD9683-250 Single-Tone FFT with fIN = 305.1 MHz 45 80 115 150 185 220 255 290 325 360 395 430 465 500 FREQUENCY (MHz) 11410-026 AMPLITUDE (dBFS) –40 90 Figure 26. AD9683-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN), RFCLK = 1.0 GHz with Divide by 4 (Address 0x09 = 0x21) 0 120 SFDR (dBFS) –20 80 SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBc AND dBFS) 100 SNR (dBFS) 60 SFDR (dBc) 40 SNR (dBc) SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 20 –80 –60 –70 –50 –40 –30 –20 –10 0 INPUT AMPLITUDE (dBFS) 11410-024 –90 –120 –90.0 –78.5 –67.0 –55.5 –44.0 –32.5 –21.0 –9.5 INPUT AMPLITUDE (dBFS) Figure 24. AD9683-250 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 185.1 MHz 11410-027 IMD3 (dBFS) 0 –100 Figure 27. AD9683-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS 0 100 95 –20 SFDR/IMD3 (dBc AND dBFS) SNR (dBFS)/SFDR (dBc) SFDR (dBc) 90 85 80 75 SNR (dBFS) 70 SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 65 80 115 150 185 220 255 290 325 360 395 430 465 500 FREQUENCY (MHz) 11410-025 45 –120 –90.0 Figure 25. AD9683-250 Single-Tone SNR/SFDR vs. Input Frequency (fIN) –78.5 –67.0 –55.5 –44.0 –32.5 INPUT AMPLITUDE (dBFS) –21.0 –9.5 11410-028 IMD3 (dBFS) 60 10 Figure 28. AD9683-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS Rev. D | Page 16 of 44 Data Sheet AD9683 100 0 250MSPS 89.12MHz AT –7dBFS 92.12MHz AT –7dBFS SFDR = 90dBc (97dBFS) SFDR (dBc) 95 SNR/SFDR (dBFS/dBc) –20 –60 –80 –100 90 85 80 75 –120 SNR (dBFS) 0 25 50 75 100 125 FREQUENCY (MHz) 70 40 11410-029 –140 80 100 120 140 160 180 200 240 220 SAMPLE RATE (MSPS) Figure 29. AD9683-250 Two-Tone FFT with fIN1 = 89.12 MHz, fIN2 = 92.12 MHz, fS = 250 MSPS Figure 31. AD9683-250 Single-Tone SNR/SFDR vs. Sample Rate (fS) with fIN = 90.1 MHz 0 700000 250MSPS 184.12MHz AT –7dBFS 187.12MHz AT –7dBFS SFDR = 87dBc (94dBFS) –20 60 11410-031 AMPLITUDE (dBFS) –40 2,097,152 TOTAL HITS 1.419 LSB rms 600000 581334 520772 500000 –60 –80 300000 200000 –120 100000 0 25 50 75 100 FREQUENCY (MHz) 125 11410-030 –100 –140 Figure 30. AD9683-250 Two-Tone FFT with fIN1 = 184.12 MHz, fIN2 = 187.12 MHz, fS = 250 MSPS 395507 400000 0 261252 181231 70369 4 N–7 161 2316 N–5 59901 15633 7965 N–3 N–1 N+1 N+3 658 N+5 OUTPUT CODE Figure 32. AD9683-250 Grounded Input Histogram Rev. D | Page 17 of 44 49 11410-032 NUMBER OF HITS AMPLITUDE (dBFS) –40 AD9683 Data Sheet EQUIVALENT CIRCUITS DVDD AVDD VIN 400Ω PDWN, SCLK, CS 11410-033 11410-038 30kΩ Figure 33. Equivalent Analog Input Circuit Figure 38. Equivalent PDWN, SCLK, or CS Input Circuit AVDD DVDD AVDD AVDD DVDD 0.9V 15kΩ DVDD 0.9V 15kΩ CLK+ 17kΩ CLK– 17kΩ SYNCINB+ 11410-039 11410-034 SYNCINB– Figure 34. Equivalent Clock lnput Circuit Figure 39. Equivalent SYNCINB± Input Circuit 0.5pF AVDD AVDD INTERNAL CLOCK DRIVER RFCLK AVDD AVDD 0.9V 10kΩ 17kΩ 17kΩ SYSREF– 11410-035 SYSREF+ 11410-040 BIAS CONTROL Figure 35. Equivalent RF Clock lnput Circuit Figure 40. Equivalent SYSREF± Input Circuit DRVDD DRVDD DRVDD DRVDD 3mA DRVDD 3mA RTERM RST VCM SERDOUT0± 3mA 11410-036 3mA 11410-041 SERDOUT0± 28kΩ 400Ω Figure 36. Digital CML Output Circuit Figure 41. Equivalent RST Input Circuit DVDD AVDD 400Ω 400Ω SDIO 11410-042 11410-037 31kΩ VCM Figure 37. Equivalent SDIO Circuit Figure 42. Equivalent VCM Circuit Rev. D | Page 18 of 44 Data Sheet AD9683 THEORY OF OPERATION The user can sample frequencies from dc to 400 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance. Operation above 400 MHz analog input is permitted but occurs at the expense of increased ADC noise and distortion. A synchronization capability is provided to allow synchronized timing between multiple devices. Programming and control of the AD9683 are accomplished using a 3-pin, SPI-compatible serial interface. ADC ARCHITECTURE The AD9683 architecture consists of a front-end, sample-andhold circuit, followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample, and the remaining stages to operate on the preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor digitalto-analog converter (DAC) and an interstage residue amplifier (MDAC). The MDAC magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The input stage contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended modes. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The output buffers are powered from a separate supply, allowing digital output noise to be separated from the analog core. ANALOG INPUT CONSIDERATIONS The analog input to the AD9683 is a differential, switched capacitor circuit that has been designed for optimum performance while processing a differential input signal. The clock signal alternatively switches the input between sample mode and hold mode (see the configuration shown in Figure 43). When the input is switched into sample mode, the signal source must be capable of charging the sampling capacitors and settling within 1/2 clock cycle. A small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. A shunt capacitor can be placed across the inputs to provide dynamic charging currents. This passive network creates a low-pass filter at the ADC input; therefore, the precise values are dependent on the application. In IF undersampling applications, reduce the shunt capacitors. In combination with the driving source impedance, the shunt capacitors limit the input bandwidth. Refer to the AN-742 Application Note, Frequency Domain Response of SwitchedCapacitor ADCs; the AN-827 Application Note, A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs; and the Analog Dialogue article, “Transformer-Coupled FrontEnd for Wideband A/D Converters,” for more information. BIAS S S CFB CS VIN+ CPAR1 CPAR2 S S H CS VIN– CPAR1 CPAR2 S CFB S BIAS 11410-043 The AD9683 has one analog input channel and one JESD204B output lane. The signal passes through several stages before appearing at the output port. Figure 43. Switched Capacitor Input For best dynamic performance, match the source impedances driving VIN+ and VIN− and differentially balance the inputs. Input Common Mode The analog inputs of the AD9683 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Configuring the input so that VCM = 0.5 × AVDD (or 0.9 V) is recommended for optimum performance. An on-board common-mode voltage reference is included in the design and is available from the VCM pin. Using the VCM output to set the input common mode is recommended. Optimum performance is achieved when the common-mode voltage of the analog input is set by the VCM pin voltage (typically 0.5 × AVDD). Decouple the VCM pin to ground by using a 0.1 µF capacitor, as described in the Applications Information section. Place this decoupling capacitor close to the pin to minimize the series resistance and inductance between the part and this capacitor. Differential Input Configurations Optimum performance is achieved while driving the AD9683 in a differential input configuration. For baseband applications, the AD8138, ADA4937-1, ADA4938-1, and ADA4930-1 differential drivers provide excellent performance and a flexible interface to the ADC. Rev. D | Page 19 of 44 AD9683 Data Sheet The output common-mode voltage of the ADA4930-1 is easily set with the VCM pin of the AD9683 (see Figure 44), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. Based on these parameters, the value of the input resistors and capacitors may need to be adjusted or some components may need to be removed. Table 9 displays recommended values to set the RC network for different input frequency ranges. However, these values are dependent on the input signal and bandwidth. Use these values only as a starting guide. Note that the values given in Table 9 are for the R1, R2, C1, C2, and R3 components shown in Figure 45 and Figure 46. 15pF 200Ω 15Ω 33Ω VIN– AVDD 5pF ADC ADA4930-1 0.1µF 33Ω 15Ω VCM VIN+ 120Ω Table 9. Example RC Network 15pF 33Ω 11410-044 200Ω 0.1µF Figure 44. Differential Input Configuration Using the ADA4930-1 For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 45. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. R2 VIN+ R1 2V p-p 49.9Ω R1 Series (Ω) 33 15 15 1000pF C1 VCM VIN– 165Ω VPOS 0.1µF 1µH 11410-045 33Ω R3 C2 Consider the signal characteristics when selecting a transformer. Most RF transformers saturate at frequencies below a few megahertz. Excessive signal power can also cause core saturation, which leads to distortion. R2 2V p-p P ADC 0.1µF R1 R2 R3 VIN– VCM 33Ω C2 0.1µF 11410-046 33Ω 165Ω 1nF 20kΩ║2.5pF 68nH A stable and accurate voltage reference is built into the AD9683. The full-scale input range can be adjusted by varying the reference voltage via the SPI. The input span of the ADC tracks the reference voltage changes linearly. VIN+ C1 0.1µF 301Ω VCM VOLTAGE REFERENCE 33Ω S 1nF ADC 3.9pF 180nH 220nH C2 R3 R1 0.1µF 5.1pF 15pF Figure 47. Differential Input Configuration Using the AD8375 At input frequencies in the second Nyquist zone and above, the noise performance of most amplifiers is not adequate to achieve the true SNR performance of the AD9683. For applications where SNR is a key parameter, differential double balun coupling is the recommended input configuration (see Figure 46). In this configuration, the input is ac-coupled and the VCM voltage is provided to each input through a 33 Ω resistor. These resistors compensate for losses in the input baluns to provide a 50 Ω impedance to the driver. S R3 Shunt (Ω) 24.9 24.9 24.9 1000pF NOTES 1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE EXCEPTION OF THE 1µH CHOKE INDUCTORS (COILCRAFT 0603LS). 2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER CENTERED AT 140MHz. Figure 45. Differential Transformer-Coupled Configuration PA C2 Shunt (pF) 15 8.2 ≤3.9 180nH 220nH 1µH R2 AD8375 0.1µF R2 Series (Ω) 0 0 0 ADC R1 0.1µF C1 Differential (pF) 8.2 8.2 ≤3.9 An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use an amplifier with variable gain. The AD8375 digital variable gain amplifier (DVGA) provides good performance for driving the AD9683. Figure 47 shows an example of the AD8375 driving the AD9683 through a band-pass antialiasing filter. C2 R3 Frequency Range (MHz) 0 to 100 100 to 400 >400 11410-047 90Ω 76.8Ω VIN Figure 46. Differential Double Balun Input Configuration Rev. D | Page 20 of 44 Data Sheet AD9683 CLOCK INPUT CONSIDERATIONS Mini-Circuits® ADT1-1WT, 1:1Z 390pF XFMR 390pF CLOCK INPUT ADC CLK+ 100Ω 50Ω 390pF CLK– 11410-049 The AD9683 has two options for deriving the input sampling clock: a differential Nyquist sampling clock input or an RF clock input (which is internally divided by 2 or 4). The clock input is selected in Address 0x09 and by default is configured for the Nyquist clock input. For optimum performance, clock the AD9683 Nyquist sample clock input, CLK+ and CLK−, with a differential signal. The signal is typically ac-coupled into the CLK+ and CLK− pins via a transformer or via capacitors. These pins are biased internally (see Figure 48) and require no external bias. If the clock inputs are floated, CLK− is pulled slightly lower than CLK+ to prevent spurious clocking. SCHOTTKY DIODES: HSMS2822 Figure 49. Transformer-Coupled Differential Clock (Up to 200 MHz) 25Ω CLOCK INPUT ADC 390pF 390pF CLK+ Nyquist Clock Input Options 390pF The Nyquist clock input pins, CLK+ and CLK−, are internally biased to 0.9 V and have a typical input impedance of 4 pF in parallel with 10 kΩ (see Figure 48). The input clock is typically ac-coupled to CLK+ and CLK−. Figure 49 through Figure 52 present some typical clock drive circuits for reference. 1nF CLK– 11410-050 The AD9683 Nyquist clock input supports a differential clock between 40 MHz and 625 MHz. The clock input structure supports differential input voltages from 0.3 V to 3.6 V and is therefore compatible with various logic family inputs such as CMOS, LVDS, and LVPECL. A sine wave input is also accepted, but higher slew rates typically provide optimal performance. Clock source jitter is a critical parameter that can affect performance, as described in the Jitter Considerations section. If the inputs are floated, pull the CLK− pin low to prevent spurious clocking. SCHOTTKY DIODES: HSMS2822 25Ω Figure 50. Balun-Coupled Differential Clock (Up to 625 MHz) In some cases, it is desirable to buffer or generate multiple clocks from a single source. In those cases, Analog Devices, Inc., offers clock drivers with excellent jitter performance. Figure 51 shows a typical PECL driver circuit that uses PECL drivers such as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516-0 through AD9516-5 device family, AD9517-0 through AD9517-4 device family, AD9518-0 through AD9518-4 device family, AD9520-0 through AD9520-5 device family, AD9522-0 through AD9522-5 device family, AD9523, AD9524, and ADCLK905/ADCLK907/ADCLK925. AVDD 0.1µF CLK+ AD95xx CLK– 0.1µF 11410-048 4pF 100Ω 0.1µF CLK– 50kΩ 240Ω 50kΩ 11410-051 CLOCK INPUT PECL DRIVER 240Ω Figure 51. Differential PECL Sample Clock (Up to 625 MHz) Figure 48. Equivalent Nyquist Clock Input Circuit For applications where a single-ended low jitter clock between 40 MHz and 200 MHz is available, an RF transformer is recommended. Figure 49 shows an example using an RF transformer in the clock network. At frequencies above 200 MHz, an RF balun is recommended, as seen in Figure 50. The back-toback Schottky diodes across the transformer secondary limit clock excursions into the AD9683 to approximately 0.8 V p-p differential. This limit helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9683, yet preserves the fast rise and fall times of the clock, which are critical to low jitter performance. Analog Devices also offers LVDS clock drivers with excellent jitter performance. A typical circuit is shown in Figure 52. It uses LVDS drivers such as the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515, AD9516-0 through AD9516-5 device family, AD9517-0 through AD9517-4 device family, AD9518-0 through AD9518-4 device family, AD9520-0 through AD9520-5 device family, AD9522-0 through AD9522-5 device family, AD9523, and AD9524. 0.1µF 0.1µF CLOCK INPUT ADC CLK+ AD95xx 0.1µF CLOCK INPUT LVDS DRIVER 100Ω 0.1µF CLK– 50kΩ 50kΩ Figure 52. Differential LVDS Sample Clock (Up to 625 MHz) Rev. D | Page 21 of 44 11410-052 CLK+ 4pF ADC 0.1µF CLOCK INPUT 0.9V AD9683 Data Sheet RF Clock Input Options The AD9683 RF clock input supports a single-ended clock between 500 MHz to 1.5 GHz. The equivalent RF clock input circuit is shown in Figure 53. The input is self biased to 0.9 V and is typically ac-coupled. The input has a typical input impedance of 10 kΩ in parallel with 0.5 pF at the RFCLK pin. divide ratios can be selected using Address 0x09 and Address 0x0B. Address 0x09 is used to set the RF clock input, and Address 0x0B can be used to set the divide ratio of the 1 to 8 divider for both the RF clock input and the Nyquist clock input. For divide ratios other than 1, the duty cycle stabilizer (DCS) is automatically enabled. 0.5pF RFCLK NYQUIST CLOCK 10kΩ Figure 55. Clock Divider Circuit 11410-053 BIAS CONTROL Figure 53. Equivalent RF Clock Input Circuit It is recommended that the RF clock input of the AD9683 be driven with a PECL or sine wave signal with a minimum signal amplitude of 600 mV p-p. Regardless of the type of signal being used, clock source jitter is of the most concern, as described in the Jitter Considerations section. Figure 54 shows the preferred method of clocking when using the RF clock input on the AD9683. It is recommended that a 50 Ω transmission line be used to route the clock signal to the RF clock input of the AD9683 due to the high frequency nature of the signal; terminate the transmission line close to the RF clock input. 0.1µF RFCLK 50Ω 11410-054 50Ω Tx LINE The AD9683 clock divider can be synchronized using the external SYSREF input. Bit 1 and Bit 2 of Address 0x3A allow the clock divider to be resynchronized on every SYSREF signal or only on the first signal after the register is written. A valid SYSREF causes the clock divider to reset to its initial state. This synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9683 contains a DCS that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD9683. ADC RF CLOCK INPUT 11410-055 ÷1 TO ÷8 DIVIDER INTERNAL CLOCK DRIVER RFCLK ÷2 OR ÷4 Figure 54. Typical RF Clock Input Circuit Figure 56 shows the RF clock input of the AD9683 being driven from the LVPECL outputs of the AD9515. The differential LVPECL output signal from the AD9515 is converted to a single-ended signal using an RF balun or RF transformer. The RF balun configuration is recommended for clock frequencies associated with the RF clock input. Input Clock Divider The AD9683 contains an input clock divider with the ability to divide the Nyquist input clock by integer values between 1 and 8. The RF clock input uses an on-chip predivider to divide the clock input by four before it reaches the 1 to 8 divider. This allows higher input frequencies to be achieved on the RF clock input. The Jitter on the rising edge of the input clock is still of paramount concern and is not reduced by the DCS. The duty cycle control loop does not function for clock rates of less than 40 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate can change dynamically. A wait time of 1.5 µs to 5 µs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time that the loop is not locked, the DCS loop is bypassed, and the internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the DCS. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. Rev. D | Page 22 of 44 Data Sheet AD9683 VDD 127Ω 0.1µF ADC 127Ω 50Ω Tx LINE 0.1µF 0.1µF RFCLK CLOCK INPUT AD9515 0.1µF 50Ω LVPECL DRIVER 0.1µF CLOCK INPUT 82.5Ω 11410-056 82.5Ω Figure 56. Differential PECL RF Clock Input Circuit POWER DISSIPATION AND STANDBY MODE SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 ( − SNRLF /10) ] In the equation, the rms aperture jitter represents the root-meansquare of all jitter sources, which include the clock input, the analog input signal, and the ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, as shown in Figure 57. 80 75 0.5 0.25 0.4 0.20 TOTAL POWER 0.3 IAVDD 0.2 0.15 0.10 IDVDD 0.1 0.05 65 0 40 60 55 70 0 85 100 115 130 145 160 175 190 205 220 235 250 ENCODE FREQUENCY (MSPS) Figure 58. AD9683-250 Power vs. Encode Rate 50 1 10 100 1000 INPUT FREQUENCY (MHz) 11410-057 0.05ps 0.2ps 0.5ps 1ps 1.5ps MEASURED 55 11410-058 SNR (dBFS) 70 As shown in Figure 58, the power dissipated by the AD9683 is proportional to its sample rate. The data in Figure 58 was taken using the same operating conditions as those used for the Typical Performance Characteristics section. IDVDD in Figure 58 is a summation of IDVDD and IDRVDD. SUPPLY CURRENT (A) High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fIN) due to jitter (tJ) can be calculated by TOTAL POWER (W) Jitter Considerations Figure 57. AD9683-250 SNR vs. Input Frequency and Jitter Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9683. Separate the power supplies for the clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), retime it using the original clock at the last step. Refer to the AN-501 Application Note, Aperture Uncertainty and ADC System Performance, and the AN-756 Application Note, Sampled Systems and the Effects of Clock Phase Noise and Jitter, for more information about jitter performance as it relates to ADCs. By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD9683 is placed in power-down mode. In this state, the ADC typically dissipates about 9 mW. Asserting the PDWN pin low returns the AD9683 to its normal operating mode. Low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. Internal capacitors are discharged when entering powerdown mode and then must be recharged when returning to normal operation. As a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. When using the SPI port interface, the user can place the ADC in power-down mode or standby mode. Standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. See the Memory Map Register Descriptions section and the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, for additional details. Rev. D | Page 23 of 44 AD9683 Data Sheet DIGITAL OUTPUTS JESD204B TRANSMIT TOP LEVEL DESCRIPTION The AD9683 digital output uses the JEDEC Standard No. JESD204B, Serial Interface for Data Converters. JESD204B is a protocol to link the AD9683 to a digital processing device over a serial interface of up to 5 Gbps link speeds. The benefits of the JESD204B interface include a reduction in required board area for data interface routing and the enabling of smaller packages for converter and logic devices. The AD9683 supports single lane interfaces. JESD204B Overview The JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8B/10B encoding as well as optional scrambling to form serial output data. Lane synchronization is supported using special characters during the initial establishment of the link, and additional synchronization is embedded in the data stream thereafter. A matching external receiver is required to lock onto the serial data stream and recover the data and clock. For additional details on the JESD204B interface, refer to the JESD204B standard. The AD9683 JESD204B transmit block maps the output of the ADC over a single link. The link is configured to use a single pair of serial differential outputs that is called a lane. The JESD204B specification refers to a number of parameters to define the link, and these parameters must match between the JESD204B transmitter (AD9683 output) and receiver. The JESD204B link is described according to the following parameters: • • • • • • • • • • • • • • Figure 59 shows a simplified block diagram of the AD9683 JESD204B link. The AD9683 uses one converter and one lane. The converter data is output to SERDOUT0+/SERDOUT0−. In the AD9683, the 14-bit converter word is divided into two octets (eight bits of data) by default. The first octet contains Bit 13 (MSB) through Bit 6. The second octet contains Bit 5 through Bit 0 (LSB) and two added tail bits. The tail bits can be configured as zeros, a pseudorandom number sequence, or control bits indicating overrange, underrange, or valid data conditions. The two resulting octets can be scrambled. Scrambling is optional; however, it is available to avoid spectral peaks when transmitting similar digital data patterns. The scrambler uses a self synchronizing, polynomial-based algorithm defined by the 1 + x14 + x15 equation. The descrambler in the receiver should be a self-synchronizing version of the scrambler polynomial. The two octets are then encoded with an 8B/10B encoder. The 8B/10B encoder works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. Figure 60 shows how the 14-bit data is taken from the ADC, the tail bits are added, the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. Figure 60 illustrates the default data format. At the data link layer, in addition to the 8B/10B encoding, the character replacement is used to allow the receiver to monitor frame alignment. The character replacement process occurs on the frame and multiframe boundaries, and implementation depends on which boundary is occurring, and if scrambling is enabled. If scrambling is disabled, the following applies: S = samples transmitted per single converter per frame cycle (AD9683 value = 1) M = number of converters per converter device (AD9683 value = 1) L = number of lanes per converter device (AD9683 value = 1) N = converter resolution (AD9683 value = 14) N’ = total number of bits per sample (AD9683 value = 16) CF = number of control words per frame clock cycle per converter device (AD9683 value = 0) CS = number of control bits/conversion sample (configurable on the AD9683 up to two bits) K = number of frames per multiframe (configurable on the AD9683) HD = high density mode (AD9683 value = 0) F = octets per frame (AD9683 value = 2) C = control bit (overrange, overflow, underflow; available on the AD9683) T = tail bit (available on the AD9683) SCR = scrambler enable/disable (configurable on the AD9683) FCHK = checksum for the JESD204B parameters (automatically calculated and stored in register map) • • If the last scrambled octet of the last frame of the multiframe equals the last octet of the previous frame, the transmitter replaces the last octet with the control character /A/ = /K28.3/. On other frames within the multiframe, if the last octet in the frame equals the last octet of the previous frame, the transmitter replaces the last octet with the control character /F/ = /K28.7/. If scrambling is enabled, the following applies: • • If the last octet of the last frame of the multiframe equals 0x7C, the transmitter replaces the last octet with the control character /A/ = /K28.3/. On other frames within the multiframe, if the last octet equals 0xFC, the transmitter replaces the last octet with the control character /F/ = /K28.7/. Refer to JEDEC Standard No. 204B, July 2011 for additional information about the JESD204B interface. Section 5.1 covers the transport layer and data format details and Section 5.2 covers scrambling and descrambling. Rev. D | Page 24 of 44 Data Sheet AD9683 JESD204B Synchronization Details • The AD9683 is a JESD204B Subclass 1 device that establishes synchronization of the link through two control signals, SYSREF and SYNC, and typically a common device clock. SYSREF and SYNC are common to all converter devices for alignment purposes at the system level. The synchronization process is accomplished over three phases: code group synchronization (CGS), initial lane alignment sequence (ILAS), and data transmission. If scrambling is enabled, the bits are not actually scrambled until the data transmission phase, and the CGS phase and ILAS phase do not use scrambling. CGS Phase In the CGS phase, the JESD204B transmit block transmits /K28.5/ characters. The receiver (external logic device) must locate /K28.5/ characters in its input data stream using clock and data recovery (CDR) techniques. When a certain number of consecutive /K28.5/ characters are detected on the link lane, the receiver initiates a SYSREF edge so that the AD9683 transmit data establishes a local multiframe clock (LMFC) internally. The SYSREF edge also resets any sampling edges within the ADC to align sampling instances to the LMFC. This is important to maintain synchronization across multiple devices. The receiver or logic device deasserts the SYNC signal (SYNCINB±), and the transmitter block begins the ILAS phase. ILAS Phase In the ILAS phase, the transmitter sends out a known pattern, and the receiver aligns the lanes in the link and verifies the parameters of the link. If scrambling is enabled and the last octet of the multiframe is equal to 0x7C, or the last octet of a frame is equal to 0xFC. Table 10. Fourteen Configuration Octets of the ILAS Phase No. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 DID[7:0] Bit 2 Bit 1 Bit 0 (LSB) BID[3:0] LID[4:0] L[4:0] SCR F[7:0] K[4:0] M[7:0] CS[1:0] SUBCLASS[2:0] JESDV[2:0] N[4:0] N’[4:0] S[4:0] CF[4:0] Reserved, don’t care Reserved, don’t care FCHK[7:0] Link Setup Parameters The following sections demonstrate how to configure the AD9683 JESD204B interface. The steps to configure the output include the following: 1. 2. 3. 4. 5. 6. Disable the lane before changing the configuration. Select a quick configuration option. Configure detailed options. Check FCHK, the checksum of the JESD204B interface parameters. Set additional digital output configuration options. Re-enable the lane. Disable Lane Before Changing Configuration The ILAS phase begins after SYNC has been deasserted (goes high). The transmit block begins to transmit four multiframes. Dummy samples are inserted between the required characters so that full multiframes are transmitted. The four multiframes include the following: Before modifying the JESD204B link parameters, disable the link and hold it in reset. This is accomplished by writing Logic 1 to Address 0x5F, Bit 0. • • • • • Multiframe 1 begins with an /R/ character [K28.0] and ends with an /A/ character [K28.3]. Multiframe 2 begins with an /R/ character followed by a /Q/ [K28.4] character, followed by link configuration parameters over 14 configuration octets (see Table 10), and ends with an /A/ character. Multiframe 3 is the same as Multiframe 1. Multiframe 4 is the same as Multiframe 1. Configure Detailed Options Configure the tail bits and control bits as follows. • With N’ = 16 and N = 14, there are two bits available per sample for transmitting additional information over the JESD204B link. The options are tail bits or control bits. By default, tail bits of 0b00 value are used. Tail bits are dummy bits sent over the link to complete the two octets and do not convey any information about the input signal. Tail bits can be fixed zeros (default) or pseudorandom numbers (Address 0x5F, Bit 6). One or two control bits can be used instead of the tail bits through Address 0x72, Bits[7:6]. The tail bits can be set using Address 0x14, Bits[7:5], and the tail bits can be enabled using Address 0x5F, Bit 6. Data Transmission Phase • In the data transmission phase, frame alignment is monitored with control characters. Character replacement is used at the end of frames. Character replacement in the transmitter occurs in the following instances: Set lane identification values. • • If scrambling is disabled and the last octet of the frame or multiframe equals the octet value of the previous frame. Rev. D | Page 25 of 44 JESD204B allows parameters to identify the device and lane. These parameters are transmitted during the ILAS phase, and they are accessible in the internal registers. AD9683 • Data Sheet There are three identification values: device identification (DID), bank identification (BID), and lane identification (LID). DID and BID are device specific; therefore, they can be used for link identification. Set the number of frames per multiframe, K. • • Per the JESD204B specification, a multiframe is defined as a group of K successive frames, where K is between 1 and 32, and it requires that the number of octets be between 17 and 1024. The K value is set to 32 by default in Address 0x70, Bits[7:0]. Note that the K value is the register value plus 1. The K value can be changed; however, it must comply with a few conditions. The AD9683 uses a fixed value for octets per frame (F) based on the JESD204B quick configuration setting. K must also be a multiple of 4 and conform to the following equation: 32 ≥ K ≥ Ceil (17/F) • The JESD204B specification also requires the number of octets per multiframe (K × F) to be between 17 and 1024. The F value is fixed through the quick configuration setting to ensure that this relationship is true. Verify read only values: lanes per link (L), octets per frame (F), number of converters (M), and samples per converter per frame (S). The AD9683 calculates values for some JESD204B parameters based on other settings, particularly the quick configuration register selection. The read only values here are available in the register map for verification. • • • • • L = lanes per link is 1; read the values from Address 0x6E, Bits[4:0] F = octets per frame is 1, 2, or 4; read the value from Address 0x6F, Bits[7:0] HD = high density mode can be 0 or 1; read the value from Address 0x75, Bit 7 M = number of converters per link is 1; read the value from Address 0x71, Bits[7:0] S = samples per converter per frame can be 1 or 2; read the value from Address 0x74, Bits[4:0] Check FCHK, Checksum of JESD204B Interface Parameters Table 11. JESD204B Configurable Identification Values The JESD204B parameters can be verified through the checksum value (FCHK) of the JESD204B interface parameters. Each lane has a FCHK value associated with it. The FCHK value is transmitted during the ILAS second multiframe and can be read from the internal registers. ID Value LID DID BID The checksum value is the modulo 256 sum of the parameters listed in the No. column of Table 12. The checksum is calculated by adding the parameter fields before they are packed into the octets shown in Table 12. Register, Bits 0x67, [4:0] 0x64, [7:0] 0x65, [3:0] Value Range 0 to 31 0 to 255 0 to 15 Scramble, SCR. • Scrambling can be enabled or disabled by setting Address 0x6E, Bit 7. By default, scrambling is enabled. Per the JESD204B protocol, scrambling is functional only after the lane synchronization has completed. Select lane synchronization options. Most of the synchronization features of the JESD204B interface are enabled, by default, for typical applications. In some cases, these features can be disabled or modified as follows: • ILAS enabling is controlled in Address 0x5F, Bits[3:2] and, by default, is enabled. Optionally, to support some unique instances of the interfaces (such as NMCDA-SL), the JESD204B interface can be programmed to either disable the ILAS sequence or continually repeat the ILAS sequence. The AD9683 has fixed values of some of the JESD204B interface parameters, and they are as follows: • • • N = 14, number of bits per converter is 14 in Address 0x72, Bits[3:0] N’ = 16, number of bits per sample is 16 in Address 0x73, Bits[3:0] CF = 0, number of control words per frame clock cycle per converter is 0 in Address 0x75, Bits[4:0] The FCHK value for the lane configuration for data coming out of the Lane 0 can be read from Address 0x79. Table 12. JESD204B Configuration Table Used in ILAS and CHKSUM Calculation No. 0 1 2 3 4 5 6 7 8 9 10 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 DID[7:0] Bit 2 Bit 1 Bit 0 (LSB) BID[3:0] LID[4:0] L[4:0] SCR F[7:0] K[4:0] M[7:0] CS[1:0] SUBCLASS[2:0] JESDV[2:0] N[4:0] N’[4:0] S[4:0] CF[4:0] Set Additional Digital Output Configuration Options Other data format controls include the following: • • • Rev. D | Page 26 of 44 Invert polarity of serial output data, Address 0x60, Bit 1 ADC data format select (offset binary or twos complement), Address 0x14, Bits[1:0] Options for interpreting signal on SYSREF± and SYNCINB±, Address 0x3A, Bits[4:0] Data Sheet AD9683 Reenable Lane After Configuration After modifying the JESD204B link parameters, enable the link so that the synchronization process can begin. This is accomplished by writing Logic 0 to Address 0x5F, Bit 0. AD9683 ADC CONVERTER INPUT CONVERTER SAMPLE CONVERTER JESD204B LANE CONTROL (M = 1, L = 1) 11410-059 SERDOUT0± SYSREF± SYNCINB± Figure 59. Transmit Link Simplified Block Diagram A PATH (LSB) 8B/10B ENCODER/ CHARACTER REPLACEMENT A6 A7 A8 A9 A10 A11 A12 A13 C0 C1 A0 A1 A2 A3 A4 A5 S8 S9 S10 S11 S12 S13 S14 S15 S0 S1 S2 S3 S4 S5 S6 S7 SERIALIZER E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 SERDOUT± E19 . . . E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 ~SYNC t SYSREF 11410-160 ADC VINA– JESD204B TEST PATTERN 10-BIT OPTIONAL SCRAMBLER 1 + x14 + x15 OCTET1 VINA+ A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 JESD204B TEST PATTERN 8-BIT OCTET0 (MSB) ADC TEST PATTERN 16-BIT Figure 60. Digital Processing of JESD204B Lane Table 13. JESD204B Typical Configurations M (No. of Converters), Address 0x71, Bits[7:0] 1 DATA FROM ADC L (No. of Lanes), Address 0x6E, Bits[4:0] 1 FRAME ASSEMBLER (ADD TAIL BITS) F (Octets/Frame), Address 0x6F, Bits[7:0], Read Only 2 OPTIONAL SCRAMBLER 1 + x14 + x15 S (Samples/ADC/Frame), Address 0x74, Bits[4:0], Read Only 1 8B/10B ENCODER TO RECEIVER HD (High Density Mode), Address 0x75, Bit 7, Read Only 0 11410-061 JESD204B Configure Setting 0x11 (Default) Figure 61. ADC Output Data Path Table 14. JESD204B Frame Alignment Monitoring and Correction Replacement Characters Scrambling Off Off Off On On On Lane Synchronization On On Off On On Off Character to be Replaced Last octet in frame repeated from previous frame Last octet in frame repeated from previous frame Last octet in frame repeated from previous frame Last octet in frame equals D28.7 Last octet in frame equals D28.3 Last octet in frame equals D28.7 Rev. D | Page 27 of 44 Last Octet in Multiframe No Yes Not applicable No Yes Not applicable Replacement Character K28.7 K28.3 K28.7 K28.7 K28.3 K28.7 AD9683 Data Sheet Frame alignment monitoring and correction is part of the JESD204B specification. The 14-bit word requires two octets to transmit all the data. The two octets (MSB and LSB), where F = 2, make up a frame. During normal operating conditions, frame alignment is monitored via alignment characters, which are inserted under certain conditions at the end of a frame. Table 14 summarizes the conditions for character insertion along with the expected characters under the various operation modes. If lane synchronization is enabled, the replacement character value depends on whether the octet is at the end of a frame or at the end of a multiframe. Based on the operating mode, the receiver can ensure that it is still synchronized to the frame boundary by correctly receiving the replacement characters. The AD9683 digital outputs can interface with custom ASICs and FPGA receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a single differential 100 Ω termination resistor placed as close to the receiver logic as possible. The common mode of the digital output automatically biases itself to half the supply of the AD9683 (that is, the common-mode voltage is 0.9 V for a supply of 1.8 V) if a dc-coupled connection is used (see Figure 63). For a receiver logic that is not within the bounds of the DRVDD supply, use an ac-coupled connection. Simply place a 0.1 µF capacitor on each output pin and derive a 100 Ω differential termination close to the receiver side. DRVDD 100Ω DIFFERENTIAL TRACE PAIR SERDOUT0+ 100Ω Digital Outputs and Timing The AD9683 has differential digital outputs that power up by default. The driver current is derived on chip and sets the output current at each output equal to a nominal 3 mA. Each output presents a 100 Ω dynamic internal termination to reduce unwanted reflections. Place a 100 Ω differential termination resistor at each receiver input to result in a nominal 600 mV p-p swing at the receiver (see Figure 62). Alternatively, single-ended 50 Ω termination can be used. When single-ended termination is used, the termination voltage must be DRVDD/2; otherwise, ac coupling capacitors can be used to terminate to any single-ended voltage. VRXCM DRVDD SERDOUT0+ OR RECEIVER SERDOUT0– VCM = Rx VCM Figure 62. AC-Coupled Digital Output Termination Example 11410-062 0.1µF OUTPUT SWING = 600mV p-p OUTPUT SWING = 600mV p-p VCM = DRVDD/2 Figure 63. DC-Coupled Digital Output Termination Example If there is no far-end receiver termination, or if there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. Figure 64 shows an example of the digital output (default) data eye and time interval error (TIE) jitter histogram and bathtub curve for the AD9683 lane running at 5 Gbps. Additional SPI options allow the user to further increase the output driver voltage swing or enable preemphasis to drive longer trace lengths (see Address 0x15 in Table 17). The power dissipation of the DRVDD supply increases when this option is used. See the Memory Map section for more details. 100Ω DIFFERENTIAL 0.1µF TRACE PAIR 100Ω RECEIVER SERDOUT0– 11410-063 Frame and Lane Alignment Monitoring and Correction The format of the output data is twos complement by default. To change the output data format to offset binary, see the Memory Map section (Address 0x14 in Table 17). Rev. D | Page 28 of 44 Data Sheet AD9683 HEIGHT1: EYE DIAGRAM 400 1 3 – 6000 200 – 1–2 1–4 5000 100 4000 BER HITS 1–6 0 1–8 3000 –100 1–10 2000 –300 1000 EYE: ALL BITS OFFSET: 0 –400 ULS: 7000; 993329 TOTAL: 7000; 993329 –100 0 TIME (ps) 100 0 200 1–12 1–14 –10 0 TIME (ps) 1–16 –0.5 10 0 ULS 11410-064 –200 –200 TJ AT BER1: BATHTUB 2 – 300 VOLTAGE (mV) PERIOD1: HISTOGRAM 7000 1 0.5 Figure 64. AD9683 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 5 Gbps HEIGHT1: EYE DIAGRAM 400 1 3 – 6000 200 – 1–2 1–4 5000 100 4000 BER HITS 1–6 0 1–8 3000 –100 1–10 2000 –300 1000 EYE: ALL BITS OFFSET: 0.0018 –400 ULS: 8000; 673330 TOTAL: 8000; 673330 –150 –50 0 50 TIME (ps) 150 0 250 1–12 1–14 –10 0 TIME (ps) 10 1–16 –0.5 0 ULS 0.5 11410-065 –200 –250 TJ AT BER1: BATHTUB 2 – 300 VOLTAGE (mV) PERIOD1: HISTOGRAM 7000 1 Figure 65. AD9683 Digital Outputs Data Eye, Histogram and Bathtub, External 100 Ω Terminations at 3.4 Gbps ADC OVERRANGE AND GAIN CONTROL ADC Overrange (OR) In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides delayed information on the state of the analog input that is of limited value in preventing clipping. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip occurs. In addition, because input signals can have significant slew rates, latency of this function is of concern. The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange condition is determined at the output of the ADC pipeline and, therefore, is subject to a latency of 36 ADC clock cycles. An overrange at the input is indicated by this bit 36 clock cycles after it occurs. Using the SPI port, the user can provide a threshold above which the FD output is active. Bit 0 of Address 0x45 enables the fast detect feature. Address 0x47 to Address 0x4A allow the user to set the threshold levels. As long as the signal is below the selected threshold, the FD output remains low. In this mode, the magnitude of the data is considered in the calculation of the condition, but the sign of the data is not considered. The threshold detection responds identically to positive and negative signals outside the desired range (magnitude). Gain Switching The AD9683 includes circuitry that is useful in applications either where large dynamic ranges exist or where gain ranging amplifiers are employed. This circuitry allows digital thresholds to be set such that an upper threshold and a lower threshold can be programmed. One such use is to detect when an ADC is about to reach full scale with a particular input condition. The result is to provide an indicator that can be used to quickly insert an attenuator that prevents ADC overdrive. Rev. D | Page 29 of 44 AD9683 Data Sheet Fast Threshold Detection (FD) comparison is subject to the ADC pipeline latency but is accurate in terms of converter resolution. The lower threshold magnitude is defined by The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located in Address 0x47 and Address 0x48. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of seven clock cycles. The approximate upper threshold magnitude is defined by Lower Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) For example, to set an upper threshold of −6 dBFS, write 0x0FFF to those registers, and to set a lower threshold of −10 dBFS, write 0x0A1D to those registers. Upper Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located in Address 0x4B and Address 0x4C. The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, located at Address 0x49 and Address 0x4A. The fast detect lower threshold register is a 16-bit register that is compared with the signal magnitude at the output of the ADC. This The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 66. UPPER THRESHOLD DWELL TIME LOWER THRESHOLD DWELL TIME FD Figure 66. Threshold Settings for FD Signals Rev. D | Page 30 of 44 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LT 11410-066 MIDSCALE TIMER RESET BY RISE ABOVE LOWER THRESHOLD Data Sheet AD9683 DC CORRECTION (DCC) Because the dc offset of the ADC may be significantly larger than the signal being measured, a dc correction circuit is included to null the dc offset before measuring the power. The dc correction circuit can also be switched into the main signal path; however, this may not be appropriate if the ADC is digitizing a time-varying signal with significant dc content, such as GSM. DC CORRECTION BANDWIDTH The dc correction circuit is a high-pass filter with a programmable bandwidth (ranging between 0.29 Hz and 2.387 kHz at 245.76 MSPS). The bandwidth is controlled by writing to the four dc correction bandwidth select bits, located at Address 0x40, Bits[5:2]. The following equation can be used to compute the bandwidth value for the dc correction circuit: DC CORRECTION READBACK The current dc correction value can be read back in Address 0x41 and Address 0x42. The dc correction value is a 16-bit value that can span the entire input range of the ADC. DC CORRECTION FREEZE Setting Bit 6 of Address 0x40 freezes the dc correction at its current state and continues to use the last updated value as the dc correction value. Clearing this bit restarts dc correction and adds the currently calculated value to the data. DC CORRECTION ENABLE BITS Setting Bit 1 of Address 0x40 enables dc correction for use in the output data signal path. DC_Corr_BW = 2−k−14 × fCLK/(2 × π) where: k is the 4-bit value programmed in Bits[5:2] of Address 0x40 (values between 0 and 13 are valid for k). fCLK is the AD9683 ADC sample rate in hertz. Rev. D | Page 31 of 44 AD9683 Data Sheet SERIAL PORT INTERFACE (SPI) The AD9683 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. CONFIGURATION USING THE SPI Three pins define the SPI of this ADC: the SCLK pin, the SDIO pin, and the CS pin (see Table 15). The SCLK (serial clock) pin is used to synchronize the read and write data presented from/to the ADC. The SDIO (serial data input/output) pin is a dual-purpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CS (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 15. Serial Port Interface Pins Pin SCLK SDIO CS Function Serial clock. The serial shift clock input, which is used to synchronize the serial interface reads and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. The falling edge of CS, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 67 and Table 5. Other modes involving CSare available. CS can be held low indefinitely, which permanently enables the device; this is called streaming. CS can stall high between bytes to allow for additional external timing. When CS is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. During an instruction phase, a 16-bit instruction is transmitted. Data follows the instruction phase, and its length is determined by the W0 and the W1 bits. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued. This allows the SDIO pin to change direction from an input to an output. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 15 comprise the physical interface between the user programming device and the serial port of the AD9683. The SCLK pin and the CS pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. Do not activate the SPI port during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CS signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9683 to prevent these signals from transitioning at the converter inputs during critical sampling periods. Rev. D | Page 32 of 44 Data Sheet AD9683 SPI ACCESSIBLE FEATURES Table 16 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9683 part-specific features are described in the Memory Map Register Descriptions section. Table 16. Features Accessible Using the SPI Feature Name Mode Clock Offset Test Input/Output Output Mode Output Phase Output Delay VREF Description Allows the user to set either power-down mode or standby mode Allows the user to access the DCS via the SPI Allows the user to digitally adjust the converter offset Allows the user to set test modes to have known data on output bits Allows the user to set up outputs Allows the user to set the output clock polarity Allows the user to vary the DCO delay Allows the user to set the reference voltage tDS tS tHIGH tCLK tDH tH tLOW CS SDIO DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 Figure 67. Serial Port Interface Timing Diagram Rev. D | Page 33 of 44 D4 D3 D2 D1 D0 DON’T CARE 11410-067 DON’T CARE SCLK DON’T CARE AD9683 Data Sheet MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Default Values Each row in the memory map register table has eight bit locations. The memory map is roughly divided into three sections: the chip configuration registers (Address 0x00 to Address 0x02); the ADC functions registers, including setup, control, and test (Address 0x08 to Address 0xA8); and the device update register (Address 0xFF). After the AD9683 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 17). The memory map register table (see Table 17) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x14, the output mode register, has a hexadecimal default value of 0x01. This means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. This application note details the functions controlled by Address 0x00 to Address 0x21 and Address 0xFF, with the exception of Address 0x08 and Address 0x14. The remaining registers, Address 0x08, Address 0x14, and Address 0x3A through Address 0xA8, are documented in the Memory Map Register Descriptions section. Logic Levels An explanation of logic level terminology follows: • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Transfer Register Map Address 0x09, Address 0x0B, Address 0x0D, Address 0x10, Address 0x14, Address 0x18, Address 21, and Address 0x3A to Address 0x4C are shadowed. Writes to these addresses do not affect part operation until a transfer command is issued by writing 0x01 to Address 0xFF, setting the transfer bit. This allows these registers to be updated internally and simultaneously when the transfer bit is set. The internal update takes place when the transfer bit is set, and then the bit autoclears. Open and Reserved Locations All address and bit locations that are not included in Table 17 are not currently supported for this device. Write unused bits of a valid address location with 0s. Writing to these locations is required only when part of an address location is open (for example, Address 0x18). If the entire address location is open (for example, Address 0x13), do not write to this address location. Rev. D | Page 34 of 44 Data Sheet AD9683 MEMORY MAP REGISTER TABLE All address and bit locations that are not included in Table 17 are not currently supported for this device. Table 17. Memory Map Registers Reg Addr (Hex) 0x00 0x01 0x02 Reg Addr Name SPI port configuration Chip ID Chip grade Bit 7 (MSB) 0 0x08 PDWN modes 0x09 Global clock Reserved 0x0A PLL status PLL locked status 0x0B Clock divide 0x0D Test mode 0x10 Customer offset Bit 6 LSB first User test mode cycle: 00 = repeat pattern (user pattern 1, 2, 3, 4, 1, 2, 3, 4, 1, …); 10 = single pattern (user pattern 1, 2, 3, 4, then all zeros) Bit 5 Soft reset Bit 4 1 Bit 3 1 Bit 2 Soft reset Bit 1 LSB first Bit 0 (LSB) 0 AD9683 8-bit chip ID is 0xC3 Speed grade: Reserved for chip die revision, currently 00 = 250 MSPS, 0x0 11 = 170 MSPS External JESD204B JESD204B power modes: ADC power modes: PDWN standby 00 = normal mode 00 = normal mode mode: (power-up); mode (power-up), 0= (when 01 = power-down 01 = power-down mode, PDWN is external mode, PLL off, serializer 10 = standby mode, full PDWN is off, clocks stopped, does not affect JESD204B powerused): digital held in reset; digital circuitry down, 0= 10 = standby mode, PLL 1= JESD204B on, serializer off, clocks PDWN core is stopped, digital circuitry puts unaffected, held in reset device in 1= standby JESD204B core is powered down except for PLL Clock selection: Clock duty 00 = Nyquist clock, cycle 01 = RF clock divide by 2, stabilizer 10 = RF clock divide by 4, enable 11 = clock off JESD204B link is ready Clock divide phase relative to Clock divider ratio relative to the encode clock: the encode clock: 0x0 = 0 input clock cycles delayed, 0x00 = divide by 1, 0x1 = 1 input clock cycles delayed, 0x01 = divide by 2, 0x2 = 2 input clock cycles delayed, 0x02 = divide by 3, … … 0x7 = 7 input clock cycles delayed 0x07 = divide by 8 Long Short Data output test generation mode: pseudopseudo0000 = off (normal mode), random random 0001 = midscale short, number number 0010 = positive full scale, generator generator 0011 = negative full scale, reset: reset: 0100 = alternating checkerboard, 0 = long 0 = short 0101 = PN sequence long, PRN PRN 0110 = PN sequence short, enabled, enabled, 0111 = 1/0 word toggle, 1 = long 1 = short 1000 = user test mode (use with Address 0x0D, PRN held PRN held in Bits[7:6] and user pattern 1, 2, 3, 4), in reset reset 1001 to 1110 = unused, 1111 = ramp output Offset adjust in LSBs from +31 to −32 (twos complement format): 01 1111 = adjust output by +31, 01 1110 = adjust output by +30, … 00 0001 = adjust output by +1, 00 0000 = adjust output by 0 (default), … 10 0001 = adjust output by −31, 10 0000 = adjust output by −32 Rev. D | Page 35 of 44 Default 0x18 Notes 0xC3 0x00 or 0x30 Read only 0x00 0x01 DCS enabled if clock divider enabled Read only 0x00 0x00 0x00 Clock divide values other than 0x00 automatically cause the DCS to become active AD9683 Reg Addr (Hex) 0x14 Reg Addr Name Output mode 0x15 CML output adjust 0x18 Input span select 0x19 User Test Pattern 1 LSB User Test Pattern 1 MSB User Test Pattern 2 LSB User Test Pattern 2 MSB User Test Pattern 3 LSB User Test Pattern 3 MSB User Test Pattern 4 LSB User Test Pattern 4 MSB PLL low encode 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x3A SYNCINB±/ SYSREF± control Data Sheet Bit 7 Bit 6 Bit 5 (MSB) JESD204B CS bits assignment (in conjunction with Address 0x72): 000 = {overrange||underrange, valid}, 001 = {overrange, underrange}, 010 = {overrange||underrange, blank}, 011 = {blank, valid}, 100 = {blank, blank}, 101 = {underrange, overrange}, 110 = {valid, overange||underrange}, 111 = {valid, blank} Bit 4 ADC output disable Bit 3 Bit 2 ADC data invert: 0 = normal (default), 1= inverted Bit 1 Bit 0 (LSB) Data format select (DFS) : 00 = offset binary, 01 = twos complement JESD204B CML differential output drive level adjustment: 000 = 75% of nominal ( 438 mV p-p), 001 = 83% of nominal (488 mV p-p), 010 = 91% of nominal (538 mV p-p), 011 = nominal (default) (588 mV p-p), 100 = 109% of nominal (638 mV p-p), 101 = 117% of nominal (690 mV p-p), 110 = 126% of nominal (740 mV p-p), 111 = 134% of nominal (790 mV p-p) Main reference full-scale VREF adjustment: 0 1111 = internal 2.087 V p-p, … 0 0001 = internal 1.772 V p-p, 0 0000 = internal 1.75 V p-p (default), 1 1111 = internal 1.727 V p-p, … 1 0000 = internal 1.383 V p-p User Test Pattern 1 LSB; use in conjunction with Address 0x0D and Address 0x61 Default 0x01 0x03 0x00 User Test Pattern 1 MSB User Test Pattern 2 LSB User Test Pattern 2 MSB User Test Pattern 3 LSB User Test Pattern 3 MSB User Test Pattern 4 LSB User Test Pattern 4 MSB 00 = for lane speeds of >2 Gbps, 01 = for lane speeds of