FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD
SPIVDD
(1.25V) (2.5V) (3.3V)
(1.25V) (1.25V) (1.25V) (1.8V TO 3.3V)
BUFFER
Rev. B
DDC
FD
4
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
CONTROL
REGISTERS
V_1P0
FAST
DETECT
÷2
÷4
÷8
AGND
SYSREF±
SPI CONTROL
AD9690
DRGND DGND SDIO SCLK CSB
PDWN/
STBY
12834-001
CLK+
CLK–
SYNCINB±
JESD204B
SUBCLASS 1
CONTROL
CLOCK
GENERATION
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
APPLICATIONS
Communications
Multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
Wideband digital predistortion
ADC 14
CORE
VIN+
VIN–
FAST
DETECT
JESD204B (Subclass 1) coded serial digital outputs
2.0 W total power at 1 GSPS (default settings)
1.5 W total power at 500 MSPS (default settings)
SFDR = 85 dBFS at 340 MHz, 80 dBFS at 985 MHz
SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS),
60.5 dBFS at 985 MHz
ENOB = 10.8 bits at 10 MHz
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −154 dBFS/Hz at 1 GSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
No missing codes
Internal ADC voltage reference
Flexible input range
AD9690-1000: 1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
AD9690-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
Programmable termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
2 GHz usable analog input full power bandwidth
Amplitude detect bits for efficient AGC implementation
2 integrated wideband digital processors
12-bit NCO, up to 4 cascaded half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither
JESD204B
HIGH SPEED SERIALIZER +
Tx OUTPUTS
Data Sheet
14-Bit, 1 GSPS/500 MSPS JESD204B,
Analog-to-Digital Converter
AD9690
4.
5.
6.
Wide full power bandwidth supports IF sampling of signals
up to 2 GHz.
Buffered inputs with programmable input termination eases
filter design and implementation.
Two integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
Programmable fast overrange detection.
9 mm × 9 mm, 64-lead LFCSP.
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Technical Support
www.analog.com
AD9690
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DDC NCO Plus Mixer Loss and SFDR ................................... 42
Applications ....................................................................................... 1
Numerically Controlled Oscillator .......................................... 42
Functional Block Diagram .............................................................. 1
FIR Filters ........................................................................................ 44
Product Highlights ........................................................................... 1
General Description ................................................................... 44
Revision History ............................................................................... 3
Half-Band Filters ........................................................................ 45
General Description ......................................................................... 4
DDC Gain Stage ......................................................................... 47
Specifications..................................................................................... 5
DDC Complex—Real Conversion ........................................... 47
DC Specifications ......................................................................... 5
DDC Example Configurations ................................................. 48
AC Specifications.......................................................................... 6
Digital Outputs ............................................................................... 49
Digital Specifications ................................................................... 7
Introduction to the JESD204B Interface ................................. 49
Switching Specifications .............................................................. 8
JESD204B Overview .................................................................. 49
Timing Specifications .................................................................. 9
Functional Overview ................................................................. 50
Absolute Maximum Ratings .......................................................... 11
JESD204B Link Establishment ................................................. 50
Thermal Characteristics ............................................................ 11
Physical Layer (Driver) Outputs .............................................. 52
ESD Caution ................................................................................ 11
JESD204B Tx Converter Mapping ........................................... 54
Pin Configuration and Function Descriptions ........................... 12
Configuring the JESD204B Link .............................................. 55
Typical Performance Characteristics ........................................... 14
Multichip Synchronization............................................................ 57
AD9690-1000 .............................................................................. 14
SYSREF± Setup/Hold Window Monitor ................................. 59
AD9690-500 ................................................................................ 18
Test Modes ....................................................................................... 61
Equivalent Circuits ......................................................................... 22
ADC Test Modes ........................................................................ 61
Theory of Operation ...................................................................... 24
JESD204B Block Test Modes .................................................... 62
ADC Architecture ...................................................................... 24
Serial Port Interface ........................................................................ 64
Analog Input Considerations.................................................... 24
Configuration Using the SPI ..................................................... 64
Voltage Reference ....................................................................... 28
Hardware Interface ..................................................................... 64
Clock Input Considerations ...................................................... 29
SPI Accessible Features .............................................................. 64
ADC Overrange and Fast Detect .................................................. 31
Memory Map .................................................................................. 65
ADC Overrange .......................................................................... 31
Reading the Memory Map Register Table............................... 65
Fast Threshold Detection (FD)................................................. 31
Memory Map Register Table ..................................................... 66
Signal Monitor ................................................................................ 32
Applications Information .............................................................. 77
SPORT Over JESD204B ............................................................. 32
Power Supply Recommendations............................................. 77
Digital Downconverter (DDC) ..................................................... 35
Exposed Pad Thermal Heat Slug Recommendations ............ 77
DDC I/Q Input Selection .......................................................... 35
AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) .............. 77
DDC I/Q Output Selection ....................................................... 35
Outline Dimensions ....................................................................... 78
DDC General Description ........................................................ 35
Ordering Guide .......................................................................... 78
Frequency Translation ................................................................... 41
General Description ................................................................... 41
Rev. B | Page 2 of 78
Data Sheet
AD9690
REVISION HISTORY
5/2017—Rev. A to Rev. B
Changes to Junction Temperature Range Parameter, Table 6 ...11
Updated Outline Dimensions ........................................................78
Changes to Ordering Guide ...........................................................78
7/2016—Rev. 0 to Rev. A
Changes to General Description Section ....................................... 4
Changes to Ordering Guide ...........................................................78
1/2015—Revision 0: Initial Version
Rev. B | Page 3 of 78
AD9690
Data Sheet
GENERAL DESCRIPTION
The AD9690 is a 14-bit, 1 GSPS/500 MSPS analog-to-digital
converter (ADC). The device has an on-chip buffer and sampleand-hold circuit designed for low power, small size, and ease of
use. This device is designed for sampling wide bandwidth
analog signals of up to 2 GHz. The AD9690 is optimized for
wide input bandwidth, high sampling rate, excellent linearity,
and low power in a small package.
The programmable threshold detector allows monitoring of the
incoming signal power using the fast detect output bits of the
ADC. If the input signal level exceeds the programmable
threshold, the fast detect indicator goes high. Because this
threshold indicator has low latency, the user can quickly turn
down the system gain to avoid an overrange condition at the
ADC input.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
Users can configure the Subclass 1 JESD204B-based high speed
serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the
acceptable lane rate of the receiving logic device. Multiple device
synchronization is supported through the SYSREF± and
SYNCINB± input pins.
The analog input and clock signals are differential inputs. The
ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal
processing stages: a 12-bit frequency translator (NCO), and four
half-band decimation filters.
In addition to the DDC blocks, the AD9690 has several
functions that simplify the automatic gain control (AGC)
function in the communications receiver.
The AD9690 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.
The AD9690 is available in a Pb-free, 64-lead LFCSP and is
specified over the −40°C to +85°C industrial temperature range.
This product may be protected by one or more U.S. or international
patents
Rev. B | Page 4 of 78
Data Sheet
AD9690
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Voltage
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage Range (Programmable)
Common-Mode Voltage (VCM)
Differential Input Capacitance
Analog Input Full Power Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
AVDD1_SR
DVDD
DRVDD
SPIVDD
IAVDD1
IAVDD2
IAVDD3
IAVDD1_SR
IDVDD1
IDRVDD1
ISPIVDD
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)1
Power-Down Dissipation
Standby2
1
2
Temperature
Full
Min
14
Full
Full
Full
Full
Full
−0.3
−6
−0.6
−4.5
AD9690-500
Typ
Max
Guaranteed
0
+0.3
0
+6
±0.5
+0.7
±2.5
+5.0
Min
14
−0.31
−6
−0.7
−5.7
AD9690-1000
Typ
Max
Guaranteed
0
+0.31
0
+6
±0.5
+0.8
±2.5
+6.9
Unit
Bits
% FSR
% FSR
LSB
LSB
25°C
25°C
−9
±25
−14
±13.8
ppm/°C
ppm/°C
Full
1.0
1.0
V
25°C
2.06
2.63
LSB rms
Full
25°C
25°C
25°C
1.46
2.06
2.05
1.5
2
2.06
1.46
1.70
2.05
1.5
2
1.94
V p-p
V
pF
GHz
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.22
2.44
3.2
1.22
1.22
1.22
1.7
1.25
2.5
3.3
1.25
1.25
1.25
1.8
245
279
61
16
73
109
5
1.28
2.56
3.4
1.28
1.28
1.28
3.4
286
343
75
18
107
181
6
1.22
2.44
3.2
1.22
1.22
1.22
1.7
1.25
2.5
3.3
1.25
1.25
1.25
1.8
370
370
83
15
129
147
5
1.28
2.56
3.4
1.28
1.28
1.28
3.4
409
456
100
18
159
175
6
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
Full
Full
Full
1.5
600
900
2.0
700
1100
W
mW
mW
Default mode. No DDCs used. 500 MSPS is L = 2, M = 1, and F = 1; 1000 MSPS is L = 4, M = 1, and F = 1. Power dissipation on DRVDD changes with lane rate and
number of lanes used. Care must be taken to ensure that the serial line rate for a given configuration is within the supported range of 3.125 Gbps to 12.5 Gbps.
Can be controlled by the SPI.
Rev. B | Page 5 of 78
AD9690
Data Sheet
AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 2.
Parameter1
ANALOG INPUT FULL SCALE
NOISE DENSITY2
SIGNAL-TO-NOISE RATIO (SNR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
SNR AND DISTORTION RATIO (SINAD)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
WORST HARMONIC, SECOND OR THIRD3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
Temperature
Full
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Rev. B | Page 6 of 78
AD9690-500
Min Typ
Max
2.06
−153
67.8
66.6
10.8
80
69.2
69.0
68.6
68.0
64.4
63.8
60.5
65.1
69.0
68.8
68.4
67.9
64.2
63.6
60.3
65.0
11.2
11.1
11.1
11.0
10.4
10.3
9.7
10.5
83
88
83
81
80
75
70
−83
−88
−83
−81
−80
−75
−70
AD9690-1000
Min Typ
Max
1.7
−154
75
−75
Unit
V p-p
dBFS/Hz
67.2
66.6
65.3
64.0
61.5
60.5
57.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
67.1
66.4
65.2
63.8
62.1
61.1
56.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
10.8
10.7
10.5
10.3
10.0
9.8
9.0
Bits
Bits
Bits
Bits
Bits
Bits
Bits
88
85
85
82
82
80
68
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−88
−85
−85
−82
−82
−80
−68
−75
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Data Sheet
Parameter1
WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD),
AIN1 AND AIN2 = −7 dBFS
fIN1 = 185 MHz, fIN2 = 188 MHz
fIN1 = 338 MHz, fIN2 = 341 MHz
FULL POWER BANDWIDTH4
AD9690
Temperature
AD9690-500
Min Typ
Max
25°C
Full
25°C
25°C
25°C
25°C
25°C
−95
−95
−93
−93
−88
−89
−84
25°C
25°C
25°C
−88
−88
2
AD9690-1000
Min Typ
Max
−82
−95
−94
−88
−86
−81
−82
−75
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−81
−87
−88
2
dBFS
dBFS
GHz
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Noise density is measured at a low analog input frequency (30 MHz).
See Table 10 for the recommended settings for full-scale voltage and buffer current.
4
Measured with the circuit shown in Figure 64.
1
2
3
DIGITAL SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
SYSREF INPUTS (SYSREF+, SYSREF−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
LOGIC INPUTS (SDI, SCLK, CSB, PDWN/STBY)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
LOGIC OUTPUT (SDIO)
Logic Compliance
Logic 1 Voltage (IOH = 800 µA)
Logic 0 Voltage (IOL = 50 µA)
SYNCIN INPUT (SYNCINB+/SYNCINB−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
600
Rev. B | Page 7 of 78
LVDS/LVPECL
1200
0.85
35
Max
Unit
1800
mV p-p
V
kΩ
pF
2.5
400
0.6
LVDS/LVPECL
1200
0.85
35
1800
2.0
2.5
0
Full
Full
Full
Full
Full
Full
Full
Full
Typ
400
0.6
mV p-p
V
kΩ
pF
CMOS
0.8 × SPIVDD
0.2 × SPIVDD
30
V
V
kΩ
CMOS
0.8 × SPIVDD
0.2 × SPIVDD
V
V
LVDS/LVPECL/CMOS
1200
1800
0.85
2.0
35
2.5
mV p-p
V
kΩ
pF
AD9690
Data Sheet
Parameter
LOGIC OUTPUT (FD)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3)
Logic Compliance
Differential Output Voltage
Output Common-Mode Voltage (VCM)
AC Coupled
Short-Circuit Current (IDSHORT)
Differential Return Loss (RLDIFF)1
Common-Mode Return Loss (RLCM)1
Differential Termination Impedance
1
Temperature
Min
Typ
Max
Full
Full
Full
Full
0.8
0
CMOS
SPIVDD
0
30
Unit
V
V
kΩ
Full
Full
360
CML
770
mV p-p
25°C
25°C
25°C
25°C
Full
0
−100
8
6
80
1.8
+100
V
mA
dB
dB
Ω
100
120
Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate.
SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
CLOCK
Clock Rate (at CLK+/CLK− Pins)
Maximum Sample Rate1
Minimum Sample Rate2
Clock Pulse Width High
Clock Pulse Width Low
OUTPUT PARAMETERS
Unit Interval (UI)3
Rise Time (tR) (20% to 80% into 100 Ω Load)
Fall Time (tF) (20% to 80% into 100 Ω Load)
PLL Lock Time
Data Rate (NRZ)4
LATENCY5
Pipeline Latency
Fast Detect Latency
Wake-Up Time6
Standby
Power-Down
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tj)
Out-of-range Recovery Time
AD9690-500
Typ
Max
Temperature
Min
Full
Full
Full
Full
Full
0.3
500
300
1000
1000
Full
25°C
25°C
25°C
25°C
80
24
24
3.125
4
200
32
32
2
5
Full
Full
55
25°C
25°C
1
Full
Full
Full
530
55
1
AD9690-1000
Min
Typ
Max
Unit
0.3
1000
300
500
500
GHz
MSPS
MSPS
ps
ps
80
24
24
12.5
3.125
4
100
32
32
2
10
The maximum sample rate is the clock rate after the divider.
The minimum sample rate operates at 300 MSPS with L = 2 or L = 1.
Baud rate = 1/UI. A subset of this range can be supported.
4
Default L = 4. This number can be changed based on the sample rate and decimation ratio.
5
No DDCs used. L = 2, M = 1, F = 1.
6
Wake-up time is defined as the time required to return to normal operation from power-down mode.
3
Rev. B | Page 8 of 78
Clock cycles
Clock cycles
4
ms
ms
1
4
2
28
55
28
1
12.5
ps
ps
ps
ms
Gbps
530
55
1
ps
fs rms
Clock Cycles
Data Sheet
AD9690
TIMING SPECIFICATIONS
Table 5.
Parameter
CLK+ to SYSREF+ TIMING REQUIREMENTS
tSU_SR
tH_SR
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Test Conditions/Comments
See Figure 3
Device clock to SYSREF+ setup time
Device clock to SYSREF+ hold time
See Figure 4
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Time required for the SDIO pin to switch from an input to an
output relative to the SCLK falling edge (not shown in Figure 4)
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in Figure 4)
tDIS_SDIO
Min
Typ
Max
117
−96
Unit
ps
ps
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
Timing Diagrams
APERTURE
DELAY
ANALOG
INPUT
SIGNAL
SAMPLE N
N – 54
N+1
N – 55
N – 53
N – 52
N–1
N – 51
CLK–
CLK+
CLK–
CLK+
SERDOUT0–
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
CONVERTER0 MSB
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
CONVERTER0 LSB
SERDOUT0+
SERDOUT1–
SAMPLE N – 55
ENCODED INTO 1
8-BIT/10-BIT SYMBOL
SAMPLE N – 54
ENCODED INTO 1
8-BIT/10-BIT SYMBOL
12834-002
SERDOUT1+
SAMPLE N – 53
ENCODED INTO 1
8-BIT/10-BIT SYMBOL
Figure 2. Data Output Timing (Full Bandwidth Mode; L = 2; M = 1; F = 1)
CLK–
CLK+
tSU_SR
tH_SR
12834-003
SYSREF–
SYSREF+
Figure 3. SYSREF± Setup and Hold Timing
Rev. B | Page 9 of 78
AD9690
Data Sheet
tHIGH
tDS
tS
tACCESS
tCLK
tDH
tH
tLOW
CSB
SCLK DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
A7
D5
Figure 4. Serial Port Interface Timing Diagram
Rev. B | Page 10 of 78
D4
D3
D2
D1
D0
DON’T CARE
12834-004
SDIO DON’T CARE
DON’T CARE
Data Sheet
AD9690
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
Electrical
AVDD1 to AGND
AVDD1_SR to AGND
AVDD2 to AGND
AVDD3 to AGND
DVDD to DGND
DRVDD to DRGND
SPIVDD to AGND
AGND to DRGND
VIN± to AGND
SCLK, SDIO, CSB to AGND
PDWN/STBY to AGND
Environmental
Operating Temperature Range
Junction Temperature Range
Storage Temperature Range
(Ambient)
Rating
1.32 V
1.32 V
2.75 V
3.63 V
1.32 V
1.32 V
3.63 V
−0.3 V to +0.3 V
3.2 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to SPIVDD + 0.3 V
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
Typical θJA, θJB, and θJC are specified vs. the number of printed
circuit board (PCB) layers in different airflow velocities (in m/sec).
Airflow increases heat dissipation effectively reducing θJA and
θJB. In addition, metal in direct contact with the package leads
and exposed pad from metal traces, through holes, ground, and
power planes, reduces θJA. Thermal performance for actual
applications requires careful inspection of the conditions in
an application. The use of appropriate thermal management
techniques is recommended to ensure that the maximum
junction temperature does not exceed the limits shown in Table 6.
Table 7. Thermal Resistance Values
PCB
Type
JEDEC
2s2p
Board
Airflow
Velocity
(m/sec)
0.0
1.0
2.5
ΨJB
6.31, 3
5.91, 3
5.71, 3
θJC_TOP
4.71, 4
N/A5
N/A5
θJC_BOT
1.21, 4
Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per JEDEC JESD51-8 (still air).
4
Per MIL-STD 883, Method 1012.1.
5
N/A means not applicable.
1
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
θJA
17.81, 2
15.61, 2
15.01, 2
2
ESD CAUTION
Rev. B | Page 11 of 78
Unit
°C/W
°C/W
°C/W
AD9690
Data Sheet
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD1
AVDD2
AVDD2
AVDD1
AGND
SYSREF–
SYSREF+
AVDD1_SR
AGND
AVDD1
CLK–
CLK+
AVDD1
AVDD2
AVDD2
AVDD1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9690
TOP VIEW
(Not to Scale)
AVDD1
AVDD1
AVDD2
AVDD3
DNC
DNC
AVDD3
AVDD2
AVDD2
AVDD2
SPIVDD
CSB
SCLK
SDIO
DVDD
DGND
NOTES
1. EXPOSED PAD. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE
PACKAGE PROVIDES THE GROUND REFENCE FOR AVDDx. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
2. DNC = DO NOT CONNECT.
12834-005
FD_A
DRGND
DRVDD
SYNCINB–
SYNCINB+
SERDOUT0–
SERDOUT0+
SERDOUT1–
SERDOUT1+
SERDOUT2–
SERDOUT2+
SERDOUT3–
SERDOUT3+
DRVDD
DRGND
DNC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD1
AVDD1
AVDD2
AVDD3
VIN–A
VIN+A
AVDD3
AVDD2
AVDD2
AVDD2
AVDD2
V_1P0
SPIVDD
PDWN/STBY
DVDD
DGND
Figure 5. Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
Power Supplies
0
Mnemonic
Type
Description
EPAD
Ground
1, 2, 47, 48, 49, 52, 55, 61, 64
3, 8, 9, 10, 11, 39, 40, 41,
46, 50, 51, 62, 63
4, 7, 42, 45
13, 38
15, 34
16, 33
18, 31
19, 30
56, 60
57
Analog
5, 6
12
AVDD1
AVDD2
Supply
Supply
Exposed Pad. The exposed thermal pad on the bottom of the
package provides the ground reference for AVDDx. This
exposed pad must be connected to ground for proper
operation.
Analog Power Supply (1.25 V Nominal).
Analog Power Supply (2.5 V Nominal).
AVDD3
SPIVDD
DVDD
DGND
DRGND
DRVDD
AGND1
AVDD1_SR1
Supply
Supply
Supply
Ground
Ground
Supply
Ground
Supply
Analog Power Supply (3.3 V Nominal).
Digital Power Supply for SPI (1.8 V to 3.3 V).
Digital Power Supply (1.25 V Nominal).
Ground Reference for DVDD.
Ground Reference for DRVDD.
Digital Driver Power Supply (1.25 V Nominal).
Ground Reference for SYSREF±.
Analog Power Supply for SYSREF± (1.25 V Nominal).
VIN−, VIN+
V_1P0
Input
Input/DNC
DNC
CLK+, CLK−
DNC
Input
ADC Analog Input Complement/True.
1.0 V Reference Voltage Input/Do Not Connect. This pin is
configurable through the SPI as a no connect or an input. Do
not connect this pin if using the internal reference. Requires a
1.0 V reference voltage input if using an external voltage
reference source.
Do Not Connect.
Clock Input True/Complement.
44, 43
53, 54
Rev. B | Page 12 of 78
Data Sheet
Pin No.
CMOS Outputs
17
32
Digital Inputs
20, 21
58, 59
Data Outputs
22, 23
24, 25
26, 27
28, 29
Device Under Test (DUT)
Controls
14
35
36
37
1
AD9690
Mnemonic
Type
Description
FD
DNC
Output
DNC
Fast Detect Output.
Do Not Connect.
SYNCINB−, SYNCINB+
SYSREF+, SYSREF−
Input
Input
Active Low JESD204B LVDS Sync Input True/Complement.
Active High JESD204B LVDS System Reference Input
True/Complement.
SERDOUT0−, SERDOUT0+
SERDOUT1−, SERDOUT1+
SERDOUT2−, SERDOUT2+
SERDOUT3−, SERDOUT3+
Output
Output
Output
Output
Lane 0 Output Data Complement/True.
Lane 1 Output Data Complement/True.
Lane 2 Output Data Complement/True.
Lane 3 Output Data Complement/True.
PDWN/STBY
Input
SDIO
SCLK
CSB
Input/Output
Input
Input
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as powerdown or standby.
SPI Serial Data Input/Output.
SPI Serial Clock.
SPI Chip Select (Active Low).
To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, refer to the Applications
Information section.
Rev. B | Page 13 of 78
AD9690
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AD9690-1000
AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.7 V p-p
full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted.
See Table 10 for recommended settings.
AIN = –1dBFS
SNR = 67.2dBFS
ENOB = 10.8 BITS
SFDR = 88dBFS
BUFFER CONTROL 1 = 1.5×
–10
–30
AMPLITUDE (dBFS)
–50
–70
–90
–50
–70
–90
0
100
200
300
400
500
FREQUENCY (MHz)
–130
12834-006
–130
0
500
AIN = –1dBFS
SNR = 61.5dBFS
ENOB = 10.1 BITS
SFDR = 82dBFS
BUFFER CONTROL 1 = 6.0×
–20
AMPLITUDE (dBFS)
–50
–70
–90
–40
–60
–80
–100
0
100
200
300
400
500
FREQUENCY (MHz)
–120
12834-007
–130
0
100
200
Figure 7. Single-Tone FFT with fIN = 170.3 MHz
0
500
AIN = –1dBFS
SNR = 60.5dBFS
ENOB = 9.9 BITS
SFDR = 80dBFS
BUFFER CONTROL 1 = 6.0×
–20
AMPLITUDE (dBFS)
–30
400
Figure 10. Single-Tone FFT with fIN = 765.3 MHz
AIN = –1dBFS
SNR = 65.3dBFS
ENOB = 10.5 BITS
SFDR = 85dBFS
BUFFER CONTROL 1 = 3.0×
–10
300
FREQUENCY (MHz)
12834-010
AMPLITUDE (dBFS)
400
0
–110
–50
–70
–90
–40
–60
–80
–100
–110
–130
0
100
200
300
400
FREQUENCY (MHz)
500
12834-008
AMPLITUDE (dBFS)
300
Figure 9. Single-Tone FFT with fIN = 450.3 MHz
AIN = –1dBFS
SNR = 66.6dBFS
ENOB = 10.7 BITS
SFDR = 85dBFS
BUFFER CONTROL 1 = 3.0×
–30
200
FREQUENCY (MHz)
Figure 6. Single-Tone FFT with fIN = 10.3 MHz
–10
100
12834-009
–110
–110
–120
0
100
200
300
400
FREQUENCY (MHz)
Figure 11. Single-Tone FFT with fIN = 985.3 MHz
Figure 8. Single-Tone FFT with fIN = 340.3 MHz
Rev. B | Page 14 of 78
500
12834-011
AMPLITUDE (dBFS)
–30
AIN = –1dBFS
SNR = 64.0dBFS
ENOB = 10.3 BITS
SFDR = 82dBFS
BUFFER CONTROL 1 = 3.0×
–10
Data Sheet
AD9690
0
90
85
SFDR (dBFS)
–40
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
AIN = –1dBFS
SNR = 59.8BFS
ENOB = 9.6 BITS
–20 SFDR = 79dBFS
BUFFER CONTROL 1 = 8.0×
–60
–80
80
75
70
SNR (dBFS)
–100
0
100
200
300
400
500
FREQUENCY (MHz)
60
700
12834-012
–120
800
850
900
950
1000
1050
1100
SAMPLE RATE (MHz)
Figure 15. SNR/SFDR vs. Sample Rate (fS), fIN = 170.3 MHz; Buffer Control 1
(0x018) = 3.0×
Figure 12. Single-Tone FFT with fIN = 1293.3 MHz
90
0
AIN = –1dBFS
SNR = 57.7dBFS
ENOB = 9.2 BITS
–20 SFDR = 70dBFS
BUFFER CONTROL 1 = 8.0×
85
80
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
750
12834-015
65
–40
–60
–80
75
70
65
55
1.5× SFDR (dBFS)
1.5× SNR (dBFS)
3.0× SFDR (dBFS)
3.0× SNR (dBFS)
0
100
200
300
400
500
FREQUENCY (MHz)
12834-013
–120
50
10.3
63.3
100.3 170.3 225.3 302.3 341.3 403.3 453.3 502.3
ANALOG INPUT FREQUENCY (MHz)
Figure 16. SNR/SFDR vs. Analog Input Frequency (fIN); fIN < 500 MHz;
Buffer Control 1 (0x018) = 1.5× and 3.0×
Figure 13. Single-Tone FFT with fIN = 1725.3 MHz
100
0
AIN = –1dBFS
SNR = 57dBFS
ENOB = 9.1 BITS
–20 SFDR = 68dBFS
BUFFER CONTROL 1 = 8.0×
SNR/SFDR (dBFS)
90
–40
–60
–80
80
70
60
–120
0
100
200
300
400
FREQUENCY (MHz)
500
Figure 14. Single-Tone FFT with fIN = 1950.3 MHz
50
476.8
4.0× SFDR
4.0× SNRFS
6.0× SFDR
6.0× SNRFS
554.4
593.2
670.8
748.4
826.0
903.6
981.2
ANALOG INPUT FREQUENCY (MHz)
Figure 17. SNR/SFDR vs. Analog Input Frequency (fIN);
500 MHz < fIN < 1 GHz;
Buffer Control1 (0x018) = 4.0× and 6.0×
Rev. B | Page 15 of 78
12834-017
–100
12834-014
AMPLITUDE (dBFS)
12834-016
60
–100
AD9690
Data Sheet
100
0
–20
AMPLITUDE (dBFS)
90
80
SFDR
70
–40
–60
–80
SNR
60
50
978.5
1065.0
1142.4
1220.0
1297.3
1374.8
1452.2
–120
ANALOG INPUT FREQUENCY (MHz)
0
100
200
300
100
20
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
0
SFDR/IMD3 (dBc AND dBFS)
90
80
SFDR
70
60
SNR
1607.4
1701.6
1889.7
1795.6
ANALOG INPUT FREQUENCY (MHz)
–60
–80
–100
–140
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
INPUT AMPLITUDE (dBFS)
Figure 19. SNR/SFDR vs. fIN; 1.5 GHz < fIN < 2 GHz;
Buffer Control 1 (0x018) = 7.5×
Figure 22. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 184 MHz and fIN2 = 187 MHz
0
20
AIN1 AND AIN2 = –7dBFS
SFDR = 87dBFS
IMD2 = 93dBFS
IMD3 = 87dBFS
BUFFER CONTROL 1 = 3.0×
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
0
SNR/SFDR (dBc AND dBFS)
–20
–40
–120
12834-019
50
1513.3
–20
12834-022
SNR/SFDR (dBFS)
500
Figure 21. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz
Figure 18. SNR/SFDR vs. fIN; 1 GHz < fIN < 1.5 GHz;
Buffer Control 1 (0x018) = 6.0×
–40
–60
–80
–20
–40
–60
–80
–100
–100
–120
0
100
200
300
400
FREQUENCY (MHz)
500
–140
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
INPUT AMPLITUDE (dBFS)
Figure 20. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz
Figure 23. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with
fIN1 = 338 MHz and fIN2 = 341 MHz
Rev. B | Page 16 of 78
12834-023
–120
12834-020
AMPLITUDE (dBFS)
400
FREQUENCY (MHz)
12834-021
–100
12834-018
SNR/SFDR (dBFS)
AIN1 AND AIN2 = –7dBFS
SFDR = 88dBFS
IMD2 = 93dBFS
IMD3 = 88dBFS
BUFFER CONTROL 1 = 4.5×
Data Sheet
AD9690
0.6
110
100
90
0.4
80
0.2
60
DNL (LSB)
SNR/SFDR (dB)
70
50
40
30
0
–0.2
20
10
0
INPUT AMPLITUDE (dBFS)
–0.6
12834-024
–20
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
0
2000
4000
6000
8000
10000 12000 14000 16000
OUTPUT CODE
Figure 24. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz
12834-027
–0.4
SFDR (dBFS)
SFDR (dBc)
SNR (dBFS)
SNR (dBc)
0
–10
Figure 27. DNL, fIN = 15 MHz
25000
100
2.63 LSB rms
20000
SFDR
NUMBER OF HITS
80
70
SNR
15000
10000
5000
60
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (°C)
0
12834-025
50
–50 –40 –30 –20 –10
N–6 N–5 N–4 N–3 N–2 N–1
N
N+1 N+2 N+3 N+4 N+5 N+6
CODE
Figure 25. SNR/SFDR vs. Temperature, fIN = 170.3 MHz
12834-028
SNR/SFDR (dBFS)
90
Figure 28. Input-Referred Noise Histogram
2.15
3
2.10
POWER DISSIPATION (W)
2
0
–1
L = 2, M = 1, F = 1
L = 4, M = 1, F = 1
2.00
1.95
1.90
1.85
1.80
–2
0
2000
4000
6000
8000
10000 12000 14000 16000
OUTPUT CODE
Figure 26. INL, fIN = 10.3 MHz
1.70
700
750
800
850
900
950
1000
1050
SAMPLE RATE (MHz)
Figure 29. Power Dissipation vs. Sample Rate (fS)
Rev. B | Page 17 of 78
1100
12834-029
1.75
–3
12834-026
INL (LSB)
1
2.05
AD9690
Data Sheet
AD9690-500
AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 2.06 V p-p
full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted.
See Table 10 for recommended settings.
0
0
AIN = −1dBFS
SNR = 68.9dBFS
ENOB = 10.9 BITS
SFDR = 83dBFS
BUFFER CONTROL 1 = 2.0×
–20
–20
–40
AMPLITUDE (dBFS)
–40
–60
–80
–100
–60
–80
–100
–120
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
–140
12834-030
–140
0
125
150
175
200
225
250
AIN = −1dBFS
SNR = 64.7dBFS
ENOB = 10.4 BITS
SFDR = 80dBFS
BUFFER CONTROL 1 = 5.0×
–20
–40
AMPLITUDE (dBFS)
–60
–80
–100
–120
–60
–80
–100
–120
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
–140
12834-031
–140
0
100
125
150
175
200
225
250
0
AIN = −1dBFS
SNR = 64.0dBFS
ENOB = 10.3 BITS
SFDR = 76dBFS
BUFFER CONTROL 1 = 5.0×
–20
–40
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–60
–80
–100
–120
0
25
50
75
100
125
150
175
200
225
FREQUENCY (MHz)
250
12834-032
–140
75
Figure 34. Single-Tone FFT with fIN = 765.3 MHz
AIN = −1dBFS
SNR = 68.5dBFS
ENOB = 10.9 BITS
SFDR = 83dBFS
BUFFER CONTROL 1 = 4.5×
–20
50
FREQUENCY (MHz)
Figure 31. Single-Tone FFT with fIN = 170.3 MHz
0
25
12834-034
AMPLITUDE (dBFS)
100
0
–40
AMPLITUDE (dBFS)
75
Figure 33. Single-Tone FFT with fIN = 450.3 MHz
AIN = −1dBFS
SNR = 68.9dBFS
ENOB = 11 BITS
SFDR = 88dBFS
BUFFER CONTROL 1 = 2.0×
–20
50
FREQUENCY (MHz)
Figure 30. Single-Tone FFT with fIN = 10.3 MHz
0
25
12834-033
–120
Figure 32. Single-Tone FFT with fIN = 340.3 MHz
–140
0
25
50
75
100
125
150
175
200
225
FREQUENCY (MHz)
Figure 35. Single-Tone FFT with fIN = 985.3 MHz
Rev. B | Page 18 of 78
250
12834-035
AMPLITUDE (dBFS)
AIN = −1dBFS
SNR = 67.8dBFS
ENOB = 10.8 BITS
SFDR = 83dBFS
BUFFER CONTROL 1 = 4.5×
Data Sheet
AD9690
95
0
AIN = −1dBFS
SNR = 63.0dBFS
ENOB = 10.0 BITS
SFDR = 69dBFS
BUFFER CONTROL 1 = 8.0×
90
SNR/SFDR (dBFS)
–60
–80
80
75
–100
70
–120
65
–140
0
25
50
75
100
125
150
175
200
250
225
FREQUENCY (MHz)
SNR
60
300 320 340 360 380 400 420 440 460 480 500 530 550
12834-036
AMPLITUDE (dBFS)
SFDR
85
–40
SAMPLE FREQUENCY (MHz)
12834-039
–20
Figure 39. SNR/SFDR vs. fS, fIN = 170.3 MHz; Buffer Control 1 = 2.0×
Figure 36. Single-Tone FFT with fIN = 1310.3 MHz
100
0
AIN = −1dBFS
SNR = 61.5dBFS
ENOB = 9.8 BITS
SFDR = 69dBFS
BUFFER CONTROL 1 = 8.0×
–20
90
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
–40
–60
–80
80
70
–100
60
0
25
50
75
100
125
150
175
200
225
50
10.3
12834-037
–140
250
FREQUENCY (MHz)
95.3
150.3
180.3
240.3
301.3
340.7
390.3
450.3
ANALOG INPUT FREQUENCY (MHz)
Figure 40. SNR/SFDR vs. fIN; fIN < 500 MHz;
Buffer Control 1 (0x018) = 2.0× and 4.5×
Figure 37. Single-Tone FFT with fIN = 1710.3 MHz
100
0
AIN = −1dBFS
SNR = 60.8dBFS
ENOB = 9.6 BITS
SFDR = 68dBFS
BUFFER CONTROL 1 = 8.0×
–20
90
SNR/SFDR (dBFS)
–40
–60
–80
–100
80
70
60
50
450.3
–140
0
25
50
75
100
125
150
175
200
FREQUENCY (MHz)
225
250
4.0× SNR
4.0× SFDR
8.0× SNR
8.0× SFDR
480.3
510.3
515.3
610.3
765.3
810.3
985.3 1010.3
ANALOG INPUT FREQUENCY (MHz)
Figure 41. SNR/SFDR vs. fIN; 500 MHz < fIN < 1 GHz;
Buffer Control 1 (0x018) = 4.0× and 8.0×
Figure 38. Single-Tone FFT with fIN = 1950.3 MHz
Rev. B | Page 19 of 78
12834-041
–120
12834-038
AMPLITUDE (dBFS)
2.0× SNR
2.0× SFDR
4.5× SNR
4.5× SFDR
12834-040
–120
AD9690
80
0
7.0× SNR
7.0× SFDR
8.0× SNR
8.0× SFDR
70
65
60
1950.3
–80
–120
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12
INPUT AMPLITUDE (dBFS)
Figure 45. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 184 MHz and fIN2 = 187 MHz
Figure 42. SNR/SFDR vs. fIN; 1 GHz < fIN < 2 GHz;
Buffer Control 1 (0x018) = 7.0× and 8.0×
0
0
AIN1 AND AIN2 = –7dBFS
SFDR = 88dBFS
IMD2 = 94dBFS
IMD3 = 88dBFS
BUFFER CONTROL 1 = 2.0×
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
–20
SFDR/IMD3 (dBc AND dBFS)
–20
–40
–60
–80
–40
–60
–80
50
100
150
250
200
FREQUENCY (MHz)
–120
–90
12834-043
0
–81
–72
–63
–54
–45
–36
–18
–9
AMPLITUDE (dBFS)
Figure 46. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with
fIN1 = 338 MHz and fIN2 = 341 MHz
Figure 43. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz
110
0
AIN1 AND AIN2 = –7dBFS
SFDR = 88dBFS
IMD2 = 88dBFS
IMD3 = 89dBFS
BUFFER CONTROL 1 = 4.5×
100
90
SNR/SFDR (dBc AND dBFS)
–20
–40
–60
–80
–100
80
70
60
50
40
30
20
10
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
0
–10
0
50
100
150
200
250
FREQUENCY (MHz)
–20
–90
12834-044
–120
–27
12834-046
–100
–100
–80
–70
–60
–50
–40
–30
–20
–10
INPUT AMPLITUDE (dBFS)
Figure 47. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz
Figure 44. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz
Rev. B | Page 20 of 78
0
12834-047
AMPLITUDE (dBFS)
–60
12834-045
1205.3
1810.3
1410.3
1600.3
ANALOG INPUT FREQUENCY (MHz)
12834-042
50
1010.3
AMPLITUDE (dBFS)
–40
–100
55
–120
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
–20
SFDR/IMD3 (dBc AND dBFS)
75
SNR/SFDR (dBFS)
Data Sheet
Data Sheet
AD9690
900000
95
2.06 LSB RMS
800000
SFDR
700000
NUMBER OF HITS
SNR/SFDR (dBFS)
90
85
80
75
600000
500000
400000
300000
200000
SNR
70
10
35
60
85
TEMPERATURE (°C)
0
OUTPUT CODE
Figure 48. SNR/SFDR vs. Temperature, fIN = 170.3 MHz
12834-051
–15
12834-048
65
–40
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
100000
Figure 51. Input-Referred Noise Histogram
1.55
3.0
2.5
L = 1, M = 1, F = 2
L = 2, M = 1, F = 2
1.50
2.0
1.45
POWER (W)
INL (LSB)
1.5
1.0
0.5
0
–0.5
1.40
1.35
1.30
–1.0
1.25
0
2000
4000
6000
8000
10000
12000
14000
16000
OUTPUT CODE
1.20
300 320 340 360 380 400 420 440 460 480 500 520 540
12834-049
–2.0
SAMPLE RATE (MHz)
Figure 49. INL, fIN = 10.3 MHz
Figure 52. Power Dissipation vs. fS
0.8
0.6
DNL (LSB)
0.4
0.2
0
–0.2
–0.4
–0.8
0
2000
4000
6000
8000
10000
12000
OUTPUT CODE
14000
16000
12834-050
–0.6
Figure 50. DNL, fIN = 15 MHz
Rev. B | Page 21 of 78
12834-052
–1.5
AD9690
Data Sheet
EQUIVALENT CIRCUITS
AVDD3
AVDD3
AVDD3
3pF 1.5pF
200Ω
VCM
BUFFER
EMPHASIS/SWING
CONTROL (SPI)
200Ω
DRVDD
AVDD3
AVDD3
DATA+
SERDOUTx+
x = 0, 1, 2, 3
VIN–
OUTPUT
DRIVER
DATA–
12834-053
AIN
CONTROL
(SPI)
3pF 1.5pF
SERDOUTx–
x = 0, 1, 2, 3
DRGND
Figure 53. Analog Inputs
Figure 56. Digital Outputs
AVDD1
DVDD
25Ω
CLK+
SYNCINB+
1kΩ
DGND
AVDD1
20kΩ
LEVEL
TRANSLATOR
25Ω
CLK–
DRGND
DRVDD
20kΩ
20kΩ
VCM = 0.85V
12834-054
DVDD
20kΩ
SYNCINB–
VCM = 0.85V
VCM
1kΩ
12834-057
67Ω
28Ω
200Ω
400Ω
10pF
SYNCINB± PIN
CONTROL (SPI)
DGND
Figure 54. Clock Inputs
Figure 57. SYNCINB± Inputs
AVDD1_SR
SYSREF+
1kΩ
SPIVDD
20kΩ
LEVEL
TRANSLATOR
AVDD1_SR
ESD
PROTECTED
SPIVDD
VCM = 0.85V
20kΩ
SCLK
1kΩ
30kΩ
1kΩ
Figure 55. SYSREF± Inputs
ESD
PROTECTED
12834-058
12834-055
SYSREF–
12834-056
67Ω
200Ω
28Ω
VIN+
Figure 58. SCLK Input
Rev. B | Page 22 of 78
Data Sheet
AD9690
SPIVDD
SPIVDD
ESD
PROTECTED
30kΩ
1kΩ
CSB
30kΩ
1kΩ
PDWN/
STBY
ESD
PROTECTED
12834-059
ESD
PROTECTED
Figure 59. CSB Input
PDWN
CONTROL (SPI)
Figure 62. PDWN/STBY Input
SPIVDD
ESD
PROTECTED
AVDD2
SDO
ESD
PROTECTED
SPIVDD
1kΩ
SDIO
12834-062
ESD
PROTECTED
SDI
V_1P0
ESD
PROTECTED
12834-060
ESD
PROTECTED
V_1P0 PIN
CONTROL (SPI)
Figure 63. V_1P0 Input/Output
Figure 60. SDIO Input
SPIVDD
ESD
PROTECTED
FD
FD
JESD LMFC
JESD SYNC~
TEMPERATURE DIODE
FD PIN CONTROL (SPI)
12834-061
ESD
PROTECTED
Figure 61. FD Outputs
Rev. B | Page 23 of 78
12834-063
30kΩ
AD9690
Data Sheet
THEORY OF OPERATION
The AD9690 has one analog input channel and two JESD204B
output lane pairs. The ADC is designed to sample wide bandwidth
analog signals of up to 2 GHz. The AD9690 is optimized for wide
input bandwidth, high sampling rate, excellent linearity, and
low power in a small package.
The ADC core features a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features a wide bandwidth input supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The AD9690 has several functions that simplify the AGC
function in a communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bit of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
The Subclass 1 JESD204B-based high speed serialized output data
rate can be configured in one-lane (L = 1), two-lane (L = 2), and
four-lane (L = 4) configurations, depending on the sample rate
and the decimation ratio. Multiple device synchronization is
supported through the SYSREF± and SYNCINB± input pins.
ADC ARCHITECTURE
The architecture of the AD9690 consists of an input buffered
pipelined ADC. The input buffer is designed to provide a
termination impedance to the analog input signal. This
termination impedance can be changed using the SPI to meet
the termination needs of the driver/amplifier. The default
termination value is set to 400 Ω. The equivalent circuit diagram of
the analog input termination is shown in Figure 53. The input
buffer is optimized for high linearity, low noise, and low power.
The input buffer provides a linear high input impedance (for
ease of drive) and reduces kickback from the ADC. The buffer
is optimized for high linearity, low noise, and low power. The
quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample; at the same time, the remaining stages operate with the
preceding samples. Sampling occurs on the rising edge of the clock.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9690 is a differential buffer. The
internal common-mode voltage of the buffer is 2.05 V. The
clock signal alternately switches the input circuit between
sample mode and hold mode.
When the input circuit is switched into sample mode, the signal
source must be capable of charging the sample capacitors and
settling within one-half of a clock cycle. A small resistor, in series
with each input, can help reduce the peak transient current
injected from the output stage of the driving source. In addition,
low Q inductors or ferrite beads can be placed on each leg of the
input to reduce high differential capacitance at the analog inputs
and, thus, achieve the maximum bandwidth of the ADC. Such use
of low Q inductors or ferrite beads is required when driving the
converter front end at high IF frequencies. Either a differential
capacitor or two single-ended capacitors can be placed on the
inputs to provide a matching passive network. This ultimately
creates a low-pass filter at the input, which limits unwanted
broadband noise. For more information, refer to the AN-742
Application Note, the AN-827 Application Note, and the Analog
Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005). In
general, the precise values depend on the application.
For best dynamic performance, the source impedances driving
VIN+ and VIN− must be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates a differential reference that defines the span of the
ADC core.
Maximum SNR performance is achieved by setting the ADC
to the largest span in a differential configuration. In the case
of the AD9690, the available span is programmable through
the SPI port from 1.46 V p-p to 2.06 V p-p differential, with
1.70 V p-p differential being the default for the AD9690-1000
and 2.06 V p-p differential being the default for the AD9690-500.
Differential Input Configurations
There are several ways to drive the AD9690, either actively or
passively. However, optimum performance is achieved by
driving the analog input differentially.
For applications where SNR and SFDR are key parameters,
differential transformer coupling is the recommended input
configuration (see Figure 64 and Table 9) because the noise
performance of most amplifiers is not adequate to achieve the
true performance of the AD9690.
For low to midrange frequencies, a double balun or double
transformer network (see Figure 64 and Table 9) is recommended
for optimum performance of the AD9690. For higher frequencies
in the second or third Nyquist zones, it is better to remove some
of the front-end passive components to ensure wideband operation
(see Figure 64 and Table 9).
Rev. B | Page 24 of 78
Data Sheet
AD9690
0.1µF
R1
R3
R2
C1
ADC
C2
R2
R1
0.1µF
0.1µF
R3
C1
12834-064
BALUN
NOTES
1. SEE TABLE 9 FOR COMPONENT VALUES.
Figure 64. Differential Transformer-Coupled Configuration for the AD9690
Table 9. Differential Transformer-Coupled Input Configuration Component Values
Device
AD9690-500
Frequency Range
DC to 250 MHz
250 MHz to 2 GHz
DC to 500 MHz
500 MHz to 2 GHz
AD9690-1000
Transformer
ETC1-1-13
BAL-0006/BAL-0006SMG
ECT1-1-13/BAL-0006SMG
BAL-0006/BAL-0006SMG
Input Common Mode
The analog inputs of the AD9690 are internally biased to the
common mode as shown in Figure 65. The common-mode
buffer has a limited range in that the performance suffers greatly
if the common-mode voltage drops by more than 100 mV.
Therefore, in dc-coupled applications, set the common-mode
voltage to 2.05 V, ±100 mV to ensure proper ADC operation.
The full-scale voltage setting must be at a 1.7 V p-p differential
if running in a dc-coupled application.
Analog Input Buffer Controls and SFDR Optimization
The AD9690 input buffer offers flexible controls for the analog
inputs, such as input termination, buffer current, and input fullscale adjustment. All the available controls are shown in Figure 65.
R1 (Ω)
10
10
25
25
R2 (Ω)
50
50
25
25
R3 (Ω)
10
10
10
0
C1 (pF)
4
4
4
Open
C2 (pF)
2
2
2
Open
Input Buffer Control Registers (0x018, 0x019, 0x01A,
0x935, 0x934, 0x11A)
The input buffer has many registers that set the bias currents and
other settings for operation at different frequencies. These bias
currents and settings can be changed to suit the input frequency
range of operation. Register 0x018 controls the buffer bias current
to help with the kickback from the ADC core. This setting can be
scaled from a low setting of 1.0× to a high setting of 8.5×. The
default setting is 3.0× for the AD9690-1000, and 2.0× for the
AD9690-500. These settings are sufficient for operation in the first
Nyquist zone for the products. When the input buffer current in
Register 0x018 is set, the amount of current required by the
AVDD3 supply changes. This relationship is shown in Figure 66.
For a complete list of buffer current settings, see Table 36.
AVDD3
300
AVDD3
AD9690-500
AD9690-1000
250
VCM
BUFFER
200Ω
67Ω
28Ω
200Ω
400Ω
10pF
200
AVDD3
3pF 1.5pF
IAVDD3 (mA)
200Ω
67Ω
200Ω
28Ω
VIN+
150
100
AVDD3
AVDD3
50
AIN CONTROL
SPI REGISTERS
(0x008, 0x015,
0x016, 0x018,
0x019, 0x01A,
0x11A, 0x934,
0x935)
0
1.5×
2.5×
3.5×
4.5×
5.5×
6.5×
7.5×
8.5×
BUFFER CONTROL 1 SETTING
12834-065
3pF 1.5pF
Figure 65. Analog Input Controls
Using the 0x018, 0x019, 0x01A, 0x11A, 0x934, and 0x935 registers,
the buffer behavior on each channel can be adjusted to optimize the
SFDR over various input frequencies and bandwidths of interest.
12834-066
VIN–
Figure 66. IAVDD3 vs. Buffer Control 1 Setting in Register 0x018
The 0x019, 0x01A, 0x11A, and 0x935 registers offer secondary
bias controls for the input buffer for frequencies >500 MHz.
Register 0x934 can be used to reduce input capacitance to achieve
wider signal bandwidth but may result in slightly lower linearity
and noise performance. These register settings do not impact the
AVDD3 power as much as Register 0x018 does. For frequencies
500 MHz for the AD9690-1000). This setting enables the ADC
sampling network to optimize the sampling and settling times
internal to the ADC for high frequency operation. For frequencies
greater than 500 MHz, it is recommended to operate the ADC core
at a 1.46 V full-scale setting irrespective of the speed grade. This
setting offers better SFDR without any significant penalty in SNR.
SFDR (dBFS)
70
4.5×
5.5×
6.5×
7.5×
8.5×
1607.4
1701.5
1795.6
12834-069
40
1513.4
1889.8
ANALOG INPUT FREQUENCY (MHz)
Figure 69. Buffer Current Sweeps, AD9690-1000 (SFDR vs. IBUFF);
1500 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 64
85
In certain high frequency applications, the SFDR can be improved
by reducing the full-scale setting, as shown in Table 10.
80
At high frequencies, the performance of the ADC core is limited
by jitter. The SFDR can be improved by backing off of the full
scale level. Figure 70 shows the SFDR and SNR vs. full-scale input
level at different high frequencies for the AD9690-1000.
75
70
65
80
60
1.5×
3.0×
4.5×
160
210
260
310
360
410
460
ANALOG INPUT FREQUENCY (MHz)
Figure 67. Buffer Current Sweeps, AD9690-1000 (SFDR vs. IBUFF);
fIN < 500 MHz; Front-End Network Shown in Figure 64
85
SFDR (dBFS)
75
110
12834-067
60
1.65GHz
1.52GHz
1.76GHz
1.95GHz
1.9GHz
75
70
70
65
65
4.0×
5.0×
6.0×
80
80
60
75
1.52GHz
1.65GHz
1.76GHz
1.9GHz
1.95GHz
SNR (dBc)
SFDR (dBFS)
55
45
90
50
10
60
50
Figure 67, Figure 68, and Figure 69 show the SFDR vs. analog
input frequency for various buffer settings for the AD9690-1000.
The recommended settings shown in Table 10 were used to take
the data while changing the contents of Register 0x018 only.
55
65
60
55
–3
65
–2
INPUT LEVEL (dBFS)
55
–1
12834-070
SFDR (dBFS)
70
60
Figure 70. SNR/SFDR vs. Analog Input Level vs. Input Frequencies, AD9690-1000
55
Figure 71, Figure 72, and Figure 73 show the SFDR vs. analog
input frequency for various buffer settings for the AD9690-500.
The recommended settings shown in Table 10 were used to take
the data while changing the contents of Register 0x018 only.
50
40
503.4
677.6
851.9
1026.2
1200.5
ANALOG INPUT FREQUENCY (MHz)
1374.8
12834-068
45
Figure 68. Buffer Current Sweeps, AD9690-1000 (SFDR vs. IBUFF);
500 MHz < fIN < 1500 MHz; Front-End Network Shown in Figure 64
Rev. B | Page 26 of 78
Data Sheet
AD9690
95
100
4.0×
5.0×
6.0×
7.0×
8.0×
90
90
80
SFDR (dBFS)
SFDR (dBFS)
85
80
70
60
75
50
480.3
510.3
515.3
610.3
765.3
810.3
985.3
ANALOG INPUT FREQUENCY (MHz)
30
10.3
12834-071
65
450.3
40
1.0×
1.5×
2.0×
3.0×
4.5×
95.3
150.3
180.3
240.3
301.3
340.7
390.3
450.3
ANALOG INPUT FREQUENCY (MHz)
Figure 71. Buffer Current Sweeps, AD9690-500 (SFDR vs. IBUFF);
450 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 64
12834-073
70
Figure 73. SFDR vs. fIN; Buffer Control 1 (0x018) = 1.0×, 1.5×, 2.0×, 3.0×, or 4.5×
80
75
SFDR (dBFS)
70
65
60
55
50
40
1010.3
4.0×
5.0×
6.0×
7.0×
8.0×
1205.3
1410.3
1600.3
1810.3
1950.3
ANALOG INPUT FREQUENCY (MHz)
12834-072
45
Figure 72. Buffer Current Sweeps, AD9690-500 (SFDR vs. IBUFF);
1 GHz < fIN < 2GHz; Front-End Network Shown in Figure 64
Table 10. Recommended Register Settings for SFDR Optimization at Different Input Frequencies
Product
AD9690500
AD96901000
1
2
Frequency
DC to
250 MHz
250 MHz to
500 MHz
500 MHz to
1 GHz
1 GHz to
2 GHz
DC to
150 MHz
DC to
500 MHz
500 MHz to
1 GHz
1 GHz to
2 GHz
Buffer
Control 1
(0x018)
0x20
Buffer
Control 2
(0x019)
0x60
Buffer
Control 3
(0x01A)
0x0A
Buffer
Control 4
(0x11A)
0x00
Buffer
Control 5
(0x935)
0x04
Input
Full-Scale
Range
(0x025)
0x0C
Input
Full-Scale
Control
(0x030)
0x04
Input
Termination
(0x016)1
0x0C/0x1C/…
Input
Capacitance
(0x934)
0x1F
0x70
0x60
0x0A
0x00
0x04
0x0C
0x04
0x0C/0x1C/…
0x1F
0x80
0x40
0x08
0x00
0x00
0x08
0x18
0x0C/0x1C/…
0xF0
0x40
0x08
0x00
0x00
0x08
0x18
0x0C/0x1C/…
0x10
0x50
0x09
0x00
0x04
0x0A
0x18
0x0E/0x1E/…
0x1F or
0x002
0x1F or
0x001
0x1F
0x40
0x50
0x09
0x00
0x04
0x0A
0x18
0x0E/0x1E/…
0x1F
0xA0
0x60
0x09
0x20
0x00
0x08
0x18
0x0E/0x1E/…
0xD0
0x70
0x09
0x20
0x00
0x08
0x18
0x0E/0x1E/…
0x1F or
0x001
0x1F or
0x001
The input termination can be changed to accommodate the application with little or no impact to ac performance.
The input capacitance can be set to 1.5 pF to achieve wider input bandwidth but results in slightly lower ac performance.
Rev. B | Page 27 of 78
AD9690
Data Sheet
Absolute Maximum Input Swing
The absolute maximum input swing allowed at the inputs of the
AD9690 is 4.3 V p-p differential. Signals operating near or at
this level can cause permanent damage to the ADC.
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9690. This internal 1.0 V reference is used to set the fullscale input range of the ADC. The full-scale input range can
be adjusted via the ADC Function Register 0x025. For more
information on adjusting the input swing, see Table 36. Figure 74
shows the block diagram of the internal 1.0 V reference controls.
For more information on adjusting the full-scale level of the
AD9690, refer to the Memory Map Register Table section.
The use of an external reference may be necessary, in some
applications, to enhance the gain accuracy of the ADC or
improve thermal drift characteristics. Figure 75 shows the
typical drift characteristics of the internal 1.0 V reference.
1.0010
1.0009
1.0008
V_1P0 VOLTAGE (V)
1.0007
VIN+
VIN–
1.0003
1.0002
1.0000
0.9998
V_1P0
–50
25
12834-074
Figure 74. Internal Reference Configuration and Controls
The SPI Register 0x024 enables the user to either use this internal
1.0 V reference, or to provide an external 1.0 V reference. When
using an external voltage reference, provide a 1.0 V reference.
The full-scale adjustment is made using the SPI, irrespective of
the reference voltage.
The external reference has to be a stable 1.0 V reference. The
ADR130 is a good option for providing the 1.0 V reference.
Figure 76 shows how the ADR130 can be used to provide the
external 1.0 V reference to the AD9690. The grayed out areas
show unused blocks within the AD9690 while using the
ADR130 to provide the external reference.
INTERNAL
V_1P0
GENERATOR
ADR130
FULL-SCALE
VOLTAGE
ADJUST
NC 6
1
NC
2
GND SET 5
3
VIN
VOUT 4
90
Figure 75. Typical V_1P0 Drift
V_1P0 PIN
CONTROL SPI
REGISTER
(0x025, 0x02,
AND 0x024)
0.1µF
0
TEMPERATURE (°C)
12834-075
0.9999
INPUT FULL-SCALE
RANGE ADJUST
SPI REGISTER
(0x025, 0x02,
AND 0x024)
INPUT
1.0004
1.0001
ADC
CORE
FULL-SCALE
VOLTAGE
ADJUST
1.0005
V_1P0
0.1µF
FULL-SCALE
CONTROL
Figure 76. External Reference Using ADR130
Rev. B | Page 28 of 78
12834-076
INTERNAL
V_1P0
GENERATOR
1.0006
Data Sheet
AD9690
CLOCK INPUT CONSIDERATIONS
Input Clock Divider
For optimum performance, drive the AD9690 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled to the CLK+ and CLK− pins via a
transformer or clock drivers. These pins are biased internally
and require no additional biasing.
The AD9690 contains an input clock divider with the ability to
divide the Nyquist input clock by 1, 2, 4, and 8. The divider
ratios can be selected using Register 0x10B. This is shown in
Figure 80.
Figure 77 shows a preferred method for clocking the AD9690.
The low jitter clock source is converted from a single-ended
signal to a differential signal using an RF transformer.
0.1µF
1:1Z
CLK+
CLK+
100Ω
CLK–
CLK–
0.1µF
÷2
÷4
÷8
Figure 77. Transformer-Coupled Differential Clock
Another option is to ac couple a differential CML or LVDS
signal to the sample clock input pins, as shown in Figure 78 and
Figure 79.
3.3V
71Ω
10pF
33Ω
33Ω
Z0 = 50Ω
0.1µF
CLK+
Z0 = 50Ω
0.1µF
0.1µF
0.1µF
LVDS
DRIVER
100Ω
50Ω1
50Ω1
Clock Fine Delay Adjust
ADC
CLK–
CLK–
CLOCK INPUT
150Ω
CLK+
CLK+
0.1µF
RESISTORS ARE OPTIONAL.
12834-079
0.1µF
The AD9690 clock divider can be synchronized using the external
SYSREF± input. A valid SYSREF± causes the clock divider to
reset to a programmable state. This synchronization feature
allows multiple devices to have their clock dividers aligned to
guarantee simultaneous input sampling.
The input clock divider inside the AD9690 provides phase delay
in increments of ½ the input clock cycle. Register 0x10C can be
programmed to enable this delay independently for each channel.
Changing this register does not affect the stability of the
JESD204B link.
Figure 78. Differential CML Sample Clock
CLOCK INPUT
Figure 80. Clock Divider Circuit
Input Clock Divider ½ Period Delay Adjust
12834-078
ADC
CLK–
REG 0x10B
12834-080
50Ω
ADC
12834-077
CLOCK
INPUT
The maximum frequency at the CLK± inputs is 4 GHz. This is
the limit of the divider. In applications where the clock input is
a multiple of the sample clock, care must be taken to program
the appropriate divider ratio into the clock divider before applying
the clock signal. This ensures that the current transients during
device startup are controlled.
Figure 79. Differential LVDS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. In applications where the clock duty cycle cannot
be guaranteed to be 50%, a higher multiple frequency clock can be
supplied to the device. The AD9690 can be clocked at 2 GHz with
the internal clock divider set to 2. The output of the divider offers
a 50% duty cycle, high slew rate (fast edge) clock signal to the
internal ADC. See the Memory Map section for more details on
using this feature.
The AD9690 sampling edge instant can be adjusted by writing to
Register 0x117 and Register 0x118. Setting Bit 0 of Register 0x117
enables the feature, and Bits[7:0] of Register 0x118 set the value
of the delay. This value can be programmed individually for
each channel. The clock delay can be adjusted from −151.7 ps
to +150 ps in ~1.7 ps increments. The clock delay adjust takes
effect immediately when it is enabled via SPI writes. Enabling
the clock fine delay adjust in Register 0x117 causes a datapath
reset. However, the contents of Register 0x118 can be changed
without affecting the stability of the JESD204B link.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fA) due only to aperture jitter (tJ) can be calculated by
SNR = 20 × log 10 (2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter specifications. IF
undersampling applications are particularly sensitive to jitter
(see Figure 81).
Rev. B | Page 29 of 78
AD9690
Data Sheet
In standby mode, the JESD204B link is not disrupted and
transmits zeroes for all converter samples. This can be changed
using Register 0x571, Bit 7 to select /K/ characters.
130
12.5fS
25fS
50fS
100fS
200fS
400fS
800fS
SNR (dB)
100
90
Temperature Diode
The AD9690 contains a diode-based temperature sensor for
measuring the temperature of the die. This diode can output a
voltage and serve as a coarse temperature sensor to monitor the
internal die temperature.
80
70
60
50
30
10
100
1000
10000
ANALOG INPUT FREQUENCY (MHz)
12834-081
40
Figure 81. Ideal SNR vs. Analog Input Frequency and Jitter
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9690. Separate
power supplies for clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
If the clock is generated from another type of source (by gating,
dividing, or other methods), retime the clock by the original clock
at the last step. Refer to the AN-501 Application Note and the
AN-756 Application Note for more in-depth information about
jitter performance as it relates to ADCs.
Power-Down/Standby Mode
The temperature diode voltage can be output to the FD pin
using the SPI. Use Register 0x028, Bit 0 to enable or disable the
diode. Configure the FD pin to output the diode voltage by
programming Register 0x040[2:0]. See Table 36 for more
information.
The voltage response of the temperature diode (SPIVDD =
1.8 V) is shown in Figure 82.
0.90
0.85
The AD9690 has a PDWN/STBY pin which can be used to
configure the device in power-down or standby mode. The
default operation is PDWN. The PDWN/STBY pin is a logic
high pin. When in power-down mode, the JESD204B link is
disrupted. The power-down option can also be set via
Register 0x03F and Register 0x040.
Rev. B | Page 30 of 78
0.80
0.75
0.70
0.65
0.60
–55 –45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115 125
TEMPERATURE (°C)
Figure 82. Temperature Diode Voltage vs. Temperature
12834-082
110
DIODE VOLTAGE (V)
120
Data Sheet
AD9690
ADC OVERRANGE AND FAST DETECT
The operation of the upper threshold and lower threshold
registers, along with the dwell time registers, is shown in
Figure 83.
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overrange bit in the JESD204B outputs provides
information on the state of the analog input that is of limited
usefulness. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip actually occurs. In addition, because input
signals can have significant slew rates, the latency of this
function is of major concern. Highly pipelined converters can
have significant latency. The AD9690 contains fast detect
circuitry to monitor the threshold and assert the FD pin.
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located at Register 0x247 and Register 0x248. The selected
threshold register is compared with the signal magnitude at the
output of the ADC. The fast upper threshold detection has a
latency of 28 clock cycles (maximum). The approximate upper
threshold magnitude is defined by
Upper Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/213)
ADC OVERRANGE
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange indicator can
be embedded within the JESD204B link as a control bit (when
CSB > 0). The latency of this overrange indicator matches the
sample latency.
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x249 and Register 0x24A. The fast
detect lower threshold register is a 13-bit register that is compared
with the signal magnitude at the output of the ADC. This
comparison is subject to the ADC pipeline latency, but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
The AD9690 also records any overrange condition in any of the
eight virtual converters. For more information on the virtual
converters, refer to Figure 88. The overrange status of each virtual
converter is registered as a sticky bit in Register 0x563. The
contents of Register 0x563 can be cleared using Register 0x562,
by toggling the bits corresponding to the virtual converter to set
and reset position.
Lower Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/213)
For example, to set an upper threshold of −6 dBFS, write 0xFFF
to Register 0x247 and Register 0x248. To set a lower threshold
of −10 dBFS, write 0xA1D to Register 0x249 and Register 0x24A.
FAST THRESHOLD DETECTION (FD)
The FD bit is immediately set whenever the absolute value of
the input signal exceeds the programmable upper threshold
level. The FD bit is only cleared when the absolute value of the
input signal drops below the lower threshold level for greater
than the programmable dwell time. This feature provides
hysteresis and prevents the FD bit from excessively toggling.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located at Register 0x24B and Register 0x24C.
See the Memory Map section (Register 0x040, and Register 0x245
to Register 0x24C in Table 36) for more details.
UPPER THRESHOLD
DWELL TIME
LOWER THRESHOLD
DWELL TIME
FD
Figure 83. Threshold Settings for FD Signals
Rev. B | Page 31 of 78
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
12834-083
MIDSCALE
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
AD9690
Data Sheet
SIGNAL MONITOR
The signal monitor block provides additional information about
the signal being digitized by the ADC. The signal monitor
computes the peak magnitude of the digitized signal. This
information can be used to drive an AGC loop to optimize the
range of the ADC in the presence of real-world signals.
The results of the signal monitor block can be obtained either by
reading back the internal values from the SPI port or by embedding
the signal monitoring information into the JESD204B interface as
special control bits. A 24-bit programmable period controls the
duration of the measurement. Figure 84 shows the simplified block
diagram of the signal monitor block.
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
(SMPR)
0x271, 0x272, 0x273
DOWN
COUNTER
IS
COUNT = 1?
LOAD
MAGNITUDE
STORAGE
REGISTER
LOAD
LOAD
SIGNAL
MONITOR
HOLDING
REGISTER
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register, which can be read through the memory map or output
through the SPORT over the JESD204B interface. The monitor
period timer is reloaded with the value in the SMPR, and the
countdown is restarted. In addition, the magnitude of the first
input sample is updated in the magnitude storage register, and
the comparison and update procedure, as explained previously,
continues.
SPORT OVER JESD204B
TO SPORT OVER
JESD204B AND
MEMORY MAP
12834-084
CLEAR
FROM
INPUT
The magnitude of the input signal is compared with the value in
the internal magnitude storage register (not accessible to the
user), and the greater of the two is updated as the current peak
level. The initial value of the magnitude storage register is set to
the current ADC input signal magnitude. This comparison
continues until the monitor period timer reaches a count of 1.
COMPARE
A>B
Figure 84. Signal Monitor Block
The peak detector captures the largest signal within the
observation period. The detector only observes the magnitude
of the signal. The resolution of the peak detector is a 13-bit
value, and the observation period is 24 bits and represents
converter output samples. The peak magnitude can be derived
by using the following equation:
Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)
The magnitude of the input port signal is monitored over a
programmable time period, which is determined by the signal
monitor period register (SMPR). The peak detector function is
enabled by setting Bit 1 of Register 0x270 in the signal monitor
control register. The 24-bit SMPR must be programmed before
activating this mode.
After enabling peak detection mode, the value in the SMPR is
loaded into a monitor period timer, which decrements at the
decimated clock rate.
The signal monitor data can also be serialized and sent over the
JESD204B interface as control bits. These control bits must be
deserialized from the samples to reconstruct the statistical data.
The signal control monitor function is enabled by setting Bits[1:0]
of Register 0x279 and Bit 1 of Register 0x27A. Figure 85 shows
two different example configurations for the signal monitor
control bit locations inside the JESD204B samples. A maximum
of three control bits can be inserted into the JESD204B samples;
however, only one control bit is required for the signal monitor.
Control bits are inserted from MSB to LSB. If only one control bit
is to be inserted (CS = 1), only the most significant control bit is
used (see Example Configuration 1 and Example Configuration 2
in Figure 85). To select the SPORT over JESD204B option,
program Register 0x559, Register 0x55A, and Register 0x58F.
See Table 36 for more information on setting these bits.
Figure 86 shows the 25-bit frame data that encapsulates the
peak detector value. The frame data is transmitted MSB first
with five 5-bit subframes. Each subframe contains a start bit
that can be used by a receiver to validate the deserialized data.
Figure 87 shows the SPORT over JESD204B signal monitor data
with a monitor period timer set to 80 samples.
Rev. B | Page 32 of 78
Data Sheet
AD9690
16-BIT JESD204B SAMPLE SIZE (N' = 16)
EXAMPLE
CONFIGURATION 1
(N' = 16, N = 15, CS = 1)
1-BIT
CONTROL
BIT
(CS = 1)
15-BIT CONVERTER RESOLUTION (N = 15)
15
S[14]
X
14
13
S[13]
X
S[12]
X
12
S[11]
X
11
9
10
S[10]
X
S[9]
X
8
7
S[7]
X
S[8]
X
6
S[6]
X
5
S[5]
X
4
S[4]
X
S[3]
X
3
S[2]
X
2
S[1]
X
1
0
S[0]
X
CTRL
[BIT 2]
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
16-BIT JESD204B SAMPLE SIZE (N' = 16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S[13]
X
S[12]
X
S[11]
X
S[10]
X
S[9]
X
S[8]
X
S[7]
X
S[6]
X
S[5]
X
S[4]
X
S[3]
X
S[2]
X
S[1]
X
S[0]
X
CTRL
[BIT 2]
X
TAIL
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
Figure 85. Signal Monitor Control Bit Locations
5-BIT SUB-FRAMES
5-BIT IDLE
SUB-FRAME
(OPTIONAL)
25-BIT
FRAME
IDLE
1
IDLE
1
IDLE
1
IDLE
1
IDLE
1
5-BIT IDENTIFIER START
0
SUB-FRAME
ID[3]
0
ID[2]
0
ID[1]
0
ID[0]
1
5-BIT DATA
MSB
SUB-FRAME
START
0
P[12]
P[11]
P[10]
P[9]
5-BIT DATA
SUB-FRAME
START
0
P[8]
P[7]
P[6]
P5]
5-BIT DATA
SUB-FRAME
START
0
P[4]
P[3]
P[2]
P1]
5-BIT DATA
LSB
SUB-FRAME
START
0
P[0]
0
0
0
P[] = PEAK MAGNITUDE VALUE
Figure 86. SPORT over JESD204B Signal Monitor Frame Data
Rev. B | Page 33 of 78
12834-086
EXAMPLE
CONFIGURATION 2
(N' = 16, N = 14, CS = 1)
12834-085
1
CONTROL
BIT
1 TAIL
(CS = 1)
BIT
14-BIT CONVERTER RESOLUTION (N = 14)
AD9690
Data Sheet
SMPR = 80 SAMPLES (0x271 = 0x50; 0x272 = 0x00; 0x273 = 0x00)
80 SAMPLE PERIOD
PAYLOAD #3
25-BIT FRAME (N)
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
80 SAMPLE PERIOD
PAYLOAD #3
25-BIT FRAME (N + 1)
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
80 SAMPLE PERIOD
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
Figure 87. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples
Rev. B | Page 34 of 78
12834-087
PAYLOAD #3
25-BIT FRAME (N + 2)
Data Sheet
AD9690
DIGITAL DOWNCONVERTER (DDC)
The AD9690 includes two digital downconverters (DDC 0 and
DDC 1) that provide filtering and reduce the output data rate.
This digital processing section includes an NCO, a half-band
decimating filter, an FIR filter, a gain stage, and a complex-real
conversion stage. Each of these processing blocks has control lines
that allow it to be independently enabled and disabled to provide
the desired processing function. The digital downconverter can
be configured to output either real data or complex output data.
DDC GENERAL DESCRIPTION
DDC I/Q INPUT SELECTION
The frequency translation stage consists of a 12-bit complex
NCO and quadrature mixers that can be used for frequency
translation of both real or complex input signals. This stage
shifts a portion of the available digital spectrum down to
baseband.
The AD9690 has one ADC channel and two DDC channels.
Each DDC channel has two input ports that can be paired to
support real inputs through the I/Q crossbar mux.
The inputs to each DDC are controlled by the DDC input
selection registers (Register 0x311, and Register 0x331). See
Table 36 for information on how to configure the DDCs.
The two DDC blocks are used to extract a portion of the full
digital spectrum captured by the ADC(s). They are intended for
IF sampling or oversampled baseband radios requiring wide
bandwidth input signals.
Each DDC block contains the following signal processing stages:
Frequency Translation Stage (Optional)
Filtering Stage
DDC I/Q OUTPUT SELECTION
Each DDC channel has two output ports that can be paired to
support both real or complex outputs. For real output signals,
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used.
The I/Q outputs to each DDC channel are controlled by the
DDC complex to real enable bit (Bit 3) in the DDC control
registers (Register 0x310, and Register 0x330).
After shifting down to baseband, the filtering stage decimates
the frequency spectrum using a chain of up to four half-band
low-pass filters for rate conversion. The decimation process
lowers the output data rate, which in turn reduces the output
interface rate.
Gain Stage (Optional)
Due to losses associated with mixing a real input signal down to
baseband, the gain stage compensates by adding an additional 0
dB or 6 dB of gain.
Complex to Real Conversion Stage (Optional)
The Chip Q ignore bit (Bit 5) in the chip application mode
register (Register 0x200) controls the chip output muxing of all
the DDC channels. When all DDC channels use real outputs,
this bit must be set high to ignore all DDC Q output ports.
When any of the DDC channels are set to use complex I/Q
outputs, the user must clear this bit to use both DDC Output
Port I and DDC Output Port Q. For more information, refer to
Figure 96.
When real outputs are necessary, the complex to real conversion
stage converts the complex outputs back to real by performing
an fS/4 mixing operation plus a filter to remove the complex
component of the signal.
Figure 88 shows the detailed block diagram of the DDCs
implemented in the AD9690.
Rev. B | Page 35 of 78
AD9690
Data Sheet
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
Q CONVERTER 1
REAL/Q Q
HB1 FIR
DCM = 2
HB2 FIR
DCM = BYPASS OR 2
I
HB3 FIR
DCM = BYPASS OR 2
DDC 1
REAL/I
Q CONVERTER 3
12834-088
SYSREF±
REAL/I
CONVERTER 2
OUTPUT INTERFACE
GAIN = 0dB
OR 6dB
REAL/I
CONVERTER 0
SYSREF±
NCO
+
MIXER
(OPTIONAL)
SYSREF
GAIN = 0dB
OR 6dB
HB1 FIR
DCM = 2
HB2 FIR
DCM = BYPASS OR 2
REAL/Q Q
HB3 FIR
DCM = BYPASS OR 2
NCO
+
MIXER
(OPTIONAL)
HB4 FIR
DCM = BYPASS OR 2
ADC
SAMPLING
AT fS
I/Q CROSSBAR MUX
REAL
I
HB4 FIR
DCM = BYPASS OR 2
DDC 0
REAL/I
SYNCHRONIZATION
CONTROL CIRCUITS
Figure 88. DDC Detailed Block Diagram
Figure 89 shows an example usage of one of the two DDC
blocks with a real input signal and four half-band filters (HB4,
HB3, HB2, and HB1). It shows both complex (decimate by 16)
and real (decimate by 8) output options.
When DDCs have different decimation ratios, the chip
decimation ratio (Register 0x201) must be set to the lowest
decimation ratio of all the DDC blocks.
In this scenario, samples of higher decimation ratio DDCs are
repeated to match the chip decimation ratio sample rate.
Whenever the NCO frequency is set or changed, the DDC soft
reset must be issued. If the DDC soft reset is not issued, the
output may potentially show amplitude variations.
Table 11, Table 12, Table 13, Table 14, and Table 15 show the
DDC samples when the chip decimation ratio is set to 1, 2, 4, 8,
or 16, respectively.
Rev. B | Page 36 of 78
Data Sheet
AD9690
ADC
ADC
SAMPLING
AT fS
REAL
REAL INPUT—SAMPLED AT fS
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
REAL
BANDWIDTH OF
INTEREST
–fS/32
fS/32
DC
fS/16
–fS/16
–fS/8
FREQUENCY TRANSLATION STAGE (OPTIONAL)
DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY
TUNING WORD = ROUND ((fS/3)/fS × 4096) = +1365 (0x555)
fS/8
fS/4
fS/3
fS/2
I
NCO TUNES CENTER OF
BANDWIDTH OF INTEREST
TO BASEBAND
cos(ωt)
REAL
12-BIT
NCO
90°
0°
–sin(ωt)
Q
DIGITAL FILTER
RESPONSE
–fS/2
–fS/3
–fS/4
BANDWIDTH OF INTEREST
(–6dB LOSS DUE TO
NCO + MIXER)
–fS/32
fS/32
DC
fS/16
–fS/16
–fS/8
BANDWIDTH OF
INTEREST IMAGE
(–6dB LOSS DUE TO
NCO + MIXER)
fS/8
fS/4
fS/3
fS/2
FILTERING STAGE
HB4 FIR
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1)
I
HALFBAND
FILTER
Q
HALFBAND
FILTER
HB3 FIR
2
HALFBAND
FILTER
2
HALFBAND
FILTER
HB4 FIR
HB2 FIR
2
HALFBAND
FILTER
2
HALFBAND
FILTER
HB3 FIR
HB1 FIR
2
HB2 FIR
HALFBAND
FILTER
I
HB1 FIR
2
HALFBAND
FILTER
Q
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
COMPLEX (I/Q) OUTPUTS
GAIN STAGE (OPTIONAL)
DIGITAL FILTER
RESPONSE
I
GAIN STAGE (OPTIONAL)
Q
0dB OR 6dB GAIN
COMPLEX TO REAL
CONVERSION STAGE (OPTIONAL)
fS/4 MIXING + COMPLEX FILTER TO REMOVE Q
–fS/32
fS/32
DC
fS/16
–fS/16
–fS/8
I
REAL (I) OUTPUTS
+6dB
+6dB
fS/8
2
+6dB
2
+6dB
I
Q
–fS/32
fS/32
DC
–fS/16
fS/16
DOWNSAMPLE BY 2
I
DECIMATE BY 8
Q
DECIMATE BY 16
0dB OR 6dB GAIN
Q
COMPLEX REAL/I
TO
REAL
–fS/8
–fS/32
fS/32
DC
–fS/16
fS/16
fS/8
Figure 89. DDC Theory of Operation Example (Real Input—Decimate by 16)
Rev. B | Page 37 of 78
12834-089
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
AD9690
Data Sheet
Table 11. DDC Samples, Chip Decimation Ratio = 1
HB1 FIR
(DCM1 = 1)
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N + 17
N + 18
N + 19
N + 20
N + 21
N + 22
N + 23
N + 24
N + 25
N + 26
N + 27
N + 28
N + 29
N + 30
N + 31
1
Real (I) Output (Complex to Real Enabled)
HB2 FIR +
HB3 FIR + HB2
HB4 FIR + HB3 FIR +
HB1 FIR
FIR + HB1 FIR
HB2 FIR + HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
N
N
N
N+1
N+1
N+1
N
N
N
N+1
N+1
N+1
N+2
N
N
N+3
N+1
N+1
N+2
N
N
N+3
N+1
N+1
N+4
N+2
N
N+5
N+3
N+1
N+4
N+2
N
N+5
N+3
N+1
N+6
N+2
N
N+7
N+3
N+1
N+6
N+2
N
N+7
N+3
N+1
N+8
N+4
N+2
N+9
N+5
N+3
N+8
N+4
N+2
N+9
N+5
N+3
N + 10
N+4
N+2
N + 11
N+5
N+3
N + 10
N+4
N+2
N + 11
N+5
N+3
N + 12
N+6
N+2
N + 13
N+7
N+3
N + 12
N+6
N+2
N + 13
N+7
N+3
N + 14
N+6
N+2
N + 15
N+7
N+3
N + 14
N+6
N+2
N + 15
N+7
N+3
Complex (I/Q) Outputs (Complex to Real Disabled)
HB1 FIR
(DCM1 = 2)
N
N+1
N
N+1
N+2
N+3
N+2
N+3
N+4
N+5
N+4
N+5
N+6
N+7
N+6
N+7
N+8
N+9
N+8
N+9
N + 10
N + 11
N + 10
N + 11
N + 12
N + 13
N + 12
N + 13
N + 14
N + 15
N + 14
N + 15
DCM = decimation.
Rev. B | Page 38 of 78
HB2 FIR +
HB1 FIR
(DCM1 = 4)
N
N+1
N
N+1
N
N+1
N
N+1
N+2
N+3
N+2
N+3
N+2
N+3
N+2
N+3
N+4
N+5
N+4
N+5
N+4
N+5
N+4
N+5
N+6
N+7
N+6
N+7
N+6
N+7
N+6
N+7
HB3 FIR + HB2
FIR + HB1 FIR
(DCM1 = 8)
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N+2
N+3
N+2
N+3
N+2
N+3
N+2
N+3
N+2
N+3
N+2
N+3
N+2
N+3
N+2
N+3
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 16)
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
N
N+1
Data Sheet
AD9690
Table 12. DDC Samples, Chip Decimation Ratio = 2
Real (I) Output (Complex to Real Enabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
N
N
N
N+1
N+1
N+1
N
N
N+2
N+1
N+1
N+3
N
+
2
N
N+4
N
+
3
N+1
N+5
N+2
N
N+6
N+3
N+1
N+7
N+4
N+2
N+8
N+5
N+3
N+9
N+4
N+2
N + 10
N+5
N+3
N + 11
N+6
N+2
N + 12
N+7
N+3
N + 13
N+6
N+2
N + 14
N+7
N+3
N + 15
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N
N
N
N
N+1
N+1
N+1
N+1
N+2
N
N
N
N+3
N+1
N+1
N+1
N+4
N+2
N
N
N+5
N+3
N+1
N+1
N+6
N+2
N
N
N+7
N+3
N+1
N+1
N+8
N+4
N+2
N
N+9
N+5
N+3
N+1
N + 10
N+4
N+2
N
N + 11
N+5
N+3
N+1
N + 12
N+6
N+2
N
N + 13
N+7
N+3
N+1
N + 14
N+6
N+2
N
N + 15
N+7
N+3
N+1
DCM = decimation.
Table 13. DDC Samples, Chip Decimation Ratio = 4
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR +
HB3 FIR + HB2 FIR +
HB2 FIR + HB1 FIR
HB1 FIR (DCM1 = 4)
(DCM1 = 8)
N
N
N+1
N+1
N
N+2
N+1
N+3
N+2
N+4
N+3
N+5
N+2
N+6
N+3
N+7
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
HB3 FIR + HB2 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 4)
HB1 FIR (DCM1 = 8)
(DCM1 = 16)
N
N
N
N+1
N+1
N+1
N+2
N
N
N+3
N+1
N+1
N+4
N+2
N
N+5
N+3
N+1
N+6
N+2
N
N+7
N+3
N+1
DCM = decimation.
Table 14. DDC Samples, Chip Decimation Ratio = 8
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8)
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB3 FIR + HB2 FIR + HB1 FIR
HB4 FIR + HB3 FIR + HB2 FIR +
(DCM1 = 8)
HB1 FIR (DCM1 = 16)
N
N
N+1
N+1
N+2
N
N+3
N+1
N+4
N+2
N+5
N+3
N+6
N+2
N+7
N+3
DCM = decimation.
Rev. B | Page 39 of 78
AD9690
Data Sheet
Table 15. DDC Samples, Chip Decimation Ratio = 16
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
Not applicable
Not applicable
Not applicable
Not applicable
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
N
N+1
N+2
N+3
DCM = decimation.
If the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs decimate by 4), and DDC 1 is
set to use HB4 + HB3 + HB2 + HB1 filters (real outputs decimate by 8), then DDC 1 repeats its output data two times for every one
DDC 0 output. The resulting output samples are shown in Table 16.
Table 16. DDC Output Samples when Chip DCM1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real)
DDC Input Samples
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
1
Output Port I
I0 [N]
DDC 0
Output Port Q
Q0 [N]
Output Port I
I1 [N]
DDC 1
Output Port Q
Not applicable
I0 [N + 1]
Q0 [N + 1]
I1 [N + 1]
Not applicable
I0 [N + 2]
Q0 [N + 2]
I1 [N]
Not applicable
I0 [N + 3]
Q0 [N + 3]
I1 [N + 1]
Not applicable
DCM = decimation.
Rev. B | Page 40 of 78
Data Sheet
AD9690
FREQUENCY TRANSLATION
GENERAL DESCRIPTION
Variable IF Mode
Frequency translation is accomplished by using a 12-bit
complex NCO along with a digital quadrature mixer. The
frequency translation translates either a real or complex input
signal from an intermediate frequency (IF) to a baseband
complex digital output (carrier frequency = 0 Hz).
NCO and mixers are enabled. NCO output frequency can be
used to digitally tune the IF frequency.
0 Hz IF (ZIF) Mode
Mixers are bypassed and the NCO disabled.
fS/4 Hz IF Mode
The frequency translation stage of each DDC can be controlled
individually and supports four different IF modes using Bits[5:4] of
the DDC control registers (Register 0x310, and Register 0x330).
These IF modes are
Test Mode
Input samples are forced to 0.999 to positive full scale. NCO is
enabled. This test mode allows the NCOs to directly drive the
decimation filters.
Variable IF mode
0 Hz IF (ZIF) mode
fS/4 Hz IF mode
Test mode
Figure 90 and Figure 91 show examples of the frequency
translation stage for both real and complex inputs.
NCO FREQUENCY TUNING WORD (FTW) SELECTION
12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096
I
ADC + DIGITAL MIXER + NCO
REAL INPUT—SAMPLED AT fS
REAL
ADC
SAMPLING
AT fS
cos(ωt)
REAL
12-BIT
NCO
90°
0°
COMPLEX
–sin(ωt)
Q
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
–fS/8
–fS/32
fS/32
DC
fS/16
–fS/16
fS/8
fS/4
fS/3
fS/2
–6dB LOSS DUE TO
NCO + MIXER
12-BIT NCO FTW =
ROUND ((fS/3)/fS × 4096) = +1365 (0x555)
POSITIVE FTW VALUES
–fS/32
DC
fS/32
12-BIT NCO FTW =
ROUND ((fS/3)/fS × 4096) = –1365 (0xAAB)
–fS/32
NEGATIVE FTW VALUES
DC
fS/32
Figure 90. DDC NCO Frequency Tuning Word Selection—Real Inputs
Rev. B | Page 41 of 78
12834-090
•
•
•
•
Mixers and NCO are enabled in special down mixing by fS/4
mode to save power.
AD9690
Data Sheet
NCO FREQUENCY TUNING WORD (FTW) SELECTION
12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096
QUADRATURE ANALOG MIXER +
2 ADCs + QUADRATURE DIGITAL REAL
MIXER + NCO
COMPLEX INPUT—SAMPLED AT fS
QUADRATURE MIXER
ADC
SAMPLING
AT fS
I
+
I
I
Q
Q
90°
PHASE
12-BIT
NCO
90°
0°
Q
Q
ADC
SAMPLING
AT fS
Q
Q
I
I
–
–sin(ωt)
I
I
+
COMPLEX
Q
+
BANDWIDTH OF
INTEREST
IMAGE DUE TO
ANALOG I/Q
MISMATCH
–fS/3
–fS/4
–fS/32
fS/32
fS/16
–fS/16
DC
–fS/8
fS/8
fS/4
fS/3
fS/2
12-BIT NCO FTW =
ROUND ((fS/3)/fS × 4096) = +1365 (0x555)
POSITIVE FTW VALUES
–fS/32
fS/32
12834-091
–fS/2
DC
Figure 91. DDC NCO Frequency Tuning Word Selection—Complex Inputs
DDC NCO PLUS MIXER LOSS AND SFDR
Setting Up the NCO FTW and POW
When mixing a real input signal down to baseband, 6 dB of loss
is introduced in the signal due to filtering of the negative image.
An additional 0.05 dB of loss is introduced by the NCO. The
total loss of a real input signal mixed down to baseband is 6.05 dB.
For this reason, it is recommended that the user compensate for
this loss by enabling the additional 6 dB of gain in the gain stage
of the DDC to recenter the dynamic range of the signal within
the full scale of the output bits.
The NCO frequency value is given by the 12-bit twos
complement number entered in the NCO FTW. Frequencies
between −fS/2 and fS/2 (fS/2 excluded) are represented using the
following frequency words:
When mixing a complex input signal down to baseband, the
maximum value each I/Q sample can reach is 1.414 × full scale
after it passes through the complex mixer. To avoid overrange
of the I/Q samples and to keep the data bitwidths aligned with
real mixing, 3.06 dB of loss (0.707 × full scale) is introduced in
the mixer for complex signals. An additional 0.05 dB of loss is
introduced by the NCO. The total loss of a complex input signal
mixed down to baseband is −3.11 dB.
The worst case spurious signal from the NCO is greater than
102 dBc SFDR for all output frequencies.
NUMERICALLY CONTROLLED OSCILLATOR
The AD9690 has a 12-bit NCO for each DDC that enables the
frequency translation process. The NCO allows the input
spectrum to be tuned to dc, where it can be effectively filtered
by the subsequent filter blocks to prevent aliasing. The NCO
can be set up by providing a frequency tuning word (FTW) and
a phase offset word (POW).
•
•
•
0x800 represents a frequency of –fS/2.
0x000 represents dc (frequency is 0 Hz).
0x7FF represents a frequency of +fS/2 – fS/212.
The NCO frequency tuning word can be calculated using the
following equation:
Mod( f C , f S )
NCO _ FTW = round 212
fS
where:
NCO_FTW is a 12-bit twos complement number representing
the NCO FTW.
fS is the AD9690 sampling frequency (clock rate) in Hz.
fC is the desired carrier frequency in Hz.
Mod( ) is a remainder function. For example, Mod(110,100) =
10, and for negative numbers, Mod(–32, 10) = –2.
round( ) is a rounding function. For example, round(3.6) = 4,
and for negative numbers, round(–3.4)= –3.
Note that this equation applies to the aliasing of signals in the
digital domain (that is, aliasing introduced when digitizing
analog signals).
Rev. B | Page 42 of 78
Data Sheet
AD9690
For example, if the ADC sampling frequency (fS) is 1250 MSPS
and the carrier frequency (fC) is 416.667 MHz,
Two methods can be used to synchronize multiple PAWs within
the chip:
Mod(416.667,1250
NCO _ FTW = round 212
= 1365 MHz
1250
•
This, in turn, converts to 0x555 in the 12-bit twos complement
representation for NCO_FTW. The actual carrier frequency can
be calculated based on the following equation:
f C − actual =
•
NCO _ FTW × f S
= 416.56 MHz
212
A 12-bit POW is available for each NCO to create a known phase
relationship between multiple AD9690 chips or individual DDC
channels inside one AD9690.
The following procedure must be followed to update the FTW
and/or POW registers to ensure proper operation of the NCO:
•
•
•
Write to the FTW registers for all the DDCs.
Write to the POW registers for all the DDCs.
Synchronize the NCOs either through the DDC soft reset
bit accessible through the SPI, or through the assertion of
the SYSREF± pin.
Note that the NCOs must be synchronized either through SPI
or through the SYSREF± pin after all writes to the FTW or POW
registers have completed. This synchronization is necessary to
ensure the proper operation of the NCO.
NCO Synchronization
Each NCO contains a separate phase accumulator word (PAW)
that determines the instantaneous phase of the NCO. The initial
reset value of each PAW is determined by the POW described
in the Setting Up the NCO FTW and POW section. The phase
increment value of each PAW is determined by the FTW.
Using the SPI. The DDC NCO soft reset bit in the DDC
synchronization control register (Register 0x300, Bit 4)
can be used to reset all the PAWs in the chip. This is
accomplished by toggling the DDC NCO soft reset bit.
This method can only be used to synchronize DDC
channels within the same AD9690 chip.
Using the SYSREF± pin. When the SYSREF± pin is enabled
in the SYSREF± control registers (Register 0x120 and
Register 0x121), and the DDC synchronization is enabled
in Bits[1:0] in the DDC synchronization control register
(Register 0x300), any subsequent SYSREF± event resets all
the PAWs in the chip. This method can be used to synchronize
DDC channels within the same AD9690 chip, or DDC
channels within separate AD9690 chips.
Mixer
The NCO is accompanied by a mixer, whose operation is
similar to an analog quadrature mixer. The mixer performs the
downconversion of input signals (real or complex) by using the
NCO frequency as a local oscillator. For real input signals, this
mixer performs a real mixer operation (with two multipliers).
For complex input signals, the mixer performs a complex mixer
operation (with four multipliers and two adders). The mixer
adjusts its operation based on the input signal (real or complex)
provided to each individual channel. The selection of real or
complex inputs can be controlled individually for each DDC
block by using Bit 7 of the DDC control register (Register 0x310,
and Register 0x330).
Rev. B | Page 43 of 78
AD9690
Data Sheet
FIR FILTERS
GENERAL DESCRIPTION
Table 17 shows the different bandwidth options by including
different half-band filters. In all cases, the DDC filtering stage of
the AD9690 provides less than −0.001 dB of pass-band ripple
and >100 dB of stop-band alias rejection.
There are four sets of decimate-by-2, low-pass, half-band, finite
impulse response (FIR) filters (HB1 FIR, HB2 FIR, HB3 FIR,
and HB4 FIR shown in Figure 88). These filters follow the
frequency translation stage. After the carrier of interest is tuned
down to dc (carrier frequency = 0 Hz), these filters efficiently lower
the sample rate while providing sufficient alias rejection from
unwanted adjacent carriers around the bandwidth of interest.
Table 18 shows the amount of stop-band alias rejection for
multiple pass-band ripple/cutoff points. The decimation ratio of
the filtering stage of each DDC can be controlled individually
through Bits[1:0] of the DDC control registers (0x310, and
0x330).
HB1 FIR is always enabled and cannot be bypassed. The HB2,
HB3, and HB4 FIR filters are optional and can be bypassed for
higher output sample rates.
Table 17. DDC Filter Characteristics
ADC
Sample
Rate
(MSPS)
1000
500
1
Half-Band
Filter
Selection
HB1
Real Output
Output
Sample
Decimation Rate
Ratio
(MSPS)
1
1000
Complex (I/Q) Output
Output
Sample
Decimation Rate
Ratio
(MSPS)
2
500 (I) +
500 (Q)
4
250 (I) +
250 (Q)
8
125 (I) +
125 (Q)
16
62.5 (I) +
62.5 (Q)
HB1 + HB2
2
500
HB1 + HB2
+ HB3
HB1 + HB2
+ HB3 +
HB4
HB1
4
250
8
125
1
500
2
HB1 + HB2
2
250
4
HB1 + HB2
+ HB3
HB1 + HB2
+ HB3 +
HB4
4
125
8
8
62.5
16
250 (I) +
250 (Q)
125 (I) +
125 (Q)
62.5 (I) +
62.5 (Q)
31.25 (I)
+ 31.25
(Q)
Alias
Protected
Bandwidth
(MHz)
385.0
Ideal SNR
Improvement
(dB)1
1
192.5
4
96.3
7
48.1
10
192.5
1
96.3
4
48.1
7
24.1
10
PassBand
Ripple
(dB)
100
90
85
63.3
25
19.3
10.7
1
Pass-Band Ripple/
Cutoff Point (dB)
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