AD9691BCPZRL7-1250

14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter AD9691 Data Sheet FUNCTIONAL BLOCK DIAGRAM FD_A FD_B VIN+B VIN–B V_1P0 BUFFER ADC CORE AVDD3 (3.3V) 14 AVDD_SR (1.25V) DVDD (1.25V) DIGITAL DOWNCONVERTER SIGNAL MONITOR ADC CORE 14 DIGITAL DOWNCONVERTER CONTROL REGISTERS BUFFER AD9691 AGND DRGND DGND JESD204B SUBCLASS 1 CONTROL SPI CONTROL ÷2 ÷4 ÷8 SDIO 8 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SERDOUT4± SERDOUT5± SERDOUT6± SERDOUT7± FAST DETECT SIGNAL MONITOR CLOCK GENERATION CLK+ CLK– SPIVDD DRVDD (1.25V) (1.8V TO 3.3V) SCLK SYNCINB± SYSREF± PDWN/ STBY CSB 13092-001 VIN+A VIN–A AVDD2 (2.50V) Tx OUTPUTS AVDD1 (1.25V) FAST DETECT JESD204B (Subclass 1) coded serial digital outputs 1.9 W total power per channel (default settings) SFDR = 77 dBFS at 340 MHz SNR = 63.4 dBFS at 340 MHz (AIN = −1.0 dBFS) Noise density = −152.6 dBFS/Hz 1.25 V, 2.50 V, and 3.3 V dc supply operation No missing codes 1.58 V p-p differential full scale input voltage Flexible termination impedance 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential 1.5 GHz usable analog input full power bandwidth 95 dB channel isolation/crosstalk Amplitude detection bits for efficient AGC implementation 2 integrated wideband digital processors per channel 12-bit NCO, up to 4 cascaded half-band filters Integer clock divide by 1, 2, 4, or 8 Flexible JESD204B lane configurations Timestamp feature Small signal dither JESD204B HIGH SPEED SERIALIZER FEATURES Figure 1. APPLICATIONS Communications (wideband receivers and digital predistortion) Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) DOCSIS 3.x CMTS upstream receive paths High speed data acquisition systems GENERAL DESCRIPTION The AD9691 is a dual, 14-bit, 1.25 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. The device is designed for sampling wide bandwidth analog signals of up to 1.5 GHz. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO) and four half-band decimation filters. In addition to the DDC blocks, the AD9691 has a programmable threshold detector that allows monitoring of the incoming signal power using the fast detect output bits of the ADC. Because Rev. 0 this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, four- or eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± input pins. The AD9691 is available in a Pb-free, 88-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. Low power consumption analog core, 14-bit, 1.25 GSPS dual ADC with 1.9 W per channel. Wide full power bandwidth supports intermediate frequency (IF) sampling of signals up to 1.5 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 12 mm × 12 mm, 88-lead LFCSP. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9691 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC NCO Plus Mixer Loss and SFDR ................................... 34 Applications ....................................................................................... 1 Numerically Controlled Oscillator .......................................... 34 General Description ......................................................................... 1 FIR Filters ........................................................................................ 36 Functional Block Diagram .............................................................. 1 General Description ................................................................... 36 Product Highlights ........................................................................... 1 Half-Band Filters ........................................................................ 37 Revision History ............................................................................... 2 DDC Gain Stage ......................................................................... 39 Specifications..................................................................................... 3 DDC Complex to Real Conversion Block............................... 39 DC Specifications ......................................................................... 3 DDC Example Configurations ................................................. 40 AC Specifications.......................................................................... 4 Digital Outputs ............................................................................... 43 Digital Specifications ................................................................... 5 Introduction to the JESD204B Interface ................................. 43 Switching Specifications .............................................................. 6 JESD204B Overview .................................................................. 43 Timing Specifications .................................................................. 7 Functional Overview ................................................................. 44 Absolute Maximum Ratings ............................................................ 9 JESD204B Link Establishment ................................................. 45 Thermal Characteristics .............................................................. 9 Physical Layer (Driver) Outputs .............................................. 47 ESD Caution .................................................................................. 9 Configuring the JESD204B Link .............................................. 48 Pin Configuration and Function Descriptions ........................... 10 Multichip Synchronization............................................................ 51 Typical Performance Characteristics ........................................... 12 SYSREF± Setup/Hold Window Monitor ................................. 52 Equivalent Circuits ......................................................................... 16 Test Modes ....................................................................................... 54 Theory of Operation ...................................................................... 18 ADC Test Modes ........................................................................ 54 ADC Architecture ...................................................................... 18 JESD204B Block Test Modes .................................................... 54 Analog Input Considerations.................................................... 18 Serial Port Interface ........................................................................ 57 Voltage Reference ....................................................................... 20 Configuration Using the SPI ..................................................... 57 Clock Input Considerations ...................................................... 21 Hardware Interface ..................................................................... 57 Power-Down/Standby Mode .................................................... 22 SPI Accessible Features .............................................................. 57 Temperature Diode .................................................................... 22 Memory Map .................................................................................. 58 ADC Overrange and Fast Detect .................................................. 23 Reading the Memory Map Register Table............................... 58 ADC Overrange .......................................................................... 23 Memory Map Register Table ..................................................... 59 Fast Threshold Detection (FD_A and FD_B) ........................ 23 Applications Information .............................................................. 71 Signal Monitor ................................................................................ 24 Power Supply Recommendations............................................. 71 Digital Downconverters (DDCs).................................................. 27 Exposed Pad Thermal Heat Slug Recommendations ............ 71 DDC I/Q Input Selection .......................................................... 27 AVDD1_SR (Pin 78) and AGND (Pin 77 and Pin 81) .............. 71 DDC I/Q Output Selection ....................................................... 27 Outline Dimensions ....................................................................... 72 DDC General Description ........................................................ 27 Ordering Guide .......................................................................... 72 Frequency Translation ................................................................... 33 General Description ................................................................... 33 REVISION HISTORY 7/15—Revision 0: Initial Version Rev. 0 | Page 2 of 72 Data Sheet AD9691 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Voltage INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage Range Common-Mode Voltage (VCM) Differential Input Capacitance Analog Input Full Power Bandwidth POWER SUPPLY AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD IAVDD1 IAVDD2 IAVDD3 IAVDD1_SR IDVDD 1 IDRVDD 2 ISPIVDD POWER CONSUMPTION Total Power Dissipation (Including Output Drivers)1 Power-Down Dissipation Standby 3 1 2 3 Temperature Full Full Full Full Full Full Full Full Min 14 −0.31 −6 −0.8 −6.5 Typ Max Unit Bits Guaranteed 0 0 0 1 ±0.5 ±2.6 +0.31 0.3 +6 3.9 +0.8 +6.5 % FSR % FSR % FSR % FSR LSB LSB 25°C 25°C −26 ±9.8 ppm/°C ppm/°C Full 1.0 V 25°C 3.53 LSB rms Full 25°C 25°C 25°C 1.58 2.05 1.5 2 V p-p V pF GHz Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Default mode. No DDCs used. L = 8, M = 2, and F = 1. All lanes running. Power dissipation on DRVDD changes with the lane rate and number of lanes used. Standby mode can be controlled by the SPI. Rev. 0 | Page 3 of 72 1.22 2.44 3.2 1.22 1.22 1.22 1.7 1.25 2.50 3.3 1.25 1.25 1.25 1.8 800 670 125 15 250 310 5 3.8 0.9 1.5 1.28 2.56 3.4 1.28 1.28 1.28 3.4 840 770 140 18 290 380 6 V V V V V V V mA mA mA mA mA mA mA W mW W AD9691 Data Sheet AC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 2. Parameter 1 ANALOG INPUT FULL SCALE NOISE DENSITY 2 SIGNAL-TO-NOISE RATIO (SNR) 3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz SNR AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz Temperature Full Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C Rev. 0 | Page 4 of 72 Min 60.8 60.5 9.7 72 Typ 1.58 −152.6 Max Unit V p-p dBFS/Hz 64.6 64.2 63.4 62.9 61.7 59.7 58.3 56.5 55.1 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 64.5 64.0 63.0 62.3 61.3 59.4 57.5 55.8 54.7 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 10.4 10.3 10.2 10.1 9.9 9.6 9.2 9.0 8.8 Bits Bits Bits Bits Bits Bits Bits Bits Bits 87 79 77 72 73 72 66 66 69 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Data Sheet AD9691 Parameter 1 WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 750 MHz fIN = 985 MHz fIN = 1205 MHz fIN = 1600 MHz fIN = 1950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz, Buffer Current Setting = 3.5× fIN1 = 449 MHz, fIN2 = 452 MHz, Buffer Current Setting = 6.5× CHANNEL ISOLATION/CROSSTALK 4 FULL POWER BANDWIDTH 5 Temperature Min Typ 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C −87 −84 −77 −72 −73 −72 −66 −66 −69 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C −93 −81 −79 −81 −77 −76 −72 −72 −73 25°C 25°C 25°C 25°C 82 78 95 1.5 Max −72 −76 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB GHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 10 for the recommended settings for full-scale voltage and buffer current control. 4 Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel. 5 Measured with the circuit shown in Figure 41. 1 2 DIGITAL SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 3. Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance SYSTEM REFERENCE INPUTS (SYSREF+, SYSREF−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) Temperature Full Full Full Full Full Full Full Full Full Full Rev. 0 | Page 5 of 72 Min 600 Typ LVDS/LVPECL 1200 0.85 35 Max Unit 1800 mV p-p V kΩ pF 2.5 400 0.6 LVDS/LVPECL 1200 0.85 35 1800 2.0 2.5 mV p-p V kΩ pF AD9691 Parameter LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUT (SDIO) Logic Compliance Logic 1 Voltage (IOH = 800 µA) Logic 0 Voltage (IOL = 50 µA) SYNC INPUTS (SYNCINB+, SYNCINB−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC OUTPUTS (FD_A, FD_B) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7) Logic Compliance Differential Output Voltage Output Common-Mode Voltage (VCM), AC-Coupled Short-Circuit Current (IDSHORT) Differential Return Loss (RLDIFF) 1 Common-Mode Return Loss (RLCM)1 Differential Termination Impedance 1 Data Sheet Temperature Min Typ Full Full Full Full 0.8 × SPIVDD 0 Max Unit 0.5 V V kΩ CMOS 30 Full Full Full CMOS 0.8 × SPIVDD 0 Full Full Full Full Full 400 0.6 Full Full Full Full V V 0.5 LVDS/LVPECL/CMOS 1200 1800 0.85 2.0 35 2.5 mV p-p V kΩ pF CMOS 0.8 × SPIVDD 0 V V kΩ 0.5 30 Full Full 25°C 25°C 25°C 25°C Full CML 360 0 −100 8 6 80 770 1.8 +100 100 mV p-p V mA dB dB Ω 120 Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate. SWITCHING SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted. Table 4. Parameter CLOCK Clock Rate (at CLK+/CLK− Pins) Maximum Sample Rate 1 Minimum Sample Rate 2 Clock Pulse Width High Low OUTPUT PARAMETERS Unit Interval (UI) 3 Rise Time (tR) (20% to 80% into 100 Ω Load) Fall Time (tF) (20% to 80% into 100 Ω Load) PLL Lock Time Data Rate per Channel (NRZ) 4 Temperature Min Full Full Full 0.3 1250 300 Full Full 400 400 Full 25°C 25°C 25°C 25°C 320 24 24 Rev. 0 | Page 6 of 72 3.125 Typ Max Unit 4 GHz MSPS MSPS ps ps 160 32 32 2 6.25 12.5 ps ps ps ms Gbps Data Sheet AD9691 Parameter LATENCY 5 Pipeline Latency Fast Detect Latency Wake-Up Time 6 Standby Power-Down APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tj) Out-of-Range Recovery Time Temperature Min Typ Full Full 55 25°C 25°C 1 Full Full Full 530 55 1 Max Unit 28 Clock cycles Clock cycles 4 ms ms ps fs rms Clock cycles The maximum sample rate is the clock rate after the divider. The minimum sample rate operates at 300 MSPS with L = 1. 3 Baud rate = 1/UI. A subset of this range is supported by the AD9691. 4 Default L = 8. This number can be changed based on the sample rate and decimation ratio. 5 No DDCs used. L = 8, M = 2, and F = 1. 6 Wake-up time is the time required to return to normal operation from power-down mode. 1 2 TIMING SPECIFICATIONS Table 5. Parameter CLK+ to SYSREF+ TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Test Conditions/Comments See Figure 2 Device clock to SYSREF+ setup time Device clock to SYSREF+ hold time See Figure 3 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK signal Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 3) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 3) Min Typ 117 −96 Max Unit ps ps 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns Timing Diagrams CLK– CLK+ tSU_SR tH_SR 13092-002 SYSREF– SYSREF+ Figure 2. SYSREF+ Setup and Hold Timing Diagram Rev. 0 | Page 7 of 72 AD9691 Data Sheet tHIGH tDS tS tCLK tDH tH tLOW CSB SDIO DON’T CARE DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 13092-003 SCLK DON’T CARE DON’T CARE Figure 3. SPI Timing Diagram APERTURE DELAY SAMPLE N N – 55 ANALOG INPUT SIGNAL N+1 N – 54 N–1 N – 53 N – 52 CLK– CLK+ CLK– CLK+ SERDOUT0– A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 LSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER0 LSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 MSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 LSB A B C D E F G H I J A B C D E F G H I J A B C D E F G H I J CONVERTER1 LSB SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ SERDOUT4– SERDOUT4+ SERDOUT5– SERDOUT5+ SERDOUT6– SERDOUT6+ SERDOUT7– SAMPLE N – 55 ENCODED INTO 1 8B/10B SYMBOL SAMPLE N – 54 ENCODED INTO 1 8B/10B SYMBOL SAMPLE N – 53 ENCODED INTO 1 8B/10B SYMBOL Figure 4. Data Output Timing (Full Bandwidth Mode, L = 8, M = 2, F = 1) Rev. 0 | Page 8 of 72 13092-004 SERDOUT7+ Data Sheet AD9691 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD1 to AGND AVDD1_SR to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD to DRGND SPIVDD to AGND AGND to DRGND VIN±x to AGND SCLK, SDIO, CSB to AGND PDWN/STBY to AGND Environmental Operating Temperature Range Maximum Junction Temperature Storage Temperature Range (Ambient) Rating 1.32 V 1.32 V 2.75 V 3.63 V 1.32 V 1.32 V 3.63 V −0.3 V to +0.3 V 3.2 V −0.3 V to SPIVDD + 0.3 V −0.3 V to SPIVDD + 0.3 V −40°C to +85°C 115°C −65°C to +150°C Typical θJA, ΨJB, θJC_TOP, and θJC_BOT values are specified vs. the number of printed circuit board (PCB) layers in different airflow velocities (in m/sec). Airflow increases heat dissipation effectively reducing θJA and ΨJB. The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 7. Table 7. PCB Type JEDEC 2s2p Board Airflow Velocity (m/sec) 0.0 1.0 2.5 ΨJB1, 3 4.70 4.32 4.21 θJC_TOP1, 4 6.01 N/A5 N/A5 θJC_BOT1, 4 1.12 N/A5 N/A5 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per JEDEC JESD51-8 (still air). 4 Per MIL-STD 883, Method 1012.1. 5 N/A means not applicable. 1 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. θJA1, 2 17.41 13.83 12.47 ESD CAUTION Rev. 0 | Page 9 of 72 Unit °C/W °C/W °C/W AD9691 Data Sheet 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 DNC AVDD1 AVDD2 DNC AVDD2 AVDD1 DNC AGND SYSREF– SYSREF+ AVDD1_SR AGND AVDD1 CLK– CLK+ DNC AVDD1 AVDD2 DNC AVDD2 AVDD1 DNC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 AD9691 TOP VIEW (Not to Scale) AVDD1 AVDD1 AVDD2 AVDD3 VIN–B VIN+B AVDD3 AVDD2 AVDD2 AVDD2 SPIVDD CSB SCLK SDIO DVDD DGND DNC DNC DNC DNC FD_B DNC NOTES 1. DNC = DO NOT CONNECT. THESE PINS MUST BE LEFT UNCONNECTED. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE GROUND REFERENCE FOR AVDDX. THE EXPOSED THERMAL PAD MUST BE CONNECTED TO AGND. 13092-005 DRGND DRVDD SYNCINB– SYNCINB+ SERDOUT0– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ SERDOUT4– SERDOUT4+ SERDOUT5– SERDOUT5+ SERDOUT6– SERDOUT6+ SERDOUT7– SERDOUT7+ DRVDD DRGND 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 AVDD1 AVDD1 AVDD2 AVDD3 VIN–A VIN+A AVDD3 AVDD2 AVDD2 AVDD2 AVDD2 V_1P0 SPIVDD PWDN/STBY DVDD DGND DNC DNC DNC DNC FD_A DNC Figure 5. Pin Configuration Table 8. Pin Function Descriptions Pin No. Power Supplies 0 Mnemonic Type Description EPAD Ground 1, 2, 65, 66, 68, 72, 76, 83, 87 3, 8, 9, 10, 11, 57, 58, 59, 64, 69, 71, 84, 86 4, 7, 60, 63 13, 56 15, 52 16, 51 23, 44 24, 43 77, 81 78 Analog 5, 6 12 AVDD1 AVDD2 Supply Supply Exposed Pad. The exposed thermal pad on the bottom of the package provides the ground reference for AVDDx. The exposed thermal pad must be connected to AGND. Analog Power Supply (1.25 V Nominal). Analog Power Supply (2.50 V Nominal). AVDD3 SPIVDD DVDD DGND DRGND DRVDD AGND 1 AVDD1_SR1 Supply Supply Supply Ground Ground Supply Ground Supply Analog Power Supply (3.3 V Nominal). Digital Power Supply for SPI (1.8 V to 3.3 V). Digital Power Supply (1.25 V Nominal). Ground Reference for DVDD. Ground Reference for DRVDD. Digital Driver Power Supply (1.25 V Nominal). Ground Reference for SYSREF±. Analog Power Supply for SYSREF± (1.25 V Nominal). VIN−A, VIN+A V_1P0 Input Input/DNC VIN+B, VIN−B CLK+, CLK− Input Input ADC A Analog Input Complement/True. 1.0 V Reference Voltage Input/Do Not Connect. This pin is configurable through the SPI as a no connect or as an input. Do not connect this pin if using the internal reference. This pin requires a 1.0 V reference voltage input if using an external voltage reference source. ADC B Analog Input True/Complement. Clock Input True/Complement. 61, 62 74, 75 Rev. 0 | Page 10 of 72 Data Sheet Pin No. CMOS Outputs 21, 46 Digital Inputs 25, 26 79, 80 Data Outputs 27, 28 29, 30 31, 32 33, 34 35, 36 37, 38 39, 40 41, 42 Device Under Test (DUT) Controls 14 53 54 55 No Connections 17, 18, 19, 20, 22, 45, 47, 48, 49, 50, 67, 70, 73, 82, 85, 88 1 AD9691 Mnemonic Type Description FD_A, FD_B Output Fast Detect Outputs for Channel A and Channel B, respectively. SYNCINB−, SYNCINB+ SYSREF+, SYSREF− Input Input Active Low JESD204B LVDS Sync Input Complement/True. Active Low JESD204B LVDS System Reference Input True/Complement. SERDOUT0−, SERDOUT0+ SERDOUT1−, SERDOUT1+ SERDOUT2−, SERDOUT2+ SERDOUT3−, SERDOUT3+ SERDOUT4−, SERDOUT4+ SERDOUT5−, SERDOUT5+ SERDOUT6−, SERDOUT6+ SERDOUT7−, SERDOUT7+ Output Output Output Output Output Output Output Output Lane 0 Output Data Complement/True. Lane 1 Output Data Complement/True. Lane 2 Output Data Complement/True. Lane 3 Output Data Complement/True. Lane 4 Output Data Complement/True. Lane 5 Output Data Complement/True. Lane 6 Output Data Complement/True. Lane 7 Output Data Complement/True. PDWN/STBY Input SDIO SCLK CSB Input/output Input Input Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as powerdown or standby. SPI Serial Data Input/Output. SPI Serial Clock. SPI Chip Select (Active Low). DNC Do No Connect. These pins must be left unconnected. To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, see the Applications Information section. Rev. 0 | Page 11 of 72 AD9691 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.50 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (1250 MSPS), 1.58 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted. 0 0 AIN = –1dBFS SNR = 64.6dBFS ENOB = 10.4 BITS SFDR = 87dBFS BUFFER CURRENT = 3.5× –40 –60 –80 –40 –60 –80 13092-006 0 125 375 250 FREQUENCY (MHz) 500 –120 625 13092-009 –100 –100 –120 AIN = –1dBFS SNR = 62.9dBFS ENOB = 10.0 BITS SFDR = 72dBFS BUFFER CURRENT = 3.5× –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 0 Figure 6. Single-Tone FFT with fIN = 10.3 MHz AIN = –1dBFS SNR = 64.2dBFS ENOB = 10.3 BITS SFDR = 79dBFS BUFFER CURRENT = 3.5× –40 AMPLITUDE (dBFS) –60 –80 –40 –60 –80 –100 13092-007 0 125 375 250 FREQUENCY (MHz) 500 –120 625 13092-010 AMPLITUDE (dBFS) 625 AIN = –1dBFS SNR = 61.7dBFS ENOB = 9.9 BITS SFDR = 73dBFS BUFFER CURRENT = 4.5× –20 –100 0 125 375 250 FREQUENCY (MHz) 500 625 Figure 10. Single-Tone FFT with fIN = 752.3 MHz Figure 7. Single-Tone FFT with fIN = 170.3 MHz 0 0 AIN = –1dBFS SNR = 63.4dBFS ENOB = 10.2 BITS SFDR = 77dBFS BUFFER CURRENT = 3.5× AIN = –1dBFS SNR = 59.7dBFS ENOB = 6.9 BITS SFDR = 72dBFS BUFFER CURRENT = 4.5× –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –40 –60 –80 –100 13092-008 –100 0 125 375 250 FREQUENCY (MHz) 500 –120 625 13092-011 AMPLITUDE (dBFS) 500 0 –20 –120 375 250 FREQUENCY (MHz) Figure 9. Single-Tone FFT with fIN = 450.3 MHz 0 –120 125 0 125 375 250 FREQUENCY (MHz) 500 Figure 11. Single-Tone FFT with fIN = 985.3 MHz Figure 8. Single-Tone FFT with fIN = 340.3 MHz Rev. 0 | Page 12 of 72 625 Data Sheet AD9691 0 85 –40 SFDR 75 SNR/SFDR (dBFS) –60 –80 65 SNR 60 –100 13092-012 55 –120 0 125 250 375 FREQUENCY (MHz) 500 50 1000 625 1050 1100 1150 1200 1250 SAMPLE RATE (MHz) Figure 15. SNR/SFDR vs. Sample Rate (fS), fIN = 170.3 MHz, Buffer Current = 3.0× Figure 12. Single-Tone FFT with fIN = 1205.3 MHz 90 0 AIN = –1dBFS SNR = 56.5dBFS ENOB = 9.0 BITS SFDR = 66dBFS BUFFER CURRENT = 5.5× –20 85 80 –40 SNR/SFDR (dBFS) AMPLITUDE (dBFS) 70 13092-015 AMPLITUDE (dBFS) 80 AIN = –1dBFS SNR = 58.2dBFS ENOB = 9.3 BITS SFDR = 67dBFS BUFFER CURRENT = 4.5× –20 –60 –80 SFDR 75 70 SNR 65 60 –100 600.3 500.3 470.3 440.3 410.3 380.3 350.3 320.3 290.3 260.3 230.3 200.3 50 625 170.3 500 130.3 250 375 FREQUENCY (MHz) 100.3 125 9.6 0 70.3 –120 13092-016 13092-013 55 INPUT FREQUENCY (MHz) Figure 13. Single-Tone FFT with fIN = 1600.3 MHz Figure 16. SNR/SFDR vs. Input Frequency (fIN), fIN < 600 MHz, Buffer Current = 3.5× (See Figure 41 and Table 9) 80 0 AIN = –1dBFS SNR = 56.5dBFS ENOB = 9.0 BITS SFDR = 66dBFS BUFFER CURRENT = 7.5× 75 SFDR SNR/SFDR (dBFS) –40 –60 –80 70 65 SNR 60 –120 0 125 250 375 FREQUENCY (MHz) 500 Figure 14. Single-Tone FFT with fIN = 1950.3 MHz 50 700.3 625 13092-017 55 –100 13092-014 AMPLITUDE (dBFS) –20 800.3 900.3 1000.3 1100.3 1200.3 INPUT FREQUENCY (MHz) Figure 17. SNR/SFDR vs. Input Frequency (fIN), 700 MHz < fIN < 1200 MHz, Buffer Current = 4.5× (See Figure 41 and Table 9) Rev. 0 | Page 13 of 72 AD9691 Data Sheet 0 75 SFDR SFDR (dBc) –20 65 60 SNR –40 –60 IMD3 (dBc) –80 SFDR (dBFS) –100 55 IMD3 (dBFS) 50 1300.3 13092-018 –120 1400.3 1500.3 1600.3 1700.3 1800.3 1900.3 –140 –80 –74 –68 –62 –56 –50 –44 –38 –32 –26 –20 –14 1990.3 Figure 21. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz Figure 18. SNR/SFDR vs. Input Frequency (fIN), 1300 MHz < fIN < 2000 MHz, Buffer Current = 7.5× (See Figure 41 and Table 9) 0 0 SFDR/IMD3 (dBc AND dBFS) –40 –60 –80 –100 500 625 Figure 22. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 449 MHz and fIN2 = 452 MHz 110 AIN1 AND AIN2 = –7dBFS SFDR = 78dBFS IMD2 = 77dBFS IMD3 = 78dBFS BUFFER CURRENT = 6.5× –80 13092-020 –100 SNR (dBFS) 60 50 SFDR (dBc) 40 30 SNR (dBc) 20 10 ANALOG INPUT LEVEL (dBFS) Figure 20. Two-Tone FFT, fIN1 = 449 MHz, fIN2 = 452 MHz Figure 23. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz, Buffer Current = 3.5× Rev. 0 | Page 14 of 72 0 –5 –10 –15 –20 –25 –30 –35 –40 0 625 –45 500 70 –65 –120 80 13092-023 SNR/SFDR (dBc AND dBFS) 90 –60 250 375 FREQUENCY (MHz) SFDR (dBFS) 100 –40 125 –8 INPUT AMPLITUDE (dBFS) 0 0 SFDR (dBFS) –100 IMD3 (dBFS) –140 –80 –74 –68 –62 –56 –50 –44 –38 –32 –26 –20 –14 Figure 19. Two-Tone FFT, fIN1 = 184 MHz, fIN2 = 187 MHz –20 –80 –50 250 375 FREQUENCY (MHz) IMD3 (dBc) –55 125 –60 –60 0 –40 –120 13092-019 –120 SFDR (dBc) –20 13092-022 AIN1 AND AIN2 = –7dBFS SFDR = 82dBFS IMD2 = 82dBFS IMD3 = 84dBFS BUFFER CURRENT = 3.5× –20 AMPLITUDE (dBFS) –8 INPUT AMPLITUDE (dBFS) INPUT FREQUENCY (MHz) AMPLITUDE (dBFS) 13092-021 SFDR/IMD3 (dBc AND dBFS) SNR/SFDR (dBFS) 70 Data Sheet 80 1000000 78 900000 SFDR 800000 NUMBER OF HITS 74 72 70 68 66 SNR 64 13092-024 600000 500000 400000 300000 20 60 40 100000 0 80 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 0 –20 700000 200000 62 60 –40 3.53 LSB RMS 13092-027 76 SNR/SFDR (dBFS) AD9691 TEMPERATURE (°C) OUTPUT CODE Figure 24. SNR/SFDR vs. Temperature, fIN = 170.3 MHz Figure 27. Input Referred Noise Histogram 4.00 2.5 2.0 3.95 1.5 0.5 POWER (W) INL (LSB) 1.0 0 –0.5 3.90 3.85 –1.0 0 2000 4000 8000 10000 6000 OUTPUT CODE 12000 14000 3.75 –40 16000 60 80 Figure 28. Power vs. Temperature 4.05 0.8 4.00 13092-029 SAMPLE RATE (MHz) Figure 26. DNL, fIN = 10 MHz Figure 29. Power Dissipation vs. Sample Rate (fS) Rev. 0 | Page 15 of 72 1300 3.60 1280 16000 1260 14000 1240 12000 1220 6000 8000 10000 OUTPUT CODE 1180 4000 1200 2000 3.65 1160 0 3.70 1000 13092-026 –0.6 3.75 1140 –0.4 3.80 1120 –0.2 3.85 1100 0 3.90 1080 0.2 1040 POWER DISSIPATION (W) 0.4 3.95 1020 0.6 DNL (LSB) 40 20 TEMPERATURE (°C) Figure 25. INL, fIN = 10.3 MHz –0.8 0 –20 1060 –2.5 13092-025 –2.0 13092-028 3.80 –1.5 AD9691 Data Sheet EQUIVALENT CIRCUITS AVDD3 AVDD3 VIN+x AVDD3 200Ω EMPHASIS/SWING CONTROL (SPI) VCM BUFFER DRVDD 200Ω DATA+ AVDD3 AVDD3 SERDOUTx+ x = 0 TO 7 3pF SERDOUTx– x = 0 TO 7 DRGND Figure 30. Analog Inputs Figure 33. Digital Outputs AVDD1 DVDD 25Ω SYNCINB+ 1kΩ DGND AVDD1 25Ω CLK– DRVDD DATA– 13092-030 AIN CONTROL (SPI) CLK+ DRGND OUTPUT DRIVER VIN–x VCM = 0.85V 13092-031 20kΩ SYNCINB– LEVEL TRANSLATOR VCM 1kΩ DGND Figure 31. Clock Inputs VCM = 0.85V 20kΩ DVDD 20kΩ 20kΩ SYNCINB± PIN CONTROL (SPI) 13092-034 200Ω 67Ω 10pF 28Ω 400Ω Figure 34. SYNCINB± Inputs AVDD1_SR SYSREF+ 1kΩ SPIVDD 20kΩ LEVEL TRANSLATOR AVDD1_SR ESD PROTECTED VCM = 0.85V 20kΩ SCLK SPIVDD 1kΩ 30kΩ 1kΩ ESD PROTECTED 13092-035 13092-032 SYSREF– 13092-033 67Ω 200Ω 28Ω 3pF Figure 35. SCLK Input Figure 32. SYSREF± Inputs Rev. 0 | Page 16 of 72 Data Sheet AD9691 SPIVDD ESD PROTECTED 30kΩ 1kΩ CSB 30kΩ 1kΩ PDWN/ STBY ESD PROTECTED 13092-036 ESD PROTECTED Figure 36. CSB Input PDWN CONTROL (SPI) Figure 39. PDWN/STBY Input AVDD2 SPIVDD ESD PROTECTED SDO ESD PROTECTED SPIVDD 1kΩ SDIO 13092-039 ESD PROTECTED SPIVDD SDI V_1P0 ESD PROTECTED 13092-037 ESD PROTECTED V_1P0 PIN CONTROL (SPI) Figure 37. SDIO Input Figure 40. V_1P0 Input SPIVDD FD_A/FD_B ESD PROTECTED FD JESD204B LMFC JESD204B SYNC~ TEMPERATURE DIODE (FD_A ONLY) FD_x PIN CONTROL (SPI) 13092-038 ESD PROTECTED Figure 38. FD_A/FD_B Outputs Rev. 0 | Page 17 of 72 13092-040 30kΩ AD9691 Data Sheet THEORY OF OPERATION The dual ADC cores feature multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The AD9691 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. The Subclass 1 JESD204B-based, high speed serialized output data rate can be configured in one-lane (L = 1), two-lane (L = 2), fourlane (L = 4), and eight-lane (L = 8) configurations, depending on the sample rate and the decimation ratio (DCM). Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins. ADC ARCHITECTURE The architecture of the AD9691 consists of an input buffered pipelined ADC. The input buffer provides a termination impedance to the analog input signal. This termination impedance can be changed using the SPI to meet the termination needs of the driver or amplifier. The default termination value is set to 400 Ω. The equivalent circuit diagram of the analog input termination is shown in Figure 30. The input buffer is optimized for high linearity, low noise, and low power. The input buffer provides a linear high input impedance (for ease of drive) and reduces the kickback from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample; at the same time, the remaining stages operate with the preceding samples. Sampling occurs on the rising edge of the clock. and settling within one-half of a clock cycle. A small resistor, in series with each input, helps reduce the peak transient current injected from the output stage of the driving source. In addition, place low Q inductors or ferrite beads on each section of the input to reduce high differential capacitance at the analog inputs and, thus, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Place either a differential capacitor or two single-ended capacitors on the inputs to provide a matching passive network. This configuration ultimately creates a low-pass filter at the input, which limits unwanted broadband noise. For more information, see the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled FrontEnd for Wideband A/D Converters” (Volume 39, April 2005). In general, the precise values depend on the application. For best dynamic performance, the source impedances driving VIN+x and VIN−x must be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. The maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9691, the available span is 1.58 V p-p differential. Differential Input Configurations There are several ways to drive the AD9691, either actively or passively. However, optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 41 and Table 9) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9691. For low to midrange frequencies, a double balun or double transformer network (see Figure 41) is recommended for optimum performance of the AD9691. For higher frequencies in the second and third Nyquist zones, it is better to remove some of the front-end passive components to ensure wideband operation (see Table 9). 0.1µF R1 ANALOG INPUT CONSIDERATIONS BALUN The analog input to the AD9691 is a differential buffer. The internal common-mode voltage of the buffer is 2.05 V. The clock signal alternately switches the input circuit between sample mode and hold mode. When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors R2 R1 R3 R2 C1 C2 0.1µF 0.1µF ADC R3 C1 NOTES 1. SEE TABLE 9 FOR COMPONENT VALUES. Rev. 0 | Page 18 of 72 Figure 41. Differential Transformer-Coupled Configuration 13092-041 The AD9691 has two analog input channels and four JESD204B output lane pairs. The ADC is designed to sample wide bandwidth analog signals of up to 1.5 GHz. The AD9691 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package. Data Sheet AD9691 Table 9. Differential Transformer-Coupled Input Configuration Component Values Frequency Range 625 MHz Transformer/Balun BAL-0006/BAL-0006SMG/ETC1-1-13 BAL-0006/BAL-0006SMG R1 (Ω) 10 10 Input Common Mode The analog inputs of the AD9691 are internally biased to the common mode as shown in Figure 42. The common-mode buffer has a limited range in that the performance suffers greatly if the common-mode voltage drops by more than 100 mV. Therefore, in dc-coupled applications, set the common-mode voltage to 2.05 V ± 100 mV to ensure proper ADC operation. R2 (Ω) 50 50 R3 (Ω) 15 0 C1 (pF) Open Open C2 (pF) 3 Open Figure 44, Figure 45, and Figure 46 show how the SFDR can be optimized using the buffer current setting in Register 0x018 for different Nyquist zones. At frequencies greater than 1 GHz, it is better to run the ADC at input amplitudes less than −1 dBFS (−3 dBFS, for example). This greatly improves the linearity of the converted signal without sacrificing SNR performance. 90 Analog Input Controls and SFDR Optimization 85 The AD9691 offers flexible controls for the analog inputs, such as input termination and buffer current. All of the available controls are shown in Figure 42. SFDR (dBFS) 80 AVDD3 AVDD3 4.5x 75 2.5x 70 VIN+x 3.5x 13092-045 600.3 500.3 470.3 440.3 410.3 380.3 350.3 320.3 290.3 260.3 230.3 200.3 170.3 Figure 44. Buffer Current Sweeps, SFDR vs. Analog Input Frequency vs. IBUFF; fIN < 600 MHz VIN–x 78 3pF 7.5x 76 13092-043 6.5x 74 SFDR (dBFS) Figure 42. Analog Input Controls Using Register 0x018, the buffer currents on each channel can be scaled to optimize the SFDR over various input frequencies and bandwidths of interest. As the input buffer currents are set, the amount of current required by the AVDD3 supply changes. This relationship is shown in Figure 43. For a complete list of buffer current settings, see Table 35. 72 5.5x 70 4.5x 68 66 64 62 700.3 270 13092-046 AIN CONTROL (SPI) REGISTERS (REG 0x008, REG 0x015, REG 0x016, REG0x018) 800.3 900.3 1000.3 1100.3 1200.3 ANALOG INPUT FREQUENCY (MHz) 250 Figure 45. Buffer Current Sweeps, SFDR vs. Analog Input Frequency vs. IBUFF; 700 MHz < fIN < 1200 MHz 225 200 175 150 125 100 75 1.5× 2.0× 2.5× 3.0× 3.5× 4.0× 4.5× 5.0× 5.5× 6.0× 6.5× 7.0× 7.5× 8.0× 8.5× BUFFER CURRENT SETTING 13092-044 IAVDD3 (mA) 130.3 9.6 ANALOG INPUT FREQUENCY (MHz) AVDD3 AVDD3 100.3 60 VCM BUFFER 70.3 200Ω 200Ω 28Ω 67Ω 400Ω 10pF 65 AVDD3 200Ω 67Ω 200Ω 28Ω 3pF Figure 43. AVDD3 Power (IAVDD3) vs. Buffer Current Setting Rev. 0 | Page 19 of 72 AD9691 Data Sheet 76 VIN+A/ VIN+B 74 7.5x 68 66 INTERNAL V_1P0 GENERATOR 6.5x V_1P0 ADJUST SPI REGISTER (REG 0x024) 64 5.5x 62 V_1P0 60 1500.3 1600.3 1700.3 1800.3 1900.3 ANALOG INPUT FREQUENCY (MHz) 1990.3 Figure 47. Internal Reference Configuration and Controls Figure 46. Buffer Current Sweeps, SFDR vs. Analog Input Frequency vs. IBUFF; 1300 MHz < fIN < 2000 MHz Table 10 shows the recommended buffer current and full-scale voltage settings for the different analog input frequency ranges. Table 10. SFDR Optimization for Input Frequencies Input Frequency 1 GHz Input Buffer Current Control Setting (Register 0x018) 3.5× 5.5× or 6.5× 6.5× or higher Buffer Control 2 Register (Register 0x935) 0x04 0x00 0x00 Register 0x024 enables the user to either use this internal 1.0 V reference, or to provide an external 1.0 V reference. When using an external voltage reference, provide a 1.0 V reference. The full-scale adjustment is made using the SPI, irrespective of the reference voltage. For more information on adjusting the full-scale level of the AD9691, see the Memory Map Register Table section. The use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 48 shows the typical drift characteristics of the internal 1.0 V reference. 1.0010 1.0009 Absolute Maximum Input Swing 1.0008 The absolute maximum input swing allowed at the inputs of the AD9691 is 4.3 V p-p differential. Signals operating near or at this level can cause permanent damage to the ADC. V_1P0 VOLTAGE (V) 1.0007 VOLTAGE REFERENCE A stable and accurate 1.0 V voltage reference is built into the AD9691. This internal 1.0 V reference sets the full-scale input range of the ADC. For more information on adjusting the input swing, see Table 35. Figure 47 shows the block diagram of the internal 1.0 V reference controls. 1.0006 1.0005 1.0004 1.0003 1.0002 1.0001 1.0000 0.9999 0.9998 –50 0 25 TEMPERATURE (°C) 90 Figure 48. Typical V_1P0 Drift The external reference must be a stable 1.0 V reference. The ADR130 is a good option for providing the 1.0 V reference. Figure 49 shows how the ADR130 can be used to provide the external 1.0 V reference to the AD9691. The grayed out areas show unused blocks within the AD9691 when using the ADR130 to provide the external reference. INTERNAL V_1P0 GENERATOR ADR130 INPUT 1 NC 2 GND SET 5 3 VIN 0.1µF V_1P0 ADJUST NC 6 VOUT 4 V_1P0 0.1µF V_1P0 ADJUST Figure 49. External Reference Using the ADR130 Rev. 0 | Page 20 of 72 13092-050 56 1400.3 V_1P0 PIN CONTROL SPI REGISTER (REG 0x024) 13092-047 58 ADC CORE FULL-SCALE VOLTAGE ADJUST 13092-048 70 SFDR (dBFS) VIN–A/ VIN–B 8.5x 13092-049 72 Data Sheet AD9691 CLOCK INPUT CONSIDERATIONS Input Clock Divider ½ Period Delay Adjust For optimum performance, drive the AD9691 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or clock drivers. These pins are biased internally and require no additional biasing. The input clock divider inside the AD9691 provides phase delay in increments of ½ the input clock cycle. Register 0x10C can be programmed to enable this delay independently for each channel. Changing this register does not affect the stability of the JESD204B link. Figure 50 shows a preferred method for clocking the AD9691. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. Input Clock Divider 0.1µF 1:1Z CLK+ ADC 100Ω CLK– 0.1µF Figure 50. Transformer-Coupled Differential Clock Another option is to ac couple a differential CML or LVDS signal to the sample clock input pins, as shown in Figure 51 and Figure 52. The maximum frequency at the CLK± inputs is 4 GHz. This is the limit of the divider. In applications where the clock input is a multiple of the sample clock, the appropriate divider ratio must be programmed into the clock divider before applying the clock signal. This ensures that the current transients during device startup are controlled. CLK+ CLK– ÷2 3.3V ÷4 71Ω 10pF 33Ω 33Ω ÷8 0.1µF Z0 = 50Ω REG 0x10B CLK+ 0.1µF Z0 = 50Ω Figure 53. Clock Divider Circuit 13092-052 ADC CLK– The AD9691 clock divider can be synchronized using the external SYSREF± input. A valid SYSREF± signal causes the clock divider to reset to a programmable state. Enable this feature by setting Bit 7 of Register 0x10D. This synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. See the Multichip Synchronization section for more information. Figure 51. Differential CML Sample Clock 0.1µF CLK+ 0.1µF CLOCK INPUT 50Ω1 150Ω LVDS DRIVER CLK– 50Ω1 CLK+ 100Ω 0.1µF RESISTORS ARE OPTIONAL. ADC CLK– Clock Fine Delay Adjust 13092-053 0.1µF CLOCK INPUT 13092-054 50Ω 13092-051 CLOCK INPUT The AD9691 contains an input clock divider with the ability to divide the Nyquist input clock by 1, 2, 4, or 8. The divider ratios can be selected using Register 0x10B. This is shown in Figure 53. Figure 52. Differential LVDS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. In applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock can be supplied to the device. The AD9691 can be clocked at 1.5 GHz with the internal clock divider set to 2. The output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal ADC. See the Memory Map section for more details on using this feature. The AD9691 sampling edge instant can be adjusted by writing to Register 0x117 and Register 0x118. Setting Bit 0 of Register 0x117 enables the feature, and Register 0x118, Bits[7:0] set the value of the delay. This value can be programmed individually for each channel. The clock delay can be adjusted from −151.7 ps to +150 ps in 1.7 ps increments. The clock delay adjust takes effect immediately when it is enabled via SPI writes. Enabling the clock fine delay adjust in Register 0x117 causes a datapath reset. However, the contents of Register 0x118 can be changed without affecting the stability of the JESD204B link. Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by Rev. 0 | Page 21 of 72 SNR = 20log10(2 × π × fA × tJ) AD9691 Data Sheet In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 54). 12.5fS 25fS 50fS 100fS 200fS 400fS 800fS 120 110 SNR (dB) 100 90 70 60 50 1000 10000 ANALOG INPUT FREQUENCY (MHz) 13092-055 40 100 The AD9691 contains a diode-based temperature sensor for measuring the temperature of the die. This diode can output a voltage and serve as a coarse temperature sensor to monitor the internal die temperature. The temperature diode voltage can be output to the FD_A pin using the SPI. Use Register 0x028, Bit 0 to enable or disable the diode. Register 0x028 is a local register; therefore, Channel A must be selected in the device index register (Register 0x008) to enable the temperature diode readout. Configure the FD_A pin to output the diode voltage by programming Register 0x040, Bits[2:0]. See Table 35 for more information. 80 30 10 TEMPERATURE DIODE The voltage response of the temperature diode (SPIVDD = 1.8 V) is shown in Figure 55. 0.90 Figure 54. Ideal SNR vs. Analog Input Frequency and Jitter 0.85 DIODE VOLTAGE (V) Treat the clock input as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9691. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. If the clock is generated from another type of source (by gating, dividing, or other methods), retime the clock by the original clock at the last step. For more in-depth information about jitter performance as it relates to ADCs, see the AN-501 Application Note and the AN-756 Application Note. POWER-DOWN/STANDBY MODE 0.80 0.75 0.70 0.65 0.60 The AD9691 has a PDWN/STBY pin that configures the device in power-down or standby mode. The default operation is the power-down function. The PDWN/STBY pin is a logic high pin. When in power-down mode, the JESD204B link is disrupted. The power-down option can also be set via Register 0x03F and Register 0x040. Rev. 0 | Page 22 of 72 –55 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 95 105 115 125 TEMPERATURE (°C) Figure 55. Diode Voltage vs. Temperature 13092-056 130 In standby mode, the JESD204B link is not disrupted and transmits zeros for all converter samples. This can be changed using Register 0x571, Bit 7 to select /K/ characters. Data Sheet AD9691 ADC OVERRANGE AND FAST DETECT The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 56. In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to clip. The standard overrange bit in the JESD204B outputs provides information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, the latency of this function is of major concern. Highly pipelined converters can have significant latency. The AD9691 contains fast detect circuitry for individual channels to monitor the threshold and assert the FD_A and FD_B pins. The FD indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, located at Register 0x247 and Register 0x248. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 28 clock cycles (maximum). The approximate upper threshold magnitude is defined by Upper Threshold Magnitude (dBFS) = 20log(Threshold Magnitude/213) ADC OVERRANGE The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, located at Register 0x249 and Register 0x24A. The fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency, but is accurate in terms of converter resolution. The lower threshold magnitude is defined by The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange indicator can be embedded within the JESD204B link as a control bit (when CSB > 0). The latency of this overrange indicator matches the sample latency. The AD9691 also records any overrange condition in any of the four virtual converters. For more information on the virtual converters, see Figure 61. The overrange status of each virtual converter is registered as a sticky bit in Register 0x563. The contents of Register 0x563 can be cleared using Register 0x562, by toggling the bits corresponding to the virtual converter to the set and reset positions. Lower Threshold Magnitude (dBFS) = 20log(Threshold Magnitude/213) For example, to set an upper threshold of −6 dBFS, write 0xFFF to Register 0x247 and Register 0x248. To set a lower threshold of −10 dBFS, write 0xA1D to Register 0x249 and Register 0x24A. FAST THRESHOLD DETECTION (FD_A AND FD_B) The fast detect (FD) bit (enabled via the control bits in Register 0x559 and Register 0x55A) is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit is cleared only when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. This feature provides hysteresis and prevents the FD bit from excessively toggling. To program the dwell time from 1 to 65,535 sample clock cycles, place the desired value in the fast detect dwell time registers, located at Register 0x24B and Register 0x24C. See the Memory Map section (Register 0x040, and Register 0x245 to Register 0x24C in Table 35) for more details. UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD DWELL TIME FD_A OR FD_B Figure 56. Threshold Settings for FD_A and FD_B Signals Rev. 0 | Page 23 of 72 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 13092-057 MIDSCALE LOWER THRESHOLD AD9691 Data Sheet SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The results of the signal monitor block can be obtained either by reading back the internal values from the SPI port or by embedding the signal monitoring information into the JESD204B interface as special control bits. A global, 24-bit programmable period controls the duration of the measurement. Figure 57 shows the simplified block diagram of the signal monitor block. SIGNAL MONITOR PERIOD REGISTER (SMPR) REG 0x271, REG 0x272, REG 0x273 CLEAR FROM INPUT MAGNITUDE STORAGE REGISTER LOAD DOWN COUNTER IS COUNT = 1? LOAD LOAD SIGNAL MONITOR HOLDING REGISTER COMPARE A>B When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the SPORT over the JESD204B interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the magnitude of the first input sample is updated in the magnitude storage register, and the comparison and update procedure continues. SPORT Over JESD204B TO SPORT OVER JESD204B AND MEMORY MAP 13092-058 FROM MEMORY MAP After enabling this mode, the value in the SMPR is loaded into a monitor period timer, which decrements at the decimated clock rate. The magnitude of the input signal is compared to the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. Figure 57. Signal Monitor Block The peak detector captures the largest signal within the observation period. The detector only observes the magnitude of the signal. The resolution of the peak detector is a 13-bit value, and the observation period is 24 bits and represents converter output samples. The peak magnitude can be derived by using the following equation: Peak Magnitude (dBFS) = 20log(Peak Detector Value/213) The magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal monitor period register (SMPR). The peak detector function is enabled by setting Bit 1 of Register 0x270 in the signal monitor control register. The 24-bit SMPR must be programmed before activating this mode. The signal monitor data can also be serialized and sent over the JESD204B interface as control bits. These control bits must be deserialized from the samples to reconstruct the statistical data. This function is enabled by setting Bits[1:0] of Register 0x279 and Bit 1 of Register 0x27A. Figure 58 shows two different example configurations for the signal monitor control bit locations inside the JESD204B samples. A maximum of three control bits can be inserted into the JESD204B samples; however, only one control bit is required for the signal monitor. Control bits are inserted from MSB to LSB. If only one control bit is to be inserted (CS = 1), only the most significant control bit is used (see Example Configuration 1 and Example Configuration 2 in Figure 58). To select the SPORT over JESD204B option, program Register 0x559, Register 0x55A, and Register 0x58F. See Table 35 for more information on setting these bits. Figure 59 shows the 25-bit frame data that encapsulates the peak detector value. The frame data is transmitted MSB first with five 5-bit subframes. Each subframe contains a start bit that can be used by a receiver to validate the deserialized data. Figure 60 shows the SPORT over JESD204B signal monitor data with a monitor period timer set to 80 samples. Rev. 0 | Page 24 of 72 Data Sheet AD9691 16-BIT JESD204B SAMPLE SIZE (N' = 16) EXAMPLE CONFIGURATION 1 (N' = 16, N = 15, CS = 1) 1-BIT CONTROL BIT (CS = 1) 15-BIT CONVERTER RESOLUTION (N = 15) 15 S[14] X 14 13 S[13] X S[12] X 12 S[11] X 11 10 S[10] X 9 S[9] X 8 S[8] X 7 S[7] X 6 S[6] X 5 S[5] X 4 S[4] X S[3] X 3 S[2] X 2 S[1] X 1 0 S[0] X CTRL [BIT 2] X SERIALIZED SIGNAL MONITOR FRAME DATA 16-BIT JESD204B SAMPLE SIZE (N' = 16) 14-BIT CONVERTER RESOLUTION (N = 14) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 S[13] X S[12] X S[11] X S[10] X S[9] X S[8] X S[7] X S[6] X S[5] X S[4] X S[3] X S[2] X S[1] X S[0] X CTRL [BIT 2] X TAIL X SERIALIZED SIGNAL MONITOR FRAME DATA Figure 58. Signal Monitor Control Bit Locations 5-BIT SUBFRAMES 5-BIT IDLE SUBFRAME (OPTIONAL) 25-BIT FRAME IDLE 1 IDLE 1 IDLE 1 IDLE 1 IDLE 1 5-BIT IDENTIFIER START 0 SUBFRAME ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 5-BIT DATA MSB SUBFRAME START 0 P[12] P[11] P[10] P[9] 5-BIT DATA SUBFRAME START 0 P[8] P[7] P[6] P5] 5-BIT DATA SUBFRAME START 0 P[4] P[3] P[2] P1] 5-BIT DATA LSB SUBFRAME START 0 P[0] 0 0 0 P[] = PEAK MAGNITUDE VALUE Figure 59. SPORT over JESD204B Signal Monitor Frame Data Rev. 0 | Page 25 of 72 13092-060 EXAMPLE CONFIGURATION 2 (N' = 16, N = 14, CS = 1) 13092-059 1 CONTROL 1 TAIL BIT BIT (CS = 1) AD9691 Data Sheet SMPR = 80 SAMPLES (REG 0x271 = 0x50; REG 0x272 = 0x00; REG 0x273 = 0x00) 80-SAMPLE PERIOD PAYLOAD No. 3 25-BIT FRAME (N) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE 80-SAMPLE PERIOD PAYLOAD No. 3 25-BIT FRAME (N + 1) IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE 80-SAMPLE PERIOD IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE Figure 60. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples Rev. 0 | Page 26 of 72 13092-061 PAYLOAD No. 3 25-BIT FRAME (N + 2) Data Sheet AD9691 DIGITAL DOWNCONVERTERS (DDCS) The AD9691 includes four digital downconverters (DDC 0 to DDC 3) that provide filtering and reduce the output data rate. This digital processing section includes a numerically controlled oscillator (NCO), a half-band decimating filter, a finite impulse response (FIR) filter, a gain stage, and a complex to real conversion stage. Each of these processing blocks have control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverters can be configured to output either real data or complex output data. DDC I/Q INPUT SELECTION The AD9691 has two ADC channels and four DDC channels. Each DDC channel has two input ports that can be paired to support both real or complex inputs through the I/Q crossbar mux. For real signals, both DDC input ports must select the same ADC channel (for example, DDC Input Port I = ADC Channel A, and Input Port Q = ADC Channel A). For complex signals, each DDC input port must select different ADC channels (for example, DDC Input Port I = ADC Channel A, and Input Port Q = ADC Channel B). The inputs to each DDC are controlled by the DDC input selection registers (Register 0x311, Register 0x331, Register 0x351, and Register 0x371). See Table 35 for information on how to configure the DDCs. DDC I/Q OUTPUT SELECTION Each DDC channel has two output ports that can be paired to support both real or complex outputs. For real output signals, only the DDC Output Port I is used (the DDC Output Port Q is invalid). For complex I/Q output signals, both DDC Output Port I and DDC Output Port Q are used. The I/Q outputs to each DDC channel are controlled by the DDC complex to real enable bit (Bit 3) in the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). The Chip Q ignore bit (Bit 5) in the chip application mode register (Register 0x200) controls the chip output muxing of all the DDC channels. When all DDC channels use real outputs, this bit must be set high to ignore all DDC Q output ports. When any of the DDC channels are set to use complex I/Q outputs, the user must clear this bit to use both DDC Output Port I and DDC Output Port Q. For more information, refer to Memory Map Register Table section. DDC GENERAL DESCRIPTION The four DDC blocks extract a portion of the full digital spectrum captured by the ADC(s). They are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. Each DDC block contains the following signal processing stages: • • • • Frequency translation stage (optional) Filtering stage Gain stage (optional) Complex to real conversion stage (optional) Frequency Translation Stage (Optional) The frequency translation stage consists of a 12-bit complex NCO and quadrature mixers that can be used for frequency translation of both real or complex input signals. This stage shifts a portion of the available digital spectrum down to baseband. Filtering Stage After shifting down to baseband, the filtering stage decimates the frequency spectrum using a chain of up to four half-band low-pass filters for rate conversion. The decimation process lowers the output data rate, which in turn reduces the output interface rate. Gain Stage (Optional) Due to losses associated with mixing a real input signal down to baseband, the gain stange compensates by adding an additional 0 dB or 6 dB of gain. Complex to Real Conversion Stage (Optional) When real outputs are necessary, the complex to real conversion stage converts the complex outputs back to real by performing an fS/4 mixing operation plus a filter to remove the complex component of the signal. Figure 61 shows the detailed block diagram of the DDCs implemented in the AD9691. Rev. 0 | Page 27 of 72 AD9691 Data Sheet ADC SAMPLING AT fS HB1 FIR DCM = 2 COMPLEX TO REAL CONVERSION (OPTIONAL) Q CONVERTER 1 REAL/I CONVERTER 2 Q CONVERTER 3 SYSREF± COMPLEX TO REAL CONVERSION (OPTIONAL) REAL/Q Q ADC SAMPLING AT fS GAIN = 0dB OR 6dB NCO + MIXER (OPTIONAL) HB1 FIR DCM = 2 I HB2 FIR DCM = BYPASS OR 2 DDC 2 REAL/I REAL/I CONVERTER 4 OUTPUT INTERFACE COMPLEX TO REAL CONVERSION (OPTIONAL) GAIN = 0dB OR 6dB HB1 FIR DCM = 2 HB2 FIR DCM = BYPASS OR 2 REAL/Q Q HB3 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 I/Q CROSSBAR MUX I HB4 FIR DCM = BYPASS OR 2 DDC 1 REAL/I REAL/I REAL/I CONVERTER 0 SYSREF± HB4 FIR DCM = BYPASS OR 2 REAL/I GAIN = 0dB OR 6dB REAL/Q Q HB2 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 I HB4 FIR DCM = BYPASS OR 2 DDC 0 REAL/I Q CONVERTER 5 SYSREF± SYNCHRONIZATION CONTROL CIRCUITS SYSREF± COMPLEX TO REAL CONVERSION (OPTIONAL) REAL/I CONVERTER 6 Q CONVERTER 7 13092-062 SYSREF GAIN = 0dB OR 6dB REAL/Q Q HB1 FIR DCM = 2 NCO + MIXER (OPTIONAL) HB2 FIR DCM = BYPASS OR 2 I HB3 FIR DCM = BYPASS OR 2 REAL/I HB4 FIR DCM = BYPASS OR 2 DDC 3 Figure 61. DDC Detailed Block Diagram Figure 62 shows an example usage of one of the four DDC blocks with a real input signal and four half-band filters (HB4, HB3, HB2, and HB1). It shows both complex (decimate by 16) and real (decimate by 8) output options. the chip decimation ratio sample rate. Whenever the NCO frequency is set or changed, the DDC soft reset must be issued. If the DDC soft reset is not issued, the output may potentially show amplitude variations. When DDCs have different decimation ratios, the chip decimation ratio (Register 0x201) must be set to the lowest decimation ratio of all the DDC blocks. In this scenario, samples of higher decimation ratio DDCs are repeated to match Table 11, Table 12, Table 13, Table 14, and Table 15 show the DDC samples when the chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively. Rev. 0 | Page 28 of 72 Data Sheet AD9691 ADC REAL INPUT—SAMPLED AT fS –fS/2 –fS/3 ADC SAMPLING AT fS REAL BANDWIDTH OF INTEREST IMAGE –fS/4 REAL BANDWIDTH OF INTEREST fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 FREQUENCY TRANSLATION STAGE (OPTIONAL) DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) fS/8 fS/4 fS/3 fS/2 I NCO TUNES CENTER OF BANDWIDTH OF INTEREST TO BASEBAND cos(ωt) REAL 12-BIT NCO 90° 0° –sin(ωt) Q DIGITAL FILTER RESPONSE –fS/2 –fS/3 –fS/4 FILTERING STAGE 4 DIGITAL HALF-BAND FILTERS (HB4 + HB3 + HB2 + HB1) fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 HB4 FIR I HALFBAND FILTER Q HALFBAND FILTER HB3 FIR 2 HALFBAND FILTER 2 HALFBAND FILTER HB4 FIR BANDWIDTH OF INTEREST IMAGE (–6dB LOSS DUE TO NCO + MIXER) BANDWIDTH OF INTEREST (–6dB LOSS DUE TO NCO + MIXER) fS/8 2 2 HALFBAND FILTER HB3 FIR fS/3 fS/2 HB1 FIR HB2 FIR HALFBAND FILTER fS/4 2 HALFBAND FILTER 2 HALFBAND FILTER 2 I HB1 FIR HB2 FIR 2 Q 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS COMPLEX (I/Q) OUTPUTS GAIN STAGE (OPTIONAL) DIGITAL FILTER RESPONSE I GAIN STAGE (OPTIONAL) Q 0dB OR 6dB GAIN COMPLEX TO REAL CONVERSION STAGE (OPTIONAL) fS/4 MIXING + COMPLEX FILTER TO REMOVE Q fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 I REAL (I) OUTPUTS +6dB +6dB fS/8 2 +6dB 2 +6dB I Q fS/32 –fS/32 DC –fS/16 fS/16 DOWNSAMPLE BY 2 I DECIMATE BY 8 Q DECIMATE BY 16 0dB OR 6dB GAIN Q COMPLEX REAL/I TO REAL –fS/8 fS/32 –fS/32 DC –fS/16 fS/16 fS/8 Figure 62. DDC Theory of Operation Example (Real Input—Decimate by 16) Rev. 0 | Page 29 of 72 13092-063 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS AD9691 Data Sheet Table 11. DDC Samples, Chip Decimation Ratio = 1 HB1 FIR (DCM 1 = 1) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 N + 24 N + 25 N + 26 N + 27 N + 28 N + 29 N + 30 N + 31 1 Real (I) Output (Complex to Real Enabled) HB2 FIR + HB3 FIR + HB2 HB4 FIR + HB3 FIR + HB1 FIR FIR + HB1 FIR HB2 FIR + HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) N N N N+1 N+1 N+1 N N N N+1 N+1 N+1 N+2 N N N+3 N+1 N+1 N+2 N N N+3 N+1 N+1 N+4 N+2 N N+5 N+3 N+1 N+4 N+2 N N+5 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+8 N+4 N+2 N+9 N+5 N+3 N+8 N+4 N+2 N+9 N+5 N+3 N + 10 N+4 N+2 N + 11 N+5 N+3 N + 10 N+4 N+2 N + 11 N+5 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 Complex (I/Q) Outputs (Complex to Real Disabled) HB1 FIR (DCM1 = 2) N N+1 N N+1 N+2 N+3 N+2 N+3 N+4 N+5 N+4 N+5 N+6 N+7 N+6 N+7 N+8 N+9 N+8 N+9 N + 10 N + 11 N + 10 N + 11 N + 12 N + 13 N + 12 N + 13 N + 14 N + 15 N + 14 N + 15 DCM is decimation. Rev. 0 | Page 30 of 72 HB2 FIR + HB1 FIR (DCM1 = 4) N N+1 N N+1 N N+1 N N+1 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+4 N+5 N+4 N+5 N+4 N+5 N+4 N+5 N+6 N+7 N+6 N+7 N+6 N+7 N+6 N+7 HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8) N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 N+2 N+3 HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 N N+1 Data Sheet AD9691 Table 12. DDC Samples, Chip Decimation Ratio = 2 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR (DCM 1 = 2) (DCM1 = 4) (DCM1 = 8) N N N N+1 N+1 N+1 N N N+2 N+1 N+1 N+3 N + 2 N N+4 N + 3 N+1 N+5 N+2 N N+6 N+3 N+1 N+7 N+4 N+2 N+8 N+5 N+3 N+9 N+4 N+2 N + 10 N+5 N+3 N + 11 N+6 N+2 N + 12 N+7 N+3 N + 13 N+6 N+2 N + 14 N+7 N+3 N + 15 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N N N N N+1 N+1 N+1 N+1 N N N N+2 N+1 N+1 N+1 N+3 N + 2 N N N+4 N + 3 N + 1 N+1 N+5 N+2 N N N+6 N+3 N+1 N+1 N+7 N+4 N+2 N N+8 N+5 N+3 N+1 N+9 N+4 N+2 N N + 10 N+5 N+3 N+1 N + 11 N+6 N+2 N N + 12 N+7 N+3 N+1 N + 13 N+6 N+2 N N + 14 N+7 N+3 N+1 N + 15 DCM is decimation. Table 13. DDC Samples, Chip Decimation Ratio = 4 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR (DCM 1 = 4) (DCM1 = 8) N N N+1 N+1 N N+2 N+1 N+3 N+2 N+4 N+3 N+5 N+2 N+6 N+3 N+7 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR HB3 FIR + HB2 FIR + HB2 FIR + HB1 FIR (DCM1 = 4) HB1 FIR (DCM1 = 8) (DCM1 = 16) N N N N+1 N+1 N+1 N N N+2 N+1 N+1 N+3 N+2 N N+4 N+3 N+1 N+5 N+2 N N+6 N+3 N+1 N+7 DCM is decimation. Table 14. DDC Samples, Chip Decimation Ratio = 8 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB3 FIR + HB2 FIR + HB1 FIR HB4 FIR + HB3 FIR + HB2 FIR + (DCM1 = 8) HB1 FIR (DCM1 = 16) N N N+1 N+1 N N+2 N+1 N+3 N+2 N+4 N+3 N+5 N+2 N+6 N+3 N+7 DCM is decimation. Rev. 0 | Page 31 of 72 AD9691 Data Sheet Table 15. DDC Samples, Chip Decimation Ratio = 16 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM = 16) Not applicable Not applicable Not applicable Not applicable 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 16) N N+1 N+2 N+3 DCM is decimation. If the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs, decimate by 4), and DDC 1 is set to use HB4 + HB3 + HB2 + HB1 filters (real outputs, decimate by 8). Then, DDC 1 repeats its output data two times for every one DDC 0 output. The resulting output samples are shown in Table 16. Table 16. DDC Output Samples when Chip DCM 1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real) DDC Input Samples N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 1 Output Port I I0 (N) DDC 0 Output Port Q Q0 (N) Output Port I I1 (N) DDC 1 Output Port Q Not applicable I0 (N + 1) Q0 (N + 1) I1 (N + 1) Not applicable I0 (N + 2) Q0 (N + 2) I1 (N) Not applicable I0 (N + 3) Q0 (N + 3) I1 (N + 1) Not applicable DCM is decimation. Rev. 0 | Page 32 of 72 Data Sheet AD9691 FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode Frequency translation is accomplished using a 12-bit complex NCO with a digital quadrature mixer. The frequency translation translates either a real or complex input signal from an IF to a baseband complex digital output (carrier frequency = 0 Hz). The NCO and the mixers are enabled. The NCO output frequency can be used to digitally tune the IF frequency. 0 Hz IF (ZIF) Mode The mixers are bypassed and the NCO is disabled. The frequency translation stage of each DDC can be controlled individually and supports four different IF modes using Bits[5:4] of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). These IF modes are The mixers and NCO are enabled in a special downmixing by fS/4 mode to save power. Test Mode Variable IF mode 0 Hz IF, or zero IF (ZIF), mode fS/4 Hz IF mode Test mode The input samples are forced to 0.999 to positive full scale. The NCO is enabled. This test mode allows the NCOs to drive the decimation filters directly. Figure 63 and Figure 64 show examples of the frequency translation stage for both real and complex inputs. NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 I ADC + DIGITAL MIXER + NCO REAL INPUT—SAMPLED AT fS REAL ADC SAMPLING AT fS REAL 12-BIT NCO cos(ωt) 90° 0° COMPLEX –sin(ωt) Q BANDWIDTH OF INTEREST BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 –fS/8 –fS/32 fS/32 DC –fS/16 fS/16 fS/8 fS/4 fS/3 fS/2 –6dB LOSS DUE TO NCO + MIXER 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 DC fS/32 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = –1365 (0xAAB) –fS/32 NEGATIVE FTW VALUES DC fS/32 Figure 63. DDC NCO Frequency Tuning Word Selection—Real Inputs Rev. 0 | Page 33 of 72 13092-064 • • • • fS/4 Hz IF Mode AD9691 Data Sheet NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 QUADRATURE ANALOG MIXER + 2 ADCs + QUADRATURE DIGITAL REAL MIXER + NCO COMPLEX INPUT—SAMPLED AT fS QUADRATURE MIXER ADC SAMPLING AT fS I + I I Q Q 90° PHASE 12-BIT NCO 90° 0° Q Q ADC SAMPLING AT fS Q Q I I – –sin(ωt) I I + COMPLEX Q + BANDWIDTH OF INTEREST IMAGE DUE TO ANALOG I/Q MISMATCH –fS/3 –fS/4 –fS/32 fS/32 –fS/16 fS/16 DC –fS/8 fS/8 fS/4 fS/3 fS/2 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 fS/32 13092-065 –fS/2 DC Figure 64. DDC NCO Frequency Tuning Word Selection—Complex Inputs DDC NCO PLUS MIXER LOSS AND SFDR Setting Up the NCO FTW and POW When mixing a real input signal down to baseband, 6 dB of loss is introduced in the signal due to filtering of the negative image. The NCO introduces an additional 0.05 dB of loss. The total loss of a real input signal mixed down to baseband is 6.05 dB. For this reason, it is recommended to compensate for this loss by enabling the additional 6 dB of gain in the gain stage of the DDC to recenter the dynamic range of the signal within the full scale of the output bits. The NCO frequency value is given by the 12-bit twos complement number entered in the NCO FTW. Frequencies between ±fS (+fS/2 excluded) are represented using the following frequency words: When mixing a complex input signal down to baseband, the maximum value that each I/Q sample can reach is 1.414 × full scale after it passes through the complex mixer. To avoid overrange of the I/Q samples and to keep the data bit-widths aligned with real mixing, introduce 3.06 dB of loss (0.707 × fullscale) in the mixer for complex signals. The NCO introduces an additional 0.05 dB of loss. The total loss of a complex input signal mixed down to baseband is −3.11 dB. The worst case spurious signal from the NCO is greater than 102 dBc SFDR for all output frequencies. NUMERICALLY CONTROLLED OSCILLATOR The AD9691 has a 12-bit NCO for each DDC that enables the frequency translation process. The NCO allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. The NCO can be set up by providing a frequency tuning word (FTW) and a phase offset word (POW).    0x800 represents a frequency of –fS/2. 0x000 represents dc (frequency is 0 Hz). 0x7FF represents a frequency of fS/2 – fS/212. Calculate the NCO frequency tuning word using the following equation:  mod  f C , f S    NCO _ FTW  round  2 12 fS   where: NCO_FTW is a 12-bit twos complement number representing the NCO FTW. fC is the desired carrier frequency in Hz. fS is the AD9691 sampling frequency (clock rate) in Hz. mod( ) is a remainder function. For example, mod(110,100) = 10, and for negative numbers, mod(−32, +10) = –2. round( ) is a rounding function. For example, round(3.6) = 4, and for negative numbers, round(−3.4) = −3. Note that this equation applies to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). Rev. 0 | Page 34 of 72 Data Sheet AD9691 For example, if the ADC sampling frequency (fS) is 1250 MSPS and the carrier frequency (fC) is 416.667 MHz,  mod(416.667,1250  NCO _ FTW = round  212  = 1365 MHz 1250   This, in turn, converts to 0x555 in the 12-bit twos complement representation for NCO_FTW. Calculate the actual carrier frequency using the following equation: f C _ ACTUAL NCO _ FTW × f S = = 416.56 MHz 212 Use the following two methods to synchronize multiple PAWs within the chip: • • A 12-bit POW is available for each NCO to create a known phase relationship between multiple AD9691 chips or individual DDC channels inside one AD9691. The following procedure must be followed to update the FTW and/or POW registers to ensure proper operation of the NCO: 1. 2. 3. Write to the FTW registers for all the DDCs. Write to the POW registers for all the DDCs. Synchronize the NCOs either through the DDC soft reset bit accessible through the SPI, or through the assertion of the SYSREF± pin. Note that the NCOs must be synchronized either through the SPI or through the SYSREF± pin after all writes to the FTW or POW registers are complete. This synchronization is necessary to ensure the proper operation of the NCO. NCO Synchronization Each NCO contains a separate phase accumulator word (PAW) that determines the instantaneous phase of the NCO. The initial reset value of each PAW is determined by the POW described in the Setting Up the NCO FTW and POW section. The phase increment value of each PAW is determined by the FTW. Using the SPI. Use the DDC NCO soft reset bit in the DDC synchronization control register (Register 0x300, Bit 4) to reset all the PAWs in the chip. This is accomplished by toggling the DDC NCO soft reset bit. This method synchronizes DDC channels within the same AD9691 chip only. Using the SYSREF± pin. When the SYSREF± pin is enabled in the SYSREF± control registers (Register 0x120 and Register 0x121), and the DDC synchronization is enabled in Bits[1:0] in the DDC synchronization control register (Register 0x300), any subsequent SYSREF± event resets all the PAWs in the chip. This method synchronizes DDC channels within the same AD9691 chip, or DDC channels within separate AD9691 chips. Mixer The NCO is accompanied by a mixer, which operates similarly to an analog quadrature mixer. It performs the downconversion of input signals (real or complex) by using the NCO frequency as a local oscillator. For real input signals, this mixer performs a real mixer operation with two multipliers. For complex input signals, the mixer performs a complex mixer operation with four multipliers and two adders. The mixer adjusts its operation based on the input signal (real or complex) provided to each individual channel. The selection of real or complex inputs can be controlled individually for each DDC block by using Bit 7 of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). Rev. 0 | Page 35 of 72 AD9691 Data Sheet FIR FILTERS GENERAL DESCRIPTION There are four sets of decimate by 2, low-pass, half-band, FIR filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in Figure 61) following the frequency translation stage. After the carrier of interest is tuned down to dc (carrier frequency = 0 Hz), these filters efficiently lower the sample rate while providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. HB1 FIR is always enabled and cannot be bypassed. The HB2, HB3, and HB4 FIR filters are optional and can be bypassed for higher output sample rates. Table 17 shows the different bandwidth options by including different half-band filters. In all cases, the DDC filtering stage of the AD9691 provides less than −0.001 dB of pass-band ripple and greater than 100 dB of stop-band alias rejection. Table 18 shows the amount of stop-band alias rejection for multiple pass-band ripple/cutoff points. The decimation ratio of the filtering stage of each DDC can be controlled individually through Bits[1:0] of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). Table 17. DDC Filter Characteristics ADC Sample Rate (MSPS) 1250 1 DDC Decimation Ratio 2 (HB1) 4 (HB1 + HB2) 8 (HB1 + HB2 + HB3) 16 (HB1 + HB2 + HB3 + HB4) Real Output Sample Rate (MSPS) 1250 625 312.5 156.25 Complex (I/Q) Output Sample Rate (MSPS) 625 (I) + 625 (Q) 312.5 (I) + 312.5 (Q) 156.25 (I) + 156.25 (Q) 78.125 (I) + 78.125 (Q) Alias Protected Bandwidth (MHz) 481.3 240.6 120.3 60.2 Ideal SNR Improvement 1 (dB) +1 +4 +7 +10 Pass-Band Ripple (dB) 100 90 85 63.3 25 19.3 10.7 1 Pass-Band Ripple/ Cutoff Point (dB)