AD9697BCPZ-1300

14-Bit, 1300 MSPS, JESD204B, Analog-to-Digital Converter AD9697 Data Sheet FEATURES APPLICATIONS JESD204B (Subclass 1) coded serial digital outputs Lane rates up to 16 Gbps Total power dissipation: 1.00 W at 1300 MSPS SNR: 65.6 dBFS at 172.3 MHz (1.59 V p-p analog input full scale) SFDR: 78 dBFS at 172.3 MHz (1.59 V p-p analog input full scale) Noise density −153.9 dBFS/Hz (1.59 V p-p analog input full scale) −155.6 dBFS/Hz (2.04 V p-p analog input full scale) 0.95 V, 1.8 V, and 2.5 V supply operation No missing codes Internal ADC voltage reference Flexible differential input voltage range 1.36 V p-p to 2.04 V p-p (1.59 V p-p typical) 2 GHz usable analog input full power bandwidth Amplitude detect bits for efficient AGC implementation 4 integrated digital downconverters 48-bit NCO Programmable decimation rates Differential clock input SPI control Integer clock divide by 2 and divide by 4 Flexible JESD204B lane configurations On-chip dithering to improve small signal linearity Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation Oscilloscopes Spectrum analyzers Network analyzers Integrated RF test solutions Radars Electronic support measures, electronic counter measures, and electronic counter to counter measures High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths Hybrid fiber coaxial digital reverse path receivers Wideband digital predistortion FUNCTIONAL BLOCK DIAGRAM FAST DETECT VIN+ VIN– VREF ADC CORE BUFFER 14 CROSSBAR MUX SIGNAL MONITOR DRVDD1 (0.95V) DVDD (0.95V) DRVDD2 (1.8V) DIGITAL DOWNCONVERTER CROSSBAR MUX AVDD3 AVDD1_SR (0.95V) (2.5V) AVDD2 (1.8V) PROGRAMMABLE FIR FILTER AVDD1 (0.95V) SPIVDD (1.8V) JESD204B LINK AND Tx OUTPUTS 4 SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SYNCINB± PDWN/STBY JESD204B SUBCLASS 1 CONTROL CLOCK DISTRIBUTION FD/GPIO1 GPIO MUX CLK+ CLK– SPI AND CONTROL REGISTERS ÷2 GPIO2 AD9697 ÷4 AGND SDIO SCLK CSB DRGND DGND 16253-001 SYSREF± Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9697 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC Complex to Real Conversion ......................................... 49 Applications ....................................................................................... 1 DDC Mixed Decimation Settings ............................................ 50 Functional Block Diagram .............................................................. 1 DDC Example Configurations ................................................. 51 Revision History ............................................................................... 3 Signal Monitor ................................................................................ 54 General Description ......................................................................... 4 SPORT over JESD204B .............................................................. 55 Product Highlights ........................................................................... 4 Digital Outputs ............................................................................... 57 Specifications..................................................................................... 5 Introduction to the JESD204B Interface ................................. 57 DC Specifications ......................................................................... 5 JESD204B Overview .................................................................. 57 AC Specifications.......................................................................... 6 Functional Overview ................................................................. 58 Digital Specifications ................................................................... 7 JESD204B Link Establishment ................................................. 58 Switching Specifications .............................................................. 8 Physical Layer (Driver) Outputs .............................................. 60 Timing Specifications .................................................................. 9 Setting Up the AD9697 Digital Interface ................................ 61 Absolute Maximum Ratings .......................................................... 11 Deterministic Latency.................................................................... 67 Thermal Characteristics ............................................................ 11 Subclass 0 Operation.................................................................. 67 ESD Caution ................................................................................ 11 Subclass 1 Operation.................................................................. 67 Pin Configuration and Function Descriptions ........................... 12 Multichip Synchronization............................................................ 69 Typical Performance Characteristics ........................................... 14 Normal Mode .............................................................................. 69 Equivalent Circuits ......................................................................... 19 Timestamp Mode ....................................................................... 69 Theory of Operation ...................................................................... 21 SYSREF± Input ........................................................................... 71 ADC Architecture ...................................................................... 21 SYSREF± Setup/Hold Window Monitor ................................. 73 Analog Input Considerations.................................................... 21 Latency ............................................................................................. 75 Voltage Reference ....................................................................... 24 End to End Total Latency .......................................................... 75 DC Offset Calibration ................................................................ 24 Example Latency Calculations.................................................. 75 Clock Input Considerations ...................................................... 24 LMFC Referenced Latency........................................................ 75 Power-Down/Standby Mode..................................................... 27 Test Modes ....................................................................................... 77 Temperature Diode .................................................................... 27 ADC Test Modes ........................................................................ 77 ADC Overrange and Fast Detect .................................................. 28 JESD204B Block Test Modes .................................................... 78 ADC Overrange .......................................................................... 28 Serial Port Interface (SPI) .............................................................. 80 Fast Threshold Detection (FD)................................................. 28 Configuration Using the SPI ..................................................... 80 ADC Application Modes and JESD204B Tx Converter Mapping ........................................................................................................... 29 Hardware Interface ..................................................................... 80 Programmable Finite Impulse Response (FIR) Filters .............. 31 Memory Map .................................................................................. 81 Supported Modes........................................................................ 31 Reading the Memory Map Register Table............................... 81 Programming Instructions ........................................................ 32 Memory Map Registers ............................................................. 82 Digital Downconverter (DDC) ..................................................... 33 Applications Information ............................................................ 128 DDC I/Q Output Selection ....................................................... 33 Power Supply Recommendations........................................... 128 DDC General Description ........................................................ 33 Layout GuideLines ................................................................... 129 DDC Frequency Translation ..................................................... 36 AVDD1_SR (Pin 57) and AGND_SR (Pin 56 and Pin 60) ..... 129 DDC Decimation Filters............................................................ 43 Outline Dimensions ..................................................................... 130 DDC Gain Stage ......................................................................... 49 Ordering Guide ........................................................................ 130 SPI Accessible Features .............................................................. 80 Rev. 0 | Page 2 of 130 Data Sheet AD9697 REVISION HISTORY 3/2018—Revision 0: Initial Version Rev. 0 | Page 3 of 130 AD9697 Data Sheet GENERAL DESCRIPTION The AD9697 is a single, 14-bit, 1300 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sampleand-hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 2 GHz. The −3 dB bandwidth of the ADC input is 2 GHz. The AD9697 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of multiple signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and decimation filters. The NCO has the option to select up to 16 preset bands over the general-purpose input/ output (GPIO) pins, or to use a coherent fast frequency hopping mechanism for band selection. Operation of the AD9697 between the DDC modes is selectable via serial port interface (SPI)programmable profiles. In addition to the DDC blocks, the AD9697 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9697 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC. The user can configure the Subclasss 1 JESD204B-based high speed serialized output using either one lane, two lanes, or four lanes, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins. The AD9697 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire SPI and or PDWN/STBY pin. The AD9697 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +105°C junction temperature (TJ) range. This product may be protected by one or more U.S. or international patents. Note that, throughout this data sheet, a multifunction pin, FD/GPIO1, is referred to either by the entire pin name or by a single function of the pin, for example, FD, when only that function is relevant. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. Rev. 0 | Page 4 of 130 Low power consumption. JESD204B lane rate support up to 16 Gbps. Wide, full power bandwidth supports intermediate frequency (IF) sampling of signals up to 2 GHz. Buffered inputs ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Programmable fast overrange detection. On-chip temperature diode for system thermal management. Data Sheet AD9697 SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, analog input (AIN) = −1.0 dBFS, default SPI settings, sample rate = 1300 MSPS, and DCS on, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating TJ range of −40°C to +105°C. Typical specifications represent performance at and TJ = 37°C (TA = 25°C). Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error 1 Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Voltage INPUT-REFERRED NOISE ANALOG INPUTS Differential Input Voltage Range Common-Mode Voltage (VCM) Differential Input Resistance Differential Input Capacitance Analog Full Power Bandwidth POWER SUPPLY AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD1 DRVDD2 SPIVDD 2 IAVDD1 IAVDD2 IAVDD3 IAVDD1_SR IDVDD IDRVDD1 3 IDRVDD2 ISPIVDD POWER CONSUMPTION Total Power Dissipation (Including Output Drivers) 4 Power-Down Dissipation Standby 5 Min 14 Typ −0.48 −2.9 −2.64 −0.7 −7 Guaranteed 5 0 ±1 ±0.18 ±1 Max +0.48 +2.9 +2.64 0.8 5 Unit Bits Codes % FSR % FSR % FSR LSB LSB ±9 69 ppm/°C ppm/°C 0.5 3.8 V LSB rms 1.36 1.59 1.41 200 1.75 2 2.04 V p-p V Ω pF GHz 0.93 1.71 2.44 0.93 0.93 0.93 1.71 1.71 0.95 1.8 2.5 0.95 0.95 0.95 1.8 1.8 177 267 29 15 121 124 21 2 0.98 1.89 2.56 0.98 0.98 0.98 1.89 1.89 250 306 33 27 302 204 25 5 V V V V V V V V mA mA mA mA mA mA mA mA 1.00 716 200 1.39 W mW mW DC offset calibration on (Register 0x0701, Bit 7 = 1 and Register 0x073B, Bit 7 = 0). The voltage level on the SPIVDD rail and on the DRVDD2 rail must be the same. All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used. 4 Default mode. No DDCs used. 5 Can be controlled by SPI. 1 2 3 Rev. 0 | Page 5 of 130 AD9697 Data Sheet AC SPECIFICATIONS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 1300 MSPS, DCS on, and buffer current settings specified in Table 10, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating TJ range of −40°C to +105°C. Typical specifications represent performance at TJ = 37°C (TA = 25°C). Table 2. Parameter 1 ANALOG INPUT FULL SCALE NOISE DENSITY 2 SIGNAL-TO-NOISE RATIO (SNR) fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) fIN = 10.3 MHz fIN = 172.3MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz Analog Input Full Scale = 1.36 V p-p Min Typ Max 1.36 −152.6 64.4 64.4 64.3 64.0 63.8 63.2 62.7 62.3 64.3 64.3 64.2 63.9 63.6 63.1 62.6 62.1 10.3 10.3 10.3 10.3 10.2 10.1 10.1 10.0 81 81 80 83 82 80 80 81 Rev. 0 | Page 6 of 130 Analog Input Full Scale = 1.59 V p-p Min Typ Max 1.59 −153.9 64.5 64.3 10.3 74 Analog Input Full Scale = 2.04 V p-p Min Typ Max 2.04 −155.6 Unit V p-p dBFS/Hz 65.7 65.6 65.6 65.2 64.9 64.2 63.6 63.0 67.5 67.5 67.3 66.6 66.1 65.2 64.5 63.9 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 65.4 65.4 65.3 65.0 64.7 63.8 63.4 62.8 66.1 66.2 65.7 65.5 65.7 62.9 64.2 61.8 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS 10.5 10.5 10.5 10.5 10.4 10.3 10.2 10.1 10.6 10.7 10.6 10.5 10.6 10.1 10.3 9.9 Bits Bits Bits Bits dBFS dBFS dBFS dBFS 79 78 77 80 81 76 80 79 73 72 71 72 79 67 78 68 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Data Sheet Parameter 1 WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC fIN = 10.3 MHz fIN = 172.3 MHz fIN = 340 MHz fIN = 750 MHz fIN = 1000 MHz fIN = 1400 MHz fIN = 1700 MHz fIN = 1980 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7.0 dBFS fIN1 = 170.8 MHz, fIN2 = 173.8 MHz fIN1 = 343.5 MHz, fIN2 = 346.5 MHz ANALOG INPUT BANDWIDTH, FULL POWER 3 AD9697 Analog Input Full Scale = 1.36 V p-p Min Typ Max Analog Input Full Scale = 1.59 V p-p Min Typ Max −96 −95 −98 −95 −96 −90 −91 −90 −94 −96 −99 −95 −93 −89 −90 −90 −84 −83 2 −84 −82 2 Analog Input Full Scale = 2.04 V p-p Min Typ Max −85 Unit −101 −95 −98 −92 −91 −86 −84 −77 dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS −83 −81 2 dBFS dBFS GHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed. Noise density is measured at a low analog input frequency (10 MHz). 3 Full power bandwidth is the bandwidth of operation to achieve proper ADC performance. 1 2 DIGITAL SPECIFICATIONS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 1300 MSPS, and DCS on, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating TJ range of −40°C to +105°C. Typical specifications represent performance at and TJ = 37°C (TA = 25°C). Table 3. Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) SYSREF INPUTS (SYSREF+, SYSREF−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD/GPIO1, GPIO2) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUT (SDIO, FD) Logic Compliance Logic 1 Voltage (IOH = 4 mA) Logic 0 Voltage (IOL = 4 mA) Min 400 Typ LVDS/LVPECL 800 0.65 32 Max Unit 1600 mV p-p V kΩ pF 0.9 400 LVDS/LVPECL 800 0.65 18 1 1800 2 mV p-p V kΩ pF CMOS 0.75 × SPIVDD 0 0.35 × SPIVDD 30 V V kΩ CMOS SPIVDD − 0.45 0 Rev. 0 | Page 7 of 130 0.45 V V AD9697 Parameter SYNCIN INPUTS (SYNCINB−, SYNCINB+) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Single-Ended per Pin) DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3) Logic Compliance Differential Output Voltage Differential Termination Impedance Data Sheet Min 400 Typ Max Unit LVDS/LVPECL/CMOS 800 1800 0.65 2 18 1 mV p-p V kΩ pF SST 360 80 520 100 770 1200 mV p-p Ω SWITCHING SPECIFICATIONS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 1300 MSPS, and DCS on, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating TJ range of −40°C to +105°C. Typical specifications represent performance at and TJ = 37°C (TA = 25°C). Table 4. Parameter CLOCK Clock Rate (at CLK+/CLK− Pins) Maximum Sample Rate 1 Minimum Sample Rate 2 Clock Pulse Width 3 High Low OUTPUT PARAMETERS Unit Interval (UI) 4 Rise Time (tR) (20% to 80% into 100 Ω Load) Fall Time (tF) (20% to 80% into 100 Ω Load) Phase-Locked Loop (PLL) Lock Time Data Rate per Channel (NRZ) 5 LATENCY 6 Pipeline Latency Fast Detect Latency Wake-Up Time 7 Standby Power-Down APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out of Range Recovery Time Min Typ 0.24 1400 240 Max Unit 1.40 GHz MSPS MSPS 156.25 156.25 62.5 1.6875 ps ps 76.9 28 28 5 13 75 26 Clock cycles Clock cycles 400 15 µs ms 192 43 1 ps fs rms Clock cycles The maximum sample rate is the clock rate after the divider. The minimum sample rate operates at 240 MSPS. See SPI Register 0x011A to reduce the threshold of the clock detect circuit. 3 Clock duty stabilizer (DCS) on. See SPI Register 0x011C and Register 0x011E to enable DCS. 4 Baud rate = 1/UI. A subset of this range can be supported. 5 Default L = 4. This number can change based on the sample rate and decimation ratio. 6 No DDCs used. L = 4, M = 2, and F = 1. 7 Wake-up time is defined as the time required to return to normal operation from power-down mode. 1 2 Rev. 0 | Page 8 of 130 16 ps ps ps ms Gbps Data Sheet AD9697 TIMING SPECIFICATIONS Table 5. Parameter CLK+ TO SYSREF+ TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tACCESS Test Conditions/Comments See Figure 3 Device clock to SYSREF+ setup time Device clock to SYSREF+ hold time See Figure 4 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Maximum time delay between falling edge of SCLK and output data valid for a read operation Time required for the SDIO pin to switch from an output to an input relative to the CSB rising edge (not shown in Figure 4) tDIS_SDIO Min 10 N – 75 N+1 N – 73 SAMPLE N N – 72 N–1 CLK– CLK+ CLK– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ A B C D E F G H I J CONVERTER0 SAMPLE N – 74 MSB A B C D E F G H I J CONVERTER0 SAMPLE N – 75 LSB A B C D E F G H I J CONVERTER0 SAMPLE N – 73 MSB A B C D E F G H I J CONVERTER0 SAMPLE N – 72 LSB SAMPLE N – 75 AND N – 74 ENCODED INTO ONE 8-BIT/10-BIT SYMBOL 16253-002 CLK+ SERDOUT0– Figure 2. Data Output Timing Diagram CLK– CLK+ tSU_SR tH_SR 16253-003 SYSREF– SYSREF+ Figure 3. SYSREF± Setup and Hold Timing Diagram Rev. 0 | Page 9 of 130 Unit −70 120 ps ps 6 ns ns ns ns ns ns ns ns 10 ns APERTURE DELAY N – 74 Max 4 2 40 2 2 10 10 Timing Diagrams ANALOG INPUT SIGNAL Typ AD9697 Data Sheet tDS tS tHIGH SDIO DON’T CARE DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 Figure 4. SPI Timing Diagram Rev. 0 | Page 10 of 130 D5 D4 D3 D2 D1 D0 DON’T CARE 16253-004 DON’T CARE tH tLOW CSB SCLK tACCESS tCLK tDH Data Sheet AD9697 ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD1 to AGND AVDD1_SR to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD1 to DRGND DRVDD2 to DRGND SPIVDD to DGND AGND to DRGND AGND to DGND DGND to DRGND VIN± to AGND CLK± to AGND SCLK, SDIO, CSB to DGND PDWN/STBY to DGND SYSREF± to AGND SYNCINB± to DRGND Junction Temperature Range (TJ) Storage Temperature Range, Ambient (TA) Rating 1.05 V 1.05 V 2.00 V 2.70 V 1.05 V 1.05 V 2.00 V 2.00 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V AGND − 0.3 V to AVDD3 + 0.3 V AGND − 0.3 V to AVDD1 + 0.3 V DGND − 0.3 V to SPIVDD + 0.3 V DGND − 0.3 V to SPIVDD + 0.3 V 2.5 V 2.5 V −40°C to +125°C −65°C to +150°C Typical θJA, θJB, and θJC are specified vs. the number of printed circuit board (PCB) layers in different airflow velocities (in m/sec). Airflow increases heat dissipation effectively reducing θJA and θJB. In addition, metal in direct contact with the package leads and exposed pad from metal traces, through holes, ground, and power planes, reduces θJA. Thermal performance for actual applications requires careful inspection of the conditions in an application. The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 6. Table 7. Thermal Resistance Package Type CP-64-17 Airflow Velocity (m/sec) 0 1.0 2.5 θJA1, 2 22.5 17.9 16.8 θJC_BOT1, 3 1.7 θJC_TOP1, 3 7.6 θJB1, 4 4.3 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 1 2 3 ESD CAUTION Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. 0 | Page 11 of 130 θJT1, 2 0.2 Unit °C/W °C/W °C/W AD9697 Data Sheet 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD1 AVDD2 AVDD2 AVDD1 AGND_SR SYSREF– SYSREF+ AVDD1_SR AGND_SR AVDD1 CLK– CLK+ AVDD1 AVDD2 AVDD2 AVDD1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD9697 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD1 AVDD1 AVDD2 AVDD3 DNC DNC AVDD3 AVDD2 AVDD2 AVDD2 SPIVDD CSB SCLK SDIO DVDD DGND NOTES 1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN. 2. ANALOG GROUND. CONNECT THE EXPOSED PAD TO THE ANALOG GROUND PLANE. 16253-005 FD/GPIO1 DRGND DRVDD1 SYNCINB– SYNCINB+ SERDOUT0– SERDOUT0+ SERDOUT1– SERDOUT1+ SERDOUT2– SERDOUT2+ SERDOUT3– SERDOUT3+ DRVDD1 DRGND GPIO2 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD1 AVDD1 AVDD2 AVDD3 VIN– VIN+ AVDD3 AVDD2 AVDD2 AVDD2 DRVDD2 VREF SPIVDD PDWN/STBY DVDD DGND Figure 5. Pin Configuration (Top View) Table 8. Pin Function Descriptions Pin No. 1, 2, 47 to 49, 52, 55, 61, 64 3, 8 to 10, 39 to 41, 46, 50, 51, 62, 63 4, 7, 42, 45 5, 6 11 12 Mnemonic AVDD1 Type Power supply Description Analog Power Supply (0.95 V Nominal). AVDD2 Power supply Analog Power Supply (1.8 V Nominal). AVDD3 VIN−, VIN+ DRVDD2 VREF Power supply Analog input Power supply Input/output 13, 38 14 SPIVDD PDWN/STBY Power supply Digital control input 15, 34 16, 33 17 18, 31 DVDD DGND FD/GPIO1 DRGND Power supply Ground power supply CMOS output Ground power supply 19, 30 20 21 22, 23 DRVDD1 SYNCINB− SYNCINB+ SERDOUT0−, SERDOUT0+ SERDOUT1−, SERDOUT1+ SERDOUT2− SERDOUT2+ Power supply Digital input Digital input Data output Analog Power Supply (2.5 V Nominal). ADC Analog Input Complement/True. Digital Driver Power Supply (1.8 V Nominal). Reference Voltage Input (0.50 V)/Do Not Connect. This pin is configurable through the SPI as a no connect pin or as an input. Do not connect this pin if using the internal reference. This pin requires a 0.50 V reference voltage input if using an external voltage reference source. Digital Power Supply for SPI (1.8 V Nominal). Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down (PDWN) or standby (STBY). Digital Power Supply (0.95 V Nominal). Digital Control Ground Supply. These pins connect to the digital ground plane. Fast Detect Output (FD). General-purpose input/output (GPIO) pin (GPIO1). Digital Driver Ground Supply. These pins connect to the digital driver ground plane. Digital Driver Power Supply (0.95 V Nominal). Active Low JESD204B LVDS/CMOS Sync Input True. Active Low JESD204B LVDS Sync Input Complement. Lane 0 Output Data Complement/True. Data output Lane 1 Output Data Complement/True. Data output Lane 2 Output Data Complement/True. 24, 25 26, 27 Rev. 0 | Page 12 of 130 Data Sheet Pin No. 28, 29 32 35 36 37 43, 44 53, 54 56, 60 57 58, 59 AD9697 Mnemonic SERDOUT3−, SERDOUT3+ GPIO2 SDIO SCLK CSB DNC CLK+, CLK− AGND_SR AVDD1_SR SYSREF+, SYSREF− EPAD Type Data output Description Lane 3 Output Data Complement/True. CMOS output Digital control input/output Digital control input Digital control input DNC Analog input Ground power supply Power supply Digital input General-Purpose Input/Output (GPIO) Pin (GPIO2). SPI Serial Data Input/Output. Ground power supply Analog Ground. Connect the exposed pad to the analog ground plane. SPI Serial Clock. SPI Chip Select (Active Low). Do Not Connect. Do not connect to these pins. Clock Input True/Complement. Ground Reference for SYSREF±. Analog Power Supply for SYSREF± (0.95 V Nominal). Active High JESD204B LVDS System Reference Input Complement/True. Rev. 0 | Page 13 of 130 AD9697 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 1300 MSPS, DCS on, buffer current setting specified in Table 10, and dc offset calibration enabled, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating TJ range of −40°C to +105°C. Typical specifications represent performance at TJ = 37°C (TA = 25°C). 10 fIN = 10.3MHz SNR = 65.7dBFS SFDR = 79.0dBFS BUFFER CURRENT = 300µA SNR = 65.2dBFS SFDR = 80.0dBFS BUFFER CURRENT = 300µA –30 –30 –50 –70 –90 –110 –50 –70 –90 200 0 400 600 FREQUENCY (MHz) –130 0 fIN = 172.3MHz SNR = 65.6dBFS SFDR = 78.0dBFS BUFFER CURRENT = 300µA SNR = 64.9dBFS SFDR = 81.0dBFS BUFFER CURRENT = 300µA –30 AMPLITUDE (dBFS) –70 –90 –50 –70 –90 400 600 FREQUENCY (MHz) –130 16253-306 200 0 0 600 Figure 10. Single-Tone FFT with fIN = 1002.3 MHz fIN = 342.3MHz fIN = 1402.3MHz SNR = 64.2dBFS SFDR = 76.0dBFS BUFFER CURRENT = 300µA –10 SNR = 65.6dBFS SFDR = 77.0dBFS BUFFER CURRENT = 300µA –30 AMPLITUDE (dBFS) –30 –50 –70 –90 –110 –50 –70 –90 –110 0 200 400 FREQUENCY (MHz) 600 16253-307 AMPLITUDE (dBFS) 400 FREQUENCY (MHz) Figure 7. Single-Tone FFT with fIN = 172.3 MHz –10 200 16253-309 –110 –110 –130 Figure 8. Single-Tone FFT with fIN = 342.3 MHz 0 200 400 FREQUENCY (MHz) Figure 11. Single-Tone FFT with fIN = 1402.3 MHz Rev. 0 | Page 14 of 130 600 16253-310 AMPLITUDE (dBFS) fIN = 1002.3MHz –10 –50 –130 600 Figure 9. Single-Tone FFT with fIN = 752.3 MHz –30 –130 400 FREQUENCY (MHz) Figure 6. Single-Tone FFT with Analog Input Frequency (fIN) = 10.3 MHz –10 200 16253-308 –110 16253-305 –130 fIN = 752.3MHz –10 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –10 Data Sheet AD9697 67 fIN = 1702.3MHz –10 SNR = 63.6dBFS SFDR = 80.0dBFS BUFFER CURRENT = 300µA TJ = +105°C ROOM TJ = –40°C 66 65 –50 SNR (dBFS) –70 63 –90 62 –110 0 200 600 400 FREQUENCY (MHz) 61 16253-311 –130 64 500 1000 1500 2000 ANALOG INPUT FREQUENCY (MHz) Figure 15. SNR vs. Analog Input Frequency at Minimum, Room, and Maximum Temperatures Figure 12. Single-Tone FFT with fIN = 1702.3 MHz 90 fIN = 1980.3MHz –10 0 16253-314 AMPLITUDE (dBFS) –30 SNR = 63.0dBFS SFDR = 79.0dBFS BUFFER CURRENT = 300µA TJ = +105°C ROOM TJ = –40°C 85 80 SDFR (dBFS) –50 –70 70 –90 200 600 400 FREQUENCY (MHz) 60 16253-312 0 0 500 1000 2000 Figure 16. SFDR vs. Analog Input Frequency at Minimum, Room, and Maximum Temperatures Figure 13. Single-Tone FFT with fIN = 1980.3 MHz 85 fIN1 = 170.8MHz fIN2 = 173.8MHz IMD = –84dBFS BUFFER CURRENT = 300µA –10 SNR SFDR AMPLITUDE (dBFS) 80 75 70 –60 –110 65 60 500 700 900 1100 1300 SAMPLE RATE (MHz) –160 16253-313 SNR/SFDR (dBFS) 1500 ANALOG INPUT FREQUENCY (MHz) 16253-315 65 –110 –130 75 0 200 400 600 FREQUENCY (MHz) Figure 17. Two-Tone FFT; fIN1 = 170.8 MHz, fIN2 = 173.8 MHz Figure 14. SNR/SFDR vs. Sample Rate, fIN = 172.3 MHz Rev. 0 | Page 15 of 130 16253-316 AMPLITUDE (dBFS) –30 AD9697 0 Data Sheet 85 fIN1 = 343.5MHz fIN2 = 346.5MHz IMD = –82dBFS BUFFER CURRENT = 300µA SNR SFDR 80 SNR/SFDR (dBFS) AMPLITUDE (dBFS) –40 –90 75 70 0 200 400 60 –40 16253-317 –140 600 FREQUENCY (MHz) 10 60 110 JUNCTION TEMPERATURE (°C) 16253-320 65 Figure 21. SNR/SFDR vs. Junction Temperature, fIN = 172.3 MHz Figure 18. Two-Tone FFT; fIN1 = 343.5 MHz, fIN2 = 346.5 MHz 2 120 100 1 80 SNR/SFDR (dB) 0 INL (LSB) 60 40 20 –1 –2 0 SFDR (dBFS) SNRFS SNR (dBc) SFDR (dBc) –60 –40 –20 0 –4 ANALOG INPUT AMPLITUDE (dBFS) 0 15000 Figure 22. INL, fIN = 10.3 MHz 0.3 10 SFDR (dBFS) SFDR (dBc) IMD3 (dBc) IMD3 (dBFS) –10 0.2 0.1 DNL (LSB) –30 –50 –70 0 –0.1 –90 –0.2 –110 –0.3 –75 –55 –35 ANALOG INPUT AMPLITUDE (dB) –15 –0.4 16253-319 SFDR/IMD3 (dB) 10000 OUTPUT CODE Figure 19. SNR/SFDR vs. Analog Input Amplitude, fIN = 172.3 MHz –130 –95 5000 16253-321 –80 0 5000 10000 OUTPUT CODE Figure 23. DNL, fIN = 10.3 MHz Figure 20. SFDR/IMD3 vs. Analog Input Amplitude, fIN = 172.3 MHz Rev. 0 | Page 16 of 130 15000 16253-322 –40 –100 –3 16253-318 –20 Data Sheet AD9697 1.10 NUMBER OF HITS 15000 10000 0 –16 –13 –10 –7 –4 –1 2 5 8 11 14 16 CODE 1.00 0.95 0.90 0.85 0.80 500 16253-323 5000 1.05 700 900 1100 1300 1500 SAMPLE RATE (MSPS) Figure 24. Input Referred Noise Histogram 16253-021 TOTAL POWER DISSIPATION (W) 20000 Figure 27. Total Power Dissipation vs. Sample Rate (fS) 66 0 –2 65 –8 –10 64 CLOCK AMPLITUDE 400mV 600mV 800mV 1000mV 1200mV 1400mV 1600mV 1800mV 2000mV 63 –12 62 –14 0 1000 2000 3000 4000 AIN FREQUENCY (MHz) 61 16253-019 –16 0 1000 1500 2000 Figure 28. SNR vs. Analog Input Frequency at Different Clock Amplitudes Figure 25. Full Power Bandwidth 86 1.4 84 1.3 82 SFDR (dBFS) 1.2 1.1 80 78 1.0 76 0.8 –40 BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT BUFFER CURRENT 74 10 60 110 JUNCTION TEMPERATURE (°C) Figure 26. Total Power Dissipation vs. Junction Temperature = 460µA = 400µA = 360µA = 300µA 72 0 500 1000 1500 ANALOG INPUT FREQUENCY (MHz) 2000 16253-328 0.9 16253-020 TOTAL POWER DISSIPATION (W) 500 ANALOG INPUT FREQUENCY (MHz) 16253-327 –6 SNR (dBFS) AMPLITUDE (dBFS) –4 Figure 29. SFDR vs. Analog Input Frequency with Different Buffer Current Settings Rev. 0 | Page 17 of 130 AD9697 Data Sheet 0.050 68 67 0.045 66 IAVDD3 (mA) SNR (dBFS) 0.040 65 64 0.035 0.030 63 2.04V 1.81V 1.59V 1.36V 61 0 500 1000 1500 2000 ANALOG INPUT FREQUENCY (MHz) 0.020 300 85 SFDR (dBFS) 80 75 70 500 1000 1500 ANALOG INPUT FREQUENCY (MHz) 2000 16253-330 2.04V 1.81V 1.59V 1.36V 0 450 500 Figure 32. IAVDD3 vs. Buffer Current Setting (Buffer Control 1 Setting in Register 0x1A4C) 90 60 400 BUFFER CURRENT SETTING (µA) Figure 30. SNR vs. Analog Input Frequency with Different Analog Input Full-Scale Values 65 350 16253-331 0.025 16253-329 62 Figure 31. SFDR vs. Analog Input Frequency with Different Analog Input Full-Scale Values Rev. 0 | Page 18 of 130 Data Sheet AD9697 EQUIVALENT CIRCUITS AVDD3 AVDD3 VIN+ 3.5pF AVDD3 400Ω EMPHASIS/SWING CONTROL (SPI) VCM BUFFER 10pF DRVDD1 AVDD3 100Ω AVDD3 DATA+ SERDOUTx+ x = 0, 1, 2, 3 VIN– DRGND OUTPUT DRIVER AIN CONTROL (SPI) DATA– 16253-029 3.5pF DRVDD1 SERDOUTx– x = 0, 1, 2, 3 DRGND Figure 33. Analog Inputs 16253-032 100Ω Figure 36. Digital Outputs (DATA+ and DATA− Refer to Internal Signals) DRVDD1 DRGND 2.5kΩ CLK+ 100Ω SYNCINB+ 25Ω DRVDD1 10kΩ 1.9pF LEVEL TRANSLATOR DRGND 16kΩ 130kΩ AVDD1 CLK– DRGND 130kΩ 100Ω SYNCINB– 25Ω 16kΩ DRVDD1 10kΩ 16253-030 1.9pF VCM = 0.65V DRGND 16253-033 AVDD1 CMOS PATH SYNCINB PIN CONTROL (SPI) DRGND Figure 37. SYNCINB± Inputs Figure 34. Clock Inputs AVDD1_SR 100Ω 10kΩ 1.9pF 130kΩ SPIVDD LEVEL TRANSLATOR 130kΩ 100Ω SPIVDD AVDD1_SR SCLK 10kΩ 1.9pF 56kΩ ESD PROTECTED DGND 16253-031 SYSREF– ESD PROTECTED Figure 38. SCLK Input Figure 35. SYSREF± Inputs Rev. 0 | Page 19 of 130 DGND 16253-034 SYSREF+ AD9697 Data Sheet SPIVDD ESD PROTECTED SPIVDD ESD PROTECTED 56kΩ PDWN/ STBY CSB 56kΩ ESD PROTECTED DGND PDWN CONTROL (SPI) 16253-035 DGND DGND DGND Figure 39. CSB Input 16253-037 ESD PROTECTED Figure 41. PDWN/STBY Input SPIVDD SPIVDD SDI DGND SDIO 56kΩ DGND DGND TEMPERATURE DIODE VOLTAGE OUTPUT AVDD2 SDO DGND EXTERNAL REFERENCE VOLTAGE INPUT VREF 16253-036 VREF PIN CONTROL (SPI) AGND Figure 42. VREF Input/Output Figure 40. SDIO Input SPIVDD SPIVDD ESD PROTECTED NCO BAND SELECT DGND FD/GPIO1, GPIO2 SPIVDD FD JESD204B LMFC 56kΩ ESD PROTECTED JESD204B SYNC~ DGND DGND DGND FD PIN CONTROL (SPI) Figure 43. FD/GPIO1, GPIO2 Input Rev. 0 | Page 20 of 130 16253-039 ESD PROTECTED VCM OUTPUT SPIVDD 16253-038 ESD PROTECTED Data Sheet AD9697 THEORY OF OPERATION The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. low-pass filter that limits unwanted broadband noise. For more information, refer to the Analog Dialogue article “TransformerCoupled Front-End for Wideband A/D Converters” (Volume 39, April 2005). In general, the precise front-end network component values depend on the application. Figure 44 shows the differential input return loss curve for the analog inputs across a frequency range of 1 MHz to 10 GHz. The reference impedance is 100 Ω. The AD9697 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. The Subclass 1 JESD204B-based high speed, serialized output data lanes can be configured in one-lane (L = 1), two-lane (L = 2), and four-lane (L = 4) configurations, depending on the sample rate and the decimation ratio. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins. The SYSREF± pin in the AD9697 can also be used as a timestamp of data as it passes through the ADC and out of the JESD204B interface. ADC ARCHITECTURE The architecture of the AD9697 consists of an input buffered pipelined ADC. The input buffer provides a termination impedance to the analog input signal. This termination impedance is set to 200 Ω. The equivalent circuit diagram of the analog input termination is shown in Figure 33. The input buffer is optimized for high linearity, low noise, and low power across a wide bandwidth. The input buffer provides a linear high input impedance (for ease of drive) and reduces kickback from the ADC. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample; at the same time, the remaining stages operate with the preceding samples. Sampling occurs on the rising edge of the clock. ANALOG INPUT CONSIDERATIONS The analog input to the AD9697 is a differential buffer. The internal common-mode voltage of the buffer is 1.41 V. The clock signal alternately switches the input circuit between sample mode and hold mode. Either a differential capacitor or two single-ended capacitors (or a combination of both) can be placed on the inputs to provide a matching passive network. These capacitors ultimately create a 1: 1.000MHz 170.59nF 2: 100.000 MHz 45.72pF 3: 200.000MHz 12.07pF 4: 300.000MHz 6.49pF 5: 400.000MHz 4.70pF 6: 500.000MHz 4.00pF 182.88Ω –932.98mΩ 177.37Ω –34.81Ω 157.29Ω –65.95Ω 128.82Ω –81.70Ω 102.55Ω –84.58Ω 82.01Ω 1 –79.60Ω 2 3 6 4 5 CH1 AVG = 1 > CH1: START 1.0MHz STOP 10.0000GHz 16253-200 The AD9697 has a single analog input channel and up to four JESD204B output lane pairs. The ADC samples wide bandwidth analog signals of up to 2 GHz. The actual −3 dB roll-off of the analog inputs is 2 GHz. The AD9697 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package. Figure 44. Different Input Return Loss For best dynamic performance, the source impedances driving VIN+ and VIN− must be matched such that any commonmode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. For the AD9697, the available span is programmable through the SPI port from 1.36 V p-p to 2.04 V p-p differential, with 1.59 V p-p differential being the default. Differential Input Configurations There are several ways to drive the AD9697, either actively or passively. Optimum performance is achieved by driving the analog input differentially. For applications where SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration (see Figure 45 and Table 9) because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9697. For low to midrange frequencies, a double balun or double transformer network (see Figure 45 and Table 9) is recommended for optimum performance of the AD9697. For higher frequencies in the second or third Nyquist zones, it is recommended to remove some of the front-end passive components to ensure wideband operation (see Table 9). Rev. 0 | Page 21 of 130 AD9697 Data Sheet C2 R1 C3 R2 MARKI BAL-0006 R3 200Ω C4 C1 ADC R2 C2 C3 R3 16253-050 R1 NOTES 1. SEE TABLE 9 FOR COMPONENT VALUES Figure 45. Differential Transformer-Coupled Configuration for the AD9697 Table 9. Differential Transformer-Coupled Input Configuration Component Values Speed Grade AD9697-1300 Transformer BAL-0006/BAL-0006SMG R1 25 Ω R2 25 Ω R3 10 Ω C1 0.1 μF C2 0.1 μF C3 DNI1 C4 DNI1 DNI means do not insert. The analog inputs of the AD9697 are internally biased to the common mode, as shown in Figure 47. For dc-coupled applications, the recommended operation procedure is to export the common-mode voltage to the VREF pin using the SPI writes listed in this section. The common-mode voltage must be set by the exported value to ensure proper ADC operation. Disconnect the internal common-mode buffer from the analog input using Register 0x1908. When performing SPI writes for dc coupling operation, use the following register settings, in order: 1. 2. 3. 4. 5. Set Register 0x1908, Bit 2 to 1 to disconnect the internal common-mode buffer from the analog input. Set Register 0x18A6 to 0x00 to turn off the voltage reference. Set Register 0x18E6 to 0x00 to turn off the temperature diode export. Set Register 0x18E3, Bit 6 to 0x01 to turn on the VCM export. Set Register 0x18E3, Bits[5:0] to the buffer current setting (copy the buffer current setting from Register 0x1A4C and Register 0x1A4D to improve the accuracy of the commonmode export). Figure 46 shows the block diagram representation of a dccoupled application. ADC AMP ADC VOCM VREF VCM EXPORT SELECT SPI REGISTERS (0x1908, 0x18A6, 0x18E3, 0x18E6) 16253-041 Input Common Mode Figure 46. DC-Coupled Application Using the AD9697 Analog Input Buffer Controls and SFDR Optimization The AD9697 input buffer offers flexible controls for the analog inputs, such as, buffer current and input full-scale adjustment. All the available controls are shown in Figure 47. AVDD3 AVDD3 VIN+ 3.5pF 100Ω AVDD3 100Ω AVDD3 VIN– REGISTERS (0x0008, AVDD3 0x1908) 3.5pF REGISTERS (0x0008, 0x1A4C, 0x1A4D, 0x1910) Figure 47. Analog Input Controls Rev. 0 | Page 22 of 130 16253-042 1 Frequency Range 0). The latency of this overrange indicator matches the sample latency. The AD9697 also records any overrange condition in any of the eight virtual converters. For more information on the virtual converters, refer to Figure 65. The overrange status of each virtual converter is registered as a sticky bit in Register 0x0563. The contents of Register 0x0563 can be cleared using Register 0x0562, by toggling the bits corresponding to the virtual converter to set and reset position. Lower Threshold Magnitude (dBFS) = 20 log (Threshold Magnitude/213) For example, to set an upper threshold of −6 dBFS, write 0xFFF to Register 0x0247 and Register 0x0248. To set a lower threshold of −10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A. FAST THRESHOLD DETECTION (FD) The fast detect bit is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit is only cleared when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. This feature provides hysteresis and prevents the FD bit from excessively toggling. The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, located at Register 0x024B and Register 0x024C. See the Memory Map section (Register 0x0040, and Register 0x0245 to Register 0x024C in Table 44) for more details. UPPER THRESHOLD DWELL TIME LOWER THRESHOLD DWELL TIME FD Figure 64. Threshold Settings for FD Signal Rev. 0 | Page 28 of 130 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 16253-060 MIDSCALE TIMER RESET BY RISE ABOVE LOWER THRESHOLD Data Sheet AD9697 ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING The AD9697 contains a configurable signal path that allows different features to be enabled for different applications. These features are controlled using the chip application mode register, Register 0x0200. The chip operating mode is controlled by Bits[3:0] in this register, and the chip Q ignore is controlled by Bit 5. Table 11 shows the number of virtual converters required and the transport layer mapping. Figure 65 shows the virtual converters and their relationship to the DDC outputs when complex outputs are used. Each DDC channel outputs either two sample streams (I/Q) for the complex data components (real + imaginary), or one sample stream for real (I) data. The AD9697 can be configured to use up to eight virtual converters, depending on the DDC configuration. The AD9697 contains the following modes:   Full bandwidth mode: 14-bit ADC core running at the full sample rate. DDC mode: up to four digital downconverter (DDC) channels. The I/Q samples are always mapped in pairs with the I samples mapped to the first virtual converter and the Q samples mapped to the second virtual converter. With this transport layer mapping, the number of virtual converters are the same whether a single real converter is used along with a digital downconverter block producing I/Q outputs, or whether an analog downconversion is used with two real converters producing I/Q outputs. After the chip application mode is selected, the output decimation ratio is set using the chip decimation ratio in Register 0x0201, Bits[3:0]. The output sample rate = ADC sample rate/the chip decimation ratio. To support the different application layer modes, the AD9697 treats each sample stream (real, I, or Q) as originating from separate virtual converters. Figure 66 shows a block diagram of the two scenarios described for I/Q transport layer mapping. Table 11. Virtual Converter Mapping 1 2 2 4 4 8 Chip Operating Mode (Reg. 0x0200, Bits[3:0]) Full bandwidth mode (0x0) One DDC mode (0x1) One DDC mode (0x1) Two DDC mode (0x2) Two DDC mode (0x2) Four DDC mode (0x3) Four DDC mode (0x3) Virtual Converter Mapping Chip Q Ignore (0x0200, Bit 5) Real or complex (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) Real (I only) (0x1) Complex (I/Q) (0x0) 0 ADC samples DDC 0 I samples DDC 0 I samples DDC 0 I samples DDC 0 I samples DDC 0 I samples DDC 0 I samples REAL REAL REAL REAL REAL/I ADC SAMPLING AT fS REAL REAL REAL REAL 1 Unused 2 Unused 3 Unused 4 Unused 5 Unused 6 Unused 7 Unused Unused Unused Unused Unused Unused Unused Unused DDC 0 Q samples DDC 1 I samples DDC 0 Q samples DDC 1 I samples DDC 0 Q samples Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused DDC 1 I samples DDC 2 I samples DDC 1 I samples DDC 1 Q samples DDC 3 I samples DDC 1 Q samples Unused Unused Unused Unused Unused Unused Unused Unused DDC 2 I samples DDC 2 Q samples DDC 3 I samples DDC 3 Q samples DDC 0 I Q DDC 1 I DDC 2 I Q DDC 3 Q REAL/I CONVERTER 2 Q Q CONVERTER 3 I Q I REAL/I CONVERTER 0 Q Q CONVERTER 1 I OUTPUT INTERFACE REAL/I I CONVERTER 4 Q Q CONVERTER 5 REAL/I CONVERTER 6 Q Q CONVERTER 7 I Figure 65. DDCs and Virtual Converter Mapping Rev. 0 | Page 29 of 130 16253-061 No. of Virtual Converters Supported 1 AD9697 Data Sheet DIGITAL DOWNCONVERSION M=2 I CONVERTER 0 ADC REAL DIGITAL DOWNCONVERSION JESD204B Tx Q CONVERTER 1 Figure 66. I/Q Transport Layer Mapping Rev. 0 | Page 30 of 130 L LANES 16253-062 REAL Data Sheet AD9697 PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS SUPPORTED MODES  The AD9697 supports the following modes of operation (the asterisk symbol (*) denotes convolution):  Real 48-tap filter (see Figure 67)  DOUT[n] = DIN[n] × XY[n] PROGRAMMABLE FILTER (PFILT) ADC CORE DIN[n] 48-TAP FIR FILTER XY[n] DOUT[n] SIGNAL PROCESSING BLOCKS JESD204B INTERFACE 16253-063 I (REAL) Figure 67. Real 48-Tap Filter Configuration PROGRAMMABLE FILTER (PFILT) ADC CORE DIN[n] 96-TAP FIR FILTER XY[n] DOUT[n] SIGNAL PROCESSING BLOCKS JESD204B INTERFACE 16253-064 I (REAL) Figure 68. Real 96-Tap Filter Configuration PROGRAMMABLE FILTER (PFILT) I (REAL) ADC A CORE DIN [n] 24-TAP FIR FILTER x [n] 24-TAP FIR FILTER y [n] I′ (REAL) SIGNAL PROCESSING BLOCKS JESD204B INTERFACE DOUTI [n] 16253-067  Real 96-tap filter (see Figure 68)  DOUT[n] = DIN[n] × XY[n] Real set of two cascaded 24-tap filters (see Figure 69)  DOUT[n] = DIN[n] × X[n] × Y[n] Figure 69. Real, Two Cascaded, 24-Tap Filter Configuration Rev. 0 | Page 31 of 130 AD9697 Data Sheet PROGRAMMING INSTRUCTIONS Table 12. Register 0x0DF8 Definition Use the following procedure to set up the programmable FIR filter: Bits [7:3] [2:0] 1. 2. 3. 4. 5. 6. Enable the sample clock to the device. Configure the mode registers as follows: a. Set the I path mode (I mode) and gain in Register 0x0DF8 and Register 0x0DF9 (see Table 12 and Table 13). Only I Mode is available. Q Mode is not available on single-channel devices. Wait at least 5 µs to allow the programmable filter to power up. Program the I path coefficients to the internal shadow registers as follows: a. Program the XI coefficients in Register 0x0E00 to Register 0x0E2F (see Table 14). b. Program the YI coefficients in Register 0x0F00 to Register 0x0F2F (see Table 14). c. Program the tapped delay in Register 0x0F30 (note that this step is optional). Set the chip transfer bit using either of the following methods (note that setting the chip transfer bit applies the programmed shadow coefficients to the filter): a. Via the register map by setting the chip transfer bit (Register 0x000F = 0x01). b. Via a GPIO pin, as follows: i. Configure one of the GPIO pin as the chip transfer bit in Register 0x0040 to Register 0x0042. ii. Toggle the GPIO pin to initiate the chip transfer (the rising edge is triggered). When the I path mode register changes in Register 0x0DF8, all coefficients must be reprogrammed. Description Reserved Filter mode (I mode or Q mode) 000: filters bypassed 001: real 24-tap filter (X only) 010: real 48-tap filter (X and Y together) 100: real set of two cascaded 24-tap filters (X then Y cascaded) 111: real 96-tap filter (X and Y together) Table 13. Register 0x0DF9 Definition Bits 7 [6:4] 3 [2:0] Description Reserved Y filter gain 110: −12 dB loss 111: −6 dB loss 000: 0 dB gain 001: 6 dB gain 010: 12 dB gain Reserved X filter gain 110: −12 dB loss 111: −6 dB loss 000: 0 dB gain 001: 6 dB gain 010: 12 dB gain Table 14 shows the coefficient tables in Register 0x0E00 to Register 0x0F30. All coefficients are Q1.15 format (sign bit + 15 fractional bits). Table 14. I Coefficient Table (Device Selection = 0x1) 1 Addr. 0x0E00 0x0E01 0x0E02 0x0E03 … 0x0E2E 0x0E2F 0x0F00 0x0F01 0x0F02 0x0F03 … 0x0F2E 0x0F2F 0x0F30 1 Single 24-Tap Filter (I Mode [2:0] = 0x1) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] Unused Unused Unused Unused … Unused Unused Unused Single 48-Tap Filter (I Mode [2:0] = 0x2) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C24 [7:0] YI C24 [15:8] YI C25 [7:0] YI C25 [15:8] … YI C47 [7:0] YI C47 [15:0] Unused Two Cascaded 24-Tap Filters (I Mode [2:0] = 0x4) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C0 [7:0] YI C0 [15:8] YI C1 [7:0] YI C1 [15:8] … YI C23 [7:0] YI C23 [15:0] Unused XI Cn means I Path X Coefficient n, and YI Cn means I Path Y Coefficient n. Rev. 0 | Page 32 of 130 Single 96-Tap Filter (I Mode[2:0] = 0x7) XI C0 [7:0] XI C0 [15:8] XI C1 [7:0] XI C1 [15:8] … XI C23 [7:0] XI C23 [15:0] YI C24 [7:0] YI C24 [15:8] YI C25 [7:0] YI C25 [15:8] … YI C47 [7:0] YI C47 [15:0] Unused Data Sheet AD9697 DIGITAL DOWNCONVERTER (DDC) The AD9697 includes four digital downconverters (DDC 0 to DDC 3) that provide filtering and reduce the output data rate. This digital processing section includes an NCO, multiple decimating FIR filters, a gain stage, and a complex to real conversion stage. Each of these processing blocks has control lines that allow it to be independently enabled and disabled to provide the desired processing function. The digital downconverter can be configured to output either real data or complex output data. The DDCs output a 16-bit stream. To enable this operation, the converter number of bits, N, is set to a default value of 16, even though the analog core only outputs 14 bits. In full bandwidth operation, the ADC outputs are the 14-bit word followed by two zeros, unless the tail bits are enabled. DDC I/Q OUTPUT SELECTION Each DDC channel has two output ports that can be paired to support both real and complex outputs. For real output signals, only the DDC Output Port I is used (the DDC Output Port Q is invalid). For complex I/Q output signals, both DDC Output Port I and DDC Output Port Q are used. The I/Q outputs to each DDC channel are controlled by the DDC complex to real enable bit, Bit 3, in the DDC control registers (Register 0x0310, Register 0x0330, Register 0x0350 and Register 0x0370). The chip Q ignore bit in the chip mode register (Register 0x0200, Bit 5) controls the chip output muxing of all the DDC channels. When all DDC channels use real outputs, set this bit high to ignore all DDC Q output ports. When any of the DDC channels are set to use complex I/Q outputs, the user must clear this bit to use both DDC Output Port I and DDC Output Port Q. For more information, see Figure 86. DDC GENERAL DESCRIPTION The four DDC blocks extract a portion of the full digital spectrum captured by the ADC(s). They are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. Each DDC block contains the following signal processing stages:     Frequency translation stage (optional) Filtering stage Gain stage (optional) Complex to real conversion stage (optional) Frequency Translation Stage (Optional) This stage consists of a phase coherent NCO and quadrature mixers that can be used for frequency translation of both real or complex input signals. The phase coherent NCO allows an infinite number of frequency hops that are all referenced back to a single synchronization event. It also includes 16 shadow registers for fast switching applications. This stage shifts a portion of the available digital spectrum down to baseband. Filtering Stage After shifting down to baseband, this stage decimates the frequency spectrum using multiple low pass finite impulse response (FIR) filters for rate conversion. The decimation process lowers the output data rate, which in turn reduces the output interface rate. Gain Stage (Optional) Due to losses associated with mixing a real input signal down to baseband, this stage compensates by adding an additional 0 dB or 6 dB of gain. Complex to Real Conversion Stage (Optional) When real outputs are necessary, this stage converts the complex outputs back to real by performing an fS/4 mixing operation plus a filter to remove the complex component of the signal. Figure 70 shows the detailed block diagram of the DDCs implemented in the AD9697. Figure 71 shows an example usage of one of the four DDC channels with a real input signal and four half-band filters (HB4 + HB3 + HB2 + HB1) used. It shows both complex (decimate by 16) and real (decimate by 8) output options. Rev. 0 | Page 33 of 130 AD9697 Data Sheet GAIN = 0 OR +6dB COMPLEX TO REAL CONVERSION (OPTIONAL) GAIN = 0 OR +6dB COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) I NCO + MIXER (OPTIONAL) REAL GAIN = 0 OR +6dB REAL GAIN = 0 OR +6dB DDC 0 DECIMATION FILTERS Q REAL/I CONVERTER 0 Q CONVERTER 1 DDC 1 I NCO + MIXER (OPTIONAL) REAL REAL/I DECIMATION FILTERS Q ADC SAMPLING AT fS REAL/I CONVERTER 2 Q CONVERTER 3 DDC 2 REAL I NCO + MIXER (OPTIONAL) REAL DECIMATION FILTERS Q REAL/I CONVERTER 4 JESD204B TRANSMIT INTERFACE REAL L JESD204B LANES AT UP TO 16Gbps Q CONVERTER 5 DDC 3 REAL I NCO + MIXER (OPTIONAL) REAL REGISTER MAP CONTROLS GPIOx PINS SYNCHRONIZATION CONTROL CIRCUITS NCO CHANNEL SELECTION CIRCUITS Q SYSREF Q CONVERTER 7 SYSREF DCM = DECIMATION 16253-068 SYSREF± PIN DECIMATION FILTERS REAL/I CONVERTER 6 NCO CHANNEL SELECTION Figure 70. DDC Detailed Block Diagram Rev. 0 | Page 34 of 130 Data Sheet AD9697 ADC –fS/2 –fS /3 ADC SAMPLING AT fS REAL REAL INPUT—SAMPLED AT fS BANDWIDTH OF INTEREST IMAGE –fS/4 REAL BANDWIDTH OF INTEREST fS/32 –fS/32 DC –fS/16 fS/16 – fS/8 fS/8 fS/4 fS/3 fS/2 FREQUENCY TRANSLATION STAGE (OPTIONAL) DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND ((fS/3)/fS × 248 ) = +9.382513 (0x5555_5555_5555) I NCO TUNES CENTER OF BANDWIDTH OF INTEREST TO BASEBAND cos(ωt) REAL 48-BIT NCO 90° 0° –sin(ωt) Q DIGITAL FILTER RESPONSE –fS /3 –fS/4 FILTERING STAGE fS/32 –fS/32 DC –fS/16 fS/16 – fS/8 HB4 FIR 4 DIGITAL HALF-BAND FILTERS (HB4 + HB3 + HB2 + HB1) HB3 FIR fS/8 HB2 FIR fS/4 fS/3 fS/2 HB1 FIR I I HB4 FIR HB3 FIR HB2 FIR HB1 FIR Q Q 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS DIGITAL FILTER RESPONSE 0dB OR 6dB GAIN I GAIN STAGE (OPTIONAL) Q 0dB OR 6dB GAIN COMPLEX TO REAL CONVERSION STAGE (OPTIONAL) fS/32 –fS/32 DC –fS/16 fS/16 – fS/8 COMPLEX (I/Q) OUTPUTS DECIMATE BY 16 GAIN STAGE (OPTIONAL) fS/8 fS/4 MIXING + COMPLEX FILTER TO REMOVE Q 2 2 I Q fS/32 –fS/32 DC –fS/16 fS/16 DOWNSAMPLE BY 2 I REAL (I) OUTPUTS I DECIMATE BY 8 Q Q COMPLEX REAL/I TO REAL 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS – fS/8 fS/32 –fS/32 DC –fS/16 fS/16 fS/8 Figure 71. DDC Theory of Operation Example (Real Input) Rev. 0 | Page 35 of 130 16253-069 –fS/2 BANDWIDTH OF INTEREST IMAGE (–6dB LOSS DUE TO NCO + MIXER) BANDWIDTH OF INTEREST (–6dB LOSS DUE TO NCO + MIXER) AD9697 Data Sheet DDC FREQUENCY TRANSLATION Variable IF Mode DDC Frequency Translation General Description NCO and mixers are enabled. NCO output frequency can be used to digitally tune the IF frequency. Frequency translation is accomplished by using a 48-bit complex NCO with a digital quadrature mixer. This stage translates either a real or complex input signal from an IF to a baseband complex digital output (carrier frequency = 0 Hz). 0 Hz IF (ZIF) Mode The mixers are bypassed, and the NCO is disabled. fS/4 Hz IF Mode The frequency translation stage of each DDC can be controlled individually and supports four different IF modes using Bits[5:4] of the DDC control registers (Register 0x0310, Register 0x0330, Register 0x0350, and Register 0x0370). These IF modes are as follows: Test Mode Input samples are forced to 0.999 to positive full scale. The NCO is enabled. This test mode allows the NCOs to directly drive the decimation filters. Variable IF mode 0 Hz IF or zero IF (ZIF) mode fS/4 Hz IF mode Test mode Figure 72 shows an example of the frequency translation stage for real inputs. NCO FREQUENCY TUNING WORD (FTW) SELECTION 48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 I ADC + DIGITAL MIXER + NCO REAL INPUT—SAMPLED AT fS REAL cos(ωt) ADC SAMPLING AT fS REAL 48-BIT NCO 90° 0° COMPLEX –sin(ωt) Q BANDWIDTH OF INTEREST BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 –fS/8 –fS/32 fS/32 DC –fS/16 fS/16 fS/8 fS/4 fS/3 fS/2 –6dB LOSS DUE TO NCO + MIXER 48-BIT NCO FTW = ROUND ((fS/3)/fS × 248) = +9.382513 (0x5555_5555_5555) POSITIVE FTW VALUES –fS/32 DC fS/32 48-BIT NCO FTW = ROUND (( fS/3)/fS × 248) = –9.382513 (0xAAAA_AAAA_AAAA) NEGATIVE FTW VALUES –fS/32 DC fS/32 Figure 72. DDC NCO Frequency Tuning Word Selection—Real Inputs Rev. 0 | Page 36 of 130 16253-070 • • • • The mixers and the NCO are enabled in special downmixing by fS/4 mode to save power. Data Sheet AD9697 DDC NCO Description DDC NCO Coherent Mode Each DDC contains one NCO. Each NCO enables the frequency translation process by creating a complex exponential frequency (e-jωct), which can be mixed with the input spectrum to translate the desired frequency band of interest to dc, where it can be filtered by the subsequent low-pass filter blocks to prevent aliasing. This mode allows an infinite number of frequency hops where the phase is referenced to a single synchronization event at Time 0. This mode is useful when phase coherency must be maintained when switching between different frequency bands. In this mode, the user can switch to any tuning frequency without the need to reset the NCO. Although only one FTW is required, the NCO contains 16 shadow registers for fast-switching applications. Selection of the shadow registers is controlled by the CMOS GPIO pins or through the register map of the SPI. In this mode, the NCO can be set up by providing the following: When placed in variable IF mode, the NCO supports two different additional modes. DDC NCO Programmable Modulus Mode This mode supports >48-bit frequency tuning accuracy for applications that require exact rational (M/N) frequency synthesis at a single carrier frequency. In this mode, the NCO is set up by providing the following: • • • • • • • Figure 73 shows a block diagram of one NCO and its connection to the rest of the design. The coherent phase accumulator block contains the logic that allows an infinite number of frequency hops. 48-bit frequency tuning word (FTW) 48-bit Modulus A word (MAW) 48-bit Modulus B word (MBW) 48-bit phase offset word (POW) NCO NCO CHANNEL SELECTION FTW/POW WRITE INDEX SYNCHRONIZATION CONTROL CIRCUITS I/O CROSSBAR MUX MODULUS ERROR 0 48-BIT FTW/POW 0 1 48-BIT FTW/POW 1 48-BIT FTW/POW 15 15 COHERENT PHASE ACCUMULATOR BLOCK COS/SIN GENERATOR cos(x) FTW/POW REGISTER MAP 48-BIT MAW/MBW SYSREF I I Q Q DIGITAL QUADRATURE MIXER FTW = FREQUENCY TUNING WORD POW = PHASE OFFSET WORD MAW = MODULUS A WORD (NUMERATOR) MBW = MODULUS B WORD (DENOMINATOR) Figure 73. NCO + Mixer Block Diagram Rev. 0 | Page 37 of 130 DECIMATION FILTERS 16253-072 MAW/MBW –sin(x) NCO CHANNEL SELECTION CIRCUITS Up to sixteen 48-bit FTWs. Up to sixteen 48-bit POWs. The 48-bit MAW must be set to zero in coherent mode. AD9697 Data Sheet NCO FTW/POW/MAW/MAB Description The NCO frequency value is determined by the following settings:    Equation 1 to Equation 4 apply to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). 48-bit twos complement number entered in the FTW 48-bit unsigned number entered in the MAW 48-bit unsigned number entered in the MBW Frequencies between −fS/2 and +fS/2 (fS/2 excluded) are represented using the following values:    floor(x) is defined as the largest integer less than or equal to x. For example, floor(3.6) = 3. FTW = 0x8000_0000_0000 and MAW = 0x0000_0000_0000 represents a frequency of –fS/2. FTW = 0x0000_0000_0000 and MAW = 0x0000_0000_0000 represents dc (frequency is 0 Hz). FTW = 0x7FFF_FFFF_FFFF and MAW = 0x0000_0000_0000 represents a frequency of +fS/2. M and N are integers reduced to their lowest terms. MAW and MBW are integers reduced to their lowest terms. When MAW is set to zero, the programmable modulus logic is automatically disabled. For example, if the ADC sampling frequency (fS) is 1300 MSPS and the carrier frequency (fC) is 417.8 MHz, then, mod  417.8,1300  M 2089   1300 N 6250  mod  2417.8,1300   FTW  floor  248  1300   NCO FTW/POW/MAW/MAB Programmable Modulus Mode For programmable modulus mode, the MAW must be set to a nonzero value (not equal to 0x0000_0000_0000). This mode is only needed when frequency accuracy of >48 bits is required. One example of a rational frequency synthesis requirement that requires >48 bits of accuracy is a carrier frequency of 1/3 the sample rate. When frequency accuracy of ≤48 bits is required, coherent mode must be used (see the NCO FTW/POW/MAW/MAB Coherent Mode section). In programmable modulus mode, the FTW, MAW, and MBW must satisfy the following four equations (for a detailed description of the programmable modulus feature, see the DDS architecture described in the AN-953 Application Note): mod ( f C , f S ) M   fS N FTW  floor (248 FTW  MAW MBW 2 48 mod( fC , f S ) fS = 0x5590_C0AD_03D9 MAW = mod(248 × 2089, 6250) = 0x0000_0000_1117 MBW = 0x0000_0000_186A The actual carrier frequency can be calculated based on the following equation: f C _ ACTUAL  FTW  MAW  fS MBW 2 48 For the previous example, the actual carrier frequency (fC_ACTUAL) is fC _ ACTUAL  (1) 0x5590_C0AD_03D9  1300 MHz  417.8MHz ) (2) MAW = mod(248 × M, N) (3) MBW = N (4) where: fC is the desired carrier frequency. fS is the ADC sampling frequency. M is the integer representing the rational numerator of the frequency ratio. N is the integer representing the rational denominator of the frequency ratio. FTW is the 48-bit twos complement number representing the NCO FTW. MAW is the 48-bit unsigned number representing the NCO MAW (must be 10log(bandwidth/fS/2). TB1 is only supported in DDC 0 and DDC 1. Table 17. DDC Filter Configurations (fS = 1300 MSPS) 1 ADC Sample Rate (MSPS) 1300 1300 1300 1300 1300 1300 1300 1300 1300 1300 1300 1300 1300 1300 1 2 DDC Filter Configuration HB1 TB1 2 HB2 + HB1 TB2 + HB1 HB3 + HB2 + HB1 FB2 + HB1 TB2 + HB2 + HB1 FB2 + TB12 HB4 + HB3 + HB2 + HB1 FB2 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 HB2 + FB2 + TB12 FB2 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 Real (I) Output Decimation Sample Rate Ratio (MSPS) 1 1300 N/A N/A 2 650 3 433.33 4 325 5 260 6 216.67 N/A N/A 8 162.5 10 130 12 108.33 N/A N/A 20 65 24 54.16 N/A means not applicable. TB1 is only supported in DDC 0 and DDC 1. Rev. 0 | Page 45 of 130 Complex (I/Q) Outputs Decimation Sample Rate Ratio (MSPS) 2 650 (I) + 650 (Q) 3 433.33 (I) + 433.33 (Q) 4 325 (I) + 325 (Q) 6 216.67 (I) + 216.67 (Q) 8 162.5 (I) + 162.5 (Q) 10 130 (I) + 130 (Q) 12 108.33 (I) + 108.33 (Q) 15 86.67 (I) + 86.67 (Q) 16 81.25 (I) + 81.25 (Q) 20 65 (I) + 65 (Q) 24 54.16 (I) + 54.16 (Q) 30 43.44 (I) + 43.44 (Q) 40 32.5 (I) + 32.5 (Q) 48 27.08 (I) + 27.08 (Q) Alias-Protected Bandwidth (MHz) 520 346.67 260 173.33 130 104 86.67 69.33 65 52 43.33 34.67 26 21.67 AD9697 Data Sheet HB4 Filter Description 20 Normalized Coefficient +0.006042 0 −0.049377 0 +0.293335 +0.5 HB4 Coefficient No. C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Decimal Coefficient (15-Bit) +99 0 −809 0 +4806 +8192 20 0 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED FREQUENCY (× Π RAD/s) Figure 80. HB3 Filter Response HB2 Filter Description The third decimate by 2, half-band, low-pass, FIR filter (HB2) uses a 19-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB2 filter is only used when complex or real outputs (decimate by 4, 8, or 16) is enabled; otherwise, it is bypassed. –40 Table 20 and Figure 81 show the coefficients and response of the HB2 filter. –60 –80 Table 20. HB2 Filter Coefficients –100 –120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) 0.9 1.0 16253-078 –140 –160 –40 Figure 79. HB4 Filter Response HB3 Filter Description The second decimate by 2, half-band, low-pass, FIR filter (HB3) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB3 filter is only used when complex outputs (decimate by 8 or 16) or real outputs (decimate by 4 or 8) are enabled; otherwise, it is bypassed. Table 19 and Figure 80 show the coefficients and response of the HB3 filter. HB2 Coefficient No. C1, C19 C2, C18 C3, C17 C4, C16 C5, C15 C6, C14 C7, C13 C8, C12 C9, C11 C10 0 –20 Decimal Coefficient (17-Bit) +435 0 −3346 0 +19,295 +32,768 MAGNITUDE (dB) HB3 Coefficient No. C1, C11 C2, C10 C3, C9 C4, C8 C5, C7 C6 Decimal Coefficient (18-Bit) +88 0 −698 0 +2981 0 −9723 0 +40120 +65536 20 Table 19. HB3 Filter Coefficients Normalized Coefficient +0.006638 0 −0.051056 0 +0.294418 +0.500000 Normalized Coefficient +0.000671 0 −0.005325 0 +0.022743 0 −0.074181 0 +0.306091 +0.5 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) Figure 81. HB2 Filter Response Rev. 0 | Page 46 of 130 0.9 1.0 16253-080 MAGNITUDE (dB) –20 –20 16253-079 Table 18. HB4 Filter Coefficients 0 MAGNITUDE (dB) The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB4 filter is only used when complex outputs (decimate by 16) or real outputs (decimate by 8) are enabled; otherwise, it is bypassed. Table 18 and Figure 79 show the coefficients and response of the HB4 filter. Data Sheet AD9697 HB1 Filter Description 20 Decimal Coefficient (20-Bit) −10 0 +38 0 −102 0 +232 0 −467 0 +862 0 −1489 0 +2440 0 −3833 0 +5831 0 −8679 0 12803 0 −19086 0 +29814 0 −53421 0 +166138 +262144 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED FREQUENCY (× Π RAD/s) Figure 82. HB1 Filter Response TB2 Filter Description The TB2 uses a 26-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The TB2 filter is only used when decimation ratios of 6, 12, or 24 are required. Table 22 and Figure 83 show the coefficients and response of the TB2 filter. Table 22. TB2 Filter Coefficients TB2 Coefficient No. C1, C26 C2, C25 C3, C24 C4, C23 C5, C22 C6, C21 C7, C20 C8, C19 C9, C18 C10, C17 C11, C16 C12, C15 C13, C14 Normalized Coefficient −0.000191 −0.000793 −0.001137 +0.000916 +0.006290 +0.009823 +0.000916 −0.023483 −0.043152 −0.019318 +0.071327 +0.201172 +0.297756 Decimal Coefficient (19-Bit) −50 +208 −298 +240 +1649 +2575 +240 −6156 −11312 −5064 +18698 +52736 +78055 20 0 –20 MAGNITUDE (dB) –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 NORMALIZED FREQUENCY (× Π RAD/s) Figure 83. TB2 Filter Response Rev. 0 | Page 47 of 130 0.9 1.0 16253-082 HB1 Coefficient No. C1, C63 C2, C62 C3, C61 C4, C60 C5, C59 C6, C58 C7, C57 C8, C56 C9, C55 C10, C54 C11, C53 C12, C52 C13, C51 C14, C50 C15, C49 C16, C48 C17, C47 C18, C46 C19, C45 C20, C44 C21, C43 C22, C42 C23, C41 C24, C40 C25, C39 C26, C38 C27, C37 C28, C36 C29, C35 C30, C34 C31, C33 C32 Normalized Coefficient −0.000019 0 +0.000072 0 −0.000195 0 +0.000443 0 −0.000891 0 +0.001644 0 −0.002840 0 +0.004654 0 −0.007311 0 +0.011122 0 −0.016554 0 0.024420 0 −0.036404 0 +0.056866 0 −0.101892 0 +0.316883 +0.5 –20 16253-081 Table 21. HB1 Filter Coefficients 0 MAGNITUDE (dB) The fourth and final decimate by 2, half-band, low-pass, FIR filter (HB1) uses a 63-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB1 filter is always enabled and cannot be bypassed. Table 21 and Figure 82 show the coefficients and response of the HB1 filter. AD9697 Data Sheet TB1 Filter Description 20 TB1 Coefficient No. 1, 76 2, 75 3, 74 4, 73 5, 72 6, 71 7, 70 8, 69 9, 68 10, 67 11, 66 12, 65 13, 64 14, 63 15, 62 16, 61 17, 60 18, 59 19, 58 20, 57 21, 56 22, 55 23, 54 24, 53 25, 52 26, 51 27, 50 28, 49 29, 48 30, 47 31, 46 32, 45 33, 44 34, 43 35, 42 36, 41 37, 40 38, 39 Normalized Coefficient −0.000023 −0.000053 −0.000037 +0.000090 +0.000291 +0.000366 +0.000095 −0.000463 −0.000822 −0.000412 +0.000739 +0.001665 +0.001132 −0.000981 −0.002961 −0.002438 +0.001087 +0.004833 +0.004614 −0.000871 −0.007410 −0.008039 +0.000053 +0.010874 +0.013313 +0.001817 −0.015579 −0.021590 −0.005603 +0.022451 +0.035774 +0.013541 −0.034655 −0.066549 −0.035213 +0.071220 +0.210777 +0.309200 Decimal Coefficient (22-Bit) −96 −224 −156 +379 +1220 +1534 +398 −1940 −3448 −1729 +3100 +6984 +4748 −4114 −12418 −10226 +4560 +20272 +19352 −3652 −31080 −33718 +222 +45608 +55840 +7620 −65344 −90556 −23502 +94167 +150046 +56796 −145352 −279128 −147694 +298720 +884064 +1296880 –20 –40 –60 –80 –100 –120 –140 –160 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED FREQUENCY (× Π RAD/s) 16253-083 Table 23. TB1 Filter Coefficients 0 MAGNITUDE (dB) The TB1 decimate by 3, low-pass, FIR filter uses a 76-tap, symmetrical, fixed coefficient filter implementation. Table 23 shows the TB1 filter coefficients, and Figure 84 shows the TB1 filter response. TB1 is only supported in DDC 0 and DDC 1. Figure 84. TB1 Filter Response FB2 Filter Description The FB2 decimate by 5, low-pass, FIR filter uses a 48-tap, symmetrical, fixed coefficient filter implementation. Table 24 shows the FB2 filter coefficients, and Figure 85 shows the FB2 filter response. Table 24. FB2 Filter Coefficients FB2 Coefficient No. 1, 48 2, 47 3, 46 4, 45 5, 44 6, 43 7, 42 8, 41 9, 40 10, 39 11, 38 12, 37 13, 36 14, 35 15, 34 16, 33 17, 32 18, 31 19, 30 20, 29 21, 28 22, 27 23, 26 24, 25 Rev. 0 | Page 48 of 130 Normalized Coefficient +0.000007 −0.000004 −0.000069 −0.000244 −0.000544 −0.000870 −0.000962 −0.000448 +0.000977 +0.003237 +0.005614 +0.006714 +0.004871 −0.001011 −0.010456 −0.020729 −0.026978 −0.023453 −0.005608 +0.027681 +0.072720 +0.121223 +0.162346 +0.185959 Decimal Coefficient (21-Bit) 7 −4 −72 −256 −570 −912 −1009 −470 +1024 +3394 +5887 +7040 +5108 −1060 −10964 −21736 −28288 −24592 −5880 +29026 +76252 +127112 +170232 +194992 Data Sheet AD9697 When mixing a complex input signal down to baseband, the mixer has already recentered the dynamic range of the signal within the full scale of the output bits, and no additional gain is necessary. However, the optional 6 dB gain compensates for low signal strengths. The downsample by 2 portion of the HB1 FIR filter is bypassed when using the complex to real conversion stage. The TB1 filter does not have the 6 dB gain stage. 20 0 MAGNITUDE (dB) –20 –40 –60 –80 DDC COMPLEX TO REAL CONVERSION –100 Each DDC contains an independently controlled complex to real conversion block. The complex to real conversion block reuses the last filter (HB1 FIR) in the filtering stage along with an fS/4 complex mixer to upconvert the signal. After upconverting the signal, the Q portion of the complex mixer is no longer needed and is dropped. The TB1 filter does not support complex to real conversion. –120 –160 0 0.2 0.1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 NORMALIZED FREQUENCY (× Π RAD/s) 16253-084 –140 Figure 85. FB2 Filter Response DDC GAIN STAGE Figure 86 shows a simplified block diagram of the complex to real conversion. Each DDC contains an independently controlled gain stage. The gain is selectable as either 0 dB or 6 dB. When mixing a real input signal down to baseband, it is recommended that the user enable the 6 dB of gain to recenter the dynamic range of the signal within the full scale of the output bits. HB1 FIR GAIN STAGE COMPLEX TO REAL ENABLE LOW-PASS FILTER I 2 0dB OR 6dB I 0 I/REAL 1 COMPLEX TO REAL CONVERSION 0dB OR 6dB I cos(wt) + REAL 90° fS/4 0° – sin(wt) LOW-PASS FILTER 2 Q 0dB OR 6dB Q Q 16253-085 Q 0dB OR 6dB HB1 FIR Figure 86. Complex to Real Conversion Block Rev. 0 | Page 49 of 130 AD9697 Data Sheet DDC MIXED DECIMATION SETTINGS The AD9697 also supports DDCs with different decimation rates. In this scenario, the chip decimation ratio must be set to the lowest decimation ratio of all the DDC channels. Samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Only mixed decimation ratios that are integer multiples of 2 are supported. For example, decimate by 1, 2, 4, 8, or 16 can be mixed together, decimate by 3, 6, 12, 24, or 48 can be mixed together, or decimate by 5, 10, 20, or 40 can be mixed together. Table 25 shows the DDC sample mapping when the chip decimation ratio is different than the DDC decimation ratio. For example, if the chip decimation ratio is set to decimate by 4, DDC 0 is set to use the HB2 + HB1 filters (complex outputs, decimate by 4) and DDC 1 is set to use the HB4 + HB3 + HB2 + HB1 filters (real outputs, decimate by 8), then DDC 1 repeats its output data two times for every one DDC 0 output. The resulting output samples are shown in Table 26. Table 25. Sample Mapping when Chip Decimation Ratio (DCM) Does Not Match DDC DCM Sample Index 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 DDC DCM = Chip DCM N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 N + 24 N + 25 N + 26 N + 27 N + 28 N + 29 N + 30 N + 31 DDC DCM = 2 × Chip DCM N N N+1 N+1 N+2 N+2 N+3 N+3 N+4 N+4 N+5 N+5 N+6 N+6 N+7 N+7 N+8 N+8 N+9 N+9 N + 10 N + 10 N + 11 N + 11 N + 12 N + 12 N + 13 N + 13 N + 14 N + 14 N + 15 N + 15 DDC DCM = 4 × Chip DCM N N N N N+1 N+1 N+1 N+1 N+2 N+2 N+2 N+2 N+3 N+3 N+3 N+3 N+4 N+4 N+4 N+4 N+5 N+5 N+5 N+5 N+6 N+6 N+6 N+6 N+7 N+7 N+7 N+7 Rev. 0 | Page 50 of 130 DDC DCM = 8 × Chip DCM N N N N N N N N N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+1 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+2 N+3 N+3 N+3 N+3 N+3 N+3 N+3 N+3 Data Sheet AD9697 Table 26. Chip DCM = 4, DDC 0 DCM = 4 (Complex), and DDC 1 DCM = 8 (Real) 1 DDC Input Samples N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 1 Output Port I I0[N] I0[N] I0[N] I0[N] I0[N + 1] I0[N + 1] I0[N + 1] I0[N + 1] I0[N + 2] I0[N + 2] I0[N + 2] I0[N + 2] I0[N + 3] I0[N + 3] I0[N + 3] I0[N + 3] DDC 0 Output Port Q Q0[N] Q0[N] Q0[N] Q0[N] Q0[N + 1] Q0[N + 1] Q0[N + 1] Q0[N + 1] Q0[N + 2] Q0[N + 2] Q0[N + 2] Q0[N + 2] Q0[N + 3] Q0[N + 3] Q0[N + 3] Q0[N + 3] Output Port I I1[N] I1[N] I1[N] I1[N] I1[N] I1[N] I1[N] I1[N] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] I1[N + 1] DDC 1 Output Port Q Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable Not applicable DCM means decimation. DDC EXAMPLE CONFIGURATIONS Table 27 describes the register settings for multiple DDC example configurations. Bandwidths listed are with 100 dB of stop band alias rejection. Table 27. DDC Example Configurations (per ADC Channel Pair) Chip Application Layer Two DDCs Chip Decimation Ratio 4 DDC Output Type Real Bandwidth Per DDC 1 10% × fS No. of Virtual Converters Required 2 Two DDCs 4 Complex 20% × fS 4 Rev. 0 | Page 51 of 130 Register Settings 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain; variable IF; real output; HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 additional decimation ratio selection 0x0331 = 0x00 (DDC 1 additional decimation ratio selection 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC 1 0x0200 = 0x02 (two DDCs; I/Q selected) 0x0201 = 0x02 (chip decimate by 4) 0x0310, 0x0330 = 0x40 (real mixer; 6 dB gain; variable IF; complex output; HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 additional decimation ratio selection 0x0331 = 0x00 (DDC 1 additional decimation ratio selection 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC 1 AD9697 Data Sheet Chip Application Layer Two DDCs Chip Decimation Ratio 8 DDC Output Type Real Bandwidth Per DDC 1 5% × fS No. of Virtual Converters Required 2 Four DDCs 8 Complex 10% × fS 8 Four DDCs 8 Real 5% × fS 4 Rev. 0 | Page 52 of 130 Register Settings 0x0200 = 0x22 (two DDCs; I only selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 additional decimation ratio selection 0x0331 = 0x00 (DDC 1 additional decimation ratio selection 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC 1 0x0200 = 0x03 (four DDCs; I/Q selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330, 0x0350, 0x0370 = 0x41 (real mixer; 6 dB gain; variable IF; complex output; HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 additional decimation ratio selection 0x0331 = 0x00 (DDC 1 additional decimation ratio selection 0x0351 = 0x00 (DDC 2 additional decimation ratio selection 0x0371 = 0x00 (DDC 3 additional decimation ratio selection 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC 1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC 2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC 3 0x0200 = 0x23 (four DDCs; I only selected) 0x0201 = 0x03 (chip decimate by 8) 0x0310, 0x0330, 0x0350, 0x0370 = 0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC 1 I input = ADC Channel A; DDC 1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC 2 I input = ADC Channel B; DDC 2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC 3 I input = ADC Channel B; DDC 3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC 1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC 2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC 3 Data Sheet Chip Application Layer Four DDCs 1 AD9697 Chip Decimation Ratio 16 DDC Output Type Complex Bandwidth Per DDC 1 5% × fS No. of Virtual Converters Required 8 fS is the ADC sample rate. Rev. 0 | Page 53 of 130 Register Settings 0x0200 = 0x03 (four DDCs; I/Q selected) 0x0201 = 0x04 (chip decimate by 16) 0x0310, 0x0330, 0x0350, 0x0370 = 0x42 (real mixer; 6 dB gain; variable IF; complex output; HB4 + HB3 + HB2 + HB1 filters) 0x0311 = 0x00 (DDC 0 I input = ADC Channel A; DDC 0 Q input = ADC Channel A) 0x0331 = 0x00 (DDC 1 I input = ADC Channel A; DDC 1 Q input = ADC Channel A) 0x0351 = 0x05 (DDC 2 I input = ADC Channel B; DDC 2 Q input = ADC Channel B) 0x0371 = 0x05 (DDC 3 I input = ADC Channel B; DDC 3 Q input = ADC Channel B) 0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B, 0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 = FTW and POW set as required by application for DDC 0 0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B, 0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 = FTW and POW set as required by application for DDC 1 0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B, 0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 = FTW and POW set as required by application for DDC 2 0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B, 0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 = FTW and POW set as required by application for DDC 3 AD9697 Data Sheet SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The results of the signal monitor block can be obtained either by reading back the internal values from the SPI port or by embedding the signal monitoring information into the JESD204B interface as special control bits. A global, 24-bit programmable period controls the duration of the measurement. Figure 87 shows the simplified block diagram of the signal monitor block. FROM MEMORY MAP SIGNAL MONITOR PERIOD REGISTERS (SMPR) 0x0271, 00x272, 0x0273 DOWN COUNTER IS COUNT = 1? LOAD MAGNITUDE STORAGE REGISTER LOAD LOAD SIGNAL MONITOR HOLDING REGISTER TO SPORT OVER JESD204B AND MEMORY MAP 16253-086 CLEAR FROM INPUT COMPARE A>B Figure 87. Signal Monitor Block The peak detector captures the largest signal within the observation period. The detector only observes the magnitude of the signal. The resolution of the peak detector is a 13-bit value, and the observation period is 24 bits and represents converter output samples. The peak magnitude can be derived by using the following equation: The magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal monitor period register (SMPR). The peak detector function is enabled by setting Bit 1 of Register 0x0270 in the signal monitor control register. The 24-bit SMPR must be programmed before activating this mode. After enabling peak detection mode, the value in the SMPR is loaded into a monitor period timer, which decrements at the decimated clock rate. The magnitude of the input signal is compared with the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map or output through the SPORT over the JESD204B interface. The monitor period timer is reloaded with the value in the SMPR, and the countdown restarts. In addition, the magnitude of the first input sample is updated in the magnitude storage register, and the comparison and update procedure, as explained previously, continues. Peak Magnitude (dBFS) = 20log(Peak Detector Value/213) Rev. 0 | Page 54 of 130 Data Sheet AD9697 SPORT OVER JESD204B significant control bit is used (see Example Configuration 1 and Example Configuration 2 in Figure 88). To select the SPORT over JESD204B option, program Register 0x0559, Register 0x055A, and Register 0x058F. See Table 44 for more information on setting these bits. The signal monitor data can also be serialized and sent over the JESD204B interface as control bits. These control bits must be deserialized from the samples to reconstruct the statistical data. The signal control monitor function is enabled by setting Bits[1:0] of Register 0x0279 and Bit 1 of Register 0x027A. Figure 88 shows two different example configurations for the signal monitor control bit locations inside the JESD204B samples. A maximum of three control bits can be inserted into the JESD204B samples; however, only one control bit is required for the signal monitor. Control bits are inserted from MSB to LSB. If only one control bit is to be inserted (CS = 1), only the most Figure 89 shows the 25-bit frame data that encapsulates the peak detector value. The frame data is transmitted MSB first with five 5-bit subframes. Each subframe contains a start bit that can be used by a receiver to validate the deserialized data. Figure 90 shows the SPORT over JESD204B signal monitor data with a monitor period timer set to 80 samples. 16-BIT JESD204B SAMPLE SIZE (N' = 16) EXAMPLE CONFIGURATION 1 (N' = 16, N = 15, CS = 1) 1-BIT CONTROL BIT (CS = 1) 15-BIT CONVERTER RESOLUTION (N = 15) 15 S[14] X 14 13 S[13] X S[12] X 12 S[11] X 11 9 10 S[10] X S[9] X 8 S[8] X 7 S[7] X 6 S[6] X 5 S[5] X 4 S[4] X S[3] X 3 S[2] X 2 S[1] X 1 0 S[0] X CTRL [BIT 2] X SERIALIZED SIGNAL MONITOR FRAME DATA 16-BIT JESD204B SAMPLE SIZE (N' = 16) 14-BIT CONVERTER RESOLUTION (N = 14) 15 S[13] X 14 13 S[12] X S[11] X 12 S[10] X 11 10 S[9] X 9 S[8] X 8 S[7] X 7 S[6] X 6 S[5] X 5 S[4] X 4 S[3] X S[2] X 3 S[1] X 2 1 0 S[0] X CTRL [BIT 2] X TAIL X SERIALIZED SIGNAL MONITOR FRAME DATA Figure 88. Signal Monitor Control Bit Locations 5-BIT SUBFRAMES 5-BIT IDLE SUBFRAME (OPTIONAL) 25-BIT FRAME IDLE 1 IDLE 1 IDLE 1 IDLE 1 IDLE 1 5-BIT IDENTIFIER START 0 SUBFRAME ID[3] 0 ID[2] 0 ID[1] 0 ID[0] 1 5-BIT DATA MSB SUBFRAME START 0 P[12] P[11] P[10] P[9] 5-BIT DATA SUBFRAME START 0 P[8] P[7] P[6] P5] 5-BIT DATA SUBFRAME START 0 P[4] P[3] P[2] P1] 5-BIT DATA LSB SUBFRAME START 0 P[0] 0 0 0 P[x] = PEAK MAGNITUDE VALUE Figure 89. SPORT over JESD204B Signal Monitor Frame Data Rev. 0 | Page 55 of 130 16253-088 EXAMPLE CONFIGURATION 2 (N' = 16, N = 14, CS = 1) 16253-087 1 CONTROL 1 TAIL BIT BIT (CS = 1) AD9697 Data Sheet SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00) 80 SAMPLE PERIOD PAYLOAD 25-BIT FRAME (N) IDENT. DATA MSB DATA DATA LSB DATA IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD PAYLOAD 25-BIT FRAME (N + 1) IDENT. DATA MSB DATA DATA LSB DATA IDLE IDLE IDLE IDLE IDLE 80 SAMPLE PERIOD IDENT. DATA MSB DATA DATA DATA LSB IDLE IDLE IDLE IDLE IDLE Figure 90. SPORT over JESD204B Signal Monitor Example Rev. 0 | Page 56 of 130 16253-089 PAYLOAD 25-BIT FRAME (N + 2) Data Sheet AD9697 DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE • The AD9697 digital outputs are designed to the JEDEC standard JESD204B, serial interface for data converters. JESD204B is a protocol to link the AD9697 to a digital processing device over a serial interface with lane rates of up to 16 Gbps. The benefits of the JESD204B interface over LVDS include a reduction in required board area for data interface routing, and an ability to enable smaller packages for converter and logic devices. JESD204B OVERVIEW • • • K is the number of frames per multiframe (AD9697 value = 4, 8, 12, 16, 20, 24, 28, or 32 ) S is the samples transmitted/single converter/frame cycle (AD9697 value = set automatically based on L, M, F, and N΄) HD is the high density mode (AD9697 = set automatically based on L, M, F, and N΄) CF is the number of control words/frame clock cycle/converter device (AD9697 value = 0) The JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8-bit/10-bit encoding as well as optional scrambling to form serial output data. Lane synchronization is supported through the use of special control characters during the initial establishment of the link. Additional control characters are embedded in the data stream to maintain synchronization thereafter. A JESD204B receiver is required to complete the serial link. For additional details on the JESD204B interface, refer to the JESD204B standard. Figure 91 shows a simplified block diagram of the AD9697 JESD204B link. By default, the AD9697 is configured to use two converters and four lanes. Converter A data is output to SERDOUT0± and/or SERDOUT1±, and Converter B is output to SERDOUT2± and/or SERDOUT3±. The AD9697 allows other configurations, such as combining the outputs of both converters onto a single lane, or changing the mapping of the A and B digital output paths. These modes are customizable, and can be set up via the SPI. Refer to the Memory Map section for more details. The AD9697 JESD204B data transmit block maps up to two physical ADCs or up to eight virtual converters (when DDCs are enabled) over a link. A link can be configured to use one, two, or four JESD204B lanes. The JESD204B specification refers to a number of parameters to define the link, and these parameters must match between the JESD204B transmitter (the AD9697 output) and the JESD204B receiver (the logic device input). By default in the AD9697, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF±, or fast detect output. The JESD204B link is described according to the following parameters: The two resulting octets can be scrambled. Scrambling is optional; however, it is recommended to avoid spectral peaks when transmitting similar digital data patterns. The scrambler uses a self-synchronizing, polynomial-based algorithm defined by the equation 1 + x14 + x15. The descrambler in the receiver is a self synchronizing version of the scrambler polynomial. • • • • • L is the number of lanes/converter device (lanes/link) (AD9697 value = 1, 2, or 4) M is the number of converters/converter device (virtual converters/link) (AD9697 value = 1, 2, 4, or 8) F is the octets/frame (AD9697 value = 1, 2, 4, 8, or 16) N΄ is the number of bits per sample (JESD204B word size) (AD9697 value = 8 or 16) N is the converter resolution (AD9697 value = 7 to 16) CS is the number of control bits/sample (AD9697 value = 0, 1, 2, or 3) CONVERTER A INPUT ADC A FORMAT (SPI REGISTER 0x0561) The two octets are then encoded with an 8-bit/10-bit encoder. The 8-bit/10-bit encoder works by taking eight bits of data (an octet) and encoding them into a 10-bit symbol. Figure 91 shows how the 14-bit data is taken from the ADC, how the tail bits are added, how the two octets are scrambled, and how the octets are encoded into two 10-bit symbols. Figure 92 shows the default data format. JESD204B LINK CONTROL (L, M, F) (SPI REGISTER 0x058B, 0x058E, 0x058C) LANE MUX AND MAPPING (SPI REGISTERS 0x05B0, 0x05B2, 0x05B3, 0x05B5, 0x05B6) SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± 16253-090 • SYSREF± SYNCINB± Figure 91. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00) Rev. 0 | Page 57 of 130 AD9697 Data Sheet JESD204B DATA LINK LAYER TEST PATTERNS 0x0574[2:0] JESD204B INTERFACE TEST PATTERN (0x0573, 0x0551 TO 0x0558) MSB A13 A12 A11 A10 A9 ADC A8 A7 A6 A5 A4 A3 A2 A1 LSB A0 OCTET1 TAIL BITS 0x0571[6] OCTET0 JESD204B SAMPLE CONSTRUCTION MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 A5 A4 A3 A2 A1 A0 C2 T MSB S7 S6 S5 S4 S3 S2 S1 LSB S0 S7 S6 S5 S4 S3 S2 S1 S0 SERIALIZER 8-BIT/ 10-BIT ENCODER a b i j a b SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± i j SYMBOL0 SYMBOL1 a b c d e f g h i j a b c d e f g h i j C2 C1 C0 16253-091 CONTROL BITS FRAME CONSTRUCTION SCRAMBLER 1 + x14 + x15 (OPTIONAL) OCTET1 ADC TEST PATTERNS (0x0550, 0x0551 TO 0x0558) OCTET0 JESD204B LONG TRANSPORT TEST PATTERN 0x0571[5] Figure 92. ADC Output Datapath Showing Data Framing TRANSPORT LAYER SAMPLE CONSTRUCTION FRAME CONSTRUCTION SCRAMBLER ALIGNMENT CHARACTER GENERATION 8-BIT/10-BIT ENCODER PHYSICAL LAYER CROSSBAR MUX SERIALIZER Tx OUTPUT 16253-092 PROCESSED SAMPLES FROM ADC DATA LINK LAYER SYSREF± SYNCINB± Figure 93. Data Flow FUNCTIONAL OVERVIEW Data Link Layer The block diagram in Figure 93 shows the flow of data through the JESD204B hardware from the sample input to the physical output. The processing can be divided into layers that are derived from the open source initiative (OSI) model, widely used to describe the abstraction layers of communications systems. These layers are the transport layer, data link layer, and physical layer (serializer and output driver). The data link layer is responsible for the low level functions of passing data across the link. These include optionally scrambling the data, inserting control characters during the initial lane alignment sequence (ILAS) and for frame and multiframe synchronization monitoring, and encoding 8-bit octets into 10-bit symbols. The data link layer is also responsible for sending the ILAS, which contains the link configuration data used by the receiver to verify the settings in the transport layer. Transport Layer The transport layer handles packing the data (consisting of samples and optional control bits) into JESD204B frames that are mapped to 8-bit octets. The packing of samples into frames are determined by the JESD204B configuration parameters for number of lanes (L), number of converters (M), the number of octets per lane per frame (F), the number of samples per converter per frame (S), and the number of bits in a nibble group (sometimes called the JESD204 word size − N’). Samples are mapped in order starting from Converter 0, then Converter 1, and so on until Converter M − 1. If S > 1, each sample from the converter is mapped before mapping the samples from the next converter. Each sample is mapped into words formed by appending converter control bits, if enabled, to the LSBs of each sample. The words are then padded with tail bits, if necessary, to form nibble groups (NGs) of the appropriate size as determined by the N’ parameter. The following equation can be used to determine the number of tail bits within a nibble group (JESD204B word): T = N΄ − N − CS Physical Layer The physical layer consists of the high speed circuitry clocked at the serial clock rate. In this layer, parallel data is converted into one, two, or four lanes of high speed differential serial data. JESD204B LINK ESTABLISHMENT The AD9697 JESD204B transmitter (Tx) interface operates in Subclass 0 or Subclass 1 as defined in the JEDEC Standard JESD204B (July 2011 specification). The link establishment process is divided into the following steps: code group synchronization, initial lane alignment sequence, and user data and error correction. Code Group Synchronization (CGS) CGS is the process by which the JESD204B receiver finds the boundaries between the 10-bit symbols in the stream of data. During the CGS phase, the JESD204B transmit block transmits /K/ characters (/K28.5/ symbols). The receiver must locate the /K/ characters in its input data stream using clock and data recovery (CDR) techniques. Rev. 0 | Page 58 of 130 Data Sheet AD9697 • The receiver issues a synchronization request by asserting the SYNCINB± pin of the AD9697 low. The JESD204B Tx then begins sending /K/ characters. Once the receiver has synchronized, it waits for the correct reception of at least four consecutive /K/ symbols. It then deasserts SYNCINB±. The AD9697 then transmits an ILAS on the following local multiframe clock (LMFC) boundary. User Data and Error Detection After the initial lane alignment sequence is complete, the user data (ADC samples) is sent. During transmission of the user data, a mechanism called character replacement monitors the frame clock and multiframe clock alignment. This mechanism replaces the last octet of a frame or multiframe with an /F/ or /A/ alignment characters when the data meets certain conditions. These conditions are different for unscrambled and scrambled data. The scrambling operation is enabled by default, but it can be disabled using the SPI. For more information on the code group synchronization phase, refer to the JEDEC Standard JESD204B, July 2011, Section 5.3.3.1. The SYNCINB± pin operation can also be controlled by the SPI. The SYNCINB± signal is a differential dc-coupled LVDS mode signal by default, but it can also be driven single-ended. For more information on configuring the SYNCINB± pin operation, refer to Register 0x0572. For scrambled data, any 0xFC character at the end of a frame is replaced by an /F/, and any 0x7C character at the end of a multiframe is replaced with an /A/. The JESD204B receiver (Rx) checks for /F/ and /A/ characters in the received data stream and verifies that they only occur in the expected locations. If an unexpected /F/ or /A/ character is found, the receiver handles the situation by using dynamic realignment or asserting the SYNCINB± signal for more than four frames to initiate a resynchronization. For unscrambled data, if the final octet of two subsequent frames are equal, the second octet is replaced with an /F/ symbol if it is at the end of a frame, and an /A/ symbol if it is at the end of a multiframe. The SYNCINB± pins can also be configured to run in CMOS (single-ended) mode by setting Bit 4 in Register 0x0572. When running SYNCINB± in CMOS mode, connect the CMOS SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20 (SYNCINB−) disconnected. Initial Lane Alignment Sequence (ILAS) The ILAS phase follows the CGS phase and begins on the next LMFC boundary after SYNCINB± deassertion. The ILAS consists of four mulitframes, with an /R/ character marking the beginning and an /A/ character marking the end. The ILAS begins by sending an /R/ character followed by 0 to 255 ramp data for one multiframe. On the second multiframe, the link configuration data is sent, starting with the third character. The second character is a /Q/ character to confirm that the link configuration data follows. All undefined data slots are filled with ramp data. The ILAS sequence is never scrambled. Insertion of alignment characters can be modified using SPI. The frame alignment character insertion (FACI) is enabled by default. More information on the link controls is available in the Memory Map section, Register 0x0571. 8-Bit/10-Bit Encoder The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols and inserts control characters into the stream when needed. The control characters used in JESD204B are shown in Table 28. The 8-bit/10-bit encoding ensures that the signal is dc balanced by using the same number of ones and zeros across multiple symbols. The ILAS sequence construction is shown in Figure 94. The four multiframes include the following: Multiframe 1 begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). Multiframe 2 begins with an /R/ character followed by a /Q/ character (/K28.4/), followed by link configuration parameters over 14 configuration octets (see Table 28) and ends with an /A/ character. Many of the parameter values are of the value – 1 notation. Multiframe 3 begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). • • K K R D ●●● D A R Q C ●●● C D ●●● The 8-bit/10-bit interface has options that can be controlled via the SPI. These operations include bypass and invert. These options are troubleshooting tools for the verification of the digital front end (DFE). Refer to the Memory Map section, Register 0x0572, Bits[2:1] for information on configuring the 8-bit/10-bit encoder. D A R D ●●● D A R D ●●● D A D END OF MULTIFRAME ●●● START OF ILAS ●●● ●●● ●●● START OF LINK CONFIGURATION DATA ●●● START OF USER DATA Figure 94. Initial Lane Alignment Sequence Rev. 0 | Page 59 of 130 16253-093 • Multiframe 4 begins with an /R/ character (/K28.0/) and ends with an /A/ character (/K28.3/). AD9697 Data Sheet Table 28. AD9697 Control Characters Used in JESD204B Abbreviation /R/ /A/ /Q/ /K/ /F/ 1 Control Symbol /K28.0/ /K28.3/ /K28.4/ /K28.5/ /K28.7/ 8-Bit Value 000 11100 011 11100 100 11100 101 11100 111 11100 10-Bit Value, RD 1 = −1 001111 0100 001111 0011 001111 0100 001111 1010 001111 1000 RD means running disparity. DRVDD1 10-Bit Value, RD1 = +1 110000 1011 110000 1100 110000 1101 110000 0101 110000 0111 Description Start of multiframe Lane alignment Start of link configuration data Group synchronization Frame alignment 100Ω DIFFERENTIAL 0.1µF TRACE PAIR SERDOUTx+ 100Ω 0.1µF RECEIVER 16253-094 SERDOUTx– OUTPUT SWING = 0.85 × DRVDD1 V p-p DIFFERENTIAL ADJUSTABLE TO 1 × DRVDD1, 0.75 × DRVDD1 Figure 95. AC-Coupled Digital Output Termination Example PHYSICAL LAYER (DRIVER) OUTPUTS The AD9697 digital outputs can interface with custom ASICs and field programmable gate array (FPGA) receivers, providing superior switching performance in noisy environments. Single point-to-point network topologies are recommended with a single differential 100 Ω termination resistor placed as close to the receiver inputs as possible. If there is no far end receiver termination, or if there is poor differential trace routing, timing errors can result. To avoid such timing errors, it is recommended that the trace length be less than six inches, and that the differential output traces be close together and at equal lengths. Figure 96. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps 16253-096 Place a 100 Ω differential termination resistor at each receiver input to result in a nominal 0.85 × DRVDD1 V p-p swing at the receiver (see Figure 95). The swing is adjustable through the SPI registers. AC coupling is recommended to connect to the receiver. See the Memory Map section (Register 0x05C0 to Register 0x05C3 in Table 44) for more details. Figure 97. Digital Outputs Jitter Histogram, External 100 Ω Terminations at 16 Gbps 16253-097 The AD9697 physical layer consists of drivers that are defined in the JEDEC Standard JESD204B, July 2011. The differential digital outputs are powered up by default. The drivers use a dynamic 100 Ω internal termination to reduce unwanted reflections. 16253-095 Digital Outputs, Timing, and Controls Figure 98. Digital Outputs Bathtub Curve, External 100 Ω Terminations at 16 Gbps Figure 96 to Figure 98 show an example of the digital outputs data eye, jitter histogram, and bathtub curve for one AD9697 lane running at 16 Gbps. The format of the output data is twos complement by default. To change the output data format, see the Memory Map section (Register 0x0561 in Table 44) for more details. Rev. 0 | Page 60 of 130 Data Sheet AD9697 De-Emphasis The initialization SPI writes are as shown in Table 30. De-emphasis enables the receiver eye diagram mask to be met in conditions where the interconnect insertion loss does not meet the JESD204B specification. Use the de-emphasis feature only when the receiver is unable to recover the clock due to excessive insertion loss. Under normal conditions, it is disabled to conserve power. Additionally, enabling and setting too high a de-emphasis value on a short link can cause the receiver eye diagram to fail. Use the de-emphasis setting with caution because it can increase electromagnetic interference (EMI). See the Memory Map section (Register 0x05C4 to Register 0x05CA in Table 44) for more details. Phase-Locked Loop (PLL) The PLL generates the serializer clock, which operates at the JESD204B lane rate. The status of the PLL lock can be checked in the PLL locked status bit (Register 0x056F, Bit 7). This read only bit notifies the user if the PLL achieved a lock for the specific setup. Register 0x056F also has a loss of lock (LOL) sticky bit (Bit 3) that notifies the user that a loss of lock is detected. The sticky bit can be reset by issuing a JESD204B link restart (Register 0x0571, Bit 0 = 0x1, followed by Register 0x0571, Bit 0 = 0x0). Refer to Table 30 for the reinitialization of the link following a link power cycle. The JESD204B lane rate control, Bits[7:4] of Register 0x056E, must be set to correspond with the lane rate. Table 29 shows the lane rates supported by the AD9697 using Register 0x056E. Table 29. AD9697 Register 0x056E Supported Lane Rates Value 0x00 0x10 0x30 0x50 Lane Rate Lane rate = 6.75 Gbps to 13.5 Lane rate = 3.375 Gbps to 6.75 Gbps (default) Lane rate = 13.5 Gbps to 16 Gbps Lane rate = 1.6875 Gbps to 3.375 Gbps SETTING UP THE AD9697 DIGITAL INTERFACE To ensure proper operation of the AD9697 at startup, some SPI writes are required to initialize the link. Additionally, these registers must be written every time the ADC is reset. Any one of the following resets warrants the initialization routine for the digital interface:       Hard reset, as with power-up. Power-up using the PDWN pin. Power-up using the SPI via Register 0x0002, Bits[1:0]. SPI soft reset by setting Register 0x0000 = 0x81. Datapath soft reset by setting Register 0x0001 = 0x02. JESD204B link power cycle by setting Register 0x0571, Bit 0 = 0x1, then 0x0. Table 30. AD9697 JESD204B Initialization Register 0x1228 0x1228 0x1222 0x1222 0x1222 0x1262 0x1262 Value 0x4F 0x0F 0x00 0x04 0x00 0x08 0x00 Comment Reset JESD204B start-up circuit JESD204B start-up circuit in normal operation JESD204B PLL force normal operation Reset JESD204B PLL calibration JESD204B PLL normal operation Clear loss of lock bit Loss of lock bit normal operation The AD9697 has one JESD204B link. The serial outputs (SERDOUT0± to SERDOUT3±) are considered to be part of one JESD204B link. The basic parameters that determine the link setup are    Number of lanes per link (L) Number of converters per link (M) Number of octets per frame (F) If the internal DDCs are used for on-chip digital processing, M represents the number of virtual converters. The virtual converter mapping setup is shown in Table 11. By default in the AD9697, the 14-bit converter word from each converter is broken into two octets (eight bits of data). Bit 13 (MSB) through Bit 6 are in the first octet. The second octet contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits can be configured as zeros or a pseudorandom number sequence. The tail bits can also be replaced with control bits indicating overrange, SYSREF±, or fast detect output. Control bits are filled and inserted MSB first such that enabling CS = 1 activates Control Bit 2, enabling CS = 2 activates Control Bit 2 and Control Bit 1, and enabling CS = 3 activates Control Bit 2, Control Bit 1, and Control Bit 0. The maximum lane rate allowed by the AD9697 is 16 Gbps. The lane rate is related to the JESD204B parameters using the following equation:  10  M  N '    fOUT 8 Lane Rate = L where fOUT = fADC_CLOCK/Decimation Ratio The decimation ratio (DCM) is the parameter programmed in Register 0x0201. Use the following procedure to configure the output: 1. 2. 3. 4. 5. 6. 7. Rev. 0 | Page 61 of 130 Power down the link. Select the JESD204B link configuration options. Configure the detailed options. Set output lane mapping (optional). Set additional driver configuration options (optional). Power up the link. Initialize the JESD204B link by issuing the commands described in Table 30. AD9697 Data Sheet Register 0x056E must be programmed according to the lane rate calculated. Refer to the Phase-Locked Loop (PLL) section for more details. Table 31 and Table 32 show the JESD204B output configurations supported for both N΄ = 16, N’=12, and N΄ = 8 for a given number of virtual converters. Take care to ensure that the serial lane rate for a given configuration is within the supported range of 1.6875 Gbps to 16 Gbps. Table 31. JESD204B Output Configurations for N΄ = 16 1 Number of Virtual Converters Supported (Same as M) 1 2 4 8 Supported Decimation Rates JESD204B Serial Lane Rate 2 20 × fOUT Lane Rate = 1.6875 Gbps to 3.375 Gbps 2, 4, 5, 6 Lane Rate = 3.375 Gbps to 6.75 Gbps 1, 2, 3 Lane Rate = 6.75 Gbps to 13.5 Gbps 1 Lane Rate = 13.5 Gbps to 16 Gbps N/A L 1 M 1 F 2 S 1 HD 0 N 8 to 16 N' 16 CS 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 1 1 4 2 0 8 to 16 16 0 to 3 10 × fOUT 1, 2, 3 1, N/A N/A 2 1 1 1 1 8 to 16 16 0 to 3 10 × fOUT 1, 2, 3 1 N/A N/A 2 1 2 2 0 8 to 16 16 0 to 3 5 × fOUT 1 N/A N/A N/A 4 1 1 2 1 8 to 16 16 0 to 3 5 × fOUT 1 N/A N/A N/A 4 1 2 4 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 5, 6 1, 2, 3 1 1 2 4 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 5, 6 1, 2, 3 1 1 2 8 2 0 8 to 16 16 0 to 3 20 × fOUT 4, 5, 6 1, 2, 3 1 N/A 2 2 2 1 0 8 to 16 16 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 2 2 4 2 0 8 to 16 16 0 to 3 10 × fOUT 1, 2, 3 1 N/A N/A 4 2 1 1 1 8 to 16 16 0 to 3 10 × fOUT 1, 2, 3 1 N/A N/A 4 2 2 2 0 8 to 16 16 0 to 3 80 × fOUT 8, 16, 20, 24 4, 8, 10, 12 2, 4, 6 2 1 4 8 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 5, 6 1, 2, 3 1 2 4 4 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 5, 6 1, 2, 3 1 2 4 8 2 0 8 to 16 16 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 4 4 2 1 0 8 to 16 16 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 4 4 4 2 0 8 to 16 16 0 to 3 160 × fOUT 16, 40, 48 8, 16, 20, 24 4, 8, 12 4 1 8 16 1 0 8 to 16 16 0 to 3 80 × fOUT 8, 16, 20, 24 4, 8, 10, 12 2, 4, 6 2 2 8 8 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 6 2 N/A 4 8 4 1 0 8 to 16 16 0 to 3 40 × fOUT 4, 8, 10, 12 2, 4, 6 2 N/A 4 8 8 2 0 8 to 16 16 0 to 3 JESD204B Transport Layer Settings 3 K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 3 fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 16 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤ 16,000 Mbps and > 13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13,500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32. 1 2 Rev. 0 | Page 62 of 130 Data Sheet AD9697 Table 32. JESD204B Output Configurations (N' = 12) 1 No. of Virtual Converters Supported (Same Value as M) 1 2 4 8 Supported Decimation Rates JESD204B Transport Layer Settings 3 Serial Lane Rate 2 15 × fOUT Lane Rate = 1.6875 Gbps to 3.375 Gbps 3 Lane Rate = 3.375 Gbps to 6.75 Gbps N/A Lane Rate = 6.75 Gbps to 13.5 Gbps N/A Lane Rate = 13.5 Gbps to 16 Gbps N/A L 1 M 1 F 3 S 2 HD 0 N 8 to 12 N' 12 L 0 to 3 7.5 × fOUT N/A N/A N/A N/A 2 1 3 4 1 8 to 12 12 0 to 3 7.5 × fOUT N/A N/A N/A N/A 2 1 6 8 0 8 to 12 12 0 to 3 5 × fOUT 1 N/A N/A N/A 3 1 1 2 1 8 to 12 12 0 to 3 30 × fOUT 3, 6 3 N/A N/A 1 2 3 1 0 8 to 12 12 0 to 3 15 × fOUT 3 N/A N/A N/A 2 2 3 2 0 8 to 12 12 0 to 3 10 × fOUT 1, 2, 3 1 N/A N/A 3 2 1 1 1 8 to 12 12 0 to 3 7.5 × fOUT N/A N/A N/A N/A 4 2 3 4 0 8 to 12 12 0 to 3 60 × fOUT 6, 12 3, 6 3 N/A 1 4 6 1 0 8 to 12 12 0 to 3 30 × fOUT 3, 6 3 N/A N/A 2 4 3 1 0 8 to 12 12 0 to 3 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 3 4 2 1 1 8 to 12 12 0 to 3 15 × fOUT 3 N/A N/A N/A 4 4 3 2 0 8 to 12 12 0 to 3 60 × fOUT 6, 12 6 N/A N/A 2 8 6 1 0 8 to 12 12 0 to 3 30 × fOUT 6 N/A N/A N/A 4 8 3 1 0 8 to 12 12 0 to 3 K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 16 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤ 16,000 Mbps and > 13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13,500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50. 3 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32. 1 2 Rev. 0 | Page 63 of 130 AD9697 Data Sheet Table 33. JESD204B Output Configurations for N΄ = 8 1 No. of Virtual Converters Supported (Same Value as M) 1 Serial Lane Rate 2 10 × fOUT Lane Rate = 1.6875 Gbps to 3.375 Gbps 1, 2, 3 Lane Rate = 3.375 Gbps to 6.75 Gbps 1 Lane Rate = 6.75 Gbps to 13.5 Gbps N/A Lane Rate = 13.5 Gbps to 16 Gbps N/A L 1 M 1 F 1 S 1 HD 0 N 7 to 8 N' 8 CS 0 to 1 1 10 × fOUT 1, 2, 3 1 N/A N/A 1 1 2 2 0 7 to 8 8 0 to 1 1 5 × fOUT 1 N/A N/A N/A 2 1 1 2 0 7 to 8 8 0 to 1 1 5 × fOUT 1 N/A N/A N/A 2 1 2 4 0 7 to 8 8 0 to 1 1 5 × fOUT 1 N/A N/A N/A 2 1 4 8 0 7 to 8 8 0 to 1 1 2.5 × fOUT N/A N/A N/A N/A 4 1 1 4 0 7 to 8 8 0 to 1 1 2.5 × fOUT N/A N/A N/A N/A 4 1 2 8 0 7 to 8 8 0 to 1 2 20 × fOUT 2, 4, 5, 6 1, 2, 3 1 N/A 1 2 2 1 0 7 to 8 8 0 to 1 2 10 × fOUT 1, 2, 3 1 N/A N/A 2 2 1 1 0 7 to 8 8 0 to 1 2 10 × fOUT 1, 2, 3 1 N/A N/A 2 2 2 2 0 7 to 8 8 0 to 1 2 5 × fOUT 1 N/A N/A N/A 4 2 1 2 0 7 to 8 8 0 to 1 2 5 × fOUT 1 N/A N/A N/A 4 2 2 4 0 7 to 8 8 0 to 1 2 5 × fOUT 1 N/A N/A N/A 4 2 4 8 0 7 to 8 8 0 to 1 Supported decimation rates JESD204B Transport Layer Settings 3 K See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 See Note 4 Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters. fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 16 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR is ≤ 16,000 Mbps and > 13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13,500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50. 3 JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per multiframe. 4 Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4, 8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32. 1 2 Rev. 0 | Page 64 of 130 Data Sheet AD9697 Example Setup 1—Full Bandwidth Mode 13Gbps 1300MSPS SYNC~ F=1 L1 VIN REAL 14-BIT ADC CORE M0 JESD204B LINK (L = 4, M = 1, F = 1, S = 2, N' = 16, N = 16, CS = 0, HD = 1) L2 L3 I = REAL COMPONENT Q = QUADRATURE COMPONENT DCM = DECIMATION C2R = COMPLEX TO REAL MX = VIRTUAL CONVERTER X LY = LANE Y SZ = SAMPLE Z INSIDE A JESD204B FRAME C = CONTROL BIT (OVERRANGE, AMONG OTHERS) T = TAIL BIT M0S0[15:8] M0S0[7:0] M0S1[15:8] M0S1[7:0] 16253-098 L0 Figure 99. Full Bandwidth Mode The AD9697 is set up as shown in Figure 99, with the following configurations: The JESD204B supported output configurations are as follows (see Table 31): • • • • • • • • • Two 14-bit converters at 1300 MSPS. Full bandwidth application layer mode. Decimation filters bypassed. The JESD204B output configuration is as follows: • • Two virtual converters required (see Table 31). Output sample rate (fOUT) = 1300/1 = 1300 MSPS. • Rev. 0 | Page 65 of 130 N΄ = 16 bits. N = 14 bits. L = 4, M = 1, and F = 1. CS = 0. K = 32. Output serial lane rate: • 6.5 Gbps per lane (L = 4). • 13 Gbps per lane (L = 2). PLL control register: • Register 0x056E is set to 0x10 (L = 4). • Register 0x056E is set to 0x00 (L = 2). AD9697 Data Sheet Example Setup 2—ADC with DDC Option (Two ADCs Plus Two DDCs) fOUT = fs / 4 (MHz) fs (MHz) 40 x fOUT MbPS SYNCAB~ DDC0 (REAL INPUT, DCM = 4 C2R = BYPASS) 14-BIT ADC CORE JESD204B LINK (L = 2 M=4 F = 4, S = 1, N' = 16, N = 16, CS = 0, HD =0) M1(Q) HB2_HB1 USED M2(I) DDC1 (REAL INPUT, DCM = 4 C2R = BYPASS) LAB0 LAB1 M3(Q) M2(I)S0[15:8] M2(I)S0[7:0] M3(Q)S0[15:8] M3(Q)S0[7:0] VIN REAL M0 (I)S0[15:8] M0(I)S0[7:0] M1 (Q)S0[15:8] M1(Q)S0[7:0] F=4 M0(I) I = REAL COMPONENT Q = QUADRATURE COMPONENT DCM = DECIMATION C2R = COMPLEX TO REAL MX= VIRTUAL CONVERTER X LY = LINK LANE Y SZ = SAMPLE Z INSIDE A JESD204B FRAME C = CONTROL BIT (OVER-RANGE, ETC.) T = TAIL BIT 16253-099 LEGEND Figure 100. Two ADCs Plus Two DDCs Mode (L = 4, M = 4, F = 2, S = 1) This example shows the flexibility in the digital and lane configurations for the AD9697. The sample rate is 1300 MSPS; whereas the outputs are all combined in a combination of either two or four lanes, depending on the input/output speed capability of the receiving device. The AD9697 is set up as shown in Figure 100, with the following configuration: • • • • One 14-bit converter at 1300 MSPS. Two DDC application layer mode with complex outputs (I/Q). Chip decimation ratio = 4. DDC decimation ratio = 4 (see the Memory Map section). The JESD204B output configuration is as follows: • • Four virtual converters required (see Table 31). Output sample rate (fOUT) = 1300 MSPS/4 = 325 MSPS. The JESD204B supported output configurations are as follows (see Table 31): • • • • • • N΄ = 16 bits. N = 14 bits. L = 2, M = 4, and F = 4, or L = 4, M = 4, and F = 4. CS = 0. K = 32. Output serial lane rate = 6.5 Gbps per lane (L = 4), 13 Gbps per lane (L = 2) For L = 2, set the PLL control register, Register 0x056E, to 0x00. For L = 4, set the PLL control register, Register 0x056E, to 0x10. Rev. 0 | Page 66 of 130 Data Sheet AD9697 DETERMINISTIC LATENCY boundaries and buffering to achieve consistent latency across lanes (or even multiple devices), and to achieve a fixed latency between power cycles and link reset conditions. Both ends of the JESD204B link contain various clock domains distributed throughout each system. Data traversing from one clock domain to a different clock domain can lead to ambiguous delays in the JESD204B link. These ambiguities lead to nonrepeatable latencies across the link from one power cycle or link reset to the next. Section 6 of the JESD204B specification addresses the issue of deterministic latency with mechanisms defined as Subclass 1 and Subclass 2. Deterministic Latency Requirements Several key factors are required for achieving deterministic latency in a JESD204B Subclass 1 system: • The AD9697 supports JESD204B Subclass 0 and Subclass 1 operation. Register 0x0590, Bit 5 sets the subclass mode for the AD9697; the default mode is the Subclass 1 operating mode (Register 0x0590, Bit 5 = 1). If deterministic latency is not a system requirement, Subclass 0 operation is recommended and the SYSREF± signal may not be required. Even in Subclass 0 mode, the SYSREF± signal may be required in an application where multiple AD9697 devices must be synchronized with each other. This topic is addressed in the Timestamp Mode section. • • SYSREF± signal distribution skew within the system must be less than the desired uncertainty for the system. SYSREF± setup and hold time requirements must be met for each device in the system. The total latency variation across all lanes, links, and devices must be ≤1 LMFC period (see Figure 101). This includes both variable delays and the variation in fixed delays from lane to lane, link to link, and device to device in the system. Setting Deterministic Latency Registers SUBCLASS 0 OPERATION The JESD204B receive buffer in the logic device buffers data starting on the LMFC boundary. If the total link latency in the system is near an integer multiple of the LMFC period, it is possible that from one power cycle to the next, the data arrival time at the receive buffer may straddle an LMFC boundary. To ensure deterministic latency in this case, a phase adjustment of the LMFC at either the transmitter or receiver must be performed. Typically, adjustments to accommodate the receive buffer are made to the LMFC of the receiver. In the AD9697, this adjustment can be made using the LMFC offset bits (Register 0x0578, Bits[4:0]). These bits delay the LMFC in frame clock increments, depending on the F parameter, which is the number of octets per lane per frame). For F = 1, every fourth setting (0, 4, 8, …, and so on) results in a one frame clock shift. For F = 2, every other setting (0, 2, 4, …, and so on) results in a 1-frame clock shift. For all other values of F, each setting results in a 1-frame clock shift. If there is no requirement for multichip synchronization while operating in Subclass 0 mode (Register 0x0590, Bit 5 = 0), the SYSREF± input can be left disconnected. In this mode, the relationship of the JESD204B clocks between the JESD204B transmitter and receiver are arbitrary but does not affect the ability of the receiver to capture and align the lanes within the link. SUBCLASS 1 OPERATION The JESD204B protocol organizes data samples into octets, frames, and multiframes as described in the Transport Layer section. The LMFC is synchronous with the beginnings of these multiframes. In Subclass 1 operation, the SYSREF± signal synchronizes the LMFCs for each device in a link or across multiple links (within the AD9697, SYSREF± also synchronizes the internal sample dividers). This synchronization is shown in Figure 101. The JESD204B receiver uses the multiframe SYSREF± DEVICE CLOCK SYSREF-ALIGNED GLOBAL LMFC SYSREF± TO LMFC DELAY ALL LMFCs DATA ILAS Figure 101. SYSREF± and LMFC Rev. 0 | Page 67 of 130 DATA 16253-100 POWER CYCLE VARIATION (MUST BE < tLMFC) AD9697 Data Sheet This function is described in the SYSREF± Setup/Hold Window Monitor section. Figure 102 shows that, in the case where the link latency is near an LMFC boundary, the local LMFC of the AD9697 can be delayed to in turn delay the data arrival time at the receiver. Figure 103 shows how the LMFC of the receiver is delayed to accommodate the receive buffer timing. Refer to the applicable JESD204B receiver user guide for details on making this adjustment. If the total latency in the system is not near an integer multiple of the LMFC period, or if the appropriate adjustments are made to the LMFC phase at the clock source, it is still possible to have variable latency from one power cycle to the next. In this case, check for the possibility that the setup and hold time requirements for the SYSREF± signal are not being met. Perform this check by reading the SYSREF± setup and hold monitor register (Register 0x0128). If reading Register 0x0128 indicates a timing problem, there are adjustments that can made in the AD9697. Changing the SYSREF± level used for alignment is possible using the SYSREF± transition select bit (Register 0x0120, Bit 4). Also, changing which edge of the clock is used to capture SYSREF± can be performed using the clock edge select bit (Register 0x0120, Bit 3). Both of these options are described in the SYREF± Control Features section. If neither of these measures help achieve an acceptable setup and hold time, adjusting the phase of SYSREF± and/or the device clock (CLK±) may be required. POWER CYCLE VARIATION LMFCTX DELAY TIME SYSREF-ALIGNED GLOBAL LMFC Tx LOCAL LMFC DATA ILAS DATA ILAS Tx LMFC MOVED (DELAYING THE ARRIVAL OF DATA RELATIVE TO THE GLOBAL LMFC) SO THE RECIEVE BUFFER RELEASE TIME IS ALWAYS REFERENCED TO THE SAME LMFC EDGE 16253-101 DATA (AT Tx INPUT) DATA (AT Rx INPUT) Figure 102. Adjusting the JESD204B Tx LMFC in the AD9697 LMFCRX DELAY TIME POWER CYCLE VARIATION SYSREF-ALIGNED GLOBAL LMFC DATA (AT Tx INPUT) DATA DATA (AT Rx INPUT) DATA Rx LMFC MOVED SO THE RECEIVE BUFFER RELEASE TIME IS ALWAYS REFERENCED TO THE SAME LMFC EDGE Figure 103. Adjusting the JESD204B Rx LMFC in the Logic Device Rev. 0 | Page 68 of 130 16253-102 Rx LOCAL LMFC Data Sheet AD9697 MULTICHIP SYNCHRONIZATION synchronization of multiple channels and/or devices. In timestamp mode, the clocks are not reset but instead, the coinciding sample is time stamped using the JESD204B control bits of that sample. To operate in timestamp mode, the following additional settings are necessary: The flowchart shown in Figure 105 describes the internal mechanism for multichip synchronization in the AD9697. There are two methods by which multichip synchronization can take place, as determined by the chip synchronization mode bit (Register 0x1FF , Bit 0). Each method involves different applications of the SYSREF± signal. • Continuous or N-shot SYSREF enabled (Register 0x0120, Bits[2:1] = 1 or 2). At least one control bit must be enabled (CS > 0, Register 0x058F, Bits[7:6] = 1, 2, or 3). Set the function for one of the control bits to SYSREF: • Register 0x0559, Bits[2:0] = 5 if using Control Bit 0. • Register 0x0559, Bits[6:4] = 5 if using Control Bit 1. • Register 0x055A, Bits[2:0] = 5 if using Control Bit 2. NORMAL MODE • The default sate of the chip synchronization mode bit is 0, which configures the AD9697 for normal chip synchronization. The JESD204B standard specifies the use of SYSREF± to provide deterministic latency within a single link. This same concept, when applied to a system with multiple converters and logic devices, can also provide multichip synchronization. In Figure 105, this is referred to as normal mode. Following the process outlined in the flowchart ensures that the AD9697 is configured appropriately. Consult the logic devices user intellectual property (IP) guide to ensure that the JESD204B receivers are configured appropriately. • Enable control bits MSB first. In other words, if only using one control bit (CS = 1), then Control Bit 2 must be enabled. If two control bits are used, then Control Bits[2:1] must be enabled. Figure 104 shows how the input sample coincident with SYSREF± is time stamped and ultimately output of the ADC. In this example, there are two control bits and Control Bit 1 is the bit indicating which sample was coincident with the SYSREF rising edge. If so desired, the SYSREF timestamp delay register (Register 0x0123) can be used to adjust the timing of which sample is time stamped. TIMESTAMP MODE For all AD9697 full bandwidth operating modes, the SYSREF± input can also be used to timestamp samples. This is another method by which multiple devices can achieve synchronization. This is especially effective when synchronizing multiple converters to one or more logic devices. The logic devices buffer the data streams, identify the time stamped samples, and align them. When the chip synchronization mode bit (Register 0x1FF, Bit 0) is set to 1, the timestamp method is used for Note that time stamping is not supported by any AD9697 operating modes that use decimation. 14-BIT SAMPLES OUT AIN1 N–1 N N+1 N+2 N+3 N – 1 00 N 01 N + 1 00 N + 2 00 N + 3 00 ADC 1 CONTROL BIT 0 USED TO TIME STAMP SAMPLE N ENCODE CLK SYSREF± N–1 N ADC 2 N+1 N+2 N – 1 00 N 01 N + 1 00 N + 2 00 N + 3 00 N+3 2 CONTROL BITS 16253-103 AIN2 Figure 104. AD9697 Timestamping—CS = 2 (Register 0x058F, Bits[7:6] = 2), Control Bit 1 is SYSREF± (Register 0x0559, Bits[6:4] = 5) Rev. 0 | Page 69 of 130 AD9697 Data Sheet INCREMENT SYSREF± IGNORE COUNTER START NO NO RESET SYSREF± IGNORE COUNTER NO SYSREF± ENABLED? (0x0120) YES SYSREF± ASSERTED? SYSREF± MODE (0x0120) YES SYSREF± IGNORE COUNTER EXPIRED? (0x0121) N SHOT MODE YES CONTINUOUS MODE CLEAR SYSREF± IGNORE COUNTER AND DISABLE SYSREF± (CLEAR BIT 2 IN 0x0120) UPDATE SETUP/HOLD DETECTOR STATUS (0x0128) ALIGN CLOCK DIVIDER PHASE TO SYSREF± YES INPUT CLOCK DIVIDER ALIGNMENT REQUIRED? NO SYNCHRONIZATION MODE? (0x01FF) TIMESTAMP MODE SYSREF± TIMESTAMP DELAY (0x0123) YES CLOCK DIVIDER AUTO ADJUST ENABLED? CLOCK DIVIDER >1? (0x010B) YES INCREMENT SYSREF± COUNTER (0x012A) NO NO SYSREF± ENABLED IN CONTROL BITS? (0x0559, 0x055A, 0x058F) SYSREF± INSERTED IN JESD204B CONTROL BITS YES NO RAMP TEST MODE ENABLED? (0x0550) NORMAL MODE SYSREF± RESETS RAMP TEST MODE GENERATOR YES BACK TO START NO YES ALIGN PHASE OF ALL INTERNAL CLOCKS (INCLUDING LMFC) TO SYSREF± SEND INVALID 8-BIT/ 10-BIT CHARACTERS (ALL 0s) SYNC~ ASSERTED NO SIGNAL MONITOR ALIGNMENT ENABLED? (0x026F) NO YES SEND K28.5 CHARACTERS NORMAL JESD204B INITIALIZATION NO YES ALIGN SIGNAL MONITOR COUNTERS DDC NCO ALIGNMENT ENABLED? (0x0300) YES ALIGN DDC NCO PHASE ACCUMULATOR NO Figure 105. SYSREF± Capture Scenarios and Multichip Synchronization Rev. 0 | Page 70 of 130 BACK TO START 16253-104 JESD204B LMFC ALIGNMENT REQUIRED? Data Sheet AD9697 The SYSREF± input signal is used as a high accuracy system reference for deterministic latency and multichip synchronization. The AD9697 accepts a single-shot or periodic input signal. The SYSREF± mode select bits (Register 0x0120, Bits[2:1]) select the input signal type and also arm the SYSREF± state machine when set. If in single- (or N) shot mode (Register 0x0120, Bits[2:1] = 2), the SYSREF± mode select bit self clears after the appropriate SYSREF± transition is detected. The pulse width must have a minimum width of two CLK± periods. If the clock divider (Register 0x010B, Bits[2:0]) is set to a value other than divide by 1, then multiply this minimum pulse width requirement by the divide ratio (for example, if set to divide by 8, the minimum pulse width is 16 CLK± cycles). When using a continuous SYSREF± signal (Register 0x0120, Bits[2:1] = 1), the period of the SYSREF± signal must be an integer multiple of the LMFC. Derive the LMFC using the following formula: mode register (Register 0x0120, Bits[2:1]) to 2’b10, which is labeled as N shot mode. The AD9697 is able to ignore N SYSREF± events, which is useful to handle periodic SYSREF± signals that require time to settle after startup. Ignoring SYSREF± until the clocks in the system have settled avoids an inaccurate SYSREF± trigger. Figure 110 shows an example of the SYSREF± ignore feature when ignoring three SYSREF± events. SETUP REQUIREMENT –70ps HOLD REQUIREMENT 120ps SYSREF± SAMPLE POINT CLK± SYSREF± 16253-105 SYSREF± INPUT KEEP OUT WINDOW Figure 106. SYSREF± Setup and Hold Time Requirements; SYSREF± Low to High Transition Using the Rising Edge Clock (Default) SETUP REQUIREMENT –70ps LMFC = ADC Clock/S × K SYREF± Control Features SYSREF± is used, along with the input clock (CLK±), as part of a source synchronous timing interface and requires setup and hold timing requirements of 117 ps and −96 ps, relative to the input clock (see Figure 106). The AD9697 has several features to meet these requirements. First, the SYSREF± sample event can be defined as either a synchronous low to high transition or synchronous high to low transition. Second, the AD9697 allows the SYSREF± signal to be sampled using either the rising edge or falling edge of the input clock. Figure 106, Figure 107, Figure 108, and Figure 109 show all four possible combinations. The third SYSREF± related feature available is the ability to ignore a programmable number (up to 16) of SYSREF± events. The SYSREF± ignore feature is enabled by setting the SYSREF± SYSREF± SAMPLE POINT 16253-106 CLK± SYSREF± Figure 107. SYSREF± Low to High Transition Using Falling Edge Clock Capture (Register 0x0120, Bit 4 = 1’b0 and Register 0x0120, Bit 3 = 1’b1) SETUP REQUIREMENT –70ps HOLD REQUIREMENT 120ps SYSREF± SAMPLE POINT CLK± 16253-107 The input clock divider, DDCs, signal monitor block, and JESD204B link are all synchronized using the SYSREF± input when in normal synchronization mode (Register 0x01FF, Bits[1:0] = 0). The SYSREF± input can also be used to time stamp an ADC sample to provide a mechanism for synchronizing multiple AD9697 devices in a system. For the highest level of timing accuracy, SYSREF± must meet the setup and hold requirements relative to the CLK± input. There are several features in the AD9697 to ensure these requirements are met (see the SYREF± Control Features section). HOLD REQUIREMENT 120ps SYSREF± Figure 108. SYSREF± High to Low Transition Using Rising Edge Clock Capture (Register 0x0120, Bit 4 = 1’b1 and Register 0x0120, Bit 3 = 1’b0) SETUP REQUIREMENT –70ps HOLD REQUIREMENT 120ps SYSREF± SAMPLE POINT CLK± SYSREF± Figure 109. SYSREF± High to Low Transition Using Falling Edge Clock Capture (Register 0x0120, Bit 4= 1’b1 and Register 0x0120, Bit 3 = 1’b1) Rev. 0 | Page 71 of 130 16253-108 where: S is the JESD204B parameter for number of samples per converter. K is JESD204B parameter for number of frames per multiframe. AD9697 Data Sheet SYSREF± SAMPLE PART 1 SYSREF± SAMPLE PART 2 SYSREF± SAMPLE PART 3 SYSREF± SAMPLE PART 4 SYSREF± SAMPLE PART 5 CLK± 16253-109 SYSREF± SAMPLE THE FOURTH SYSREF IGNORE FIRST THREE SYSREFs Figure 110. SYSREF± Ignore Example; SYSREF± Ignore Count Bits (Register 0x0121, Bits[3:0]) = 3 SYSREF± SKEW WINDOW = ±3 SYSREF± SKEW WINDOW = ±2 SYSREF± SKEW WINDOW = ±1 SYSREF± SKEW WINDOW = 0 16253-110 SAMPLE CLOCK SYSREF± Figure 111. SYSREF± Skew Window When in continuous SYSREF± mode (Register 0x0120, Bits[2:1] = 1), the AD9697 monitors the placement of the SYSREF± leading edge compared to the internal LMFC. If the SYSREF± edge is captured with a clock edge other than the one that is aligned with LMFC, the AD9697 initiates a resynchronization of the link. Because the input clock rates for the AD9697 can be up to 4 GHz, the AD9697 provides another SYSREF± related feature that makes it possible to accommodate periodic SYSREF± signals where cycle accurate capture is not feasible or not required. For these scenarios, the AD9697 has a programmable SYSREF± skew window that allows the internal dividers to remain undisturbed, unless SYSREF± occurs outside the skew window. The resolution of the SYSREF± skew window is set in sample clock cycles. If the SYSREF± negative skew window is 1 and the positive skew window is 1, then the total skew window is ±1 sample clock cycles, meaning that, as long as SYSREF± is captured within ±1 sample clock cycle of the clock that is aligned with LMFC, the link continues to operate normally. If the SYSREF± has jitter, which can cause a misalignment between SYSREF± and the LMFC, the system continues to run without a resynchronization, while still allowing the device to monitor for larger errors not caused by jitter. For the AD9697, the positive and negative skew window is controlled by the SYSREF± window negative bits (Register 0x0122, Bits[3:2]) and the SYSREF± window positive bits (Register 0x0122, Bits[1:0]). Figure 111 shows information on the location of the skew window settings relative to Phase 0 of the internal dividers. Negative skew is defined as occurring before the internal dividers reach Phase 0 and positive skew is defined after the internal dividers reach Phase 0. Rev. 0 | Page 72 of 130 Data Sheet AD9697 SYSREF± SETUP/HOLD WINDOW MONITOR To ensure a valid SYSREF± signal capture, the AD9697 has a SYSREF± setup/hold window monitor. This feature allows the system designer to determine the location of the SYSREF± signals relative to the CLK± signals by reading back the amount of setup/hold margin on the interface through the memory map. Figure 112 and Figure 113 show the setup and hold status values for different phases of SYSREF±. The setup detector returns the status of the SYSREF± signal before the CLK± edge, and the hold detector returns the status of the SYSREF signal after the CLK± edge. Register 0x0128 stores the status of SYSREF± and lets the user know if the SYSREF± signal is captured by the ADC. Table 34 describes the contents of Register 0x0128 and how to interpret them. 0xF 0xE 0xD 0xC 0xB 0xA 0x9 REG 0x0128[3:0] 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 CLK± INPUT VALID SYSREF± INPUT FLIP-FLOP HOLD (MIN) FLIP-FLOP HOLD (MIN) Figure 112. SYSREF± Setup Detector Rev. 0 | Page 73 of 130 16253-111 FLIP-FLOP SETUP (MIN) AD9697 Data Sheet 0xF 0xE 0xD 0xC 0xB 0xA 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 REG 0x0128[7:4] 0x0 CLK± INPUT SYSREF± INPUT FLIP-FLOP SETUP (MIN) FLIP-FLOP HOLD (MIN) FLIP-FLOP HOLD (MIN) 16253-112 VALID Figure 113. SYSREF± Hold Detector Table 34. SYSREF± Setup/Hold Monitor, Register 0x0128 Register 0x0128, Bits[7:4] Hold Status 0x0 Register 0x0128, Bits[3:0] Setup Status 0x0 to 0x7 0x0 to 0x8 0x8 0x8 0x9 to 0xF 0x8 0x9 to 0xF 0x0 0x0 0x0 0x0 Rev. 0 | Page 74 of 130 Description Possible setup error. The smaller this number, the smaller the setup margin. No setup or hold error (best hold margin). No setup or hold error (best setup and hold margin). No setup or hold error (best setup margin). Possible hold error. The larger this number, the smaller the hold margin. Possible setup or hold error. Data Sheet AD9697 LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATIONS Total latency in the AD9697 is dependent on the chip application mode and the JESD204B configuration. For any given combination of these parameters, the latency is deterministic, however, the value of this deterministic latency must be calculated as described in the Example Latency Calculations section. Example Configuration 1 is as follows: Table 35 shows the combined latency through the ADC and DSP for the different chip application modes supported by the AD9697. Table 36 shows the latency through the JESD204B block for each application mode based on the M/L ratio. For both tables, latency is typical and is in units of the encode clock. The latency through the JESD204B block does not depend on the output data type (real or complex). Therefore, data type is not included in Table 35 and Table 36. To determine the total latency, select the appropriate ADC + DSP latency from Table 35 and add it to the appropriate JESD204B latency from Table 36. Example calculations are provided in the following section. • • • • • ADC application mode = full bandwidth Real outputs L = 4, M = 1, F = 1, S = 2 (JESD204B mode) M/L = 0.25 Latency = 31 + 44 = 75 encode clocks Example Configuration 2 is as follows: • • • • • ADC application mode = DCM4 Complex outputs L = 2, M = 2, F = 2, S = 1 (JESD204B mode) M/L = 1 Latency = 162 + 50 = 212 encode clocks LMFC REFERENCED LATENCY Some FPGA vendors may require the end user to know LMFC referenced latency to make appropriate deterministic latency adjustments. If they are required, the latency values in Table 35 and Table 36 can be used for the analog input to LMFC and LMFC to data output latency values, respectively. Rev. 0 | Page 75 of 130 AD9697 Data Sheet Table 35. Latency Through the ADC + DSP Blocks (Number of Sample Clocks) 1 Chip Application Mode Full Bandwidth DCM1 (Real) DCM2 (Complex) DCM3 (Complex) DCM2 (Real) DCM4 (Complex) DCM3 (Real) DCM6 (Complex) DCM4 (Real) DCM8 (Complex) DCM5 (Real) DCM10 (Complex) DCM6 (Real) DCM12 (Complex) DCM15 (Real) DCM8 (Real) DCM16 (Complex) DCM10 (Real) DCM20 (Complex) DCM12 (Real) DCM24 (Complex) DCM30 (Complex) DCM20 (Real) DCM40 (Complex) DCM24 (Real) DCM48 (Complex) 1 Enabled Filters Not applicable HB1 HB1 TB1 HB2 + HB1 HB2 + HB1 TB2 + HB1 TB2 + HB1 HB3 +HB2 + HB1 HB3 +HB2 + HB1 FB2 + HB1 FB2 + HB1 TB2 + HB2 + HB1 TB2 + HB2 + HB1 FB2 + TB1 HB4 + HB3 + HB2 + HB1 HB4 + HB3 + HB2 + HB1 FB2 + HB2 + HB1 FB2 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 TB2 + HB3 + HB2 + HB1 HB2 + FB2 + TB1 FB2 + HB3 + HB2 + HB1 FB2 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 TB2 + HB4 + HB3 + HB2 + HB1 ADC + DSP Latency 31 90 90 102 162 162 212 212 292 292 380 380 424 424 500 552 552 694 694 814 814 836 1420 1420 1594 1594 DCMx indicates the decimation ratio. Table 36. Latency Through JESD204B Block (Number of Sample Clocks) 1 Chip Application Mode Full Bandwidth DCM1 DCM2 DCM3 DCM4 DCM5 DCM6 DCM8 DCM10 DCM12 DCM15 DCM16 DCM20 DCM24 DCM30 DCM40 DCM48 0.125 82 82 160 237 315 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.25 44 44 84 124 164 203 3 243 323 N/A N/A N/A N/A N/A N/A N/A N/A N/A 0.5 25 25 46 67 88 1093 130 172 213 255 318 4 3394 N/A N/A N/A N/A N/A M/L Ratio 2 1 14 14 27 39 50 623 73 96 119 142 1764 1884 233 279 3484 N/A N/A N/A means not applicable and indicates that the application mode is not supported at the M/L ratio listed. M/L ratio is the number of converters divided by the number of lanes for the configuration. The application mode at the M/L ratio listed is only supported in real output mode. 4 The application mode at the M/L ratio listed is only supported in complex output mode. 1 2 3 Rev. 0 | Page 76 of 130 2 7 7 14 21 27 433 39 50 62 73 904 964 119 142 1764 2334 2794 4 9 N/A 7 11 14 N/A 21 27 33 39 474 504 62 73 904 1194 1424 8 3 N/A N/A N/A 9 N/A 14 18 22 27 334 354 43 51 624 824 974 Data Sheet AD9697 TEST MODES without an analog signal (if present, the analog signal is ignored); however, they do require an encode clock. ADC TEST MODES The AD9697 has various test options that aid in the system level implementation. The AD9697 has ADC test modes that are available in Register 0x0550. These test modes are described in Table 37. When an output test mode is enabled, the analog section of the ADC is disconnected from the digital back end blocks, and the test pattern is run through the output formatting block. Some of the test patterns are subject to output formatting and some are not. The pseudorandom number (PN) generators from the PN sequence tests can be reset by setting Bit 4 or Bit 5 of Register 0x0550. These tests can be performed with or JESD204B INTERFACE TEST PATTERN (REG 0x573, REG 0x551 TO REG 0x558) JESD204B LONG TRANSPORT TEST PATTERN REG 0x571[5] JESD204B DATA LINK LAYER TEST PATTERNS REG 0x574[2:0] SERIALIZER MSB A13 A12 A11 A10 A9 A8 A7 LSB A6 A5 A4 A3 A2 A1 A0 C2 T 8-BIT/10-BIT ENCODER MSB S7 S6 S5 S4 S3 S2 S1 LSB S0 S7 S6 S5 S4 S3 S2 S1 S0 a b c d e f g h i j a b SERDOUT0± SERDOUT1± i j a b SYMBOL0 i j SYMBOL1 a b c d e f g h i j 16253-214 TAIL BITS 0x571[6] SCRAMBLER 1 + x14 + x15 (OPTIONAL) OCTET 1 JESD204B SAMPLE CONSTRUCTION MSB A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 LSB A0 OCTET 1 OCTET 0 FRAME CONSTRUCTION OCTET 0 ADC TEST PATTERNS (RE0x550, REG 0x551 TO REG 0x558) ADC If application mode is set to select a DDC mode of operation, the test modes must be enabled for each DDC enabled. The test patterns can be enabled via Bit 0 of Register 0x0327, Register 0x0347, Register 0x0367, and Register 0x0387 depending on which DDC(s) are selected. The (I) data uses the test patterns selected, and the (Q) data does not output test patterns. For more information, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. C2 CONTROL BITS C1 C0 Figure 114. ADC Output Datapath Showing Data Framing Table 37. ADC Test Modes1 Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 Pattern Name Off (default) Midscale short Positive full-scale short Negative full-scale short Checkerboard PN sequence long PN sequence short One-/zero-word toggle User input Expression N/A 0000 0000 0000 01 1111 1111 1111 10 0000 0000 0000 10 1010 1010 1010 x23 + x18 + 1 x9 + x5 + 1 11 1111 1111 1111 Register 0x0551 to Register 0x0558 1111 Ramp output (x) % 214 1 Default/ Seed Value N/A N/A N/A N/A N/A 0x3AFF 0x0092 N/A N/A N/A N/A means not applicable. Rev. 0 | Page 77 of 130 Sample (N, N + 1, N + 2, …) N/A N/A N/A N/A 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555 0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6 0x125B, 0x3C9A, 0x2660, 0x0C65, 0x0697 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000 User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], User Pattern 1[15:2] … for repeat mode. User Pattern 1[15:2], User Pattern 2[15:2], User Pattern 3[15:2], User Pattern 4[15:2], 0x0000 … for single mode. (x) % 214, (x +1) % 214, (x +2) % 214, (x +3) % 214 AD9697 Data Sheet JESD204B BLOCK TEST MODES In addition to the ADC pipeline test modes, the AD9697 also has flexible test modes in the JESD204B block. These test modes are listed in Register 0x0573 and Register 0x0574. These test patterns can be injected at various points along the output datapath. These test injection points are shown in Figure 114. Table 38 describes the various test modes available in the JESD204B block. For the AD9697, a transition from test modes (Register 0x0573 ≠ 0x00) to normal mode (Register 0x0573 = 0x00) requires an SPI soft reset. This is done by writing 0x81 to Register 0x0000 (self cleared). Transport Layer Sample Test Mode The transport layer samples are implemented in the AD9697 as defined by Section 5.1.6.3 in the JEDEC JESD204B specification. These tests are shown in Register 0x0571, Bit 5. The test pattern is equivalent to the raw samples from the ADC. Interface Test Modes The interface test modes are described in Register 0x0573, Bits[3:0]. These test modes are also explained in Table 38. The interface tests can be injected at various points along the data. See Figure 114 for more information on the test injection points. Register 0x0573, Bits[5:4] show where these tests are injected. Table 39, Table 40, and Table 41 show examples of some of the test modes when injected at the JESD sample input, PHY 10-bit input, and scrambler 8-bit input. UPx in the tables represent the user pattern control bits from the customer register map. Table 38. JESD204B Interface Test Modes Output Test Mode Bit Sequence 0000 0001 0010 0011 0100 0101 0110 0111 1000 1110 1111 Pattern Name Off (default) Alternating checker board 1/0 word toggle 31-bit PN sequence 23-bit PN sequence 15-bit PN sequence 9-bit PN sequence 7-bit PN sequence Ramp output Continuous/repeat user test Single user test Expression Not applicable 0x5555, 0xAAAA, 0x5555, … 0x0000, 0xFFFF, 0x0000, … x31 + x28 + 1 x23 + x18 + 1 x15 + x14 + 1 x9 + x 5 + 1 x7 + x 6 + 1 (x) % 216 Register 0x0551 to Register 0x0558 Register 0x0551 to Register 0x0558 Default Not applicable Not applicable Not applicable 0x0003AFFF 0x003AFF 0x03AF 0x092 0x07 Ramp size depends on test injection point User Pattern 1 to User Pattern 4, then repeat User Pattern 1 to User Pattern 4, then zeros Table 39. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00) Frame No. 0 0 0 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 Converter No. 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Sample No. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Alternating Checkerboard 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 0xAAAA 0xAAAA 0xAAAA 0xAAAA 0x5555 0x5555 0x5555 0x5555 1/0 Word Toggle 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x0000 0x0000 0x0000 0x0000 Ramp (x) % 216 (x) % 216 (x) % 216 (x) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +1) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +2) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 (x +3) % 216 (x +4) % 216 (x +4) % 216 (x +4) % 216 (x +4) % 216 Rev. 0 | Page 78 of 130 PN9 0x496F 0x496F 0x496F 0x496F 0xC9A9 0xC9A9 0xC9A9 0xC9A9 0x980C 0x980C 0x980C 0x980C 0x651A 0x651A 0x651A 0x651A 0x5FD1 0x5FD1 0x5FD1 0x5FD1 PN23 0xFF5C 0xFF5C 0xFF5C 0xFF5C 0x0029 0x0029 0x0029 0x0029 0xB80A 0xB80A 0xB80A 0xB80A 0x3D72 0x3D72 0x3D72 0x3D72 0x9B26 0x9B26 0x9B26 0x9B26 User Repeat UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] User Single UP1[15:0] UP1[15:0] UP1[15:0] UP1[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP2[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP3[15:0] UP4[15:0] UP4[15:0] UP4[15:0] UP4[15:0] 0x0000 0x0000 0x0000 0x0000 Data Sheet AD9697 Table 40. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 'b01) 10-Bit Symbol Number 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 0x155 0x2AA 1/0 Word Toggle 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF 0x000 0x3FF Ramp (x) % 210 (x + 1) % 210 (x + 2) % 210 (x + 3) % 210 (x + 4) % 210 (x + 5) % 210 (x + 6) % 210 (x + 7) % 210 (x + 8) % 210 (x + 9) % 210 (x + 10) % 210 (x + 11) % 210 PN9 0x125 0x2FC 0x26A 0x198 0x031 0x251 0x297 0x3D1 0x18E 0x2CB 0x0F1 0x3DD PN23 0x3FD 0x1C0 0x00A 0x1B8 0x028 0x3D7 0x0A6 0x326 0x10F 0x3FD 0x31E 0x008 User Repeat UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] User Single UP1[15:6] UP2[15:6] UP3[15:6] UP4[15:6] 0x000 0x000 0x000 0x000 0x000 0x000 0x000 0x000 Table 41. Scrambler 8-Bit Input (Register 0x0573, Bits[5:4] = 'b10) 8-Bit Octet Number 0 1 2 3 4 5 6 7 8 9 10 11 Alternating Checkerboard 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 0x55 0xAA 1/0 Word Toggle 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF Ramp (x) % 28 (x + 1) % 28 (x + 2) % 28 (x + 3) % 28 (x + 4) % 28 (x + 5) % 28 (x + 6) % 28 (x + 7) % 28 (x + 8) % 28 (x + 9) % 28 (x + 10) % 28 (x + 11) % 28 Data Link Layer Test Modes The data link layer test modes are implemented in the AD9697 as defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification. These tests are shown in Register 0x0574, PN9 0x49 0x6F 0xC9 0xA9 0x98 0x0C 0x65 0x1A 0x5F 0xD1 0x63 0xAC PN23 0xFF 0x5C 0x00 0x29 0xB8 0x0A 0x3D 0x72 0x9B 0x26 0x43 0xFF User Repeat UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] User Single UP1[15:9] UP2[15:9] UP3[15:9] UP4[15:9] 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Bits[2:0]. Test patterns inserted at this point are useful for verifying the functionality of the data link layer. When the data link layer test modes are enabled, disable SYNCINB± by writing 0xC0 to Register 0x0572. Rev. 0 | Page 79 of 130 AD9697 Data Sheet SERIAL PORT INTERFACE (SPI) The AD9697 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields. These fields are documented in the Memory Map section. For detailed operational information, see the Serial Control Interface Standard (Rev. 1.0). CONFIGURATION USING THE SPI Three pins define the SPI of the AD9697 ADC: the SCLK pin, the SDIO pin, and the CSB pin (see Table 42). The SCLK (serial clock) pin is used to synchronize the read and write data presented to and from the ADC. The SDIO (serial data input/ output) pin is a dual-purpose pin that allows data to be sent and read from the internal ADC memory map registers. The CSB (chip select bar) pin is an active low control that enables or disables the read and write cycles. Table 42. Serial Port Interface Pins Mnemonic SCLK SDIO CSB Function Serial clock. The serial shift clock input that is used to synchronize serial interface, reads, and writes. Serial data input/output. A dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. Chip select bar. An active low control that gates the read and write cycles. The falling edge of CSB, in conjunction with the rising edge of SCLK, determines the start of the framing. An example of the serial timing and its definitions can be found in Figure 4 and Table 5. Other modes involving the CSB pin are available. The CSB pin can be held low indefinitely, which permanently enables the device; this is called streaming. The CSB can stall high between bytes to allow additional external timing. When CSB is tied high, SPI functions are placed in a high impedance mode. This mode turns on any SPI pin secondary functions. All data is composed of 8-bit words. The first bit of each individual byte of serial data indicates whether a read or write command is issued, which allows the SDIO pin to change direction from an input to an output. In addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change direction from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB first mode or in LSB first mode. MSB first is the default on power-up and can be changed via the SPI port configuration register. For more information about this and other features, see the Serial Control Interface Standard (Rev. 1.0). HARDWARE INTERFACE The pins described in Table 42 comprise the physical interface between the user programming device and the serial port of the AD9697. The SCLK pin and the CSB pin function as inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. The SPI interface is flexible enough to be controlled by either FPGAs or microcontrollers. One method for SPI configuration is described in detail in the AN-812 Application Note, Microcontroller-Based Serial Port Interface (SPI) Boot Circuit. Do not activate the SPI port during periods when the full dynamic performance of the converter is required. Because the SCLK signal, the CSB signal, and the SDIO signal are typically asynchronous to the ADC clock, noise from these signals can degrade converter performance. If the on-board SPI bus is used for other devices, it may be necessary to provide buffers between this bus and the AD9697 to prevent these signals from transitioning at the converter inputs during critical sampling periods. SPI ACCESSIBLE FEATURES Table 43 provides a brief description of the general features that are accessible via the SPI. These features are described in detail in the Serial Control Interface Standard (Rev. 1.0). The AD9697 device specific features are described in the Memory Map section. Table 43. Features Accessible Using the SPI Feature Name Mode Clock DDC Test Input/Output Output Mode SERDES Output Setup Description Allows the user to set either power-down mode or standby mode. Allows the user to access the clock divider via the SPI. Allows the user to set up decimation filters for different applications. Allows the user to set test modes to have known data on output bits. Allows the user to set up outputs. Allows the user to vary SERDES settings such as swing and emphasis. Rev. 0 | Page 80 of 130 Data Sheet AD9697 MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Each row in the memory map register table has eight bit locations. The memory map is divided into the following sections: All address and bit locations that are not included in Table 44 are not currently supported for this device. Write unused bits of a valid address location with 0s unless the default value is set otherwise. Writing to these locations is required only when part of an address location is unassigned (for example, Address 0x0561). If the entire address location is open (for example, Address 0x0013), do not write to this address location. • • • • • • • Analog Devices SPI registers (Register 0x0000 to Register 0x000F) Clock/SYSREF/chip power-down pin control registers (Register 0x003F to Register 0x0201) Fast detect and signal monitor control registers (Register 0x0245 to Register 0x027A) DDC function registers (Register 0x0300 to Register 0x03CD) Digital outputs and test modes registers (Register 0x0550 to Register 0x05CB) Programmable filter control and coefficients registers (Register 0x0DF8 to Register 0x0F7F) VREF/analog input control registers (Register 0x18A6 to Register 0x1A4D) Table 44 (see the Memory Map section) documents the default hexadecimal value for each hexadecimal address shown. The column with the heading Bit 7 (MSB) is the start of the default hexadecimal value given. For example, Address 0x0561, the output sample mode register, has a hexadecimal default value of 0x01, which means that Bit 0 = 1, and the remaining bits are 0s. This setting is the default output format value, which is twos complement. For more information on this function and others, see Table 44. Default Values After the AD9697 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table, Table 44. Logic Levels An explanation of logic level terminology follows: • • • “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” “Clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” X denotes a don’t care bit. SPI Soft Reset After issuing a soft reset by programming 0x81 to Register 0x0000, the AD9697 requires 5 ms to recover. When programming the AD9697 for application setup, ensure that an adequate delay is programmed into the firmware after asserting the soft reset and before starting the device setup. Rev. 0 | Page 81 of 130 AD9697 Data Sheet MEMORY MAP REGISTERS All address locations that are not included in Table 44 are not currently supported for this device and must not be written. Table 44. Memory Map Registers Address Name Analog Devices SPI Registers 0x0000 SPI Configuration A Bits Bit Name Settings 7 Soft reset mirror (self clearing) 0 1 6 LSB first mirror 1 0 5 Address ascension mirror 0 1 [4:3] 2 Reserved Address ascension 0 1 1 LSB first 1 0 0 Soft reset (self clearing) 0 1 0x0001 SPI Configuration B [7:2] 1 0 Reserved Datapath soft reset (self clearing) Reserved Rev. 0 | Page 82 of 130 0 1 Description Reset Access Whenever a soft reset is issued, the user must wait 5 ms before writing to any other register; this provides sufficient time for the boot loader to complete. Do nothing. Reset the SPI and registers (self clearing). Least significant bit shifted first for all SPI operations. Most significant bit shifted first for all SPI operations. Multibyte SPI operations cause addresses to auto decrement. Multibyte SPI operations cause addresses to auto increment. Reserved. Multibyte SPI operations cause addresses to auto decrement. Multibyte SPI operations cause addresses to auto increment. Least significant bit shifted first for all SPI operations. Most significant bit shifted first for all SPI operations. Whenever a soft reset is issued, the user must wait 5 ms before writing to any other register; this provides sufficient time for the boot loader to complete. Do nothing. Reset the SPI and registers (self clearing). Reserved. Normal operation. 0x0 R/WC 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/WC 0x0 0x0 R R/WC 0x0 R Datapath soft reset (self clearing). Reserved. Data Sheet Address 0x0002 Name Chip configuration (local) AD9697 Bits [7:2] [1:0] Bit Name Reserved Power mode Settings 00 10 11 0x0003 Chip type [7:0] Chip type 0x3 0x0004 Chip ID LSB [7:0] Chip ID LSB [7:0] 0xDE 0x0005 0x0006 Chip ID MSB Chip grade [7:0] [7:4] Chip ID MSB [15:8] Chip speed grade 0x000A Scratch pad [3:0] [7:0] Reserved Scratch pad 0x000B SPI revision [7:0] SPI revision 0x00 0x01 00000001 0x000C 0x000D 0x000F Vendor ID LSB Vendor ID MSB Transfer [7:0] [7:0] [7:1] 0 Reserved Chip transfer 0 1 Rev. 0 | Page 83 of 130 Description Reserved. Power modes. Normal mode (power-up). Standby mode. Digital datapath clocks disabled; JESD204B interface enabled. Power-down mode. Digital datapath clocks disabled; digital datapath held in reset; JESD204B interface disabled. Chip type. High speed ADC. Chip ID. AD9697. Chip ID. Chip speed grade. 1300 MSPS. Reserved. Chip scratch pad register. This register provides a consistent memory location for software debug. SPI revision register. Revision 1.0. Revision 1.0. Vendor ID [7:0]. Vendor ID [15:8]. Reserved. Self clearing chip transfer bit. This bit is used to update the DDC phase increment and phase offset registers when the DDC phase update mode bit (Register 0x0300, Bit 7) = 1. This setting makes it possible to synchronously update the DDC mixer frequencies. It is also used to update the coefficients for the programmable filter (PFILT). Do nothing. This bit it is only cleared after the transfer completes. Self clearing bit used to synchronize the transfer of data from master to slave registers. Reset 0x0 0x0 Access R R/W 0x3 R R 0x0 0x0 R R DNC 0x0 R R/W 0x1 R 0x56 0x04 0x0 0x0 R R R R/W AD9697 Data Sheet Address Name Bits Bit Name Clock/SYSREF±/Chip Power-Down Pin Control Registers 0x003F Chip power7 Local chip powerdown pin down pin disable (local) Settings 0 1 0x0040 Chip Pin Control 1 [6:0] [7:6] Reserved Global chip powerdown pin functionality 00 01 10 [5:3] GPIO2 pin functionality 110 111 [2:0] Chip FD/GPIO1 pin functionality 000 001 110 111 Rev. 0 | Page 84 of 130 Description Reset Access Function is determined by Register 0x0040, Bits[7:6]. 0x0 R/W 0x0 0x0 R R/W 0x7 R/W 0x7 R/W Power-down pin (PDWN/STBY) enabled (default). Power-down pin (PDWN/STBY) disabled/ignored. Reserved. External power-down pin functionality. Assertion of the external power-down pin (PDWN/STBY) has higher priority than the power mode control bits (Register 0x0002, Bits[1:0]). The PDWN/STBY pin is only used when Register 0x0040, Bits[7:6] = 00 or 01. Power-down pin (default). Assertion of the external power-down pin (PDWN/STBY) causes the chip to enter full powerdown mode. Standby-pin. Assertion of the external power-down pin (PDWN/STBY) causes the chip to enter standby mode. Pin disabled. Power-down pin (PDWN/STBY) is ignored. GPIO2 pin functionality. Pin functionality determined by Register 0x0041, Bits[7:4]. Disabled. Configured as input with weak pulldown (default). FD/GPIO1 pin functionality. Fast detect output. JESD204B LMFC output. Pin functionality determined by Register 0x0041, Bits[3:0]. Disabled. Configured as input with weak pulldown. (default) Data Sheet Address 0x0041 Name Chip Pin Control 2 AD9697 Bits [7:4] Bit Name GPIO2 pin secondary functionality Settings 0000 [3:0] Chip FD/GPIO1 pin secondary functionality 0000 0001 1000 1001 0x0042 Chip Pin Control 3 [7:4] Reserved 1111 [3:0] Chip GPIO1 pin functionality 0000 1000 1001 1111 0x0108 0x0109 Clock divider control [7:3] [2:0] Reserved Input clock divider (CLK± pins) Clock divider phase (local) [7:4] [3:0] Reserved Clock divider phase offset 00 01 11 0000 0001 0010 1110 1111 Rev. 0 | Page 85 of 130 Description GPIO2 pin secondary functionality. Only used when Register 0x0040, Bits[5:3] = 110. Chip GPIO2 input (NCO channel selection). FD/GPIO1 pin secondary functionality. Only used when Register 0x0040, Bits[2:0] = 110. Chip GPIO1 input (NCO channel selection). Chip transfer input. Master next trigger output (MNTO). Slave next trigger input (SNTI). Reserved Reset 0x0 Access R/W 0x0 R/W 0xF R GPIO1 pin functionality. Chip GPIO1 input (NCO channel selection). Master next trigger output (MNTO). Slave next trigger input (SNTI). Disabled (configured as an input with a weak pull down). Reserved. Divide by 1. Divide by 2. Divide by 4. Reserved. 0 input clock cycles delayed. 1/2 input clock cycles delayed (invert clock). 1 input clock cycles delayed. … 7 input clock cycles delayed. 7 1/2 input clock cycles delayed. 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W AD9697 Address 0x010A Data Sheet Name Clock divider and SYSREF± control Bits 7 Bit Name Clock divider autophase adjust enable Settings 0 1 [6:4] [3:2] Reserved Clock divider negative skew window 0 1 10 11 Rev. 0 | Page 86 of 130 Description Clock divider autophase adjust enable. When enabled, Register 0x0129, Bits[3:0] contain the phase of the divider when SYSREF± occurred. The actual divider phase offset = Register 0x0129, Bits[3:0] + Register 0x0109, Bits[3:0]. Clock divider phase is not changed by SYSREF± (disabled). Clock divider phase is automatically adjusted by SYSREF± (enabled). Reserved. Clock divider negative skew window (measured in 1/2 input device clocks). Number of 1/2 clock cycles before the input device clock by which captured SYSREF± transitions are ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]; this allows some uncertainty in the sampling of SYSREF± without disturbing the input clock divider. Also, SYSREF± must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. No negative skew. SYSREF± must be captured accurately. 1/2 device clock of negative skew. 1 device clocks of negative skew. 1 1/2 device clocks of negative skew. Reset 0x0 Access R/W 0x0 0x0 R R/W Data Sheet Address Name AD9697 Bits [1:0] Bit Name Clock divider positive skew window Settings 0 1 10 11 0x010B Clock divider SYSREF status [7:4] [3:0] Reserved Clock divider SYSREF± offset 0x0110 Clock delay control [7:3] [2:0] Reserved Clock delay mode select 000 010 011 100 Rev. 0 | Page 87 of 130 Description Clock divider positive skew window (measured in 1/2 input device clocks). Number of clock cycles after the input device clock by which captured SYSREF± transitions are ignored. Only used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]; this allows some uncertainty in the sampling of SYSREF± without disturbing the input clock divider. Also, SYSREF± must be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this control field. No positive skew. SYSREF± must be captured accurately. 1/2 device clock of positive skew. 1 device clocks of positive skew. 1 1/2 device clocks of positive skew. Reserved Clock divider phase status (measured in 1/2 clock cycles). Internal clock divider phase of the captured SYSREF± signal applied to the phase offset. Only used when Register 0x010A, Bit 7 = 1. When Register 0x010A, Bit 7 = 1, Register 0x010A, Bits[3:2] = 0, and Register 0x010A, Bits[1:0] = 0, clock divider SYSREF± offset = Register 0x0129, Bits[3:0]. Reserved. Clock delay mode select. Used in conjunction with Register 0x0111 and Register 0x0112. No clock delay. Fine delay. Only Delay Step 0 to Delay Step 16 are valid. Fine delay (lowest jitter). Only Delay Step 0 to Delay Step 16 are valid. Fine delay. All 192 delay steps valid. Reset 0x0 Access R/W 0x0 0x0 R R 0x0 0x0 R R/W AD9697 Data Sheet Address Name Bits Bit Name Settings 110 0x0111 Clock super fine delay (local) [7:0] Clock super fine delay adjust 0x0112 Clock fine delay (local) [7:0] Set clock fine delay 0x0113 Digital clock super fine delay [7:0] Digital clock super fine delay adjust Rev. 0 | Page 88 of 130 Description Fine delay enabled (all 192 delay steps valid). Super fine delay enabled (all 128 delay steps valid). Clock super fine delay adjust. This is an unsigned control to adjust the super fine sample clock delay in 0.25 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 010 or 110. 0x00 = 0 delay steps. … 0x08 = 8 delay steps. … 0x80 = 128 delay steps. Clock fine delay adjust. This is an unsigned control to adjust the fine sample clock skew in 1.725 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6. 0x00 = 0 delay steps. … 0x08 = 8 delay steps. … 0xC0 = 192 delay steps. Minimum = 0. Maximum = 192. Increment = 1. Unit = delay steps. Digital clock super fine delay adjust. This is an unsigned control to adjust the super fine sample clock delay in 0.25ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 010 or 110. 0x00 = 0 delay steps. … 0x08 = 8 delay steps. … 0x80 = 128 delay steps. Reset Access 0x0 R/W 0xC0 R/W 0x0 R/W Data Sheet AD9697 Address 0x0114 Name Digital clock fine delay Bits [7:0] Bit Name Set digital clock fine delay 0x011A Clock detection control [7:5] [4:3] Reserved Clock detection threshold Settings 01 11 0x011B Clock status [2:0] [7:1] 0 Reserved Reserved Input clock detect 0 1 0x011C Clock Duty Cycle Stabilizer 1 (DCS1) control (local) [7:2] 1 Reserved DCS1 enable 0 1 0 DCS1 power-up 0 1 0x011E Clock Duty Cycle Stabilizer 2 (DCS2) control [7:2] 1 Reserved DCS2 enable 0 1 0 DCS2 power-up 0 1 0x0120 SYSREF± Control 1 7 6 Reserved SYSREF± flag reset 5 Reserved Rev. 0 | Page 89 of 130 0 1 Description Digital clock fine delay adjust. This is an unsigned control to adjust the fine sample clock skew in 1.725 ps steps. These bits are only used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4 or 0x6. 0x00 = 0 delay steps. … 0x08 = 8 delay steps. … 0xC0 = 192 delay steps. Minimum = 0. Maximum = 192. Increment = 1. Unit = delay steps. Reserved. Clock detection threshold. Threshold 1 for sample rate ≥ 300 MSPS. Threshold 2 for sample rate