AD9708ARUZRL7

a FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 8-Bit Resolution Linearity: 1/4 LSB DNL Linearity: 1/4 LSB INL Differential Current Outputs SINAD @ 5 MHz Output: 50 dB Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V Power-Down Mode: 20 mW @ 5 V On-Chip 1.20 V Reference Single +5 V or +3 V Supply Operation Packages: 28-Lead SOIC and 28-Lead TSSOP Edge-Triggered Latches Fast Settling: 35 ns Full-Scale Settling to 0.1% APPLICATIONS Communications Signal Reconstruction Instrumentation PRODUCT DESCRIPTION The AD9708 is the 8-bit resolution member of the TxDAC series of high performance, low power CMOS digital-to-analog converters (DACs). The TxDAC family, which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, was specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. The AD9708 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The AD9708’s flexible single-supply operating range of +2.7 V to +5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further reduced to 45 mW, without a significant degradation in performance, by lowering the full-scale current output. In addition, a power-down mode reduces the standby power dissipation to approximately 20 mW. The AD9708 is manufactured on an advanced CMOS process. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solution. Flexible supply options support +3 V and +5 V CMOS logic families. The AD9708 is a current-output DAC with a nominal full-scale output current of 20 mA and > 100 kΩ output impedance. TxDAC is a registered trademark of Analog Devices, Inc. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. 8-Bit, 100 MSPS+ TxDAC® D/A Converter AD9708 FUNCTIONAL BLOCK DIAGRAM +5V 0.1mF REFLO COMP1 AVDD +1.20V REF 0.1mF 50pF REF IO CURRENT SOURCE ARRAY FS ADJ ACOM AD9708 COMP2 0.1mF RSET +5V CLOCK IOUTA DVDD DCOM SEGMENTED SWITCHES CLOCK IOUTB LATCHES SLEEP DIGITAL DATA INPUTS (DB7–DB0) Differential current outputs are provided to support singleended or differential applications. The current outputs may be directly tied to an output resistor to provide two complementary, single-ended voltage outputs. The output voltage compliance range is 1.25 V. The AD9708 contains a 1.2 V on-chip reference and reference control amplifier, which allows the full-scale output current to be simply set by a single resistor. The AD9708 can be driven by a variety of external reference voltages. The AD9708’s full-scale current can be adjusted over a 2 mA to 20 mA range without any degradation in dynamic performance. Thus, the AD9708 may operate at reduced power levels or be adjusted over a 20 dB range to provide additional gain ranging capabilities. The AD9708 is available in 28-lead SOIC and 28-lead TSSOP packages. It is specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS 1. The AD9708 is a member of the TxDAC product family, which provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and cost. 2. Manufactured on a CMOS process, the AD9708 uses a proprietary switching technique that enhances dynamic performance well beyond 8- and 10-bit video DACs. 3. On-chip, edge-triggered input CMOS latches readily interface to +3 V and +5 V CMOS logic families. The AD9708 can support update rates up to 125 MSPS. 4. A flexible single-supply operating range of +2.7 V to +5.5 V and a wide full-scale current adjustment span of 2 mA to 20 mA allows the AD9708 to operate at reduced power levels (i.e., 45 mW) without any degradation in dynamic performance. 5. A temperature compensated, 1.20 V bandgap reference is included on-chip providing a complete DAC solution. An external reference may be used. 6. The current output(s) of the AD9708 can easily be configured for various single-ended or differential applications. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9708–SPECIFICATIONS DC SPECIFICATIONS (T MIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted) Parameter Min RESOLUTION 8 MONOTONICITY Typ Max Units Bits GUARANTEED OVER SPECIFIED TEMPERATURE RANGE 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth (w/o CCOMP1)4 ± 1/4 ± 1/4 –1/2 –1/2 –0.025 –10 –10 2.0 –1.0 OPERATING RANGE LSB LSB +0.025 +10 +10 20.0 1.25 % of FSR % of FSR % of FSR mA V kΩ pF 1.32 V nA 1.25 1 1.4 V MΩ MHz 0 ± 50 ± 100 ± 50 ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm/°C ±2 ±1 100 5 1.08 1.20 100 0.1 TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD5 DVDD Analog Supply Current (IAVDD ) Digital Supply Current (IDVDD)6 Supply Current Sleep Mode (IAVDD) Power Dissipation6 (5 V, IOUTFS = 20 mA) Power Dissipation7 (5 V, IOUTFS = 20 mA) Power Dissipation7 (3 V, IOUTFS = 2 mA) Power Supply Rejection Ratio—AVDD Power Supply Rejection Ratio—DVDD +1/2 +1/2 2.7 2.7 5.0 5.0 25 3 –0.4 –0.025 +0.4 +0.025 V V mA mA mA mW mW mW % of FSR/V % of FSR/V –40 +85 °C 140 190 45 5.5 5.5 30 6 8.5 175 NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 × the I REF current. 3 Use an external buffer amplifier to drive any external load. 4 Reference bandwidth is a function of external cap at COMP1 pin. 5 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 6 Measured at fCLOCK = 50 MSPS and fOUT = 1.0 MHz. 7 Measured as unbuffered voltage output into 50 Ω RLOAD at IOUTA and IOUTB, f CLOCK = 100 MSPS and fOUT = 40 MHz. Specifications subject to change without notice. –2– REV. B AD9708 (TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Single-Ended Output, IOUTA, 50 ⍀ Doubly DYNAMIC SPECIFICATIONS Terminated, unless otherwise noted) Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST ) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (I OUTFS = 20 mA) Output Noise (I OUTFS = 2 mA) AC LINEARITY TO NYQUIST Signal-to-Noise and Distortion Ratio fCLOCK = 10 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 12.51 MHz fCLOCK = 100 MSPS; fOUT = 5.01 MHz fCLOCK = 100 MSPS; fOUT = 25.01 MHz Total Harmonic Distortion fCLOCK = 10 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 12.51 MHz fCLOCK = 100 MSPS; fOUT = 5.01 MHz fCLOCK = 100 MSPS; fOUT = 25.01 MHz Spurious-Free Dynamic Range to Nyquist fCLOCK = 10 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 12.51 MHz fCLOCK = 100 MSPS; fOUT = 5.01 MHz fCLOCK = 100 MSPS; fOUT = 25.01 MHz Min Typ 100 125 35 1 5 2.5 2.5 50 30 MSPS ns ns pV-s ns ns pA/√Hz pA/√Hz 50 50 48 50 45 dB dB dB dB dB –67 –67 –59 –64 –48 Max –62 68 68 63 67 50 62 Units dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc NOTES 1 Measured single ended into 50 Ω load. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (T MIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted) Parameter DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V Logic “1” Voltage @ DVDD = +3 V Logic “0” Voltage @ DVDD = +5 V Logic “0” Voltage @ DVDD = +3 V Logic “1” Current Logic “0” Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (t LPW) Min Typ 3.5 2.1 5 3 0 0 2.0 1.5 3.5 ns 5 Specifications subject to change without notice. DB0–DB7 tS tH tLPW tPD tST IOUTA OR IOUTB 0.1% 0.1% Figure 1. Timing Diagram REV. B –3– Units V V V V µA µA pF ns ns –10 –10 CLOCK Max 1.3 0.9 +10 +10 AD9708 ABSOLUTE MAXIMUM RATINGS* PIN FUNCTION DESCRIPTIONS With Respect to Min Max Units ACOM DCOM DCOM DVDD DCOM DCOM ACOM ACOM ACOM ACOM –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –1.0 –0.3 –0.3 –0.3 +6.5 +6.5 +0.3 +6.5 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +0.3 +150 +150 V V V V V V V V V V °C °C +300 °C Pin No. Name Description 1 2–7 8 9–14, 25 15 DB7 DB6–DB1 DB0 NC SLEEP 16 REFLO 17 REFIO 18 19 FS ADJ COMP1 28-Lead 300 mil SOIC θJA = 71.4°C/W θJC = 23°C/W 20 21 ACOM IOUTB 28-Lead TSSOP θJA = 97.9°C/W θJC = 14.0°C/W 22 IOUTA 23 COMP2 24 AVDD 26 27 DCOM DVDD 28 CLOCK Most Significant Data Bit (MSB). Data Bits 1–6. Least Significant Data Bit (LSB). No Internal Connection. Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance. Analog Common. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor. Analog Supply Voltage (+2.7 V to +5.5 V). Digital Common. Digital Supply Voltage (+2.7 V to +5.5 V). Clock Input. Data latched on positive edge of clock. Parameter AVDD DVDD ACOM AVDD CLOCK, SLEEP Digital Inputs IOUTA, IOUTB COMP1, COMP2 REFIO, FSADJ REFLO Junction Temperature Storage Temperature Lead Temperature (10 sec) –65 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. THERMAL CHARACTERISTICS Thermal Resistance PIN CONFIGURATION 28 CLOCK (MSB) DB7 1 DB6 2 27 DVDD DB5 3 26 DCOM DB4 4 25 NC DB3 5 DB2 6 AD9708 24 AVDD TOP VIEW 23 COMP2 DB1 7 (Not to Scale) 22 IOUTA DB0 8 21 IOUTB NC 9 20 ACOM NC 10 19 COMP1 NC 11 18 FS ADJ NC 12 17 REFIO NC 13 16 REFLO NC 14 15 SLEEP ORDERING GUIDE Model Temperature Range Package Descriptions Package Options* AD9708AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28 AD9708ARU –40°C to +85°C 28-Lead TSSOP RU-28 AD9708-EB Evaluation Board NC = NO CONNECT *R = Small Outline IC; RU = Thin Small Outline IC. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9708 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. B AD9708 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Differential Nonlinearity (or DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Settling Time Monotonicity A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Offset Error Glitch Impulse The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Gain Error The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Spurious-Free Dynamic Range The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio S/N+D is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. Total Harmonic Distortion THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured output signal. It is expressed as a percentage or in decibels (dB). Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either TMIN or TMAX . For +5V 0.1mF REFLO +1.20V REF 0.1mF REF IO COMP1 AVDD AD9708 CURRENT SOURCE ARRAY FS ADJ RSET 2kV +5V ACOM 50pF COMP2 0.1mF IOUTA DVDD SEGMENTED SWITCHES DCOM IOUTB CLOCK 50V LATCHES DVDD DCOM 50V RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR SLEEP 50V CLOCK OUTPUT DIGITAL DATA TEKTRONIX AWG-2021 Figure 2. Basic AC Characterization Test Setup REV. B –5– 20pF TO HP3589A SPECTRUM/ NETWORK ANALYZER 50V INPUT 20pF * AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. AD9708 Typical AC Characterization Curves (AVDD = +5 V or +3 V, DVDD = +5 V or +3 V, 50 ⍀ Doubly Terminated Load, Single-Ended Output, IOUTA, IOUTFS = 20 mA, TA = +25ⴗC, unless otherwise noted) 70 70 55 THD @ 10MSPS THD @ 50MSPS THD @ 10MSPS 55 SINAD @ 10MSPS SINAD @ 50MSPS 45 THD @ 50MSPS 55 50 10 1 FREQUENCY – MHz 30 100 Figure 4. SINAD/THD vs. f OUT (Differential Output, AVDD and DVDD = 5.0 V) THD @ 100MSPS 60 THD @ 50MSPS 55 SINAD @ 10MSPS IOUTFS = 20mA THD @ 50MSPS 50 IOUTFS = 10mA IOUTFS = 5mA 55 THD @ 100MSPS 50 100 10 FREQUENCY – MHz 60 48 IOUTFS = 2.5mA 46 SINAD @ 10MSPS 44 45 SINAD @ 100MSPS SINAD @ 100MSPS 1 10 FREQUENCY – MHz 1 Figure 5. SINAD vs. IOUTFS @ 100 MSPS SINAD @ 50MSPS SINAD @ 50MSPS 40 0.1 IOUTFS = 2.5mA 52 THD @ 10MSPS 65 SINAD/THD – dB SINAD/THD – dB 10 1 FREQUENCY – MHz 70 45 40 SINAD @ 100MSPS 40 0.1 100 70 50 IOUTFS = 5mA 35 SINAD @ 50MSPS 45 Figure 3. SINAD/THD vs. fOUT (AVDD and DVDD = 5.0 V) 65 THD @ 10MSPS 45 SINAD @ 10MSPS SINAD @ 100MSPS 40 0.1 IOUTFS = 10mA 60 SINAD – dB 50 50 THD @ 100MSPS SINAD – dB 60 IOUTFS = 20mA 65 THD @ 100MSPS SINAD/THD – dB SINAD/THD – dB 65 40 0.1 100 Figure 6. SINAD/THD vs. fOUT (AVDD and DVDD = 3.0 V) 1 10 FREQUENCY – MHz 42 0.1 100 Figure 7. SINAD/THD vs. f OUT (Differential Output, AVDD and DVDD = 3.0 V) Figure 8. SINAD vs. IOUTFS @ 20 MSPS 0 0 0.6 fCLOCK = 25MSPS fOUT = 7.81MHz SFDR = +60.7dBc AMPLITUDE = 0dBFS fCLOCK = 125MSPS fOUT = 27.0MHz SFDR = +52.7dBc AMPLITUDE = 0dBc 0.5 0.4 0.3 VOLTS 10dB – Div 10dB – Div 10 1 FREQUENCY – MHz 0.2 0.1 0.0 –0.1 –100 –100 START: 0Hz STOP: 12.5MHz Figure 9. Single-Tone Spectral Plot @ 25 MSPS –0.2 START: 0Hz STOP: 62.5MHz Figure 10. Single-Tone Spectral Plot @ 125 MSPS –6– TIME – 5ns/Div Figure 11. Step Response REV. B AD9708 FUNCTIONAL DESCRIPTION As previously mentioned, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage VREFIO and external resistor RSET. It can be expressed as: Figure 12 shows a simplified block diagram of the AD9708. The AD9708 consists of a large PMOS current source array capable of providing up to 20 mA of total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The remaining 3 LSBs are also implemented with equally weighted current sources whose sum total equals 7/8th of an MSB current source. Implementing the upper and lower bits with current sources helps maintain the DAC’s high output impedance (i.e. > 100 kΩ). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. IOUTFS = 32 × IREF (3) where IREF = VREFIO /RSET (4) The two current outputs will typically drive a resistive load directly. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, which are tied to analog common, ACOM. Note, RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply: The analog and digital sections of the AD9708 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 2.7 volt to 5.5 volt range. The digital section, which is capable of operating up to a 125 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.20 V bandgap voltage reference and a reference control amplifier. VOUTA = IOUTA × R LOAD (5) V OUTB = IOUTB × R LOAD (6) Note the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. The differential voltage, VDIFF , appearing across IOUTA and IOUTB is: The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET. The external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current I REF, which is mirrored over to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is thirty-two times the value of IREF. Substituting the values of IOUTA , IOUTB, and IREF; VDIFF can be expressed as: DAC TRANSFER FUNCTION VOLTAGE REFERENCE AND CONTROL AMPLIFIER The AD9708 provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 255), while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB are a function of both the input code and IOUTFS and can be expressed as: The AD9708 contains an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external reference. REFIO serves as either an input or output depending on whether the internal or an external reference is selected. If REFLO is tied to ACOM, as shown in Figure 13, the internal reference is activated and REFIO provides a 1.20 V output. In this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 µF or greater from REFIO to REFLO. Note that REFIO is not designed to drive any external load. It should be buffered with an external amplifier having an input bias current less than 100 nA if any additional loading is required. IOUTA = (DAC CODE/256) × IOUTFS VDIFF = (IOUTA – IOUTB) × RLOAD VDIFF = {(2 DAC CODE – 255)/256}/ × (32 RLOAD /RSET) × VREFIO (1) IOUTB = (255 – DAC CODE)/256 × IOUTFS (2) where DAC CODE = 0 to 255 (i.e., Decimal Representation). +5V 0.1mF REFLO +1.20V REF VREFIO REFIO IREF 0.1mF RSET 2kV ACOM AD9708 50pF CURRENT SOURCE ARRAY FS ADJ COMP2 DVDD IOUTA SEGMENTED SWITCHES IOUTB CLOCK LATCHES SLEEP DIGITAL DATA INPUTS (DB7–DB0) Figure 12. Functional Block Diagram REV. B 0.1mF VDIFF = VOUTA – VOUTB +5V DCOM CLOCK AVDD COMP1 –7– IOUTA IOUTB VOUTA VOUTB RLOAD 50V RLOAD 50V (7) (8) AD9708 +5V The small signal bandwidth of the reference control amplifier is approximately 1.8 MHz and can be reduced by connecting an external capacitor between COMP1 and AVDD. The output of the control amplifier, COMP1, is internally compensated via a 50 pF capacitor that limits the control amplifier small-signal bandwidth and reduces its output impedance. Any additional external capacitance further limits the bandwidth and acts as a filter to reduce the noise contribution from the reference amplifier. If IREF is fixed for an application, a 0.1 µF ceramic chip capacitor is recommended. 0.1mF OPTIONAL EXTERNAL REF BUFFER REFLO COMP1 +1.2V REF 50pF REFIO ADDITIONAL LOAD 0.1mF CURRENT SOURCE ARRAY FS ADJ 2kV AVDD AD9708 Figure 13. Internal Reference Configuration IREF can be varied for a fixed RSET by disabling the internal reference and varying the common-mode voltage over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply amplifier or DAC, thus allowing IREF to be varied for a fixed RSET. Since the input impedance of REFIO is approximately 1 MΩ, a simple R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown in Figure 15 using the AD7524 and an external 1.2 V reference, the AD1580. Note another AD9708 could also be used as the gain control DAC since it can also provide a programmable unipolar output up to 1.2 V. The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied to REFIO as shown in Figure 14. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 µF compensation capacitor is not required since the internal reference is disabled, and the high input impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the external reference. AVDD ANALOG OUTPUTS AND OUTPUT CONFIGURATIONS The AD9708 produces two complementary current outputs, IOUTA and IOUTB , which may be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC TRANSFER FUNCTION section. Figure 16 shows the AD9708 configured to provide a positive unipolar output range of approximately 0 V to +0.5 V for a double terminated 50 Ω cable for a nominal full-scale current, IOUTFS, of 20 mA. In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB and is equal to 25 Ω. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. 0.1mF REFLO AVDD COMP1 AVDD +1.2V REF 50pF VREFIO EXTERNAL REF REFIO CURRENT SOURCE ARRAY FS ADJ RSET IREF = VREFIO/RSET REFERENCE CONTROL AMPLIFIER AD9708 Figure 14. External Reference Configuration The AD9708 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 14, such that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 µA and 625 µA. The wide adjustment span of IOUTFS provides several application benefits. The first benefit relates directly to the power dissipation of the AD9708, which is proportional to IOUTFS (refer to the POWER DISSIPATION section). The second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes. AD9708 IOUTFS = 20mA VOUTA = 0 TO +0.5V IOUTA 22 50V 50V IOUTB 21 25V Figure 16. 0 V to +0.5 V Unbuffered Voltage Output Alternatively, an amplifier could be configured as an I-V converter thus converting IOUTA or IOUTB into a negative unipolar AVDD OPTIONAL BANDLIMITING CAPACITOR AVDD REFLO RFB 1.2V AD1580 OUT1 +1.2V REF VDD AD7524 VREF 0.1V TO 1.2V OUT2 COMP1 50pF REFIO FS ADJ AGND RSET IREF = VREF/RSET AVDD CURRENT SOURCE ARRAY AD9708 DB7–DB0 Figure 15. Single-Supply Gain Control Circuit –8– REV. B AD9708 voltage. Figure 17 shows a buffered singled-ended output configuration in which the op amp, U1, performs an I-V conversion on the AD9708 output current. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1’s voltage output swing capabilities by scaling IOUTFS and/or RFB . An improvement in ac distortion performance may result with a reduced IOUTFS, since the signal current U1 will be required to sink and will be subsequently reduced. Note, the ac distortion performance of this circuit at higher DAC update rates may be limited by U1’s slewing capabilities. over a digital supply range of 2.7 V to 5.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage, VOH(MAX) , of the TTL drivers. A DVDD of 3 V to 3.3 V will typically ensure upper compatibility of most TTL logic families. DVDD DIGITAL INPUT COPT RFB 200V AD9708 Figure 18. Equivalent Digital Input IOUTFS = 10mA IOUTA 22 U1 VOUT = IOUTFS 3 RFB IOUTB 21 200V Figure 17. Unipolar Buffered Voltage Output IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA. Applications requiring the AD9708’s output (i.e., VOUTA and/or VOUTB) to extend up to its output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect the AD9708’s linearity. The differential voltage, VDIFF , existing between VOUTA and VOUTB may also be converted to a single-ended voltage via a transformer or differential amplifier configuration. Refer to the DIFFERENTIAL OUTPUT CONFIGURATION section for more information. DIGITAL INPUTS The AD9708’s digital input consists of eight data input pins and a clock input pin. The 8-bit parallel data inputs follow standard positive binary coding where DB7 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). The digital interface is implemented using an edge-triggered master slave latch. The DAC output is updated following the rising edge of the clock as shown in Figure 1 and is designed to support a clock rate as high as 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth. The setup-and-hold times can also be varied within the clock cycle as long as the specified minimum times are met; although the location of these transition edges may affect digital feedthrough and distortion performance. The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD set to approximately half the digital positive supply (DVDD) or VTHRESHOLD = DVDD/2 (±20%) Figure 18 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar, except that it contains an active pull-down circuit, thus ensuring that the AD9708 remains enabled if this input is left disconnected. The internal digital circuitry of the AD9708 is capable of operating REV. B Since the AD9708 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum setup-and-hold times of the AD9708 as well as its required min/ max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 20 Ω to 100 Ω) between the AD9708 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. For longer run lengths and high data update rates, strip line techniques with proper termination resistors should be considered to maintain “clean” digital inputs. Also, operating the AD9708 with reduced logic swings and a corresponding digital supply (DVDD) will also reduce data feedthrough. The external clock driver circuitry should provide the AD9708 with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform. However, the clock input could also be driven by via a sine wave, which is centered around the digital threshold (i.e., DVDD/2), and meets the min/max logic threshold. This may result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. Note, at higher sampling rates the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and subsequently cut into the required data setup-and-hold times. SLEEP MODE OPERATION The AD9708 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 2.7 V to 5.5 V and temperature range. This mode can be activated by applying a logic level “1” to the SLEEP pin. This digital input also contains an active pull-down circuit that ensures the AD9708 remains enabled if this input is left disconnected. The SLEEP input with active pull-down requires