AD9709-EB

a FEATURES 8-Bit Dual Transmit DAC 125 MSPS Update Rate Excellent SFDR to Nyquist @ 5 MHz Output = 66 dBc Excellent Gain and Offset Matching: 0.1% Fully Independent or Single Resistor Gain Control Dual Port or Interleaved Data On-Chip 1.2 V Reference Single 5 V or 3 V Supply Operation Power Dissipation: 380 mW @ 5 V Power-Down Mode: 50 mW @ 5 V 48-Lead LQFP APPLICATIONS Communications Basestations Digital Synthesis Quadrature Modulation 3D Ultrasound PRODUCT DESCRIPTION 8-Bit, 125 MSPS Dual TxDAC+® D/A Converter AD9709* FUNCTIONAL BLOCK DIAGRAM DVDD DCOM AVDD ACOM CLK1 “1” DAC IOUTA1 IOUTB1 REFIO FSADJ1 FSADJ2 GAINCTRL SLEEP IOUTA2 IOUTB2 PORT1 “1” LATCH WRT1 WRT2 REFERENCE DIGITAL INTERFACE AD9709 BIAS GENERATOR PORT2 “2” LATCH MODE “2” DAC CLK2 The AD9709 is a dual-port, high-speed, two-channel, 8-bit CMOS DAC. It integrates two high-quality 8-bit TxDAC+ cores, a voltage reference, and digital interface circuitry into a small 48-lead LQFP package. The AD9709 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The AD9709 has been optimized for processing I and Q data in communications applications. The digital interface consists of two double-buffered latches as well as control logic. Separate write inputs allow data to be written to the two DAC ports independent of one another. Separate clocks control the update rate of the DACs. A mode control pin allows the AD9709 to interface to two separate data ports, or to a single interleaved high-speed data port. In interleaving mode, the input data stream is demuxed into its original I and Q data and then latched. The I and Q data is then converted by the two DACs and updated at half the input data rate. The GAINCTRL pin allows two modes for setting the full-scale current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set independently using two external resistors, or IOUTFS for both DACs can be set using a single external resistor. The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. Each DAC provides differential current output thus supporting single-ended or differential applications. Both DACs can be simultaneously updated and provide a nominal full-scale current of 20 mA. The full-scale currents between each DAC are matched to within 0.1%. The AD9709 is manufactured on an advanced low-cost CMOS process. It operates from a single supply of 3.0 V to 5.0 V and consumes 380 mW of power. PRODUCT HIGHLIGHTS 1. The AD9709 is a member of a pin-compatible family of dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution. 2. Dual 8-Bit, 125 MSPS DACs: A pair of high-performance DACs optimized for low-distortion performance provide for flexible transmission of I and Q information. 3. Matching: Gain matching is typically 0.1% of full-scale, and offset error is better than 0.02%. 4. Low Power: Complete CMOS Dual DAC function operates on 380 mW from a 3.0 V to 5.0 V single supply. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for low-power idle periods. 5. On-Chip Voltage Reference: The AD9709 includes a 1.20 V temperature-compensated bandgap voltage reference. TxDAC+ is a registered trademark of Analog Devices, Inc. *Patent pending. 6. Dual 8-Bit Inputs: The AD9709 features a flexible dual-port interface allowing dual or interleaved input data. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 AD9709–SPECIFICATIONS DC SPECIFICATIONS (T Parameter RESOLUTION DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Gain Match TA = 25°C TMIN to TMAX TMIN to TMAX Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD Analog Supply Current (IAVDD) Digital Supply Current (IDVDD)4 Digital Supply Current (IDVDD)5 Supply Current Sleep Mode (IAVDD) Power Dissipation4 (5 V, IOUTFS = 20 mA) Power Dissipation5 (5 V, IOUTFS = 20 mA) Power Dissipation6 (5 V, IOUTFS = 20 mA) Power Supply Rejection Ratio7—AVDD Power Supply Rejection Ratio7—DVDD OPERATING RANGE 1 MIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 20 mA, unless otherwise noted) Min 8 –0.5 –0.5 –0.02 –2 –5 –0.3 –1.6 –0.14 2.0 –1.0 ± 0.1 ± 0.1 +0.5 +0.5 +0.02 +2 +5 +0.3 +1.6 +0.14 20.0 +1.25 Typ Max Unit Bits LSB LSB % of FSR % of FSR % of FSR % of FSR % of FSR dB mA V kΩ pF V nA V MΩ MHz ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm/°C ± 0.25 ±1 ± 0.1 100 5 1.14 1.20 100 1.26 0.1 1 0.5 0 ± 50 ± 100 ± 50 1.25 3 2.7 5 5 71 5 8 380 420 450 5.5 5.5 75 7 15 12 410 450 +0.4 +0.025 +85 –0.4 –0.025 –40 V V mA mA mA mA mW mW mW % of FSR/V % of FSR/V °C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 times the IREF current. 3 An external buffer amplifier with input bias current 100 kΩ). All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. This new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. The analog and digital sections of the AD9709 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently over a 3 V to 5.5 V range. The digital section, which is capable of operating up to a 125 MSPS clock rate, consists of edge-triggered latches and segment decoding logic circuitry. The analog section includes the PMOS current sources, the associated differential switches, a 1.20 V bandgap voltage reference and two reference control amplifiers. The full-scale output current of each DAC is regulated by separate reference control amplifiers and can be set from 2 mA to 20 mA via an external resistor, RSET, connected to the Full-Scale Adjust (FSADJ) pin. The external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current IREF, which is replicated to the segmented current sources with the proper scaling factor. The fullscale current, IOUTFS, is 32 × IREF. 5V AVDD CLK DIVIDER FSADJ1 RSET1 2k IREF1 REFIO 0.1 F PMOS CURRENT SOURCE ARRAY CLK1/ IQCLK The AD9709 contains an internal 1.20 V bandgap reference. This can be easily overridden by an external reference with no effect on performance. REFIO serves as either an input or output depending on whether the internal or an external reference is used. To use the internal reference, simply decouple the REFIO pin to ACOM with a 0.1 µF capacitor. The internal reference voltage will be present at REFIO. If the voltage at REFIO is to be used elsewhere in the circuit, an external buffer amplifier with an input bias current of less than 100 nA should be used. An example of the use of the internal reference is shown in Figure 21. An external reference can be applied to REFIO as shown in Figure 22. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 µF compensation capacitor is not required since the internal reference is overridden, and the relatively high-input impedance of REFIO minimizes any loading of the external reference. GAINCTRL MODE The AD9709 allows the gain of each channel to be set independently by connecting one RSET resistor to FSADJ1 and another RSET resistor to FSADJ2. To add flexibility and reduce system cost, a single RSET resistor can be used to set the gain of both channels simultaneously. When GAINCTRL is low (i.e., connected to AGND), the independent channel gain control mode using two resistors is enabled. In this mode, individual RSET resistors should be connected to FSADJ1 and FSADJ2. When GAINCTRL is high (i.e., connected to AVDD), the master/slave channel gain control mode using one resistor is enabled. In this mode, a single RSET resistor is connected to FSADJ1 and the resistor on FSADJ2 can be removed. CLK2/ IQRESET SLEEP AD9709 IOUTA1 SEGMENTED SWITCHES FOR DAC1 LSB SWITCH VDIFF = VOUTA – VOUTB VOUT1A RL1A 50 DAC1 LATCH IOUTB1 IOUTA2 VOUT2A VOUT2B RL2B 50 VOUT1B RL1B 50 FSADJ2 RSET2 2k IREF2 PMOS CURRENT SOURCE ARRAY 1.2V REF DAC2 LATCH SEGMENTED SWITCHES FOR DAC2 LSB SWITCH IOUTB2 RL2A 50 MULTIPLEXING LOGIC CHANNEL 1 LATCH GAINCTRL WRT1/ IQWRT CHANNEL 2 LATCH DVDD ACOM DCOM 5V DB0-DB7 DB0-DB7 DIGITAL DATA INPUTS WRT2/ MODE IQSEL Figure 20. Simplified Block Diagram REV. 0 –9– AD9709 REFERENCE CONTROL AMPLIFIER Both of the DACs in the AD9709 contain a control amplifier that is used to regulate the full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter as shown in Figure 21, so that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied to the segmented current sources with the proper scale factor to set IOUTFS as stated in Equation 3. OPTIONAL EXTERNAL REFERENCE BUFFER GAINCTRL +1.2V REF REFIO 0.1 F IREF 2k FSADJ AVDD The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, that are tied to analog common, ACOM. Note, RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply : VOUTA = IOUTA × RLOAD VOUTB = IOUTB × RLOAD (5) (6) AD9709 REFERENCE SECTION CURRENT SOURCE ARRAY ACOM ADDITIONAL EXTERNAL LOAD Note the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. VDIFF = (IOUTA – IOUTB) × RLOAD (7) Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be expressed as: VDIFF = {(2 × DAC CODE – 255)/256} × (32 × RLOAD/RSET) × VREFIO (8) Figure 21. Internal Reference Configuration GAINCTRL AVDD +1.2V REF REFIO FSADJ IREF 2k AVDD AD9709 REFERENCE SECTION CURRENT SOURCE ARRAY ACOM EXTERNAL REFERENCE These last two equations highlight some of the advantages of operating the AD9709 differentially. First, the differential operation will help cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion and dc offsets. Second, the differential code dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal power to the load. Note, the gain drift temperature performance for a single-ended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9709 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship as shown in Equation 8. ANALOG OUTPUTS Figure 22. External Reference Configuration The control amplifier allows a wide (10:1) adjustment span of IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 µA and 625 µA. The wide adjustment range of IOUTFS provides several benefits. The first relates directly to the power dissipation of the AD9709, which is proportional to IOUTFS (refer to the Power Dissipation section). The second relates to the 20 dB adjustment, which is useful for system gain control purposes. The small signal bandwidth of the reference control amplifier is approximately 500 kHz and can be used for low frequency, small signal multiplying applications. DAC TRANSFER FUNCTION Both DACs in the AD9709 provide complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 1023) while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as: IOUTA = (DAC CODE/256) × IOUTFS IOUTB = (255 – DAC CODE)/256 × IOUTFS (1) (2) The complementary current outputs in each DAC, IOUTA and IOUTB, may be configured for single-ended or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9709 is optimum and specified using a differential transformer coupled output in which the voltage swing at IOUTA and IOUTB is limited to ± 0.5 V. If a single-ended unipolar output is desirable, IOUTA should be selected. The distortion and noise performance of the AD9709 can be enhanced when it is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB can be significantly reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed waveform increases. This is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digital feedthrough and noise. where DAC CODE = 0 to 255 (i.e., Decimal Representation). As mentioned previously, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage, VREFIO and external resistor RSET. It can be expressed as: IOUTFS = 32 × IREF where IREF = VREFIO /RSET (4) (3) –10– REV. 0 AD9709 Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source termination). Since the output currents of IOUTA and IOUTB are complementary, they become additive when processed differentially. A properly selected transformer will allow the AD9709 to provide the required power and voltage levels to different loads. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ in parallel with 5 pF. It is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS device. As a result, maintaining IOUTA and/or IOUTB at a virtual ground via an I-V op amp configuration will result in the optimum dc linearity. Note the INL/DNL specifications for the AD9709 are measured with IOUTA maintained at a virtual ground via an op amp. IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of –1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9709. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA. The optimum distortion performance for a single-ended or differential output is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. Applications requiring the AD9709’s output (i.e., VOUTA and/or VOUTB) to extend its output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect the AD9709’s linearity performance and subsequently degrade its distortion performance. DIGITAL INPUTS DAC TIMING The AD9709 can operate in two timing modes, dual and interleaved, which are described below. The block diagram in Figure 25 represents the latch architecture in the interleaved timing mode. DUAL PORT MODE TIMING When the mode pin is at Logic 1, the AD9709 operates in dual port mode. The AD9709 functions as two distinct DACs. Each DAC has its own completely independent digital input and control lines. The AD9709 features a double buffered data path. Data enters the device through the channel input latches. This data is then transferred to the DAC latch in each signal path. Once the data is loaded into the DAC latch, the analog output will settle to its new value. For general consideration, the WRT lines control the channel input latches and the CLK lines control the DAC latches. Both sets of latches are updated on the rising edge of their respective control signals. The rising edge of CLK should occur before or simultaneously with the rising edge of WRT. Should the rising edge of CLK occur after the rising edge of WRT, a 2 ns minimum delay should be maintained from rising edge of WRT to rising edge of CLK. tS DATA IN tH WRT1/WRT2 CLK1/CLK2 t LPW t CPW IOUTA OR IOUTB t PD Figure 23. Dual Mode Timing The AD9709’s digital inputs consists of two independent channels. For the dual port mode, each DAC has its own dedicated 8-bit data port, WRT line and CLK line. In the interleaved timing mode, the function of the digital control pins changes as described below under the Interleaved Mode Timing section. The 8-bit parallel data inputs follow straight binary coding where DB7 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. The digital interface is implemented using an edge-triggered master slave latch. The DAC outputs are updated following either the rising edge, or every other rising edge of the clock, depending on whether dual or interleaved mode is being used. The DAC outputs are designed to support a clock rate as high as 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met, although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. Timing specifications for dual port mode are given in Figures 23 and 24. DATAIN D1 D2 D3 D4 D5 WRT1/WRT2 CLK1/CLK2 IOUTA OR IOUTB xx D1 D2 D3 D4 Figure 24. Dual Mode Timing INTERLEAVED MODE TIMING When the mode pin is at Logic 0, the AD9709 operates in interleaved mode. WRT1 now functions as IQWRT and CLK1 functions as IQCLK. WRT2 functions as IQSEL and CLK2 functions as IQRESET. Data enters the device on the rising edge of IQWRT. The logic level of IQSEL will steer the data to either Channel Latch 1 (IQSEL = 1) or to Channel Latch 2 (IQSEL = 0). Note: For proper operation, IQSEL should only change state when IQWRT and IQCLK are low. –11– REV. 0 AD9709 When IQRESET is high, IQCLK is disabled. When IQRESET goes low, the following rising edge on IQCLK will update both DAC latches with the data present at their inputs. In the interleaved mode IQCLK is divided by 2 internally. Following this first rising edge, the DAC latches will only be updated on every other rising edge of IQCLK. In this way, IQRESET can be used to synchronize the routing of the data to the DACs. As with the dual port mode, IQCLK should occur before or simultaneously with IQWRT. INTERLEAVED DATA IN, PORT 1 PORT 1 INPUT LATCH DAC1 LATCH DAC1 IQWRT IQSEL PORT 2 INPUT LATCH IQCLK IQRESET DEINTERLEAVED DATA OUT DAC2 LATCH DAC2 The digital inputs are CMOS-compatible with logic thresholds, VTHRESHOLD, set to approximately half the digital positive supply (DVDD) or VTHRESHOLD = DVDD/2 (± 20%) The internal digital circuitry of the AD9709 is capable of operating over a digital supply range of 3 V to 5.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high-level voltage of the TTL drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure proper compatibility with most TTL logic families. Figure 28 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar with the exception that it contains an active pull-down circuit, thus ensuring that the AD9709 remains enabled if this input is left disconnected. Since the AD9709 is capable of being clocked up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9709 with reduced logic swings and a corresponding digital supply (DVDD) will result in the lowest data feedthrough and on-chip digital noise. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9709 as well as its required min/max input logic level thresholds. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a lowvalue resistor network (i.e., 20 Ω to 100 Ω) between the AD9709 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to digital feedthrough. For longer board traces and high-data update rates, stripline techniques with proper impedance and termination resistors should be considered to maintain “clean” digital inputs. The external clock driver circuitry should provide the AD9709 with a low-jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform. Thus, the clock input should be driven by the fastest logic family suitable for the application. DVDD 2 Figure 25. Latch Structure in Interleaved Mode Timing specifications for interleaved mode are given in Figures 26 and 27. tS DATA IN tH IQSEL t H* IQWRT t LPW IQCLK IOUTA OR IOUTB t PD *APPLIES TO FALLING EDGE OF IQCLK /IQWRT AND IQSEL ONLY Figure 26. Interleaved Mode Timing INTERLEAVED DATA IQSEL xx D1 D2 D3 D4 D5 DIGITAL INPUT IQWRT IQCLK Figure 28. Equivalent Digital Input IQRESET DAC OUTPUT PORT 1 DAC OUTPUT PORT 2 xx xx D1 D2 D3 D4 Figure 27. Interleaved Mode Timing Note that the clock input could also be driven via a sine wave, which is centered around the digital threshold (i.e., DVDD/2) and meets the min/max logic threshold. This will typically result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. Also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and, subsequently, cut into the required data setup and hold times. –12– REV. 0 AD9709 60 50 40 SINAD – dBc 30 the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high-frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting, within the bandwidth of the chosen op amp. 80 20 10 70 0 –4 –3 IAVDD – mA 0 –2 –1 1 2 TIME OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE – ns 3 4 60 50 40 30 20 10 0 5 15 10 IOUTFS – mA 20 25 Figure 29. SINAD vs. Clock Placement @ fOUT = 20 MHz INPUT CLOCK AND DATA TIMING RELATIONSHIP SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9709 is rising edge triggered, and so exhibits SNR sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9709 is to make the data transition close to the falling clock edge. This becomes more important as the sample rate increases. Figure 29 shows the relationship of SNR to clock/data placement. SLEEP MODE OPERATION Figure 30. IAVDD vs. IOUTFS 35 30 125MSPS 25 100MSPS IDVDD – mA The AD9709 has a power down function that turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 3.0 V to 5.5 V and temperature range. This mode can be activated by applying a logic level 1 to the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5 × AVDD. This digital input also contains an active pull-down circuit that ensures the AD9709 remains enabled if this input is left disconnected. The AD9709 takes less than 50 ns to power down and approximately 5 µs to power back up. POWER DISSIPATION 20 65MSPS 15 10 5 0 25MSPS 5MSPS 0 0.1 The power dissipation, PD, of the AD9709 is dependent on several factors that include: (1) The power supply voltages (AVDD and DVDD), (2) the full-scale current output IOUTFS, (3) the update rate fCLOCK, (4) and the reconstructed digital input waveform. The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS as shown in Figure 30 and is insensitive to fCLOCK. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figures 31 and 32 show IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 5 V and DVDD = 3 V, respectively. Note how IDVDD is reduced by more than a factor of 2 when DVDD is reduced from 5 V to 3 V. APPLYING THE AD9709 Output Configurations IDVDD – mA 0.2 0.3 RATIO – fOUT /fCLK 0.4 0.5 Figure 31. IDVDD vs. Ratio @ DVDD = 5 V 18 16 125MSPS 14 12 10 65MSPS 8 6 4 2 0 0.1 25MSPS 5MSPS 100MSPS 0 The following sections illustrate some typical output configurations for the AD9709. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring REV. 0 –13– 0.2 0.3 RATIO – fOUT /fCLK 0.4 0.5 Figure 32. IDVDD vs. Ratio @ DVDD = 3 V AD9709 A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dccoupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. Note that IOUTA provides slightly better performance than IOUTB. DIFFERENTIAL COUPLING USING A TRANSFORMER some additional signal gain. The op amp must operate off of a dual supply since its output is approximately ± 1.0 V. A highspeed amplifier capable of preserving the differential performance of the AD9709 while meeting other system level objectives (i.e., cost, power) should be selected. The op amp’s differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. The differential circuit shown in Figure 35 provides the necessary level-shifting required in a single supply system. In this case, AVDD which is the positive analog supply for both the AD9709 and the op amp is also used to level-shift the differential output of the AD9709 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 33. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s passband. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only. MINI-CIRCUITS T1-1T RLOAD IOUTA Figure 36 shows the AD9709 configured to provide a unipolar output range of approximately 0 V to 0.5 V for a doubly terminated 50 Ω cable since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 Ω. In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL) as discussed in the Analog Output section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. 500 AD9709 IOUTB OPTIONAL RDIFF AD9709 IOUTA 225 Figure 33. Differential Output Using a Transformer 225 IOUTB COPT 500 25 25 AD8047 The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9709. A differential resistor, RDIFF, may be inserted in applications where the output of the transformer is connected to the load, RLOAD , via a passive reconstruction filter or cable. RDIFF i s determined by the transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. DIFFERENTIAL COUPLING USING AN OP AMP Figure 34. DC Differential Coupling Using an Op Amp 500 AD9709 IOUTA 225 225 IOUTB COPT 25 25 500 AD8041 1k AVDD An op amp can also be used to perform a differential to singleended conversion as shown in Figure 34. The AD9709 is configured with two equal load resistors, RLOAD, of 25 Ω. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amps distortion performance by preventing the DACs high-slewing output from overloading the op amp’s input. The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide –14– Figure 35. Single Supply DC Differential Coupled Circuit AD9709 IOUTA 50 IOUTB Figure 36. 0 V to 0.5 V Unbuffered Voltage Output REV. 0 AD9709 SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION Figure 37 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9709 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, thus minimizing the nonlinear output impedance effect on the DAC’s INL performance as discussed in the Analog Output section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by U1’s slewing capabilities. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1’s voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since the signal current U1 will be required to sink will be subsequently reduced. RFB 200 variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC’s full-scale current, IOUTFS. AC noise on the DC supplies is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise will occur over the spectrum from tens of kHz to several MHz. The PSRR vs. frequency of the AD9709 AVDD supply over this frequency range is shown in Figure 38. Note that the units in Figure 38 are given in units of (amps out/ volts in). Noise on the analog power supply has the effect of modulating the internal current sources, and therefore the output current. The voltage noise on AVDD, therefore, will be added in a nonlinear manner to the desired IOUT. PSRR is very code dependent, thus producing mixing effects which can modulate low-frequency power supply noise to higher frequencies. Worst case PSRR for either one of the differential DAC outputs will occur when the full-scale current is directed towards that output. As a result, the PSRR measurement in Figure 38 represents a worst-case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV of noise and for simplicity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise will appear as current noise superimposed on the dc’s full-scale current, IOUTFS, one must determine the PSRR in dB using Figure 38 at 250 kHz. To calculate the PSRR for a given RLOAD, such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 38 by the scaling factor 20 × Log (RLOAD ). For instance, if RLOAD is the PSRR is reduced by 34 dB (i.e., PSRR of the DAC at 250 kHz which is 85 dB in Figure 38 becomes 51 dB VOUT/VIN). Proper grounding and decoupling should be a primary objective in any high-speed, high-resolution system. The AD9709 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close to the chip as physically possible. AD9709 IOUTA U1 IOUTB 200 VOUT = IOUTFS RFB Figure 37. Unipolar Buffered Voltage Output 90 85 PSRR – dB 80 75 70 0.2 0.3 0.4 0.5 0.6 0.7 0.8 FREQUENCY – MHz 0.9 1.0 1.1 FERRITE BEADS TTL/CMOS LOGIC CIRCUITS ELECTROLYTIC CERAMIC AVDD Figure 38. AVDD Power Supply Rejection Ratio POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION 100 F 10 F–22 F 0.1 F ACOM TANTALUM +5V POWER SUPPLY Many applications seek high-speed and high-performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the printed circuit board is as important as the circuit design. Proper RF techniques must be used for device selection, placement and routing as well as power supply bypassing and grounding to ensure optimum performance. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution. This is referred to as the Power Supply Rejection Ratio. For dc REV. 0 Figure 39. Differential LC Filter for Single 5 V and 3 V Applications For those applications that require a single 5 V or 3 V supply for both the analog and digital supplies, a clean analog supply may be generated using the circuit shown in Figure 39. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained by using low-ESR type electrolytic and tantalum capacitors. –15– AD9709 APPLICATIONS Using the AD9709 for Quadrature Amplitude Modulation QAM is one of the most widely used digital modulation schemes in digital communications systems. This modulation technique can be found in FDM as well as spread spectrum (i.e., CDMA) based systems. A QAM signal is a carrier frequency that is modulated in both amplitude (i.e., AM modulation) and phase (i.e., PM modulation). It can be generated by independently modulating two carriers of identical frequency but with a 90° phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90° phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. 8 DAC DSP OR ASIC 8 DAC NYQUIST FILTERS QUADRATURE MODULATOR CARRIER FREQUENCY 0 90 implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. A quadrature mixer modulates the I and Q components with the in-phase and quadrature carrier frequency and then sums the two outputs to provide the QAM signal. In this implementation, it is much more difficult to maintain proper gain and phase matching between the I and Q channels. The circuit implementation shown in Figure 41 helps improve upon the matching between the I and Q channels, as well as showing a path for up-conversion using the AD8346 quadrature modulator. The AD9709 provides both I and Q DACs as well as a common reference that will improve the gain matching and stability. RCAL can be used to compensate for any mismatch in gain between the two channels. The mismatch may be attributed to the mismatch between RSET1 and RSET2, effective load resistance of each channel, and/or the voltage offset of the control amplifier in each DAC. The differential voltage outputs of both DACs in the AD9709 are fed into the respective differential inputs of the AD8346 via matching networks. I and Q digital data can be fed into the AD9709 in two different ways. In dual port mode, The digital I information drives one input port, while the digital Q information drives the other input port. If no interpolation filter precedes the DAC, the symbol rate will be the rate at which the system clock drives the CLK and WRT pins on the AD9709. In interleaved mode, the digital input stream at Port I contains the I and the Q information in alternating digital words. Using IQSEL and IQRESET, the AD9709 can be synchronized to the I and Q data stream. The internal timing of the AD9709 routes the selected I and Q data to the correct DAC output. In interleaved mode, if no interpolation filter precedes the AD9709, the symbol rate will be half that of the system clock driving the digital datastream and the IQWRT and IQCLK pins on the AD9709. Σ TO MIXER Figure 40. Typical Analog QAM Architecture A common and traditional implementation of a QAM modulator is shown in Figure 40. The modulation is performed in the analog domain in which two DACs are used to generate the baseband I and Q components. Each component is then typically applied to a Nyquist filter before being applied to a quadrature mixer. The matching Nyquist filters shape and limit each components spectral envelope while minimizing intersymbol interference. The DAC is typically updated at the QAM symbol rate or possibly a multiple of it if an interpolating filter precedes the DAC. The use of an interpolating filter typically eases the AVDD 0.1 F DCOM DVDD ACOM AVDD RL IOUTA LA CA IOUTB RL LA RL RB CB RB BBIN RL LOIP RA RA BBIP VPBF VOUT ROHDE & SCHWARZ FSEA30B SPECTRUM ANALYZER TEKTRONICS AWG2021 W/OPTION 4 IQWRT IQCLK PORT I “I” DAC LATCH “I” DAC D I G I T A L I N T E R F A C E AD9709 RL QOUTA RL LA CA QOUTB FSADJI FSADJQ REFIO RL LA RB CB RB CFILTER RL BBQN VDIFF = 1.82V p-p PHASE SPLITTER RA RA BBQP LOIN PORT Q IQSEL SLEEP MODE “Q” DAC LATCH “Q” DAC AD8346 ROHDE & SCHWARZ SIGNAL GENERATOR RSET 3.9k RSET 3.9k DIFFERENTIAL 0.1 F RLC FILTER AVDD NOTE: DACs Full-Scale OUTPUT CURRENT = IOUTFS RA, RB AND RL ARE THIN FILM RESISTOR NETWORKSWITH 0.1% MATCHING, 1% ACCURACY. AVAILABLE FROM OHMTEK ORNXXXXD SERIES. NOTE: RL = 200 RA = 2500 RB = 500 RP = 200 CA = 280pF CB = 45pF LA = 10 H IOUTFS = 11mA AVDD = 5.0V VCM = 1.2V AD976x 0 TO IOUTFS RL RB RA AD8346 VMOD VDAC Figure 41. Baseband QAM Implementation Using an AD9709 and AD8346 –16– REV. 0 AD9709 CDMA –30 –40 –50 –60 –70 Carrier Division Multiple Access, or CDMA, is an air transmit/ receive scheme where the signal in the transmit path is modulated with a pseudorandom digital code (sometimes referred to as the spreading code). The effect of this is to spread the transmitted signal across a wide spectrum. Similar to a DMT waveform, a CDMA waveform containing multiple subscribers can be characterized as having a high peak to average ratio (i.e., crest factor), thus demanding highly linear components in the transmit signal path. The bandwidth of the spectrum is defined by the CDMA standard being used, and in operation is implemented by using a spreading code with particular characteristics. Distortion in the transmit path can lead to power being transmitted out of the defined band. The ratio of power transmitted in-band to out-of-band is often referred to as Adjacent Channel Power (ACP). This is a regulatory issue due to the possibility of interference with other signals being transmitted by air. Regulatory bodies define a spectral mask outside of the transmit band, and the ACP must fall under this mask. If distortion in the transmit path causes the ACP to be above the spectral mask, then filtering, or different component selection is needed to meet the mask requirements. Figure 42 shows the AD9709/AD8346 application circuit of Figure 41 reconstructing a wideband, or W-CDMA test vector with a bandwith of 8 MHz, centered at 2.4 GHz and being sampled at 62.5 MHz. The IF frequency at the DAC output is 15.625 MHz. ACPR for the given test vector is measured at greater than 54 dB. dBm –80 –90 –100 –110 c11 –120 –130 CENTER 2.4GHz 1 c11 C2 cu1 C0 cu1 3MHz FREQUENCY SPAN 30MHz Figure 42. CDMA Signal, 8 M Chips Sampled at 65 MSPS, Recreated at 2.4 GHz, Adjacent Channel Power > 54 dBm Figure 43 shows an example of the AD9709 used in a W-CDMA transmitter application using the AD6122 CDMA 3 V IF subsystem. The AD6122 has functions, such as external gain control and low-distortion characteristics, needed for the superior Adjacent Channel Power (ACP) requirements of W-CDMA. DVDD CLK1 RSET1 2k AVDD 3V 634 AD9709 (“I DAC”) FSADJ1 U1 DAC DAC LATCH IOUTA 500 500 500 500 IIPP IIPN AD6122 I DATA INPUT WRT1 WRT2 Q DATA INPUT RSET2 1.9k INPUT LATCHES IOUTB 50 50 LOIPP LOIPN IIQP IIQN MODOPN 2 PHASE SPLITTER 500 INPUT LATCHES 500 U2 DAC DAC LATCH QOUTA 500 500 MODOPP FSADJ2 RCAL 220 QOUTB SLEEP CLK2 ACOM DCOM (“Q DAC”) REFIO 50 50 TEMPERATURE COMPENSATION REFIN GAIN CONTROL VGAIN GAIN CONTROL SCALE FACTOR VCC VCC 0.1 F TXOPP TXOPN Figure 43. CDMA Transmit Application Using AD9709 and AD6122 REV. 0 –17– AD9709 EVALUATION BOARD General Description The AD9709-EB is an evaluation board for the AD9709 8-bit dual D/A converter. Careful attention to layout and circuit design, combined with a prototyping area, allow the user to easily and effectively evaluate the AD9709 in any application where high resolution, high speed conversion is required. This board allows the user flexibility to operate the AD9709 in various configurations. Possible output configurations include transformer coupled, resistor terminated, and single and differential outputs. The digital inputs can be used in dual port or interleaved mode, and are designed to be driven from various word generators, with the on-board option to add a resistor network for proper load termination. When operating the AD9709, best performance is obtained when running the Digital Supply (DVDD) at 3 V and the Analog Supply (AVDD) at 5 V. POWER DECOUPLING AND INPUT CLOCKS B1 DVDDIN BAN-JACK B2 BAN-JACK RED TP10 L1 BEAD DVDD C9 BLK 10 F TP37 2 25V 1 B3 AVDDIN BLK TP39 RED TP11 L2 BEAD 1 DVDD AVDD C10 10 F BLK TP40 BLK TP41 BLK TP42 1 C7 2 0.1 F 1 C8 2 0.01 F BLK TP38 BAN-JACK B4 BAN-JACK 2 25V TP43 BLK DGND TP44 BLK AGND JP9 DCLKIN1 WHT TP29 DGND;3,4,5 1 2 3 AB DCLKIN2 DVDD 1 JP6 2 3 AB WRT1IN S1 IQWRT JP16 JP2 4 10 5 11 13 CLK1IN S2 IQCLK WHT TP30 DGND;3,4,5 1 JP5 A2B I C 3 PRE J PRE J JP1 3 1 2 U1 Q U2 Q Q 9 CLK K CLR 15 DVDD Q 6 CLK K CLR 14 12 7 CLK2IN S3 RESET WHT TP31 DGND;3,4,5 1 JP4 A2B I C TSSOP112 TSSOP112 3 DGND;8 DVDD;16 3 DGND;8 DVDD;16 DVDD AB 1 2 WRT2IN S4 IQSEL WHT TP32 DGND;3,4,5 1 2 1 2 1 2 1 2 1 JP3 A2B I C JP7 3 /2 CLOCK DIVIDER WRT1 CLK1 CLK2 WRT2 SLEEP R1 50 R2 50 R3 50 R4 50 WHT TP33 SLEEP 1 2 R13 50 RP16 RCOM 1 RP9 RCOM 1 R1 22 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 R8 22 9 R9 22 10 R1 22 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 R8 22 9 R9 22 10 INP1 INP2 INP3 INP4 INP5 INP6 INP7 INP8 RP10 INP9 INP10 INP11 INP12 INP13 INP14 INCK1 RP15 RCOM 1 R1 22 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 R8 22 9 R9 22 10 RCOM 1 R1 22 2 R2 22 3 R3 22 4 R4 22 5 R5 22 6 R6 22 7 R7 22 8 R8 22 9 R9 22 10 INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30 INP31 INP32 INP33 INP34 INP35 INP36 INCK2 Figure 44. Power Decoupling and Clocks on AD9709 Evaluation Board –18– REV. 0 AD9709 DIGITAL INPUT SIGNAL CONDITIONING RP3 RCOM R1 22 1 2 3 4 5 6 7 8 9 10 1 R9 RP1 RCOM R1 22 2 3 4 5 6 7 8 9 10 R9 RP13 RCOM R1 33 1 2 3 4 5 6 7 8 9 10 R9 RP11 RCOM R1 33 1 2 3 4 5 6 7 8 9 10 R9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 P1 1 3 5 7 9 INP1 INP2 INP3 INP4 INP5 INP6 INP7 INP8 INP9 INP10 INP11 INP12 INP13 INP14 RP5, 10 1 16 DVDD RP5, 10 2 15 DVDD DUTP1 DUTP2 DUTP3 DUTP4 DUTP5 DUTP6 DUTP7 DUTP8 DUTP9 DUTP10 DUTP11 DUTP12 DUTP13 DUTP14 RP5, 10 3 14 RP5, 10 4 13 RP5, 10 5 12 RP5, 10 6 11 P1 11 P1 13 P1 15 P1 17 P1 19 P1 21 P1 23 P1 25 P1 27 RP5, 10 7 10 RP5, 10 8 9 RP6, 10 1 16 RP6, 10 2 15 RP6, 10 3 14 RP6, 10 4 13 RP6, 10 5 12 RP6, 10 6 11 P1 29 P1 31 P1 33 P1 35 P1 37 P1 39 INCK1 RP6, 10 8 9 DCLKIN1 RP4 RCOM R1 22 1 2 3 4 5 6 7 8 9 10 R9 RP2 RCOM R1 22 1 2 3 4 5 6 7 8 9 10 R9 RP14 RCOM R1 33 1 2 3 4 5 6 7 8 9 10 R9 RP12 RCOM R1 33 1 2 3 4 5 6 7 8 9 10 R9 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 P2 1 3 5 7 9 INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30 INP31 INP32 INP33 INP34 INP35 INP36 RP7, 10 1 16 DVDD RP7, 10 2 15 DVDD DUTP23 DUTP24 DUTP25 DUTP26 DUTP27 DUTP28 DUTP29 DUTP30 DUTP31 DUTP32 DUTP33 DUTP34 DUTP35 DUTP36 RP7, 10 3 14 RP7, 10 4 13 RP7, 10 5 12 RP7, 10 6 11 P2 11 P2 13 P2 15 P2 17 P2 19 P2 21 P2 23 P2 25 P2 27 RP7, 10 7 10 RP7, 10 8 9 RP8, 10 1 16 RP8, 10 2 15 RP8, 10 3 14 RP8, 10 4 13 RP8, 10 5 12 RP8, 10 6 11 P2 29 P2 31 P2 33 P2 35 P2 37 P2 39 INCK2 RP8, 10 8 9 DCLKIN2 SPARES RP5, 10 7 10 RP8, 10 7 10 Figure 45. Digital Input Signal Conditioning REV. 0 –19– AD9709 DUT AND ANALOG OUTPUT SIGNAL CONDITIONING BL1 TP34 WHT DVDD 1 ACOM JP15 1 2 3 3 NC = 5 1:1 4 AGND;3,4,5 6 C1 2 VAL 1 C2 2 0.01 F 1 C3 2 0.1 F S6 OUT1 AVDD AB R11 VAL 2 1 MODE JP8 DVDD DUTP1 DUTP2 DUTP3 DUTP4 DUTP5 DUTP6 DUTP7 DUTP8 DUTP9 DUTP10 DUTP11 DUTP12 DUTP13 DUTP14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 1 2 T1 BL2 R5 50 C5 2 10pF 1 1 2 AB DB13P1MSB DB12P1 DB11P1 DB10P1 DB9P1 DB8P1 DB7P1 DB6P1 DB5P1 DB4P1 DB3P1 DB2P1 DB1P1 DB0P1 DCOM1 DVDD1 WRT1 CLK1 CLK2 WRT2 DCOM2 DVDD2 DB13P2MSB DB12P2 MODE 48 AVDD 47 IA1 46 IB1 45 FSADJ1 44 REFIO 43 GAINCTRL 42 FSADJ2 41 IA2 40 R6 50 C4 2 10pF 1 TP45 WHT R9 1.92k 1 2 C16 22nF 1 2 R15 256 1 2 REFIO TP36 WHT 1 2 C17 22nF 1 2 R14 256 1 2 C14 0.1 F R10 1.92k C15 2 10pF 1 1 2 JP10 2 U2 IB2 39 ACOM 38 SLEEP 37 DB0P2 36 DB1P2 35 DB2P2 34 DB3P2 33 DB4P2 32 DB5P2 31 DB6P2 30 DB7P2 29 DB8P2 28 DB9P2 27 DB10P2 26 DB11P2 25 SLEEP DUTP36 DUTP35 DUTP34 DUTP33 DUTP32 DUTP31 DUTP30 DUTP29 DUTP28 DUTP27 DUTP26 DUTP25 AVDD 1 C6 2 10pF 1 R7 50 1 2 1 R8 50 WHT TP46 BL3 TP35 WHT 3 NC = 5 1:1 4 AGND;3,4,5 6 S11 OUT2 WRT1 CLK1 CLK2 WRT2 17 18 19 20 21 22 R12 VAL 2 1 T2 BL4 DUTP23 DUTP24 23 24 C11 21 F 1 C12 2 0.01 F 1 C13 2 0.1 F Figure 46. AD9709 and Output Signal Conditioning –20– REV. 0 AD9709 Figure 47. Assembly, Top Side REV. 0 –21– AD9709 Figure 48. Assembly, Bottom Side –22– REV. 0 AD9709 Figure 49. Layer 1, Top Side REV. 0 –23– AD9709 Figure 50. Layer 2, Ground Plane –24– REV. 0 AD9709 Figure 51. Layer 3, Power Plane REV. 0 –25– AD9709 Figure 52. Layer 4, Bottom Side –26– REV. 0 AD9709 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead Thin Plastic Quad Flatpack (LQFP) (ST-48) 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 1 0.354 (9.00) BSC SQ 48 37 36 TOP VIEW (PINS DOWN) 0.276 (7.00) BSC SQ 25 COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09) 0 MIN 12 13 24 0.019 (0.5) BSC 7 0 0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) SEATING 0.002 (0.05) PLANE REV. 0 –27– PRINTED IN U.S.A. C3701–8–5/00 (rev. 0) 00606