AD9712BAN

a 12-Bit, 100 MSPS D/A Converters AD9712B/AD9713B FUNCTIONAL BLOCK DIAGRAM FEATURES 100 MSPS Update Rate ECL/TTL Compatibility SFDR @ 1 MHz: 70 dBc Low Glitch Impulse: 28 pV-s Fast Settling: 27 ns Low Power: 725 mW 1/2 LSB DNL (B Grade) 40 MHz Multiplying Bandwidth AD9712B/AD9713B LATCH 26 ENABLE DIGITAL INPUTS D1 OBS APPLICATIONS ATE Signal Reconstruction Arbitrary Waveform Generators Digital Synthesizers Signal Generators GENERAL DESCRIPTION (MSB) 1 TRANSPARENT LATCHES 28 DECODERS AND DRIVERS THRU D12 OLE The AD9712B and AD9713B D/A converters are replacements for the AD9712 and AD9713 units which offer improved ac and dc performance. Like their predecessors, they are 12-bit, high speed digital-to-analog converters fabricated in an advanced oxide isolated bipolar process. The AD9712B is an ECLcompatible device featuring update rates of 100 MSPS minimum; the TTL-compatible AD9713B will update at 80 MSPS minimum. 11 (LSB) 20 REFERENCE OUT SWITCH NETWORK 16 I OUT 17 REFERENCE IN + R SET 24 INTERNAL VOLTAGE REFERENCE 14 I OUT CONTROL AMP CONTROL AMP OUT TE – 18 19 CONTROL AMP IN Designed for direct digital synthesis, waveform reconstruction, and high resolution imaging applications, both devices feature low glitch impulse of 28 pV-s and fast settling times of 27 ns. Both units are characterized for dynamic performance and have excellent harmonic suppression. The AD9712B and AD9713B are available in 28-pin plastic DIPs and PLCCs, with an operating temperature range of –25°C to +85°C. Both are also available for extended temperature ranges of –55°C to +125°C in cerdips and 28-pin LCC packages. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 AD9712B/AD9713B–SPECIFICATIONS ELECTRICAL CHARACTERISTICS Parameter (Conditions) Temp Test Level [–VS = –5.2 V; +VS = +5 V (AD9713B only); Reference Voltage = –1.2 V; RSET = 7.5 kV; VOUT = 0 V (virtual ground); unless otherwise noted] AD9712B/AD9713B AN/AP Min Typ Max RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity (“Best Fit” Straight Line) AD9712B/AD9713B BN/BP Min Typ Max 12 +25°C Full +25°C Full I VI I VI –1.25 –2.0 –1.5 –2.0 OBS Parameter (Conditions) INITIAL OFFSET ERROR Zero-Scale Offset Error Full-Scale Gain Error1 Offset Drift Coefficient REFERENCE/CONTROL AMP Internal Reference Voltage 1.0 1.0 Temp Test Level +25°C Full +25°C Full +25°C I VI I VI V REFERENCE INPUT2 Reference Input Impedance Reference Multiplying Bandwidth3 +25°C +25°C DYNAMIC PERFORMANCE Full-Scale Output Current4 Output Compliance Range Output Resistance Output Capacitance Output Update Rate5 Output Settling Time (tST)6 Output Propagation Delay (tPD)7 Glitch Impulse8 Output Rise Time9 Output Fall Time9 +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C V IV IV V IV V V V V V Full Full Full Full +25°C +25°C Full +25°C Full +25°C Full VI VI VI VI V IV IV IV IV IV +25°C +25°C +25°C +25°C V V V V Input Hold Time (tH)11 Latch Pulse Width (tLPW) (LOW) (Transparent) AC LINEARITY12 Spurious-Free Dynamic Range (SFDR) 1.23 MHz; 10 MSPS; 2 MHz Span 5.055 MHz; 20 MSPS; 2 MHz Span 10.1 MHz; 50 MSPS; 2 MHz Span 16 MHz; 40 MSPS; 10 MHz Span 12 +1.25 2.0 1.5 2.0 –0.75 –1.5 –1.0 –1.75 Min 0.5 0.75 AD9712B All Grades Typ 0.5 12 +0.75 1.5 1.0 1.75 –1.5 1.0 –2.0 –1.75 1.5 –2.0 Max 12 +1.5 2.0 1.75 2.0 I VI V IV V V 1.0 2.5 5.0 5 8 –1.18 –1.22 –1.24 –1.14 –1.12 +500 –50 50 –50 50 300 V V 3 40 20.48 –1.2 2.0 100 –1.0 2.5 15 110 27 6 28 2 2 –0.8 –1.7 3 –0.3 0.5 0.8 1.8 2.0 2.5 2.8 1.2 1.7 70 72 68 68 –2– –1.2 2.0 80 +1.0 1.5 1.25 1.75 LSB LSB LSB LSB 2.5 5.0 5 8 µA µA % % µA/°C –1.22 –1.24 50 300 V V ppm/°C µA kΩ kHz 3 40 kΩ MHz 1.0 0.01 –1.18 TE 50 +500 2.5 15 100 27 7 28 2 2 +2 3.0 2.0 –1.5 20 10 0.8 20 600 0.5 0.8 1.8 2.0 2.5 2.8 Bits Units 20.48 +2 3.0 Units Max 0.5 0.01 –1.14 –1.12 –1.0 0.5 –1.5 –1.25 1.0 –1.75 AD9713B All Grades Min Typ OLE Internal Reference Voltage Drift Internal Reference Output Current Amplifier Input Impedance Amplifier Bandwidth +25°C Full Full Full +25°C +25°C DIGITAL INPUTS Logic “1” Voltage Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance Input Setup Time (tS)10 AD9712B/AD9713B AD9712B/AD9713B SE/SQ TE/TQ Min Typ Max Min Typ Max 3 –0.3 1.2 1.7 70 72 68 68 mA V kΩ pF MSPS ns ns pV-s ns ns V V µA µA pF ns ns ns ns ns ns dB dB dB dB REV. B AD9712B/AD9713B Parameter (Conditions) Temp Test Level +25°C Full +25°C Full +25°C +25°C I VI I VI V I Min AD9712B All Grades Typ Max AD9713B All Grades Min Typ Max Units 12 14 184 188 mA mA mA mA mW µA/V 13 POWER SUPPLY Positive Supply Current (+5.0 V) Negative Supply Current (–5.2 V)14 Nominal Power Dissipation Power Supply Rejection Radio (PSRR)15 6 140 728 30 178 183 145 784 30 100 100 NOTES 1 Measured as error in ratio of full-scale current to current through R SET (160 µA nominal); ratio is nominally 128. 2 Full-scale variations among devices are higher when driving REFERENCE INPUT directly. 3 Frequency at which the gain is flat ± 0.5 dB; R L = 50 Ω; 50% modulation at midscale. 4 Based on IFS = 128 (VREF/RSET) when using internal amplifier. 5 Data registered into DAC accurately at this rate; does not imply settling to 12-bit accuracy. 6 Measured as voltage settling at midscale transition to ± 0.024%, RL = 50 Ω. 7 Measured as the time between the 50% point of the falling edge of LATCH ENABLE and the point where the output signal has left a 1 LSB error band around its previous value. 8 Peak glitch impulse is measured as the largest area under a single positive or negative transient. 9 Measured with R L = 50 Ω and DAC operating in latched mode. 10 Data must remain stable for specified time prior to falling edge of LATCH ENABLE signal. 11 Data must remain stable for specified time after rising edge of LATCH ENABLE signal. 12 SFDR is defined as the difference in signal energy between the fundamental and worst case spurious frequencies in the output spectrum window, which is centered at the fundamental frequency and covers the indicated span. 13 Supply voltages should remain stable within ± 5% for normal operation. 14 108 mA typ on Digital –V S, 37 mA typ on Analog –V S. 15 Measured at ± 5% of +VS (AD9713B only) and –V S (AD9712B or AD9713B) using external reference. Specifications subject to change without notice. OBS ABSOLUTE MAXIMUM RATINGS 1 OLE NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances with parts soldered in place: 28-pin plastic DIP: θJA = 37°C/W, θJC = 10°C/W; 28-pin PLCC: θJA = 44°C/W, θJC = 14°C/W; Cerdip: θJA = 32°C/W, θJC = 10°C/W; LCC: θJA = 41°C/W, θJC = 13°C/W. No air flow. Model Temperature Range Package Description Package Option AD9712BAN AD9712BBN AD9712BAP AD9712BBP AD9712BSQ/883B AD9712BSE/883B AD9712BTQ/883B AD9712BTE/883B –25°C to +85°C –25°C to +85°C –25°C to +85°C –25°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C 28-Pin PDIP 28-Pin PDIP 28-Pin PLCC 28-Pin PLCC 28-Pin Cerdip 28-Pin LCC 28-Pin Cerdip 28-Pin LCC N-28 N-28 P-28A P-28A Q-28 E-28A Q-28 E-28A AD9713BAN AD9713BBN AD9713BAP AD9713BBP AD9713BSQ/883B AD9713BSE/883B AD9713BTQ/883B AD9713BTE/883B –25°C to +85°C –25°C to +85°C –25°C to +85°C –25°C to +85°C –55°C to +125°C –55°C to +125°C –55°C to +125°C –55°C to +125°C 28-Pin PDIP 28-Pin PDIP 28-Pin PLCC 28-Pin PLCC 28-Pin Cerdip 28-Pin LCC 28-Pin Cerdip 28-Pin LCC N-28 N-28 P-28A P-28A Q-28 E-28A Q-28 E-28A EXPLANATION OF TEST LEVELS Test Level I – II – III – IV – V – VI – REV. B TE ORDERING GUIDE Positive Supply Voltage (+VS) (AD9713B Only) . . . . . . . +6 V Negative Supply Voltage (–VS) . . . . . . . . . . . . . . . . . . . . . –7 V Analog-to-Digital Ground Voltage Differential . . . . . . . . 0.5 V Digital Input Voltages (D1–D12, LATCH ENABLE) AD9712B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to –VS AD9713B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +VS Internal Reference Output Current . . . . . . . . . . . . . . . . 500 µA Control Amplifier Input Voltage Range . . . . . . . . . 0 V to –4 V Control Amplifier Output Current . . . . . . . . . . . . . . . ± 2.5 mA Reference Input Voltage Range (VREF) . . . . . . . . . . . 0 V to –VS Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Operating Temperature Range AD9712B/AD9713BAN/AP/BN/BP . . . . . . . –25°C to +85°C AD9712B/AD9713BSE/SQ/TE/TQ . . . . . . –55°C to +125°C Maximum Junction Temperature2 AD9712B/AD9713BAN/AP/BN/BP . . . . . . . . . . . . . +150°C AD9712B/AD9713BSE/SQ/TE/TQ . . . . . . . . . . . . . +175°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C –3– 100% production tested. 100% production tested at +25°C, and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. All devices are 100% tested at +25°C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. AD9712B/AD9713B PIN DESCRIPTIONS Pin # Name Function 1–10 11 D2–D11 D12 (LSB) Ten bits of twelve-bit digital input word. Least Significant Bit (LSB) of digital input word. Input Coding vs. Current Output Input Code D1–D12 IOUT (mA) IOUT (mA) 1111111111 0000000000 DIGITAL –VS ANALOG RETURN 0 –20.475 One of two negative digital supply pins; nominally –5.2 V. Analog ground return. This point and the reference side of the DAC load resistors should be connected to the same potential (nominally ground). Analog current output; full-scale output occurs with digital inputs at all “1.” One of two negative analog supply pins; nominally –5.2 V. Complementary analog current output; zero scale output occurs with digital inputs at all “1.” Normally connected to CONTROL AMP OUT (Pin 18). Direct line to DAC current source network. Voltage changes at this point have a direct effect on the full-scale output value of unit. Full-scale current output = 128 (Reference voltage/RSET) when using internal amplifier. Normally connected to REFERENCE INPUT (Pin 17). Output of internal control amplifier, which provides a temperature-compensated drive level to the current switch network. Normally connected to REFERENCE OUT (Pin 20) if not connected to external reference. Normally connected to CONTROL AMP IN (Pin 19). Internal voltage reference, nominally –1.18 V. One of two negative digital supply pins; nominally –5.2 V. Ground return for the internal voltage reference and amplifier. Positive digital supply pin, used only on the AD9713B; nominally +5 V. No connection to this pin on AD9712B. Connection for external resistance reference. Full-scale current out = 128 (Reference voltage/ RSET) when using internal amplifier. Nominally 7.5 kΩ. One of two negative analog supply pins; nominally –5.2 V. Transparent latch control line. Register is transparent when LATCH ENABLE is LOW. Digital ground return. Most Significant Bit (MSB) of digital input word. OBS 14 15 16 17 IOUT ANALOG –VS IOUT REFERENCE IN 18 CONTROL AMP OUT 19 20 CONTROL AMP IN REFERENCE OUT 21 22 23 DIGITAL –VS REFERENCE GROUND DIGITAL +VS 24 RSET 25 26 27 28 ANALOG –VS LATCH ENABLE DIGITAL GROUND D1 (MSB) OLE TE PIN CONFIGURATIONS 28 D1 (MSB0) D3 2 27 DIGITAL GROUND D3 D2 D4 3 26 LATCH ENABLE 4 3 2 1 D5 4 25 ANALOG –VS D6 5 24 RSET D7 6 D8 7 25 ANALOG –VS D7 24 R SET D8 7 D9 8 9 DIGITAL –VS D10 9 20 REFERENCE OUT D11 10 10 19 CONTROL AMP IN D12 (LSB) 11 D12 (LSB) 11 18 CONTROL AMP OUT DIGITAL –VS 12 17 REFERENCE IN ANALOG RETURN 13 16 I OUT 14 15 ANALOG –VS 21 DIGITAL –VS REFERENCE 20 OUT 19 CONTROL AMP IN 12 –4– REFERENCE 22 GROUND TOP VIEW (Not to Scale) DIGITAL –V S IOUT 23 DIGITAL +VS 13 14 15 16 17 18 CONTROL AMP OUT 21 AD9712B AD9713B REFERENCE IN D11 REFERENCE GROUND 5 6 I OUT D10 22 DIGITAL +VS 26 D6 ANALOG –VS 8 TOP VIEW (Not to Scale) 23 28 27 ANALOG RETURN D9 AD9712B AD9713B D1 (MSB) 1 DIGITAL GROUND LATCH ENABLE D2 D4 PLCC/LCC D5 DIP I OUT 12 13 –20.475 0 REV. B AD9712B/AD9713B DIE LAYOUT AND METALIZATION INFORMATION Digital Inputs/Timing Die Dimensions . . . . . . . . . . . . . . . . . 220 × 196 × 15 (± 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride The AD9712B employs single-ended ECL-compatible inputs for data inputs D1–D12 and LATCH ENABLE. The internal ECL midpoint reference is designed to match 10K ECL device thresholds. On the AD9713B, a TTL translator is added at each input; with this exception, the AD9712B and AD9713B are identical. In the Decoder/Driver section, the four MSBs (D1–D4) are decoded to 15 “thermometer code” lines. An equalizing delay is included for the eight Least Significant Bits (LSBs) and LATCH ENABLE. This delay minimizes data skew, and data setup and hold times at the latch inputs; this is important when operating the latches in the transparent mode. Without the delay, skew caused by the decoding circuits would degrade glitch impulse. OBS The latches operate in their transparent mode when LATCH ENABLE (Pin 26) is at logic level “0.” The latches should be used to synchronize data to the current switches by applying a narrow LATCH ENABLE pulse with proper data setup and hold times as shown in the Timing Diagram. An external latch at each data input, clocked out of phase with the Latch Enable, operates the AD9712B/AD9713B in a master slave (edgetriggered) mode. This is the optimum way to operate the DAC because data is always stable at the DAC input. An external latch eases timing constraints when using the converter. OLE TE Although the AD9712B/AD9713B chip is designed to provide isolation from digital inputs to the outputs, some coupling of digital transitions is inevitable, especially with TTL or CMOS inputs applied to the AD9713B. Digital feedthrough can be reduced by forming a low-pass filter using a (200 Ω) series resistor in series with the capacitance of each digital input; this rolls off the slew rate of the digital inputs. THEORY AND APPLICATIONS The AD9712B and AD9713B high speed digital-to-analog converters utilize Most Significant Bit (MSB) decoding and segmentation techniques to reduce glitch impulse and maintain 12-bit linearity without trimming. References As shown in the functional block diagram, the internal bandgap reference, control amplifier, and reference input are pinned out for maximum user flexibility when setting the reference. As shown in the functional block diagram, the design is based on four main subsections: the Decoder/Driver circuits, the Transparent Latches, the Switch Network, and the Control Amplifier. An internal bandgap reference is also included to allow operation with a minimum of external components. When using the internal reference, REFERENCE OUT (Pin 20) should be connected to CONTROL AMP IN (Pin 19). CONTROL AMP OUT (Pin 18) should be connected to REFERENCE IN (Pin 17) through a 20 Ω resistor. A 0.1 µF ceramic capacitor from Pin 17 to –VS (Pin 15) improves settling by decoupling switching noise from the current sink base line. A reference current cell provides feedback to the control amp by sinking current through RSET (Pin 24). t LPW LATCH ENABLE LATCH ENABLE tS ERROR BAND tH OUTPUT ERROR VALID DATA DATA INPUTS t PD OUTPUT t PD t LPW – LATCH PULSE WIDTH t S – INPUT SETUP TIME Timing Diagram REV. B –5– t H – INPUT HOLD TIME t ST – OUTPUT SETTLING TIME t PD – OUTPUT PROPAGATION DELAY t ST AD9712B/AD9713B Full-scale output current is determined by CONTROL AMP IN and RSET according to the equation: The REFERENCE IN pin can also be driven directly for wider bandwidth multiplying operation. The analog signal for this mode of operation must have a signal swing in the range of –3.75 V to –4.25 V. This can be implemented by capacitively coupling into REFERENCE IN a signal with a dc bias of –3.75 V to –4.25 V, as shown in Figure 3; or by driving REFERENCE IN with a low impedance op amp whose signal swing is limited to the stated range. IOUT (FS) = (CONTROL AMP IN/RSET) × 128 The internal reference is nominally –1.18 V with a tolerance of ± 3.5% and typical drift over temperature of 50 ppm/°C. If greater accuracy or better temperature stability is required, an external reference can be utilized. The AD589 reference shown in Figure 1 features ± 10 ppm/°C drift over temperatures from 0°C to +70°C. Outputs As indicated earlier, D1–D4 (four MSBs) are decoded and drive 15 discrete current sinks. D5 and D6 are binarily weighted; and D7–D12 are applied to the R-2R network. This segmented architecture reduces frequency domain errors due to glitch impulse. AD9712B AD9713B + OBS AD589 – 19 AD9712B AD9713B CONTROL AMP IN R1 ~ –11k REFERENCE IN OLE –VS 17 ~– –4V Figure 1. Use of AD589 as External Reference –V S Two modes of multiplying operation are possible with the AD9712B/AD9713B. Signals with small signal bandwidths up to 300 kHz and input swings of 100 mV, or dc signals from –0.6 V to –1.2 V can be applied to the CONTROL AMP input as shown in Figure 2. Because the control amplifier is internally compensated, the 0.1 µF capacitor at Pin 17 can be reduced to 0.01 µF to maximize the multiplying bandwidth. However, it should be noted that settling time for changes to the digital inputs will be degraded. Figure 3. Wideband Multiplying Circuit The Switch Network provides complementary current outputs IOUT and IOUT. These current outputs are based on statistical current source matching which provides 12-bit linearity without trim. Current is steered to either IOUT or IOUT in proportion to the digital input code. The sum of the two currents is always equal to the full-scale output current minus one LSB. The current output can be converted to a voltage by resistive loading as shown in Figure 4. Both IOUT and IOUT should be loaded equally for best overall performance. The voltage which is developed is the product of the output current and the value of the load resistor. RSET 24 R SET –0.6V TO –1.2V 300 kHz MAX 19 TE –VS CONTROL AMP IN AD9712B AD9713B RT 18 CONTROL AMP OUT 18 17 REFERENCE IN Figure 2. Low Frequency Multiplying Circuit –6– REV. B AD9712B/AD9713B 0.1µF DAC current across feedback resistor RFB determines the AD9617 output swing. A current divider formed by RL and RFF limits the current used in the I-to-V conversion, and provides an output voltage swing within the specifications of the AD9617. Current through R2 provides dc offset at the output of the AD9617. Adjusting the value of R1 adjusts the value of offset current. This offset current is based on the reference of the AD9712B/AD9713B, to avoid coupling noise into the output signal. 0.01µF –5.2V 0.01µF 0.1µF 12,21 28 15,25 DIGITAL –VS ANALOG –VS D 1 (MSB) REFERENCE IN 17 CONTROL AMP OUT 18 REFERENCE OUT 20 CONTROL AMP IN 19 1 D2 2 D3 3 D4 4 D5 0.1µF The resistor values in Figure 5 provide a 4.096 V swing, centered at ground, at the output of the AD9617 amplifier. 20Ω Maintaining low noise on power supplies and ground is critical for obtaining optimum results with the AD9712B or AD9713B. DACs are most often used in circuits which are predominantly digital. To preserve 12-bit performance, especially at conversion speeds up to 100 MSPS, special precautions are necessary for power supplies and grounding. OBS ECL DRIVE LOGIC 5 D6 6 D7 7 D8 R SET 24 8 D9 I OUT 16 9 D10 10 D11 11 D12 (LSB) AD9712B AD9713B 26 LATCH ENABLE I OUT 14 ANALOG REFERENCE DIGITAL RETURN GROUND GROUND 22 13 27 SYSTEM GROUND Power and Grounding OLE Ideally, the DAC should have a separate analog ground plane. All ground pins of the DAC, as well as reference and analog output components, should be tied directly to this analog ground plane. The DAC’s ground plane should be connected to the system ground plane at a single point. RL VOUT = RL TE IFS x RL Ferrite beads such as the Stackpole 57-1392 or Amidon FB-43B-101, along with high frequency, low-inductance decoupling capacitors, should be used for the supply connections to isolate digital switching currents from the DAC supply pins. Separate isolation networks for the digital and analog supply connections will further reduce supply noise coupling to the output. Figure 4. Typical Resistive Load Connection Molded socket assemblies should be avoided even when prototyping circuits with the AD9712B or AD9713B. When the DAC cannot be directly soldered into the board, individual pin sockets such as AMP #6-330808-0 (knock-out end), or #60330808-3 (open end) should be used. These have much less effect on inter-lead capacitance than do molded assemblies. An operational amplifier can also be used to perform the I to V conversion of the DAC output. Figure 5 shows an example of a circuit which uses the AD9617, a high speed, current feedback amplifier. DDS Applications 10k + Numerically controlled oscillators (NCOs) are digital devices which generate samples of a sine wave. When the NCO is combined with a high performance D/A converter (DAC), the combination system is referred to as a Direct Digital Synthesizer (DDS). 10k – 1/2 AD708 – 200 1/2 AD708 + 20 19 REF OUT CONTROL AMP IN R1 100 R2 400 25 RFF I FS R FB – I OUT 14 AD9712B AD9713B The digital samples generated by the NCO are reconstructed by the DAC and the resulting sine wave is usable in any system which requires a stable, spectrally pure, frequency-agile reference. The DAC is often the limiting factor in DDS applications, since it is the only analog function in the circuit. The AD9712B/ AD9713B D/A converters offer the highest level of performance available for DDS applications. I OS 25 RL V OUT ±2.048V AD9617 + DC linearity errors of a DAC are the dominant effect in lowfrequency applications and can affect both noise and harmonic content in the output waveform. Differential Nonlinearity (DNL) errors determine the quantization error between adjacent codes, while Integral Nonlinearity (INL) is a measure of how closely the overall transfer function of the DAC compares with an ideal device. Together, these errors establish the limits of phase and amplitude accuracy in the output waveform. 12.5 I OUT 16 Figure 5. I/VConversion Using Current Feedback REV. B –7– AD9712B/AD9713B SYSTEM CLOCK NUMERICALLY-CONTROLLED OSCILLATOR D1 TUNING WORD 32 PHASE ACCUMULATOR 14 OUTPUT PHASE-TO-AMPLITUDE CONVERSION TTL REGISTER 12 SINE DATA LATCH ENABLE AD9712B AD9713B 12 D 12 D/A CONVERTER Figure 6. Direct Digital Synthesizer Block Diagram OBS When the analog frequency (fA) is exactly fC/N and N is an even integer, the DDS continually uses a small subset of the available DAC codes. The DNL of the converter is effectively the DNL error of the codes used, and is typically worse than the error measured against all available DAC codes. This increase in DNL is translated into higher harmonic and noise levels at the output. 100 90 OLE 5mV/div Glitch impulse, often considered a figure of merit in DDS applications, is simply the initial transient response of the DAC as it moves between two output levels. This nonlinearity is commonly associated with external data skew, but this effect is minimized by using the on-board registers of the AD9712B/AD9713B converters (see Digital Inputs/Timing section). The majority of the glitch impulse, shown below, is produced as the current in the R-2R ladder network settles, and is fairly constant over the full-scale range of the DAC. The fast transients which form the glitch impulse appear as high-frequency spurs in the output spectrum. 10 0% TE 5ns/div Figure 7. AD9712B/AD9713B Glitch Impulse 200mV/div 100 90 While it is difficult to predict the effects of glitch on the output waveform, slew rate limitations translate directly into harmonics. This makes slew rate the dominant effect in ac linearity of the DAC. Applications in which the ratio of analog frequency (fA) to clock frequency (fC) is relatively high will benefit from the high slew rate and low output capacitance of the AD9712B/ AD9713B devices. 10 0% Another concern in DDS applications is the presence of aliased harmonics in the output spectrum. Aliased harmonics appear as spurs in the output spectrum at frequencies which are determined by: 1ns/div Figure 8. Rise and Fall Characteristics MfA ± NfC where M and N are integers. The effects of these spurs are most easily observed in applications where fA is nearly equal to an integer fraction of the clock rate. This condition causes the aliased harmonics to fold near the fundamental output frequency (see Performance Curves.) –8– REV. B AD9712B/AD9713B OBS Figure 9a. Figure 9d. OLE TE Figure 9b. Figure 9e. Figure 9c. Figure 9f. Figure 9. Typical Spectral Performance REV. B –9– AD9712B/AD9713B OBS Figure 10c. Figure 10a. OLE TE Figure 10d. Figure 10b. Figure 10e. Figure 10. Typical Spectral Performance –10– REV. B AD9712B/AD9713B +5V 10 kΩ CONTROL 19 AMP IN TTL IN ECL V MID ECL IN –5.2 V –5.2 V ECL Input Buffer TTL Input Buffer OBS Control Amplifier Input ± 24 R SET REFERENCE 20 OUT + CONTROL AMP CONTROL 19 AMP IN – OLE VBIAS 18 17 CONTROL AMP OUT REFERENCE IN –5.2 V Full-Scale Current Control Loop R 2R 2R R R 2R 2R R ANALOG RETURN 14 I OUT 2R R R 13 R 18 CONTROL AMP OUT –5.2 V TE Control Amp Output 138 CURRENT SOURCES REFERENCE 17 IN or 16 D12 D11 D10 D9 D7 D8 I OUT D1 – D 6 –5.2 V Reference Input R-2R DAC (for 6 LSBs) 2.5kΩ I OUT I OUT ANALOG RETURN 14 16 13 16pF 16pF 2.5kΩ 20 REFERENCE OUT –5.2 V –VS Reference Output Output Circuit Figure 11. Equivalent Circuits REV. B –11– AD9712B/AD9713B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Pin Plastic DIP (Suffix N) 4 0.060 (1.52) 0.015 (0.38) 0.250 (6.35) MAX 0.140 (3.56) MIN 11 0.70 (1.77) MAX 0.100 (2.54) BSC 28-Pin Cerdip (Suffix Q) 1.490 (37.84) MAX 15 28 0.610 (15.49) 0.500 (12.70) 1 14 GLASS SEALANT 19 12 0.125 (3.175) MIN 0.021 (0.53) 0.013 (0.33) 0.032 (0.81) 0.026 (0.66) 0.025 (0.63) 0.040 (1.01) 0.015 (0.38) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) 0.180 (4.57) 0.165 (4.19) 0.495 (12.57) 0.485 (12.32) OLE 28-Pin LCC Package (Suffix E) 0.055 (1.40) 0.045 (1.14) 26 27 28 1 25 24 0.018 (0.45) 0.008 (0.20) 15 0 TE 2 3 4 5 21 20 0.028 (0.71) 0.022 (0.56) 6 7 BOTTOM VIEW 22 0.075 (1.91) REF 8 0.050 (1.27) 9 10 19 11 18 17 16 15 14 13 12 0.458 (11.63) 0.442 (11.23) 0.100 (2.54) 0.064 (1.63) PRINTED IN U.S.A. 0.07 (1.78) 0.03 (0.76) 0.430 (10.92) 0.390 (9.91) 18 23 0.026 (0.660) 0.110 (2.79) 0.014 (0.356) 0.098 (2.45) 0.050 (1.27) BSC 0.456 (11.58) 0.450 (11.43) 0.620 (15.74) 0.590 (14.93) 0.22 (5.59) MAX 25 0.015 (0.381) 0.008 (0.204) OBS 0.022 (0.558) 0.014 (0.356) 26 PIN 1 IDENTIFIER 0.048 (1.21) 0.042 (1.07) 1.565 (39.70) 1.380 (35.10) 5 0.625 (15.8) 0.600 (15.24) 0.495 (12.57) 0.485 (12.32) 14 0.456 (11.58) 0.450 (11.43) 0.550 (13.97) 0.530 (13.46) 1 0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07) 15 28 C1635–24–3/92 28-Pin Plastic Leaded Chip Carrier (Suffix P) –12– REV. B