AD9739BBC

14-Bit, 2.5 GSPS, RF Digital-to-Analog Converter AD9739 Data Sheet FUNCTIONAL BLOCK DIAGRAM RESET AD9739 SYNC_OUT SYNC_IN I120 4-TO-1 DATA ASSEMBLER CLK DISTRIBUTION (DIV-BY-4) SYNCCONTROLLER TxDAC CORE IOUTP IOUTN DACCLK 07851-001 Broadband communications systems Military jammers Instrumentation, automatic test equipment Radar, avionics VREF DLL (MU CONTROLLER) DCO 1.2V DAC BIAS LVDS DDR RECEIVER DB1[13:0] APPLICATIONS SPI DATA CONTROLLER DB0[13:0] SDIO SDO CS SCLK DCI IRQ LVDS DDR RECEIVER Direct RF synthesis at 2.5 GSPS update rate DC to 1.25 GHz in baseband mode 1.25 GHz to 3.0 GHz in mix mode Industry leading single/multicarrier IF or RF synthesis fOUT = 350 MHz, ACLR =80 dBc fOUT = 950 MHz, ACLR = 78 dBc fOUT = 2100 MHz, ACLR = 69 dBc Dual-port LVDS data interface Up to 1.25 GSPS operation Source synchronous DDR clocking Pin-compatible with the AD9739A Multichip synchronization capability Programmable output current: 8.7 mA to 31.7 mA Low power: 1.16 W at 2.5 GSPS DATA LATCH FEATURES Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD9739 is a 14-bit, 2.5 GSPS high performance RF digitalto-analog converter (DAC) capable of synthesizing wideband signals from dc up to 3.0 GHz. Its DAC core features a quadswitch architecture that provides exceptionally low distortion performance with an industry-leading direct RF synthesis capability. This feature enables multicarrier generation up to the Nyquist frequency in baseband mode as well as second and third Nyquist zones in mix mode. The output current can be programmed over the 8.66 mA to 31.66 mA range. 1. The inclusion of on-chip controllers simplifies system integration. A dual-port, source synchronous, LVDS interface simplifies the digital interface with existing FGPA/ASIC technology. On-chip controllers are used to manage external and internal clock domain variations over temperature to ensure reliable data transfer from the host to the DAC core. Multichip synchronization is possible with an on-chip synchronization controller. A serial peripheral interface (SPI) is used for device configuration as well as readback of status registers. 2. 3. 4. 5. 6. Ability to synthesize high quality wideband signals with bandwidths of up to 1.25 GHz in the first or second Nyquist zone. A proprietary quad-switch DAC architecture provides exceptional ac linearity performance while enabling mix mode operation. A dual-port, double data rate, LVDS interface supports the maximum conversion rate of 2500 MSPS. On-chip controllers manage external and internal clock domain skews. A multichip synchronization capability. Programmable differential current output with an 8.66 mA to 31.66 mA range. The AD9739 is manufactured on a 0.18 μm CMOS process and operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-ball chip scale ball grid array for reduced package parasitics. Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9739 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DCI Phase Alignment Status .................................................... 25 Applications ....................................................................................... 1 SYNC_IN Phase Alignment Status .......................................... 25 General Description ......................................................................... 1 Data Receiver Controller Configuration ................................. 25 Functional Block Diagram .............................................................. 1 Data Receiver Controller_Data Sample Delay Value ............ 26 Product Highlights ........................................................................... 1 Data and Sync Receiver Controller_DCI Delay Value/Window and Phase Rotation ......................................... 26 Revision History ............................................................................... 3 Specifications..................................................................................... 5 DC Specifications ......................................................................... 5 LVDS Digital Specifications ........................................................ 6 Serial Port Specifications ............................................................. 7 AC Specifications.......................................................................... 8 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution .................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 13 AC (Normal Mode) .................................................................... 13 AC (Mix Mode) .......................................................................... 16 Terminology .................................................................................... 19 Serial Port Interface (SPI) Register............................................... 20 SPI Register Map Description ................................................... 20 SPI Operation.............................................................................. 20 SPI Register Map ............................................................................. 22 SPI Port Configuration and Software Reset............................ 24 Power-Down LVDS Interface and TxDAC® ............................ 24 Controller Clock Disable ........................................................... 24 Interrupt Request (IRQ) Enable/Status ................................... 24 TxDAC Full-Scale Current Setting (IOUTFS) and Sleep ........... 25 Data Receiver Controller_Delay Line Status and Sync Controller SYNC_OUT Status ................................................. 26 Sync and Data Receiver Controller Lock/Tracking Status .... 27 CLK Input Common Mode ...................................................... 27 Microcontroller Configuration and Status ............................. 27 Part ID.......................................................................................... 28 Theory of Operation ...................................................................... 29 LVDS Data Port Interface .......................................................... 30 Microcontroller .......................................................................... 34 Interrupt Requests ...................................................................... 36 Multiple Device Synchronization ............................................. 37 Analog Interface Considerations.................................................. 40 Analog Modes of Operation ..................................................... 40 Clock Input Considerations ...................................................... 41 Voltage Reference ....................................................................... 42 Analog Outputs .......................................................................... 42 Nonideal Spectral Artifacts ....................................................... 45 Lab Evaluation of the AD9739 ................................................. 46 Power Dissipation and Supply Domains ................................. 46 Recommended Start-Up Sequence .......................................... 47 Outline Dimensions ....................................................................... 50 Ordering Guide .......................................................................... 50 TxDAC Quad-Switch Mode of Operation .............................. 25 Rev. E | Page 2 of 50 Data Sheet AD9739 REVISION HISTORY 6/2018—Rev. D to Rev. E Changes to Table 7 ..........................................................................11 Data Receiver Operation at Lower Clock Rates Section ............32 5/2017—Rev. C to Rev. D Changes to Table 32 ........................................................................48 2/2015—Rev. B to Rev. C Moved Revision History ................................................................... 3 Changes to Figure 6.........................................................................11 Changes to Table 19 ........................................................................25 Changes to Theory of Operation Section ....................................28 Changes to Figure 52 ......................................................................36 Changes to Clock Input Considerations Section ........................40 Deleted Figure 60 ............................................................................40 Changes to Table 32 ........................................................................48 1/2012—Rev. A to Rev. B Changes to Features Section, Applications Section, General Description Section, Figure 1, Product Highlights Section......... 1 Changes to DC Specifications Section ........................................... 4 Changed Digital Specifications Section to LVDS Digital Specifications Section ....................................................................... 5 Changes to LVDS Digital Specifications Section .......................... 5 Added Serial Port Specifications Section and Table 3; Renumbered Sequentially ................................................................ 6 Changes to AC Specifications Section ............................................ 7 Changes to Table 5 ............................................................................ 8 Changes to Table 7 ..........................................................................10 Deleted Static Linearity Section and Figure 7 to Figure 17; Renumbered Sequentially ..............................................................11 Changed Dynamic Performance Normal Mode, 20 mA Full Scale (Unless Otherwise Noted) Section to AC (Normal Mode) Section ..............................................................................................12 Changes to AC (Normal Mode) Section ......................................12 Changed Dynamic Performance Mix Mode, 20 mA Full Scale Section to AC (Mix Mode) Section...............................................15 Changes to AC (Mix Mode) Section.............................................15 Added Serial Port Interface (SPI) Register Section, SPI Register Map Description Section, Reset Section, Table 8, and SPI Operation Section and Figure 34 ..................................................18 Deleted DOCSIS Performance Section and Figure 46 to Figure 72 and added Figure 35 through Figure 38; Renumbered Sequentially ................................................................................................. 19 Changes to SPI Register Map Section and Table 9......................20 Added SPI Port Configuration and Software Reset Section, Power-Down LVDS Interface and TxDAC® Section, Controller Clock Disable Section, Interrupt Request (IRQ) Enable/Status Section, and Table 10 to Table 13 ..................................................22 Added TxDAC Full-Scale Current Setting (IOUTFS) and Sleep Section, TxDAC Quad-Switch Mode of Operation Section, DCI Phase Alignment Status Section, SYNC_IN Phase Alignment Status Section, Data Receiver Controller Configuration Section, and Table 14 to Table 18 .................................................................23 Added Data Receiver Controller_Data Sample Delay Value Section, Data and Sync Receiver Controller_DCI Delay Value/Window and Phase Rotation Section, Data Receiver Controller_Delay Line Status and Sync Controller SYNC_OUT Status Section, and Table 19 to Table 21 ...................................... 24 Deleted Serial Peripheral Interface Section, General Operation of the Serial Interface Section, Instruction Mode (8-Bit Instruction) Section, and Serial Interface Port Pin Description Section ....... 25 Added Sync and Data Receiver Controller Lock/Tracking Status Section, CLK Input Common Mode Section, Mu Controller Configuration and Status Section, and Table 22 to Table 24 ..... 25 Deleted MSB/LSB Transfers Section, Serial Port Configuration Section, and Figure 74 to Figure 79 .............................................. 26 Added Part ID Section and Table 25 ............................................ 26 Changes to Theory of Operation Section .................................... 27 Added Figure 39 .............................................................................. 27 Deleted SPI Registers Section and Table 8 to Table 31............... 28 Moved and Changes to LVDS Data Port Interface Section ....... 28 Added Figure 40 and Figure 41 ..................................................... 28 Changes to Figure 42 ...................................................................... 29 Moved and Changes to Figure 43 ................................................. 29 Added Data Receiver Controller Initialization Description Section, Table 26, and Data Receiver Operation at Lower Clock Rates Section .................................................................................... 30 Added LVDS Driver and Receiver Input Section, Figure 44 to Figure 47, and Table 27................................................................... 31 Changed and Moved Mu Delay Controller Section to Mu Controller Section ........................................................................... 32 Changes to Mu Controller Section, Figure 48, and Figure 49... 32 Added Figure 50 and Table 28 ....................................................... 32 Added Mu Controller Initialization Description Section .......... 33 Changes to Interrupt Requests Section ........................................ 34 Added Table 29 ................................................................................ 34 Changed Synchronization Controller Section to Multiple Device Synchronization Section ................................................... 35 Added Figure 52 .............................................................................. 35 Changes to Figure 53 ...................................................................... 36 Added Sync Controller Initialization Description Section ....... 36 Added Synchronization Limitations Section............................... 37 Changed Applications Information to Analog Interface Considerations Section................................................................... 38 Changes to Analog Modes of Operation Section ....................... 38 Deleted Clocking the AD9739 Section, Figure 85, and Figure 86 ..39 Added Clock Input Considerations Section, Figure 58 to Figure 60 ........................................................................................... 39 Deleted Clock Phase Noise Affects on AC Performance Section, Table 32 to Table 34, Applying Data to the AD9739 Section, and Figure 87 ........................................................................................... 40 Moved Figure 61 .............................................................................. 40 Changes to Voltage References Section and Analog Outputs Section .............................................................................................. 40 Added Equivalent DAC Output and Transfer Function and Figure 63 ........................................................................................... 40 Rev. E | Page 3 of 50 AD9739 Data Sheet Deleted Mu Control Operation Section, Search Mode Section, and Figure 89 ................................................................................... 41 Moved Figure 64 ............................................................................. 41 Added Peak DAC Output Power Capability Section and Figure 65..41 Deleted Figure 90, Figure 91, Track Mode Section, Mu Delay and Phase Readback Section, Operating the Mu Controller Manually Section, and Calculating Mu Delay Line Step Size Section .............................................................................................. 42 Added Output Stage Configuration Section and Figure 66 to Figure 70 .......................................................................................... 42 Added Nonideal Spectral Artifacts Section, Figure 71, and Table 30 ............................................................................................ 43 Deleted Operation in Master Mode, Figure 93, and Figure 94 ....... 44 Added Lab Evaluation of the AD9739 Section, Power Dissipation and Supply Domains Section, and Figure 72 to Figure 74 ........ 44 Deleted Figure 95, Operation in Slave Mode Section, and Data Receiver Operation in Auto Mode Section ................................. 45 Changes to Recommended Start-Up Sequence Section ............ 45 Added Figure 75.............................................................................. 45 Deleted Figure 97, Data Receiver Operation in Manual Mode Section, Calculating the DCI Delay Line Step Size Section, and Maximum Allowable Data Timing Skew/Jitter Section ............ 46 Added Table 31 ............................................................................... 46 Deleted Optimizing the Clock Common-Mode Voltage Section, Figure 99, Analog Control Registers Section, Mirror Roll-Off Frequency Control Section, and Figure 101 ............................... 47 Added Table 32 ............................................................................... 47 Deleted Figure 103, Figure 104, and Figure 106......................... 48 Updated Outline Dimensions ....................................................... 48 Deleted Figure 107 to Figure 109 ................................................. 49 Deleted Table 35 to Table 44 ......................................................... 50 7/2011—Rev 0 to Rev A Changes to Table 2, DAC CLOCK INPUT (DACCLK_P, DACCLK_N), Added DAC Clock Rate..........................................4 Changes to Table 3, Added Dynamic Performance Parameters .......5 Change to Ordering Guide............................................................ 53 2/2009—Revision 0: Initial Version Rev. E | Page 4 of 50 Data Sheet AD9739 SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. Table 1. Parameter RESOLUTION ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) ANALOG OUTPUTS Gain Error (with Internal Reference) Full-Scale Output Current Output Compliance Range Common-Mode Output Resistance Differential Output Resistance Output Capacitance DAC CLOCK INPUT (DACCLK_P, DACCLK_N) Differential Peak-to-Peak Voltage Common-Mode Voltage DAC Clock Rate TEMPERATURE DRIFT Gain Reference Voltage REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES VDDA VDDC DIGITAL SUPPLY VOLTAGES VDD33 VDD SUPPLY CURRENTS AND POWER DISSIPATION, 2.0 GSPS IVDDA IVDDC IVDD33 IVDD Power Dissipation Sleep Mode, IVDDA Power-Down Mode (Register 0x01 = 0x33 and Register 0x02 = 0x80) IVDDA IVDDC IVDD33 IVDD SUPPLY CURRENTS AND POWER DISSIPATION, 2.5 GSPS IVDDA IVDDC IVDD33 IVDD Power Dissipation Rev. E | Page 5 of 50 Min Typ 14 Max ±1.3 ±0.8 8.66 −1.0 5.5 20.2 LSB LSB 31.66 +1.0 10 70 1 1.2 1.6 900 0.8 Unit Bits 2.0 2.5 60 20 % mA V MΩ Ω pF V mV GHz ppm/°C ppm/°C 1.15 1.2 5 1.25 V kΩ 3.1 1.70 3.3 1.8 3.5 1.90 V V 3.10 1.70 3.3 1.8 3.5 1.90 V V 37 159 34 233 0.940 2.5 38 166 37 238 0.975 2.75 mA mA mA mA W mA 0.02 3.8 0.5 0.1 mA mA mA mA 37 223 34 290 1.16 mA mA mA mA W AD9739 Data Sheet LVDS DIGITAL SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA. LVDS drivers and receivers are compliant to the IEEE Standard 1596.31996 reduced range link, unless otherwise noted. Table 2. Parameter LVDS DATA INPUTS (DB0[13:0], DB1[13:0]) 1 Input Common-Mode Voltage Range, VCOM Logic High Differential Input Threshold, VIH_DTH Logic Low Differential Input Threshold, VIL_DTH Receiver Differential Input Impedance, RIN Input Capacitance LVDS Input Rate LVDS Minimum Data Valid Period, tVALID (See Figure 41) LVDS CLOCK INPUT (DCI and SYNC_IN) 2 Input Common-Mode Voltage Range, VCOM Logic High Differential Input Threshold, VIH_DTH Logic Low Differential Input Threshold, VIL_DTH Receiver Differential Input Impedance, RIN Input Capacitance Maximum Clock Rate LVDS CLOCK OUTPUT (DCO and SYNC_OUT) 3 Output Voltage High (x_P or x_N) Output Voltage Low (x_P or x_N) Output Differential Voltage, |VOD| Output Offset Voltage, VOS Output Impedance, Single-Ended, RO RO Single-Ended Mismatch Maximum Clock Rate 1 2 3 Min Typ 825 175 −175 80 400 −400 Max Unit 1575 mV mV mV Ω pF MSPS ps 120 1.2 1250 344 825 175 −175 80 1575 400 −400 120 1.2 625 1375 1025 150 1150 80 625 DB0[x]P, DB0[x]N, DB1[x]P, and DB1[x]N pins. DCI_P and DCI_N pins, as well as SYNC_IN_P and SYNC_IN_N pins. DCO_P and DCO_N pins, as well as SYNC_OUT_P/SYNC_OUT_N pins with 100 Ω differential termination. Rev. E | Page 6 of 50 200 100 250 1250 120 10 mV mV mV Ω pF MHz mV mV mV mV Ω % MHz Data Sheet AD9739 SERIAL PORT SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V. Table 3. Parameter WRITE OPERATION (See Figure 36) SCLK Clock Rate, fSCLK (or /tSCLK) SCLK Clock High, tHI SCLK Clock Low, tLOW SDIO to SCLK Setup Time, tDS SCLK to SDIO Hold Time, tDH CS to SCLK Setup Time, tS SCLK to CS Hold Time, tH Min Typ Max Unit 20 MHz ns ns ns ns ns ns 20 MHz ns ns ns ns ns ns ns 18 18 2 1 3 2 READ OPERATION (See Figure 37 and Figure 38) SCLK Clock Rate, fSCLK (or /tSCLK) SCLK Clock High, tHI SCLK Clock Low, tLOW SDIO to SCLK Setup Time, tDS SCLK to SDIO Hold Time, tDH CS to SCLK Setup Time, tS SCLK to SDIO (or SDO) Data Valid Time, tDV CS to SDIO (or SDO) Output Valid to High-Z, tEZ 18 18 2 1 3 15 2 INPUTS (SDIO, SCLK, CS) Voltage in High, VIH Voltage in Low, VIL Current in High, IIH Current in Low, IIL OUTPUT (SDIO) Voltage Out High, VOH Voltage Out Low, VOL Current Out High, IOH Current Out Low, IOL 2.0 3.3 0 −10 −10 0.8 +10 +10 2.4 0 3.5 0.4 4 4 Rev. E | Page 7 of 50 V V µA µA V V mA mA AD9739 Data Sheet AC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, IOUTFS = 20 mA, fDAC = 2400 MSPS. Table 4. Parameter DYNAMIC PERFORMANCE DAC Clock Rate Adjusted DAC Update Rate 1 Output Settling Time (tst) to 0.1% SPURIOUS-FREE DYNAMIC RANGE (SFDR) fOUT = 100 MHz fOUT = 350 MHz fOUT = 550 MHz fOUT = 950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), fOUT2 = fOUT1 + 1.25 MHz fOUT = 100 MHz fOUT = 350 MHz fOUT = 550 MHz fOUT = 950 MHz NOISE SPECTRAL DENSITY (NSD), 0 dBFS SINGLE TONE fOUT = 100 MHz fOUT = 350 MHz fOUT = 550 MHz fOUT = 850 MHz WCDMA ACLR (SINGLE CARRIER), ADJACENT/ALTERNATE ADJACENT CHANNEL fDAC = 2457.6 MSPS fOUT = 350 MHz fDAC = 2457.6 MSPS, fOUT = 950 MHz fDAC = 2457.6 MSPS, fOUT = 1700 MHz (Mix Mode) fDAC = 2457.6 MSPS, fOUT = 2100 MHz (Mix Mode) 1 Min Typ Max Unit 2500 2500 13 MSPS MSPS ns 69.5 58.5 54 60 dBc dBc dBc dBc 94 78 72 68 dBc dBc dBc dBc −166 −161 −160 −160 dBm/Hz dBm/Hz dBm/Hz dBm/Hz 80/80 78/79 74/74 69/72 dBc dBc dBc dBc 800 800 Adjusted DAC updated rate is calculated as fDAC divided by the minimum required interpolation factor. For the AD9739, the minimum interpolation factor is 1. Thus, with fDAC = 2500 MSPS, fDAC adjusted = 2500 MSPS. Rev. E | Page 8 of 50 Data Sheet AD9739 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter VDDA VDD33 VDD VDDC VSSA VSSA VSS DACCLK_P, DACCLK_N DCI, DCO, SYNC_IN, SYNC_OUT LVDS Data Inputs IOUTP, IOUTN I120, VREF IRQ, CS, SCLK, SDO, SDIO, RESET Junction Temperature Storage Temperature With Respect To VSSA VSS VSS VSSC VSS VSSC VSSC VSSC VSS Rating −0.3 V to +3.6 V −0.3 V to +3.6 V −0.3 V to +1.98 V −0.3 V to +1.98 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to VDDC + 0.18 V −0.3 V to VDD33 + 0.3 V VSS VSSA VSSA VSS −0.3 V to VDD33 + 0.3 V −1.0 V to VDDA + 0.3 V −0.3 V to VDDA + 0.3 V −0.3 V to VDD33 + 0.3 V θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type 160-Ball CSP_BGA 1 With no airflow movement. ESD CAUTION 150°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. E | Page 9 of 50 θJA 31.2 θJC 7.0 Unit °C/W1 AD9739 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 2 3 4 5 6 7 8 9 10 11 12 13 14 1 A A B B C C D D E E F F G G H H J J K K L L M M N N P P VDDA, 3.3V, ANALOG SUPPLY 07851-002 VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD 3 4 5 6 7 8 4 5 6 7 8 9 10 11 12 13 14 VSSC, CLOCK SUPPLY GROUND Figure 4. Digital LVDS Clock Supply Pins (Top View) Figure 2. Analog Supply Pins (Top View) 2 3 VDDC, 1.8V, CLOCK SUPPLY VSSA, ANALOG SUPPLY GROUND 1 2 07851-004 1 1 9 10 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 A A B B DACCLK_N C C DACCLK_P D D E E F F G G H H SYNC_OUT_P/_N J J SYNC_IN_P/_N K K DCO_P/_N DCI_P/_N DB1[0:13]P L L DB0[0:13]P N N DB0[0:13]N P P DIFFERENTIAL INPUT SIGNAL (CLOCK OR DATA) VSS DIGITAL SUPPLY GROUND VDD33, 3.3V DIGITAL SUPPLY 07851-003 VDD, 1.8V, DIGITAL SUPPLY Figure 5. Digital LVDS Input, Clock I/O (Top View) Figure 3. Digital Supply Pins (Top View) Rev. E | Page 10 of 50 07851-005 DB1[0:13]N M M 1 2 3 4 5 6 IOUTP AD9739 IOUTN Data Sheet 7 8 9 10 11 12 13 14 A B I120 C VREF D E F IRQ G AD9739 H RESET CS SDIO SCLK SDO J K L M 07851-006 N P Figure 6. Analog I/O and SPI Control Pins (Top View) Table 7. AD9739 Pin Function Descriptions Pin No. C1, C2, D1, D2, E1, E2, E3, E4 A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, C5, D4, D5 A10, A11, B10, B11, C10, C11, D10, D11 A12, A13, B12, B13, C12, C13, D12, D13, A6, A9, B6, B9, C6, C9, D6, D9, F1, F2, F3, F4, E11, E12, E13, E14, F11, F12 A14 A7, B7, C7, D7 A8, B8, C8, D8 B14 Mnemonic VDDC VSSC Description 1.8 V Clock Supply Input. Clock Supply Return. VDDA VSSA VSSA Shield 3.3 V Analog Supply Input. Analog Supply Return. Analog Supply Return Shield. Tie to VSSA at the DAC. NC IOUTN IOUTP I120 C14 VREF D14 C3, D3 F13 NC DACCLK_N/DACCLK_P IRQ F14 G13 G14 H13 H14 J3, J4, J11, J12 G1, G2, G3, G4, G11, G12 H1, H2, H3, H4, H11, H12, K3, K4, K11, K12 J1, J2 K1, K2 J13, J14 K13, K14 L1, M1 L2, M2 L3, M3 RESET CS SDIO SCLK SDO VDD33 VDD VSS SYNC_OUT_P/SYNC_OUT_N SYNC_IN_P/SYNC_IN_N DCO_P/DCO_N DCI_P/DCI_N DB1[0]P/DB1[0]N DB1[1]P/DB1[1]N DB1[2]P/DB1[2]N No Connect. Do not connect to this pin. DAC Negative Current Output Source. DAC Positive Current Output Source. Nominal 1.2 V Reference. Tie to analog ground via a 10 kΩ resistor to generate a 120 µA reference current. Voltage Reference Input/Output. Decouple to VSSA with a 1 nF capacitor. Factory Test Pin. Do not connect to this pin. Negative/Positive DAC Clock Input (DACCLK). Interrupt Request Open Drain Output. Active high. Pull up to VDD33 with a 10 kΩ resistor. Reset Input. Active high. Tie to VSS if unused. Serial Port Enable Input. Serial Port Data Input/Output. Serial Port Clock Input. Serial Port Data Output. 3.3 V Digital Supply Input. 1.8 V Digital Supply. Input. Digital Supply Return. Positive/Negative SYNC Output (SYNC_OUT) Positive/Negative SYNC Input (SYNC_IN) Positive/Negative Data Clock Output (DCO). Positive/Negative Data Clock Input (DCI). Port 1 Positive/Negative Data Input Bit 0, LSB. Port 1 Positive/Negative Data Input Bit 1. Port 1 Positive/Negative Data Input Bit 2. Rev. E | Page 11 of 50 AD9739 Pin No. L4, M4 L5, M5 L6, M6 L7, M7 L8, M8 L9, M9 L10, M10 L11, M11 L12, M12 L13, M13 L14, M14 N1, P1 N2, P2 N3, P3 N4, P4 N5, P5 N6, P6 N7, P7 N8, P8 N9, P9 N10, P10 N11, P11 N12, P12 N13, P13 N14, P14 Data Sheet Mnemonic DB1[3]P/DB1[3]N DB1[4]P/DB1[4]N DB1[5]P/DB1[5]N DB1[6]P/DB1[6]N DB1[7]P/DB1[7]N DB1[8]P/DB1[8]N DB1[9]P/DB1[9]N DB1[10]P/DB1[10]N DB1[11]P/DB1[11]N DB1[12]P/DB1[12]N DB1[13]P/DB1[13]N DB0[0]P/DB0[0]N DB0[1]P/DB0[1]N DB0[2]P/DB0[2]N DB0[3]P/DB0[3]N DB0[4]P/DB0[4]N DB0[5]P/DB0[5]N DB0[6]P/DB0[6]N DB0[7]P/DB0[7]N DB0[8]P/DB0[8]N DB0[9]P/DB0[9]N DB0[10]P/DB0[10]N DB0[11]P/DB0[11]N DB0[12]P/DB0[12]N DB0[13]P/DB0[13]N Description Port 1 Positive/Negative Data Input Bit 3. Port 1 Positive/Negative Data Input Bit 4. Port 1 Positive/Negative Data Input Bit 5. Port 1 Positive/Negative Data Input Bit 6. Port 1 Positive/Negative Data Input Bit 7. Port 1 Positive/Negative Data Input Bit 8. Port 1 Positive/Negative Data Input Bit 9. Port 1 Positive/Negative Data Input Bit 10. Port 1 Positive/Negative Data Input Bit 11. Port 1 Positive/Negative Data Input Bit 12. Port 1 Positive/Negative Data Input Bit 13, MSB. Port 0 Positive/Negative Data Input Bit 0, LSB. Port 0 Positive/Negative Data Input Bit 1. Port 0 Positive/Negative Data Input Bit 2. Port 0 Positive/Negative Data Input Bit 3. Port 0 Positive/Negative Data Input Bit 4. Port 0 Positive/Negative Data Input Bit 5. Port 0 Positive/Negative Data Input Bit 6. Port 0 Positive/Negative Data Input Bit 7. Port 0 Positive/Negative Data Input Bit 8. Port 0 Positive/Negative Data Input Bit 9. Port 0 Positive/Negative Data Input Bit 10. Port 0 Positive/Negative Data Input Bit 11. Port 0 Positive/Negative Data Input Bit 12. Port 0 Positive/Negative Data Input Bit 13, MSB. Rev. E | Page 12 of 50 Data Sheet AD9739 TYPICAL PERFORMANCE CHARACTERISTICS AC (NORMAL MODE) STOP 2.4GHz VBW 10kHz START 20MHz Figure 7. Single-Tone Spectrum at fOUT = 91 MHz, fDAC = 2.4 GSPS 80 1.2GSPS 75 Figure 10. Single-Tone Spectrum at fOUT = 1091 MHz, fDAC = 2.4 GSPS 100 95 1.6GSPS 2.0GSPS 85 80 65 75 60 IMD (dBc) 2.4GSPS 55 2.0GSPS 50 1.6GSPS 70 65 2.4GSPS 60 55 45 50 45 40 40 35 100 200 300 400 500 600 700 800 900 1000 1100 1200 fOUT (MHz) 30 07851-008 0 0 fOUT (MHz) Figure 11. IMD vs. fOUT over fDAC –160 –152 –161 –154 –162 –156 –163 NSD (dBm/Hz) –150 2.4GSPS –160 –162 –164 –164 –165 –166 –168 –168 –169 –170 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 fOUT (MHz) 2.4GSPS –166 –167 1.2GSPS 07851-009 NSD (dBm/Hz) Figure 8. SFDR vs. fOUT over fDAC –158 100 200 300 400 500 600 700 800 900 1000 1100 1200 07851-011 35 Figure 9. Single-Tone NSD over fOUT –170 1.2GSPS 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 fOUT (MHz) Figure 12. Eight-Tone NSD over fOUT Rev. E | Page 13 of 50 07851-012 SFDR (dBc) 1.2GSPS 90 70 30 STOP 2.4GHz VBW 10kHz 07851-010 START 20MHz 07851-007 10dB/DIV 10dB/DIV IOUTFS = 20 mA, nominal supplies, 25°C, unless otherwise noted. AD9739 Data Sheet fDAC = 2 GSPS, IOUTFS = 20 mA, nominal supplies, 25°C, unless otherwise noted. 110 90 100 80 –6dBFS –6dBFS 80 IMD (dBc) SFDR (dBc) 90 –3dBFS 70 60 0dBFS 50 70 –3dBFS 60 0dBFS 50 40 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 30 0 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 07851-016 0 07851-013 30 40 Figure 16. IMD vs. fOUT over Digital Full Scale Figure 13. SFDR vs. fOUT over Digital Full Scale 90 90 –6dBFS 80 –6dBFS 80 –3dBFS 70 0dBFS –3dBFS 50 50 40 40 30 0 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 30 0dBFS 0 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) Figure 17. SFDR for Third Harmonic over fOUT vs. Digital Full Scale Figure 14. SFDR for Second Harmonic over fOUT vs. Digital Full Scale 110 90 100 80 IMD (dBc) 80 60 20mA FS 50 20mA FS 90 30mA FS 10mA FS 70 70 10mA FS 60 30mA FS 50 40 0 100 200 300 400 500 600 700 800 fOUT (MHz) 900 1000 30 0 100 200 300 400 500 600 700 800 fOUT (MHz) Figure 18. IMD vs. fOUT over DAC IOUTFS Figure 15. SFDR vs. fOUT over DAC IOUTFS Rev. E | Page 14 of 50 900 1000 07851-018 30 40 07851-015 SFDR (dBc) 60 07851-017 SFDR (dB) 60 07851-014 SFDR (dB) 70 Data Sheet AD9739 110 90 100 80 90 +85°C –40°C 60 +25°C 50 +85°C 80 IMD (dBc) SFDR (dBc) 70 70 +25°C 60 –40°C 50 40 0 100 200 300 400 500 600 700 800 900 1000 fOUT (MHz) 30 07851-019 0 100 400 500 600 700 800 900 1000 900 1000 Figure 22. IMD vs. fOUT over Temperature –150 –150 –152 –152 –154 –154 –156 –156 NSD (dBm/Hz) –40°C –158 –160 –162 +85°C –164 –166 100 200 300 –162 –40°C +85°C –168 400 500 600 700 800 900 1000 fOUT (MHz) –170 07851-020 0 –160 –166 +25°C –168 –158 –164 +25°C 0 100 200 300 400 500 600 700 800 fOUT (MHz) Figure 20. Single-Tone NSD vs. fOUT over Temperature Figure 23. Eight-Tone NSD vs. fOUT over Temperature –50 –55 ACLR (dBc) –60 10dB/DIV –65 –70 FIRST ADJ CH –75 –80 CENTER 350.27MHz #RES BW 30kHz FREQ VBW 300kHz REF RMS RESULTS OFFSET BW CARRIER POWER (MHz) 5 –14.54dBm/ 10 3.84MHz 15 20 25 (MHz) 3.84 3.84 3.84 3.84 3.84 –90 SPAN 53.84MHz SWEEP 174.6ms (601pts) LOWER (dBc) (dBm) –79.90 –94.44 –80.60 –95.14 –80.90 –95.45 –80.62 –95.16 –80.76 –95.30 UPPER (dBc) (dBm) –79.03 –93.57 –79.36 –94.40 –80.73 –95.27 –80.97 –95.51 –80.95 –95.49 0 SECOND ADJ CH 491.52 737.28 983.04 1228.80 245.76 368.64 614.40 860.16 1105.90 122.88 fOUT (MHz) Figure 24. Four-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS Figure 21. Single-Carrier WCDMA at 350 MHz, fDAC = 2457.6 MSPS Rev. E | Page 15 of 50 07851-024 FIFTH ADJ CH –85 07851-021 NSD (dBm/Hz) 300 fOUT (MHz) Figure 19. SFDR vs. fOUT over Temperature –170 200 07851-023 30 07851-022 40 AD9739 Data Sheet AC (MIX MODE) VBW 10kHz STOP 2.4GHz SWEEP 28.7s (601pts) CENTER 2.10706MHz #RES VW 30kHz FREQ RMS RESULTS OFFSET CARRIER POWER (MHz) 5 –21.43dBm/ 10 3.84MHz 15 20 25 VBW 300kHz REF BW (MHz) 3.84 3.84 3.84 3.84 3.84 SPAN 53.84MHz SWEEP 174.6ms (601pts) LOWER (dBc) (dBm) –68.99 –90.43 –72.09 –93.52 –72.86 –94.30 –74.34 –95.77 –74.77 –96.20 UPPER (dBc) (dBm) –63.94 –90.37 –71.07 –92.50 –71.34 –92.77 –72.60 –94.03 –73.26 –94.70 07851-027 START 20MHz #RES BW 10kHz 07851-025 10dB/DIV 10dB/DIV fDAC = 2.4 GSPS, IOUTFS = 20 mA, nominal supplies, 25°C, unless otherwise noted. Figure 27. Typical Single-Carrier WCDMA ACLR Performance at 2.1 GHz, fDAC = 2457.6 MSPS (Second Nyquist Zone) Figure 25. Single-Tone Spectrum at fOUT = 2.31 GHz, fDAC = 2.4 GSPS 80 75 70 65 60 10dB/DIV 50 45 40 35 30 25 20 10 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 fOUT (MHz) Figure 26. SFDR in Mix Mode vs. fOUT at 2.4 GSPS START 20MHz #RES BW 10kHz VBW 10kHz STOP 2.4GHz SWEEP 28.7s (601pts) 07851-028 15 07851-026 SFDR (dBc) 55 Figure 28. Single-Tone Spectrum in Mix Mode at fOUT = 1.31 GHz, fDAC = 2.4 GSPS Rev. E | Page 16 of 50 Data Sheet AD9739 90 85 80 75 65 10dB/DIV IMD (dBc) 70 60 55 50 45 40 35 CENTER 2.807GHz #RES BW 30kHz FREQ VBW 300kHz REF RMS RESULTS OFFSET BW CARRIER POWER (MHz) 5 –24.4dBm/ 10 3.84MHz 15 20 25 (MHz) 3.84 3.84 3.84 3.84 3.84 SPAN 53.84MHz SWEEP 174.6ms (601pts) LOWER (dBc) (dBm) –64.90 –89.30 –66.27 –90.67 –68.44 –92.84 –70.20 –94.60 –70.85 –95.25 UPPER (dBc) (dBm) –63.82 –88.22 –65.70 –90.10 –66.55 –90.95 –68.95 –93.35 –70.45 –94.85 07851-031 fOUT (MHz) 07851-029 30 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 Figure 31. Typical Single-Carrier WCDMA ACLR Performance at 2.8 GHz, fDAC = 2457.6 MSPS (Third Nyquist Zone) Figure 29. IMD in Mix Mode vs. fOUT at 2.4 GSPS –40 –45 SECOND NYQUIST ZONE THIRD NYQUIST ZONE –50 –65 10dB/DIV –60 FIRST ADJ CH –70 SECOND ADJ CH –75 –80 FIFTH ADJ CH –85 fOUT (MHz) CENTER 2.09758GHz #RES BW 30kHz FREQ VBW 300kHz REF RMS RESULTS OFFSET BW CARRIER POWER (MHz) 5 –25.53dBm/ 10 3.84MHz 15 20 25 30 Figure 30. Single-Carrier WCDMA ACLR vs. fOUT at 2457.6 MSPS (MHz) 3.84 3.84 3.84 3.84 3.84 3.84 SPAN 63.84MHz SWEEP 207ms (601pts) LOWER (dBc) (dBm) 0.22 –25.31 –66.68 –92.21 –68.01 –93.53 –68.61 –94.14 –68.87 –94.40 –69.21 –94.74 UPPER (dBc) (dBm) 0.24 –25.29 0.14 –25.38 –66.82 –92.35 –67.83 –93.36 –67.64 –93.17 –68.50 –94.03 07851-032 –90 1229 1475 1720 1966 2212 2458 2703 2949 3195 3441 3686 07851-030 ACLR (dBc) –55 Figure 32. Typical Four-Carrier WCDMA ACLR Performance at 2.1 GHz, fDAC = 2457.6 MSPS (Second Nyquist Zone) Rev. E | Page 17 of 50 Data Sheet 10dB/DIV AD9739 FREQ VBW 300kHz REF RMS RESULTS OFFSET BW CARRIER POWER (MHz) 5 –27.98dBm/ 10 3.84MHz 15 20 25 30 (MHz) 3.84 3.84 3.84 3.84 3.84 3.84 SPAN 63.84MHz SWEEP 207ms (601pts) LOWER (dBc) (dBm) –0.42 –28.40 –64.32 –92.30 –66.03 –94.01 –66.27 –94.24 –66.82 –94.79 –67.16 –95.13 UPPER (dBc) (dBm) –0.10 –28.07 –0.08 –28.06 –65.37 –93.34 –66.06 –94.03 –63.36 –93.34 –66.54 –94.51 07851-033 CENTER 2.81271GHz #RES BW 30kHz Figure 33. Typical Four-Carrier WCDMA ACLR Performance at 2.8 GHz, fDAC = 2457.6 MSPS (Third Nyquist Zone) Rev. E | Page 18 of 50 Data Sheet AD9739 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) The maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from 0 to full scale. Power Supply Rejection (PSR) The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Differential Nonlinearity (DNL) The measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of 0 is called the offset error. For IOUTP, 0 mA output is expected when the inputs are all 0s. For IOUTN, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1 minus the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. Total Harmonic Distortion (THD) The ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Noise Spectral Density (NSD) NSD is the converter noise power per unit of bandwidth. This is usually specified in dBm/Hz in the presence of a 0 dBm full-scale signal. Adjacent Channel Leakage Ratio (ACLR) The adjacent channel leakage (power) ratio is a ratio, in dBc, of the measured power within a channel relative to its adjacent channels. Modulation Error Ratio (MER) Modulated signals create a discrete set of output values referred to as a constellation. Each symbol creates an output signal corresponding to one point on the constellation. MER is a measure of the discrepancy between the average output symbol magnitude and the rms error magnitude of the individual symbol. Intermodulation Distortion (IMD) IMD is the result of two or more signals at different frequencies mixing together. Many products are created according to the formula, aF1 ± bF2, where a and b are integer values. Rev. E | Page 19 of 50 AD9739 Data Sheet SERIAL PORT INTERFACE (SPI) REGISTER SPI REGISTER MAP DESCRIPTION SPI OPERATION The AD9739 contains a set of programmable registers described in Table 10 that are used to configure and monitor various internal parameters. Note the following points when programming the AD9739 SPI registers: The serial port of the AD9739 shown in Figure 34 has a 3- or 4-wire SPI capability, allowing read/write access to all registers that configure the device’s internal parameters. It provides a flexible, synchronous serial communications port, allowing easy interface to many industry-standard microcontrollers and microprocessors. The 3.3 V serial I/O is compatible with most synchronous transfer formats, including the Motorola® SPI and the Intel® SSR protocols. • • • • Registers pertaining to similar functions are grouped together and assigned adjacent addresses. Bits that are undefined within a register should be assigned a 0 when writing to that register. Registers that are undefined should not be written to. A hardware or software reset is recommended upon power-up to place SPI registers in a known state. A SPI initialization routine is required as part of the boot process. See Table 31 and Table 32 for example procedures. SDO (PIN H14) SDIO (PIN G14) AD9739 SPI PORT SCLK (PIN H13) 07851-034 • CS (PIN G13) Figure 34. AD9739 SPI Port Reset Issuing a hardware or software reset places the AD9739 SPI registers in a known state. All SPI registers (excluding 0x00) are set to their default states as described in Table 10 upon issuing a reset. After issuing a reset, the SPI initialization process need only write to registers that are required for the boot process as well as any other register settings that must be modified, depending on the target application. The default 4-wire SPI interface consists of a clock (SCLK), serial port enable (CS), serial data input (SDIO), and serial data output (SDO). The inputs to SCLK, CS, and SDIO contain a Schmitt trigger with a nominal hysteresis of 0.4 V centered about VDD33/2. The maximum frequency for SCLK is 20 MHz. The SDO pin is active only during the transmission of data and remains threestated at any other time. Although the AD9739 does feature an internal power-on-reset (POR), it is still recommended that a software or hardware reset be implemented shortly after power-up. The internal reset signal is derived from a logical OR operation from the internal POR signal, the RESET pin, and the software reset state. A software reset can be issued via the reset bit (Register 0x00, Bit 5) by toggling the bit high then low. Note that, because the MSB/LSB format may still be unknown upon initial power-up (that is, internal POR is unsuccessful), it is also recommended that the bit settings for Bits[7:5] be mirrored onto Bits[2:0] for the instruction cycle that issues a software reset. A hardware reset can be issued from a host or external supervisory IC by applying a high pulse with a minimum width of 40 ns to the RESET pin (that is, Pin F14). RESET should be tied to VSS if unused. A 3-wire SPI interface can be enabled by setting the SDIO_DIR bit (Register 0x00, Bit 7). This causes the SDIO pin to become bidirectional such that output data only appears on the SDIO pin during a read operation. The SDO pin remains three-stated in a 3-wire SPI interface. Table 8. SPI Registers Pertaining to SPI Options Address (Hex) 0x00 Bit 7 6 5 Description Enable 3-wire SPI Enable SPI LSB first Software reset Instruction Header Information MSB 17 R/W 16 A6 15 A5 14 A4 13 A3 12 A2 11 A1 LSB 10 A0 An 8-bit instruction header must accompany each read and write operation. The MSB is a R/W indicator bit with logic high indicating a read operation. The remaining seven bits specify the address bits to be accessed during the data transfer portion. The eight data bits immediately follow the instruction header for both read and write operations. For write operations, registers change immediately upon writing to the last bit of each transfer byte. CS can be raised after each sequence of eight bits (except the last byte) to stall the bus. The serial transfer resumes when CS is lowered. Stalling on nonbyte boundaries resets the SPI. Rev. E | Page 20 of 50 Data Sheet AD9739 The AD9739 serial port can support both most significant bit (MSB) first and least significant bit (LSB) first data formats. Figure 35 illustrates how the serial port words are formed for the MSB first and LSB first modes. The bit order is controlled by the SDIO_DIR bit (Register 0x00, Bit 7). The default value is 0, MSB first. When the LSB first bit is set high, the serial port interprets both instruction and data bytes LSB first. INSTRUCTION CYCLE DATA TRANSFER CYCLE Figure 37 illustrates the timing for a 3-wire read operation to the SPI port. After CS goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of SCLK. A read operation occurs if the read/not-write indicator is set high. After the address bits of the instruction header are read, the eight data bits pertaining to the specified register are shifted out of the SDIO pin on the falling edges of the next eight clock cycles. SCLK N2 A4 A3 A2 A1 A0 D71 D61 DATA TRANSFER CYCLE INSTRUCTION CYCLE CS D1N D0N SCLK A0 A1 A2 A3 A4 N2 N1 R/W D01 D11 Figure 38 illustrates the timing for a 4-wire read operation to the SPI port. The timing is similar to the 3-wire read operation with the exception that data appears at the SDO pin only, while the SDIO pin remains at high impedance throughout the operation. The SDO pin is an active output only during the data transfer phase and remains three-stated at all other times. D6N D7N 07851-035 SDATA Figure 35. SPI Timing, MSB First (Upper) and LSB First (Lower) tS 1/fSCLK CS tH tLOW tHI SCLK tDS tDH SDIO R/W N1 N0 A0 D6 D1 D7 D0 07851-036 R/W N1 Figure 36. SPI Write Operation Timing tS 1/fSCLK CS tLOW tHI SCLK tDS tDV tDH SDIO R/W N1 A2 A1 A0 tEZ D7 D6 D1 D0 07851-037 SDATA Figure 37. SPI 3-Wire Read Operation Timing tS 1/fSCLK CS tLOW tHI SCLK tDS SDIO tEZ tDH R/W N1 A2 A1 A0 tEZ tDV D7 SDO D6 D1 Figure 38. SPI 4-Wire Read Operation Timing Rev. E | Page 21 of 50 D0 07851-038 CS Figure 36 illustrates the timing requirements for a write operation to the SPI port. After the serial port enable (CS) signal goes low, data (SDIO) pertaining to the instruction header is read on the rising edges of the clock (SCLK). To initiate a write operation, the read/not-write bit is set low. After the instruction header is read, the eight data bits pertaining to the specified register are shifted into the SDIO pin on the rising edge of the next eight clock cycles. AD9739 Data Sheet SPI REGISTER MAP Table 9. Full Register Map (N/A = Not Applicable) Hex Addr 00 01 Bit 7 SDIO_DIR N/A Bit 6 LSB/MSB N/A 02 N/A N/A 03 N/A N/A IRQ_REQ 04 N/A N/A RSVD FSC_1 FSC_2 DEC_ CNT RSVD LVDS_ CNT DIG_ STAT LVDS_ STAT1 LVDS_ STAT2 RSVD RSVD LVDS_ REC_ CNT1 LVDS_ REC_ CNT2 LVDS_ REC_ CNT3 LVDS_ REC_ CNT4 LVDS_ REC_ CNT5 LVDS_ REC_ CNT6 LVDS_ REC_ CNT7 LVDS_ REC_ CNT8 LVDS_ REC_ CNT9 LVDS_ REC_ STAT1 LVDS_ REC_ STAT2 05 06 07 08 N/A FSC[7] Sleep N/A 09 0A 0B Name Mode PowerDown CNT_ CLK_DIS IRQ_EN 0C 0D 0E 0F 10 Bit 5 Reset LVDS_ DRVR_PD N/A Bit 4 N/A LVDS_ RCVR_PD N/A Bit 3 N/A N/A Bit 2 N/A N/A CLKGEN_PD N/A SYNC_ LCK_EN SYNC_ LCK_IRQ N/A FSC[4] N/A N/A MU_LST_EN MU_LCK_EN N/A FSC[6] N/A N/A SYNC_ LST_EN SYNC_ LST_IRQ N/A FSC[5] N/A N/A MU_LST_ IRQ N/A FSC[3] N/A N/A MU_LCK_ IRQ N/A FSC[2] N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A HNDOFF_ Fall[3] SUP/HLD_ Edge1 SUP/HLD_ SYNC N/A N/A SYNC_ FLG_RST HNDOFF_ Fall[2] N/A HNDOFF_ Fall[1] DCI_ PHS3 SYNC_ SAMP1 N/A N/A SYNC_ MST/SLV HNDOFF_ Fall[0] DCI_ PHS1 SYNC_ SAMP0 N/A N/A SYNC_ CNT_ENA N/A HNDOFF_ CHK_RST HNDOFF_ Rise[3] DCI_PRE_ PH2 LVDS1_HI FINE_ DEL_ MID[2] SMP_ DEL[6] SUP/HLD_ Edge0 N/A N/A SYNC_ LOOP_ON Bit 1 N/A CLK_ RCVR_PD REC_CNT_ CLK RCV_ LST_EN RCVLST_ IRQ N/A FSC[1] FSC[9] DAC_DEC[1] Bit 0 N/A DAC_ BIAS_PD MU_CNT_ CLK RCV_ LCK_EN RCVLCK_ IRQ N/A FSC[0] FSC[8] DAC_DEC[0] Default 0x00 0x00 N/A LVDS_ Bias[0] HNDOFF_ Rise[0] DCI_PST_ PH0 LVDS0_LO N/A 0x00 HNDOFF_ Rise[2] DCI_PRE_ PH0 LVDS1_LO N/A LVDS_ Bias[1] HNDOFF_ Rise[1] DCI_PST_ PH2 LVDS0_HI N/A N/A N/A N/A N/A RCVR_ FLG_RST N/A N/A RCVR_ LOOP_ON N/A N/A RCVR_ CNT_ENA N/A N/A 0x42 FINE_DEL_ MID[1] FINE_DEL_ MID[0] RCVR_ GAIN[1] RCVR_ GAIN[0] 0xDD SMP_ DEL[5] SMP_ DEL[4] SMP_ DEL[3] SMP_ DEL[2] 0x29 0x03 0x00 0x00 N/A 0x00 0x02 0x00 RNDM RNDM RNDM/0 11 SMP_DEL[1] SMP_ DEL[0] 12 SMP_DEL[9] SMP_ DEL[8] FINE_ DEL_ MID[3] SMP_ DEL[7] 13 DCI_DEL[3] DCI_ DEL[2] DCI_ DEL[1] DCI_ DEL[0] FINE_DEL_ SKW[3] FINE_DEL_ SKW[2] FINE_DEL_ SKW[1] FINE_DEL_ SKW[0] 0x71 14 CLKDIVPH[1] CLKDIVPH[0] DCI_ DEL[9] DCI_ DEL[8] DCI_ DEL[7] DCI_ DEL[6] DCI_ DEL[5] DCI_ DEL[4] 0x0A 15 SYNC_ GAIN[1] SYNC_ GAIN[0] SYNCOUT_ PH[1] SYNCOUT_ PH[0] LCKTHR[3] LCKTHR[2] LCKTHR[1] LCKTHR[0] 0x42 16 N/A SYNCO_ DEL[6] SYNCO_ DEL[5] SYNCO_ DEL[4] SYNCO_ DEL[3] SYNCO_ DEL[2] SYNCO_ DEL[1] SYNCO_ DEL[0] 0x00 17 SYNCSH_ DEL[0] N/A N/A N/A N/A N/A N/A N/A 0x00 18 SYNCSH_ DEL[8] SYNCSH_ DEL[7] SYNCSH_ DEL[6] SYNCSH_ DEL[5] SYNCSH_ DEL[4] SYNCSH_ DEL[3] SYNCSH_ DEL[2] SYNCSH_ DEL[1] 0x00 19 SMP_DEL[1] SMP_DEL[0] N/A N/A SMP_DEL[9] SMP_ DEL[8] SMP_ DEL[7] SMP_ DEL[6] SMP_ FINE_ DEL[2] SMP_ DEL[4] SMP_ FINE_ DEL[1] SMP_ DEL[3] SMP_ FINE_ DEL[0] SMP_ DEL[2] 0xC7 1A SMP_ FINE_ DEL[3] SMP_ DEL[5] Rev. E | Page 22 of 50 0x29 Data Sheet Name LVDS_ REC_ STAT3 LVDS_ REC_ STAT4 LVDS_ REC_ STAT5 LVDS_ REC_ STAT6 LVDS_ REC_ STAT7 LVDS_ REC_ STAT8 LVDS_ REC_ STAT9 CROSS_ CNT1 CROSS_ CNT2 PHS_ DET MU_ DUTY MU_ CNT1 MU_ CNT2 MU_ CNT3 MU_ CNT4 MU_ STAT1 RSVD RSVD ANA_ CNT1 ANA_ CNT2 RSVD PART ID AD9739 Hex Addr 1B Bit 7 DCI_DEL[1] Bit 6 DCI_DEL[0] Bit 5 N/A Bit 4 N/A Bit 3 SYNCOUT PH[1] Bit 2 SYNCOUT PH[0] Bit 1 CLKDIV PH[1] Bit 0 CLKDIV PH[0] Default 0xC0 1C DCI_DEL[9] DCI_ DEL[8] DCI_ DEL[7] DCI_ DEL[6] DCI_ DEL[5] DCI_ DEL[4] DCI_ DEL[3] DCI_ DEL[2] 0x29 1D FINE_DEL_ PST[3] FINE_DEL_ PST[2] FINE_DEL_ PST[1] FINE_DEL_ PST[0] FINE_DEL_ PRE[3] FINE_DEL_ PRE[2] FINE_DEL_ PRE[1] FINE_DEL_ PRE[0] 0x86 1E N/A SYNCO_ DEL[6] SYNCO_ DEL[5] SYNCO_ DEL[4] SYNCO_ DEL[3] SYNCO_ DEL[2] SYNCO_ DEL[1] SYNCO_ DEL[0] 0x00 1F SYNCSH_ DEL[0] N/A N/A N/A N/A N/A N/A N/A 0x00 20 SYNCSH_ DEL[8] SYNCSH_ DEL[7] SYNCSH_ DEL[6] SYNCSH_ DEL[5] SYNCSH_ DEL[4] SYNCSH_ DEL[3] SYNCSH_ DEL[2] SYNCSH_ DEL[1] 0x00 21 SYNC_ TRK_ON SYNC_ INIT_ON SYNC_ LST_LCK SYNC_LCK RCVR_ TRK_ON RCVR_ FE_ON RCVR_LST RCVR_LCK 0x00 22 N/A N/A N/A DIR_P N/A N/A N/A DIR_N 24 N/A N/A CMP_BST PHS_DET AUTO_EN CLKP_ OFFSET[2] CLKN_ OFFSET[2] Bias[2] CLKP_ OFFSET[1] CLKN_ OFFSET[1] Bias[1] CLKP_ OFFSET[0] CLKN_ OFFSET[0] Bias[0] 0x00 23 CLKP_ OFFSET[3] CLKN_ OFFSET[3] Bias[3] 0x00 25 POS/NEG ADJ[5] ADJ[4] ADJ[3] ADJ[2] ADJ[1] ADJ[0] 0x00 26 MU_ DUTYAUTO_EN N/A Slope Mode[1] Mode[0] Read Gain[1] Gain[0] Enable 0x42 27 MUDEL[0] SRCH_MODE [1] SRCH_MODE [0] SET_PHS[4] SET_PHS[3] SET_PHS[2] SET_PHS[1] SETPHS[0] 0x40 28 MUDEL[8] MUDEL[7] MUDEL[6] MUDEL[5] MUDEL[4] MUDEL[3] MUDEL[2] MUDEL[1] 0x00 29 SEARCH_TOL Retry CONTRST Guard[4] Guard[3] Guard[2] Guard[1] Guard[0] 0x0B 2A N/A N/A N/A N/A N/A N/A MU_LOST MU_LKD 0x00 2B 2C 32 N/A N/A HDRM[7] N/A N/A HDRM[6] N/A N/A HDRM[5] N/A N/A HDRM[4] N/A N/A HDRM[3] N/A N/A HDRM[2] N/A N/A HDRM[1] N/A N/A HDRM[0] N/A N/A 0xCA 33 N/A N/A N/A N/A N/A N/A MSEL[1] MSEL[0] 0x03 34 35 N/A ID[7] N/A ID[6] N/A ID[5] N/A ID[4] N/A ID[3] N/A ID[2] N/A ID[1] N/A ID[0] N/A 0x20 Rev. E | Page 23 of 50 0x00 AD9739 Data Sheet SPI PORT CONFIGURATION AND SOFTWARE RESET Table 10. SPI Port Configuration and Software Reset Register Address (Hex) 0x00 Name SDIO_DIR LSB/MSB Reset Bit 7 6 5 R/W R/W R/W R/W Default Setting 0 0 0 Comments 0 = 4-wire SPI, 1 = 3-wire SPI. 0 = MSB first, 1 = LSB first. Software reset is recommended before modification of other SPI registers from the default setting. Setting the bit to 1 causes all registers (except 0x00) to be set to the default setting. Setting the bit to 0 corresponds to the inactive state, allowing the user to modify registers from the default setting. POWER-DOWN LVDS INTERFACE AND TXDAC® Table 11. Power-Down LVDS Interface and TxDAC Register Address (Hex) 0x01 Name LVDS_DRVR_PD LVDS_RCVR_PD CLK_RCVR_PD DAC_BIAS_PD Bit 5 4 1 0 R/W R/W R/W R/W R/W Default Setting 0 0 0 0 Comments Power-down of the LVDS drivers/receivers and TxDAC. 0 = enable, 1 = disable. CONTROLLER CLOCK DISABLE Table 12. Controller Clock Disable Register Address (Hex) 0x02 Name CLKGEN_PD Bit 3 R/W R/W Default Setting 0 REC_CNT_CLK MU_CNT_CLK 1 0 R/W R/W 1 1 Comments Internal CLK distribution enable: 0 = enable, 1 = disable. LVDS receiver (REC_CNT_CLK) and mu controller clock disable (MU_CNT_CLK). 0 = disable, 1 = enable. INTERRUPT REQUEST (IRQ) ENABLE/STATUS Table 13. Interrupt Request (IRQ) Enable/Status Register Address (Hex) 0x03 0x04 Name SYNC_LST_EN SYNC_LCK_EN MU_LST_EN MU_LCK_EN RCV_LST_EN RCV_LCK_EN SYNC_LST_IRQ SYNC_LCK_IRQ MU_LST_IRQ MU_LCK_IRQ RCV_LST_IRQ RCV_LCK_IRQ Bit 5 4 3 2 1 0 5 4 3 2 1 0 R/W W W W W W W R R R R R R Default Setting 0 0 0 0 0 0 0 0 0 0 0 0 Comments This register enables the sync, mu, and LVDS Rx controllers to update their corresponding IRQ status bits in Register 0x04, which defines whether the controller is locked (LCK) or unlocked (LST). 0 = disable (resets the status bit). 1 = enable. This register indicates the status of the controllers. For LCK_IQR bits: 0 = lost locked, 1 = locked. For LST_IQR bits: 0 = not lost locked, 1 = unlocked. Note that, if the controller IRQ is serviced, the relevant bits in Register 0x03 should be reset by writing 0, followed by another write of 1 to enable. Rev. E | Page 24 of 50 Data Sheet AD9739 TxDAC FULL-SCALE CURRENT SETTING (IOUTFS) AND SLEEP Table 14. TxDAC Full-Scale Current Setting (IOUTFS) and Sleep Register Address (Hex) 0x06 0x07 Name FSC_1 FSC_2 Sleep Bit [7:0] [1:0] 7 Default Setting 0x00 0x02 R/W R/W R/W R/W Comments Sets the TxDAC IOUTFS current between 8 mA and 31 mA (default = 20 mA). IOUTFS = 0.0226 × FSC[9:0] + 8.58, where FSC = 0 to 1023. 0 = enable DAC output, 1 = disable DAC output (sleep). TxDAC QUAD-SWITCH MODE OF OPERATION Table 15. TxDAC Quad-Switch Mode of Operation Register Address (Hex) 0x08 Name DAC-DEC Bit [1:0] Default Setting 0x00 R/W R/W Comments 0x00 = normal baseband mode. 0x01 = return-to-zero mode. 0x02 = mix mode. DCI PHASE ALIGNMENT STATUS Table 16. DCI Phase Alignment Status Register Address (Hex) 0x0C Name DCI_PRE_PH0 Bit 2 R/W R Default Setting 0 DCI_PST_PH0 0 R 0 Comments 0 = DCI rising edge is after the PRE delayed version of the Phase 0 sampling edge. 1 = DCI rising edge is before the PRE delayed version of the Phase 0 sampling edge. 0 = DCI rising edge is after the POST delayed version of the Phase 0 sampling edge. 1 = DCI rising edge is before the POST delayed version of the Phase 0 sampling edge. SYNC_IN PHASE ALIGNMENT STATUS Table 17. SYNC_IN Phase Alignment Status Register Address (Hex) 0x0D Name SYNC_IN_PH90 Bit 5 R/W R Default Setting 0 SYNC_IN_PH0 4 R 0 Comments 0 = SYNCIN rising edge is after Phase 90 sampling edge. 1 = SYNCIN rising edge is before Phase 90 sampling edge. 0 = SYNCIN rising edge is after Phase 0 sampling edge. 1 = SYNCIN rising edge is before Phase 0 sampling edge. DATA RECEIVER CONTROLLER CONFIGURATION Table 18. Data Receiver Controller Configuration Register Address (Hex) 0x10 Name SYNC_FLG_RST SYNC_LOOP_ON Bit 7 6 R/W W R/W Default Setting 0 1 SYNC_MST/SLV SYNC_CNT_ENA RCVR_FLG_RST RCVR_LOOP_ON 5 4 2 1 R/W R/W W R/W 0 0 0 1 RCVR_CNT_ENA 0 R/W 0 Comments Sync controller flag reset. Write 1 followed by 0 to reset flags. 0 = disable, 1 = enable. Enable for master only. When enabled, sync controller generates an IRQ when master falls out of lock and automatically begins search/track routine. Sync controller configuration. 0 = slave, 1 = master. Sync controller enable. 0 = disable, 1 = enable Data receiver controller flag reset. Write 1 followed by 0 to reset flags. 0 = disable, 1 = enable. When enabled, the data receiver controller generates an IRQ; it falls out of lock and automatically begins a search/track routine. Data receiver controller enabled. 0 = disable, 1 = enable. Rev. E | Page 25 of 50 AD9739 Data Sheet DATA RECEIVER CONTROLLER_DATA SAMPLE DELAY VALUE Table 19. Data Receiver Controller_Data Sample Delay Value Register Address (Hex) 0x11 Name SMP_DEL[1:0] Bit [7:6] R/W R/W Default Setting 0xDD 0x12 SMP_DEL[9:2] [7:0] R/W 0x29 Comments Controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by the state machine to sample data. Leave at the default setting of 167, which represents the midpoint of the delay line. Controller disabled: the value sets the actual value of the delay line. DATA AND SYNC RECEIVER CONTROLLER_DCI DELAY VALUE/WINDOW AND PHASE ROTATION Table 20. Data and Sync Receiver Controller_DCI Delay Value/Window and Phase Rotation Register Address (Hex) 0x13 Name DCI_DEL[3:0] Bit [7:4] R/W R/W Default Setting 0111 FINE_DEL_SKEW [3:0] R/W 0001 CLKDIVPH[1:0] [7:6] R/W 00 DCI_DEL[9:4] [5:0] R/W 001010 SYNC GAIN[1:0] [7:6] R/W 00 A 4-bit value sets the difference (that is, window) for the DCI PRE and POST sampling clocks. Leave at the default value of 1 for a narrow window. Relative phase of internal divide-by-4 circuit. This feature allows phase rotation in 90° increments (that is, 1 count) to extend Rx controllers locking range for clock rates between 0.8 GSPS to 1.6 GSPS (only valid with sync controller disabled). Controller enabled: the 10-bit value (with a maximum of 332) represents the start value for the delay line used by the state machine to sample the DCI input. Leave at the default setting of 167, which represents the midpoint of the delay line. Controller disabled: the value sets the actual value of the delay line. Sets the sync tracking gain (optimal value is 1). SYNCOUT_PH[1:0] [5:4] R/W 00 Readback of the present SYNC_OUT phase selection. LCKTHR[3:0] [3:0] R/W 0000 Sets the difference between the sample and DCI delays to lock (optimal value is 2). 0x16 SYNCO_DEL[6:0] [6:0] R/W 0x00 Sets the sync output delay value when the synch controller is disabled; otherwise, is the read status of the sync output delay value when sync is enabled. 0x17 SYNCSH_DEL[0] [7] R/W 0x00 Sets the sync setup and hold delay value when the synch controller is disabled; otherwise, is the read status of sync setup and hold value when sync is enabled. 0x18 SYNCSH_DEL[8:1] [7:0] R/W 0x00 Sets the sync setup and hold delay value when the synch controller is disabled; otherwise, is the read status of sync setup and hold value when sync is enabled. 0x14 0x15 Comments Refer to the DCI_DEL description in Register 0x14. DATA RECEIVER CONTROLLER_DELAY LINE STATUS AND SYNC CONTROLLER SYNC_OUT STATUS Table 21. Data Receiver Controller_Delay Line Status and Sync Controller SYNC_OUT Status Register Address (Hex) 0x19 0x1A 0x1B 0x1C Name SMP_DEL[1:0] SMP_DEL[9:2] SYNCOUT_PH[1:0] CLKDIV PH[1:0] DCI_DEL[1:0] DCI_DEL[9:2] Bit [7:6] [7:0] 3:2 1:0 [7:6] [7:0] R/W R R R R R R Default Setting 00 0x00 00 00 00 0x00 Comments The actual value of the DCI and data delay lines determined by the data receiver controller (when enabled) after the state machine completes its search and enters track mode. Note that these values should be equal. SYNCOUT_PH provides phase status (0/90/180/270) of phase select mux, while CLKDIVPH provides phase status of data receiver controller (Register 0x14). Rev. E | Page 26 of 50 Data Sheet AD9739 SYNC AND DATA RECEIVER CONTROLLER LOCK/TRACKING STATUS Table 22. Sync and Data Receiver Controller Lock/Tracking Status Register Address (Hex) 0x21 Name SYNC_TRK_ON SYNC_LST SYNC_LCK RCVR_TRK_ON RCVR_LST Bit 7 5 4 3 1 R/W R R R R R Default Setting 0 0 0 0 0 RCVR_LCK 0 R 0 Comments SYNC_TRK_ON and RCVR_TRK_ON: 0 = tracking not established. 1 = tracking established. SYNC_LCK and RCVR_LCK: 0 = controller is not locked. 1 = controller is locked. SYNC_LST and RCVR_LST: 0 = lock has not been lost. 1 = lock has been lost at some point. CLK INPUT COMMON MODE Table 23. CLK Input Common Mode Register Address (Hex) 0x22 0x23 Name DIR_P CLKP_OFFSET[3:0] DIR_N CLKN_OFFSET[3:0] Bit 4 [3:0] 4 [3:0] R/W R/W R/W R/W R/W Default Setting 0 0000 0 0000 Comments DIR_P and DIR_N: 0 = VCM at the DACCLK_P input decreases with the offset value. 1 = VCM at the DACCLK_P input increases with the offset value. CLKx_OFFSET sets the magnitude of the offset for the DACCLK_P and DACCLK_N inputs. For optimum performance, set to 1111. MU CONTROLLER CONFIGURATION AND STATUS Table 24. Mu Controller Configuration and Status Register Address (Hex) 0x24 0x25 0x26 0x27 Name CMP_BST Bit 5 R/W R/W Default Setting 0 PHS_DET AUTO_EN MU_DUTY AUTO_EN Slope 4 R/W 0 7 R/W 0 Mu controller duty cycle enable. Note that this bit should always be set to 1 to enable. 6 R/W 1 Mode[1:0] [5:4] R/W 00 Read 3 R/W 0 Mu controller phase slope lock. 0 = negative slope, 1 = positive slope. Refer to Table 28 for optimum setting. Sets the mu controller mode of operation. 00 = search and track (recommended). 01 = search only. 10 = track. Set to 1 to read the current value of the mu delay line in. Gain[1:0] [2:1] R/W 01 Sets the mu controller tracking gain. Recommended to leave at the default 01 setting. Enable 0 R/W 0 MUDEL[0] SRCH_MODE[1:0] 7 [6:5] R/W R/W 0 0 SET_PHS[4:0] [4:0] R/W 0 1 = enable the mu controller. 0 = disable the mu controller. The LSB of the 9-bit MUDEL setting. Sets the direction in which the mu controller searches (from its initial MUDEL setting) for the optimum mu delay line setting that corresponds to the desired phase/slope setting (that is, SET_PHS and slope ). 00 = down. 01 = up. 10 = down/up (recommended). Sets the target phase that the mu controller locks to with a maximum setting of 16. Refer to Table 28 for optimum setting. Comments Phase detector enable and boost bias bits. Note that both bits should always be set to 1 to enable these functions. Rev. E | Page 27 of 50 AD9739 Address (Hex) 0x28 0x29 0x2A Name MUDEL[8:1] Data Sheet Bit [7:0] R/W W Default Setting 0x00 R 0x00 SEARCH_TOL 7 R/W 0 Retry 6 R/W 0 CONTRST 5 R/W 0 Guard[4:0] 4 R/W 01011 MU_LST 1 R 0 MU_LKD 0 R 0 Comments With enable (Bit 0, Register 0x26) set to 0, this 9-bit value represents the value that the mu delay is set to. Note that the maximum value is 432. With enable set to 1, this value represents the mu delay value at which the controller begins its search. Setting this value to the delay line midpoint of 216 is recommended. When read (Bit 3, Register 0x26) is set to 1, the value read back is equal to the value written into the register when enable = 0 or the value that the mu controller locks to when enable = 1. 0 = not exact (can find a phase within two values of the desired phase). 1 = finds the exact phase that is targeted (optimal setting). 0 = stop the search if the correct value is not found. 1 = retry the search if the correct value is not found. Controls whether the controller resets or continues when it does not find the desired phase. 0 = continue (optimal setting). 1 = reset. Sets a guard band from the beginning and end of the mu delay line which the mu controller does not enter into unless it does not find a valid phase outside the guard band (optimal value is Decimal 11 or 0x0B). 0 = mu controller has not lost lock. 1 = mu controller has lost lock. 0 = mu controller is not locked. 1= mu controller is locked. PART ID Table 25. Part ID Register Address (Hex) 0x35 Name PART_ID Bit [7:0] R/W R Rev. E | Page 28 of 50 Default Setting 0x20 Comments Part ID number. Data Sheet AD9739 THEORY OF OPERATION Figure 39 shows a top-level functional diagram of the AD9739. A high performance TxDAC core delivers a signal dependent, differential current (nominal ±10 mA) to a balanced load referenced to ground. The frequency of the clock signal appearing at the AD9739 differential clock receiver, DACCLK, sets the TxDAC’s update rate. This clock signal, which serves as the master clock, is routed directly to the TxDAC as well as to a clock distribution block that generates all critical internal and external clocks. RESET AD9739 DAC BIAS VREF IOUTP IOUTN DACCLK 07851-039 SYNCCONTROLLER DATA LATCH 4-TO-1 DATA ASSEMBLER LVDS DDR RECEIVER CLK DISTRIBUTION (DIV-BY-4) TxDAC CORE DLL (MU CONTROLLER) SYNC_OUT SYNC_IN 1.2V I120 LVDS DDR RECEIVER DB1[13:0] DCO SPI DATA CONTROLLER DB0[13:0] SDIO SDO CS SCLK DCI IRQ Figure 39. Functional Block Diagram of the AD9739 The AD9739 includes two 14-bit LVDS data ports (DB0 and DB1) to reduce the data interface rate to ½ the TxDAC update rate. The host processor drives deinterleaved data with offset binary format onto the DB0 and DB1 ports, along with an embedded DCI clock that is synchronous with the data. Because the interface is double data rate (DDR), the DCI clock is essentially an alternating 010101……….01010 bit pattern with a frequency equal to ¼ the TxDAC update rate (fDAC). To simplify synchronization with the host processor, the AD9739 passes an LVDS clock output (DCO) that is also equal to the DCI frequency. The AD9739 data receiver controller generates an internal sampling clock offset by 90° from the DCI to sample the input data on the DB0 and DB1 ports. When enabled and configured properly for track mode, it ensures proper data recovery between the host and the AD9739 clock domains. The data receiver controller has the ability to track several hundreds of ps of drift between these clock domains, typically caused by supply and temperature variation. As mentioned, the host processor provides the AD9739 with a deinterleaved data stream such that the DB0 and DB1 data ports receive alternating samples (that is, odd/even data streams). The AD9739 data assembler is used to reassemble (that is, multiplex) the odd/even data streams into their original order before delivery into the TxDAC for signal reconstruction. The pipeline delay from a sample being latched into the data port to when it appears at the DAC output is on the order of 78 (±2) DACCLK cycles. Applications that require matching pipeline delays (that is, synchronization) between multiple AD9739 devices can use the SYNC controller. The SYNC controller phase aligns the outputs of one or more AD9739 devices (that is, slaves) to a master AD9739 device. The AD9739 includes a delay lock loop (DLL) circuit controlled via a mu controller to optimize the timing hand-off between the AD9739 digital clock domain and TxDAC core. Besides ensuring proper data reconstruction, the TxDAC’s ac performance is also dependent on this critical hand-off between these clock domains with speeds of up to 2.5 GSPS. Once properly initialized and configured for track mode, the DLL maintains optimum timing alignment over temperature, time, and power supply variation. A SPI interface is used to configure the various functional blocks as well as monitor their status for debug purposes. Proper operation of the AD9739 requires that controller blocks be initialized upon power-up. A simple SPI initialization routine is used to configure the controller blocks (see Figure 51 and Figure 52). An IRQ output signal is available to alert the host should any of the controllers fall out of lock during normal operation. The following sections discuss the various functional blocks in more detail as well as their implications when interfacing to external ICs and circuitry. While a detailed description of the various controllers (and associated SPI registers used to configure and monitor) is also included for completeness, the recommended SPI boot procedure can be used to ensure reliable operation. Rev. E | Page 29 of 50 AD9739 Data Sheet LVDS DATA PORT INTERFACE The AD9739 supports input data rates from 1.6 GSPS to 2.5 GSPS using dual LVDS data ports. The interface is source synchronous and double data rate (DDR) where the host provides an embedded data clock input (DCI) at fDAC/4 with its rising and falling edges aligned with the data transitions. The data format is offset binary; however, twos complement format can be realized by reversing the polarity of the MSB differential trace. As shown in Figure 40, the host feeds the AD9739 with deinterleaved input data into two 14-bit LVDS data ports (DB0 and DB1) at ½ the DAC clock rate (that is, fDAC/2). The AD9739 internal data receiver controller then generates a phase shifted version of DCI to register the input data on both the rising and falling edges. HOST PROCESSOR 14 × 2 LVDS DDR RECEIVER ODD DATA SAMPLES DB1[13:0] fDATA = fDAC /2 1×2 DCI DCO 1×2 DIV-BY-4 fDAC 07851-040 fDCI = fDAC /4 fDCO = fDAC /4 MaxSkew + Jitter = Period(ns) − ValidWindow(ps) − Guard = 800 ps − 344 ps − 100 ps = 356 ps where ValidWindow(ps) is represented by tVALID and Guard is represented by tGUARD in Figure 41. The minimum specified LVDS valid window is 344 ps, and a guard band of 100 ps is recommended. Therefore, at the maximum operating frequency of 2.5 GSPS, the maximum allowable FPGA and PCB bit skew plus jitter is equal to 356 ps. For synchronous operation, the AD9739 provides a data clock output, DCO, to the host at the same rate as DCI (that is, fDAC/4) to maintain the lowest skew variation between these clock domains. Because the DCO signal is generated from a separate clock divider, its phase relationship relative to the fDAC/4 clocks used by the data receiver controller varies upon each power-up. Applications sensitive to this phase ambiguity (resulting in a ±2 DACCLK pipeline variation) should consider using the sync controller. DATA CONTROLLER DB0[13:0] 14 × 2 LVDS DDR DRIVER DATA DEINTERLEAVER EVEN DATA SAMPLES LVDS DDR RECEIVER AD9739 The maximum allowable skew and jitter out of the host processor with respect to the DCI clock edge on each LVDS port is calculated as Figure 40. Recommended Digital Interface Between the AD9739 and Host Processor As shown in Figure 41, the DCI clocks edges must be coincident with the data bit transitions with minimum skew, jitter, and intersymbol interference. To ensure coincident transitions with the data bits, the DCI signal should be implemented as an additional data line with an alternating (010101…) bit sequence from the same output drivers used for the data. Maximizing the opening of the eye in both the DCI and data signals improves the reliability of the data port interface. Differential controlled impedance traces of equal length (that is, delay) should also be used between the host processor and AD9739 input to limit bit-to-bit skew. The host processor has a worst-case skew between DCO and DCI that is both implementation and process dependent. This worst-case skew can also vary an additional 30% over temperature and supply corners. The delay line within the data receiver controller can track a ±1.5 ns skew variation after initial lock. While it is possible for the host to have an internal PLL that generates a synchronous fDAC/4 from which the DCI signal is derived, digital implementations that result in the shortest propagation delays result in the lowest skew variation. The data receiver controller is used to ensure proper data hand-off between the host and AD9739 internal digital clock domains. The circuit shown in Figure 42 functions as a delay lock loop in which a 90o phase shifted version of the DCI clock input is used to sample the input data into the DDR receiver registers. This ensures that the sampling instance occurs in the middle of the data pattern eyes (assuming matched DCI and DBx[13:0] delays). Note that, because the DCI delay and sample delay clocks are derived from the divide-by-4 circuitry, this 90° phase relationship holds as long as the delay settings (that is, DCI_DEL, SMP_DEL) are also matched. 2 × 1/fDAC DCI tVALID + tGUARD tVALID 07851-041 DB0[13:0] AND DB1[13:0] MAX SKEW + JITTER Figure 41. LVDS Data Port Timing Requirements Rev. E | Page 30 of 50 Data Sheet AD9739 DATA RECEIVER CONTROLLER DCI DDR FF DCI WINDOW PRE FINE DELAY PRE DDR FF DELAY DELAY FROM SYNC CONTROLLER OR SPI REG 0x14, BIT[7:6] PHASE ROTATION DCI DELAY DCI WINDOW POST 0 90 DIV-BY-4 180 270 STATE MACHINE/ TRACKING LOOP FINE DELAY POST DDR FF DCI DELAY PATH FDAC SAMPLE DELAY DCI WINDOW SAMPLE FINE DELAY SAMPLE DELAY PATH DELAY TO SYNC CONTROLLER DELAY SAMPLE DBx[13:1] DDR FF DDR FF DDR FF DDR FF DATA TO CORE DCO 07851-042 ELASTIC FIFO DIV-BY-4 Figure 42. Top Level Diagram of the Data Receiver Controller Once this data has been successively sampled into the first set of registers, an elastic FIFO is used to transfer the data into the AD9739 clock domain. To continuously track any phase variation between the two clock domains, the data receiver controller should always be enabled and placed into track mode (Register 0x10, Bit 1 and Bit 0). Tracking mode operates continuously in the background to track delay variations between the host and AD9739 clock domains. It does so by ensuring that the DCI signal is sampled within a very narrow window defined by two internally generated clocks (that is, PRE and PST), as shown in Figure 43. Proper sampling of the DCI signal can also be confirmed by monitoring the status of DCI_PRE_PH0 (Register 0x0C, Bit 2) and DCI_PST_PH0 (Register 0x0C, Bit 0). If the delay settings are correct, the state of DCI_ PRE_PH0 should be 0, and the state of DCI_PST_PH0 should be 1. Note that the states of these status bits may toggle occasionally due to cycle-to cycle jitter exceeding the window width. However, the controller averages these status bits over multiple clock cycles to ensure that the DCI signal falls within a programmable window. DCI FINE DELAY PST FINE DELAY PRE FINE_DEL_SKEW 07851-043 The divide-by-4 circuit generates four clock phases that serve as inputs to the data receiver controller. All of the DDR registers in the data and DCI paths operate on both clock edges; however, for clarity purposes, only the phases (that is, 0o and 90o) corresponding to the positive edge of each path are shown. One of the divide-by-4 phases is used to generate the DCO signal; therefore, the phase relationship between DCO and clocks fed into the controller remains fixed. Note that it is this attribute that allows possible factory calibration of images and clock spurs attributed to fDAC/4 modulation of the critical DAC clock. Figure 43. Pre- and Post-Delay Sampling Diagram The skew or window width (FINE_DEL_SKEW) is set via Register 0x13, Bits[3:0], with a maximum skew of approximately 180 ps and resolution of 12 ps. It is recommended that the skew be set to 36 ps (that is, Register 0x13 = 0x72) during initialization. The skew setting also affects the speed of the controller loop, with tighter skew settings corresponding to longer response time. Data Receiver Controller Initialization Description The data controller should be initialized and placed into track mode as the second step in the SPI boot sequence. The following steps are recommended for the initialization of the data receiver controller: Rev. E | Page 31 of 50 AD9739 1. 2. 3. 4. 5. 6. Data Sheet Set FINE_DEL_SKEW to 2 for a larger DCI sampling window (Register 0x13 = 0x72). Note that the default DCI_DEL and SMP_DEL settings of 167 are optimum. Disable the controller before enabling (that is, Register 0x10 = 0x00). on whether the synchronization controller is enabled as shown in Table 26. Table 26. Typical/Worst-Case Lock Times for LVDS Controller (Relative to 1/fDAC) Enable the Rx controller in two steps: Register 0x10 = 0x02 followed by Register 0x10 = 0x03. Wait 135K clock cycles. Read back Register 0x21 and confirm that it is equal to 0x05 to ensure that the DLL loop is locked and tracking. Include this step for operation 2 GSPS) when the output bandwidth of DAC core and the interface network (that is, balun) contributes to additional roll-off. FIRST NYQUIST ZONE TWO-SWITCH DAC OUTPUT D4 07851-056 The AD9739 uses the quad-switch architecture shown in Figure 54. The quad-switch architecture masks the code-dependent glitches that occur in a conventional two-switch DAC. Figure 55 compares the waveforms for a conventional DAC and the quad-switch DAC. In the two-switch architecture, a code-dependent glitch occurs each time the DAC switches to a different state (that is, D1 to D2). This code-dependent glitching causes an increased amount of distortion in the DAC. In a quad-switch architecture (no matter what the codes are), there are always two switches transitioning at each half clock cycle, thus eliminating the codedependent glitches. However, a constant glitch occurs at 2 × DACCLK because half of the internal switches change state on the rising DACCLK edge, while the other half change state on the falling DACCLK edge. D2 D1 SECOND NYQUIST ZONE 0 t THIRD NYQUIST ZONE MIX MODE –5 RZ MODE –10 D3 D4 D7 D8 D9 D10 D5 t dBFS D6 D2 07851-055 FOUR-SWITCH DAC OUTPUT (NORMAL MODE) D1 –15 NORMAL MODE –20 Figure 55. Two-Switch and Quad-Switch DAC Waveforms Rev. E | Page 40 of 50 –25 –30 –35 0FS 0.25FS 0.50FS 0.75FS 1.00FS 1.25FS 1.50FS FREQUENCY (Hz) Figure 57. Sinc Roll-Off for Each Analog Operating Mode 07851-057 Another attribute of the quad-switch architecture is that it also enables the DAC core to operate in one of the following three modes: normal mode, mix mode, and return-to-zero (RZ) mode. The mode is selected via SPI Register 0x08, Bits[1:0] with normal mode being the default value. In the mix mode, the output is effectively chopped at the DAC sample rate. This has the effect of reducing the power of the fundamental signal while increasing the power of the images centered around the DAC sample rate, thus improving the output power of these images. The RZ mode is similar to the analog mix mode, except that the intermediate data samples are replaced with midscale values. Data Sheet AD9739 VDDC CLOCK INPUT CONSIDERATIONS 4-BIT PMOS IOUT ARRAY VCC VREF VT 10nF 50Ω 50Ω 50Ω ESD CLKx_OFFSET DIR_x = 0 CLKx_OFFSET DIR_x = 0 4-BIT NMOS IOUT ARRAY VSSC Figure 58. Clock Input and Common-Mode Control The AD9739 clock receiver features the ability to independently adjust the common-mode level of its inputs over a span of ±100 mV centered about its midsupply point (that is, VDDC/2) as well as an offset for hysteresis purposes. Figure 58 shows the equivalent input circuit of one of the inputs. ESD diodes are not shown for clarity purposes. It has been found through characterization that the optimum setting is for both inputs to be biased at approximately 0.8 V. This can be achieved by writing a 0x0F (corresponding to a −15) setting to both cross controller registers (that is, Register 0x22 and Register 0x23). ADCLK914 AD9739 50Ω 50Ω D Q D Q 50Ω 1nF DACCLK_P 100Ω DACCLK_N 1nF 10nF VEE Figure 59. ADCLK914 Interface to the AD9739 CLK Input Rev. E | Page 41 of 50 07851-058 The AD9739 clock receiver provides optimum jitter performance when driven by a fast slew rate originating from the LVPECL or CML output drivers. For optimal ac performance out of the AD9739, the recommended minimum differential peak-to-peak voltage is approximately 1.4 V p-p. For a low jitter sinusoidal clock source, the ADCLK914 can be used to square-up the signal and provide a CML input signal for the AD9739 clock receiver. Note that all specifications and characterization presented in the data sheet are with the ADCLK914 driven by a high quality RF signal generator with the clock receiver biased at an 800 mV level. A dc blocking capacitor is used between the clock driver output and clock receiver input to allow for different dc bias levels. To minimize signal loss for high clock rates, a high quality, dc blocking RF capacitor is recommended. DACCLK_P DACCLK_N 07851-060 The quality of the clock source and its drive strength are important considerations in maintaining the specified ac performance. The phase noise and spur characteristics of the clock source should be selected to meet the target application requirements. Phase noise and spurs at a given frequency offset on the clock source are directly translated to the output signal. It can be shown that the phase noise characteristics of a reconstructed output sine wave are related to the clock source by 20 × log10 (fOUT/fCLK) when the DAC clock path contribution, along with thermal and quantization effects, are negligible. AD9739 Data Sheet 1.10 The following equation relates IOUTFS to the FSC[9:0] register, which can be set from 0 to 1023: CLKP CLKN 1.05 IOUTFS = 22.6 × FSC[9:0]/1000 + 8.7 COMMON-MODE (V) 1.00 0.90 Note that a default value of 0x200 generates 20 mA full scale, which is used for most of the characterization presented in this data sheet (unless noted otherwise). 0.85 ANALOG OUTPUTS 0.95 Equivalent DAC Output and Transfer Function 0.80 The AD9739 provides complementary current outputs, IOUTP and IOUTN, that source current into an external ground reference load. Figure 62 shows an equivalent output circuit for the DAC. Note that, compared to most current output DACs of this type, the AD9739 outputs exhibit a slight offset current (that is, IOUTFS/16), and the peak differential ac current is slightly below IOUTFS/2 (that is, 15/32 × IOUTFS). 0.70 –15 –13 –11 –9 –7 –5 –3 –1 1 3 5 7 9 11 13 15 OFFSET CODE 07851-061 0.75 Figure 60. Common-Mode Voltage with Respect to CLKP_OFFSET/CLKN_OFFSET and DIR_P/DIR_N VOLTAGE REFERENCE IOUTFS = 8.6 – 31.2mA The AD9739 output current is set by a combination of digital control bits and the I120 reference current, as shown in Figure 61. – I120 1nF + 10kΩ AGND IPEAK = 15/32 × IOUTFS DAC • • 70Ω 2.2pF IFULL-SCALE I120 Figure 62. Equivalent DAC Output Circuit The reference current is obtained by forcing the band gap voltage across an external 10 kΩ resistor from I120 (Pin B14) to ground. The 1.2 V nominal band gap voltage (VREF) generates a 120 µA reference current in the 10 kΩ resistor. Note the following constraints when configuring the voltage reference circuit: • AC 17/32 × IOUTFS CURRENT SCALING Figure 61. Voltage Reference Circuit • 17/32 × IOUTFS 07851-063 VREF FSC[9:0] 07851-062 AD9739 VBG 1.2V • (1) Both the 10 kΩ resistor and 1 nF bypass capacitor are required for proper operation. Adjusting the output full-scale current, IOUTFS, of the DAC from its default setting of 20 mA should be performed digitally. The AD9739 is not a multiplying DAC. Modulating the reference current, I120, with an ac signal is not supported. The band gap voltage appearing at VREF (Pin C14) must be buffered for use with external circuitry because its output impedance is approximately 5 kΩ. An external reference can be used to overdrive the internal reference by connecting it to VREF (Pin C14). As shown in Figure 62, the DAC output can be modeled as a pair of dc current sources that source a current of 17/32 × IOUTFS to each output. A differential ac current source, IPEAK, is used to model the signal-dependent nature of the DAC output. The polarity and signal dependency of this ac current source are related to the digital code by the following equations: F(Code) = (DACCODE − 8192)/8192 (2) −1 ≤ F(Code) < 1 (3) where DACCODE = 0 to 16,383 (decimal). Because IPEAK can swing ±(15/32) × IOUTFS, the output currents measured at IOUTP and IOUTN can span from IOUTFS/16 to IOUTFS. However, because the ac signal-dependent current component is complementary, the sum of the two outputs is always constant (that is, IOUTP + IOUTN = (34/32) × IOUTFS). The code-dependent current measured at the IOUTP (and IOUTN) output is as follows: IOUTFS can be adjusted digitally over 8.7 mA to 31.7 mA by using FSC[9:0] (Register 0x06 and Register 0x07). Rev. E | Page 42 of 50 IOUTP = 17/32 × IOUTFS + 15/32 × IOUTFS × F(Code) (4) IOUTN = 17/32 × IOUTFS − 15/32 × IOUTFS × F(Code) (5) Data Sheet AD9739 If the AD9739 is programmed for IOUTFS = 20 mA, its peak ac current is 9.375 mA and its peak power delivered to the equivalent load is 2.2 mW (that is, P = I2R). Because the source and load resistance seen by the 1:1 balun are equal, this power is shared equally; therefore, the output load receives 1.1 mW or 0.4 dBm. Figure 63 shows the IOUTP vs. DACCODE transfer function when IOUTFS is set to 19.65 mA. 20 18 OUTPUT CURRENT (mA) 16 To calculate the rms power delivered to the load, the following must be considered: 14 12 • • • 10 8 6 4 For example, a reconstructed sine wave with no digital backoff ideally measures −2.6 dBm because it has a peak-to-rms ratio of 3 dB. If a typical balun loss of 0.4 dBm is included, −3 dBm of actual power can be expected in the region where the sinc response of the DAC has negligible influence. Increasing the output power is best accomplished by increasing IOUTFS, although any degradation in linearity performance must be considered acceptable for the target application. 0 4096 8192 12,288 16,384 DAC CODE 07851-064 2 0 Figure 63. Gain Curve for FSC[9:0] = 512, DAC Offset = 1.228 mA Peak DAC Output Power Capability The maximum peak power capability of a differential current output DAC is dependent on its peak differential ac current, IPEAK, and the equivalent load resistance it sees. Because the AD9739 includes a differential 70 Ω resistance, it is best to use a doubly terminated external output network similar to what is shown in Figure 64. In this case, the equivalent load seen by the ac current source of the DAC is 25 Ω. RSOURCE = 50Ω IOUTFS = 8.6 – 31.2mA AC 70Ω 180Ω LOSSLESS BALUN 1:1 RLOAD = 50Ω 07851-065 IPEAK = 15/32 × IOUTFS Peak-to-rms of the digital waveform Any digital backoff from digital full scale The DAC’s sinc response and nonideal losses in external network Figure 64. Equivalent Circuit for Determining Maximum Peak Power to a 50 Ω Load Rev. E | Page 43 of 50 AD9739 Data Sheet The AD9739 is intended to serve high dynamic range applications that require wide signal reconstruction bandwidth (that is, DOCSIS CMTS) and/or high IF/RF signal generation. Optimum ac performance can only be realized if the DAC output is configured for differential (that is, balanced) operation with its output common-mode voltage biased to analog ground. The output network used to interface to the DAC should provide a near 0 Ω dc bias path to analog ground. Any imbalance in the output impedance between the IOUTP and IOUTN pins results in asymmetrical signal swings that degrade the distortion performance (mostly even order) and noise performance. Component selection and layout are critical in realizing the performance potential of the AD9739. OPTIONAL BALUN AND FILTER IOUTP 90Ω 90Ω 90Ω RF DIFF AMP Figure 65. Recommended Balun for Wideband Applications with Upper Bandwidths of up to 2.2 GHz Most applications requiring balanced-to-unbalanced conversion can take advantage of the Ruthroff 1:1 balun configuration shown in Figure 65. This configuration provides excellent amplitude/phase balance over a wide frequency range while providing a 0 Ω dc bias path to each DAC output. Also, its design provides exceptional bandwidth and can be considered for applications requiring signal reconstruction of up to 2.2 GHz. The characterization plots shown in this data sheet are based on the AD9739 evaluation board, which uses this configuration. Figure 66 compares the measured frequency response for normal and mix mode using the AD9739 evaluation board vs. the ideal frequency response. For applications operating the AD9739 in mix mode with output frequencies extending beyond 2.2 GHz, the circuits shown in Figure 68 should be considered. The circuit in Figure 68 uses a wideband balun with a configuration similar to the one shown in Figure 67 to provide a dc bias path for the DAC outputs. The circuit in Figure 69 takes advantage of ceramic chip baluns to provide a dc bias path for the DAC outputs while providing excellent amplitude/phase balance over a narrower RF band. These low cost, low insertion loss baluns are available for different popular RF bands and provide excellent amplitude/ phase balance over their specified frequency range. C IOUTP BASEBAND –6 TC1-33-75G 90Ω L IOUTN C MIX MODE TC1-33-75G –12 L 70Ω Figure 68. Recommended Mix Mode Configuration Offering Extended RF Bandwidth Using a TC1-1-43A+ Balun IDEAL BASEBAND MODE –9 90Ω MINI-CIRCUITS TC1-1-462M 07851-069 07851-066 90Ω MURATA JOHANSON TECHNOLOGY CHIP BALUNS IOUTP IDEAL MIX MODE 70Ω –18 –21 IOUTN –24 –27 180Ω 07851-070 –15 Figure 69. Lowest Cost and Size Configuration for Narrow RF Band Operation –30 0 500 1000 1500 2000 2500 FREQUENCY (MHz) 3000 3500 07851-067 –33 –36 C Figure 67. Interfacing the DAC Output to the Self-Biased Differential Gain Stage IOUTN –3 LPF L IOUTN 70Ω 0 C L 70Ω MINI-CIRCUITS® TC1-33-75G+ IOUTP POWER (dBc) Figure 67 shows an interface that can be considered when interfacing the DAC output to a self-biased differential gain block. The inductors shown serve as RF chokes (L) that provide the dc bias path to analog ground. The value of the inductor, along with the dc blocking capacitors (C), determines the lower cutoff frequency of the composite pass-band response. An RF balun should also be considered before the RF differential gain stage and any filtering to ensure symmetrical common-mode impedance seen by the DAC output while suppressing any common-mode noise, harmonics, and clock spurs prior to amplification. 07851-068 Output Stage Configuration Figure 66. Measured vs. Ideal Frequency Response for Normal (Baseband) and Mix Mode Operation Using a TC1-33-75G Transformer on the AD9739 Evaluation Board Rev. E | Page 44 of 50 Data Sheet AD9739 NONIDEAL SPECTRAL ARTIFACTS 3. The AD9739 output spectrum contains spectral artifacts that are not part of the original digital input waveform. These nonideal artifacts included harmonics (including alias harmonics), images, and clock spurs. Figure 70 shows a spectral plot of the AD9739 within the first Nyquist zone (that is, dc to fDAC/2) reconstructing a 650 MHz, 0 dBFS sine wave at 2.4 GSPS. Besides the desired fundamental tone at the −7.8 dBm level, the spectrum also reveals these nonideal artifacts that also appear as spurs above the measurement noise floor. Because these nonideal artifacts are also evident in the second and third Nyquist zones during mix mode operation, the effects of these artifacts should also be considered when selecting the DAC clock rate for a target RF band. 4. 0 FUND AT –7.6dBm –10 –20 POWER (dBc) –30 –40 fDAC /2 – fDAC /4 fOUT –50 fDAC /4 – fOUT –60 –70 3/4 × fDAC /4 – fOUT HD3 HD2 HD5 HD6 HD4 HD9 –80 –90 Table 30. Image Magnitude vs. Phase (PHZ) Setting 0 200 400 600 800 FREQUENCY (MHz) 1000 1200 07851-071 –100 Figure 70. Spectral Plot Note the following important observations pertaining to these nonideal spectral artifacts: 1. 2. Images appear as replicas of the original signal, therefore, can be easier to identify. In the case of the AD9739, internal modulation of the sampling clock at intervals related to fDAC/4 generate image pairs at ¼ × fDAC, ½ × fDAC, and ¾ × fDAC. Both upper and lower sideband images associated with ¼ × fDAC fall within the first Nyquist zone, while only the lower image of ½ × fDAC and ¾ × fDAC fall back. Note that the lower images appear frequency inverted. The difference in dBc between the fundamental and various images remains mostly signal independent because the mechanism causing these images is related to corruption of the sampling clock. The magnitude of these images for a given device is dependent on several factors including DAC clock rate, output frequency, mu controller phase setting, and divide-by-4 clock divider phase (Register 0x14, bit [7:6]. Table 30 shows how the magnitude of these images vary as the phase is varied for the case represented in Figure 70. Because the phase varies at power up, the image magnitude varies making it difficult to compensate digitally through a one-time factory calibration procedure. Also, the image magnitude can vary a few decibels over temperature and between devices due to process dependencies. (Note that the AD9739A is a viable option if factory calibration is considered acceptable for nonmultichip synchronization applications operating with clock rates in the 1.6 GSPS to 2.5 GSPS range). A full-scale sine wave (that is, single-tone) typically represents the worst-case condition because it has a peak-to-rms ratio of 3 dB and is unmodulated. Harmonics and aliased harmonics of a sine wave are easy to identify because they also appear as discrete spurs. Significant characterization of a high speed DAC is performed using single (or multitone) signals for this reason. Modulated signals (that is, AM, PM, or FM) do not appear as spurs but rather as signals whose power spectral density is spread over a defined bandwidth determined by the modulation parameters of the signals. Any harmonics from the DAC spread over a wider bandwidth determined by the order of the harmonic and bandwidth of the modulated signal. For this reason, harmonics often appear as slight bumps in the measurement noise floor and can be difficult to discern. Image location fDAC/4 − fOUT fDAC/2 − fOUT ¾ × fDAC − fOUT 5. 6. Rev. E | Page 45 of 50 PHZ0 −70.2 −80.2 −69.9 PHZ1 −71.4 −71.3 −72.5 PHZ2 −72.2 −69.9 −73.4 PHZ3 −77.1 −74.9 −73.7 A clock spur appears at fDAC/4 and integer multiples of this frequency. Similar to images, the spur magnitude is also dependent on the same factors that cause variations in image levels. However, unlike images and harmonics, clock spurs always appear as discrete spurs, albeit their magnitude shows a slight dependency on the digital waveform and output frequency. Note that the clock spur appearing at fDAC/4 can also be factory calibrated. A large clock spur also appears at 2 × fDAC in either normal or mix mode operation. This clock spur is due to the quad switch DAC architecture causing switching events to occur on both edges of fDAC. AD9739 Data Sheet LAB EVALUATION OF THE AD9739 POWER DISSIPATION AND SUPPLY DOMAINS Figure 71 shows a recommended lab setup that was used to characterize the performance of the AD9739. The DPG2 is a dual port LVDS/CMOS data pattern generator available from Analog Devices, Inc., with an up to 1.25 GSPS data rate. The DPG2 directly interfaces to the AD9739 evaluation board via Tyco Z-PACK HM-Zd connectors. A low phase noise/jitter RF source, such as an R&S SMA100A signal generator, is used for the DAC clock. A 5 V power supply is used to power up the AD9739 evaluation board, and SMA cabling is used to interface to the supply, clock source, and spectrum analyzer. A USB 2.0 interface to a host PC is used to communicate to both the AD9739 evaluation board and the DPG2. The power dissipation of the AD9739 is dependent on the DAC clock rate as shown in Figure 72 and Figure 73. The current consumption from the 3.3 V supply remains relatively constant because it is used for biasing the DAC core (that is, VDDA) and differential input receivers (that is, VDD33). However, the current consumption from the 1.8 V supply is clock rate dependent and increases linearly with frequency because this supply is used by the digital path (that is, VDD) as well as the clock distribution circuitry (that is, VDDC). 1.0 TOTAL 0.9 0.8 LAB PC 0.7 0.6 0.5 VDD 0.4 VDDC 0.3 0.2 LVDS DATA AND DCI VDDA VDD33 0.1 0 GPIB 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 fDAC (MHz) 360 330 10 MHz REOUT AGILENT PSA E4440A Figure 71. Lab Test Setup Used to Characterize the AD9739 300 270 CURRENT (mA) 10 MHz REFIN AD9739 EVAL. BOARD Figure 72. Power Consumption vs. fDAC @ 25°C POWER SUPPLY +5V 07851-072 1.6GHz TO 2.5GHz 3dBm RHODE AND SCHWARTZ SMA 100A 240 210 I_VDD 180 150 I_VDDC 120 90 60 I_VDDA 30 0 I_VDD33 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 fDAC (MHz) Figure 73. Current Consumption vs. fDAC @ 25°C Rev. E | Page 46 of 50 07851-074 DCO USB 2.0 1.1 07851-073 ADI PATTERN GENERATOR DPG2 1.2 POWER (W) A high dynamic range spectrum analyzer is required to evaluate the AD9739 reconstructed waveform’s ac performance. This is especially the case when measuring ACLR performance for high dynamic range applications, such as multicarrier DOCSIS CMTS applications. Harmonic, SFDR, and IMD measurements pertaining to unmodulated carriers can benefit by using a sufficiently high RF attenuation setting because these artifacts are easy to identify above the spectrum analyzer noise floor. However, reconstructed waveforms having modulated carrier(s) often benefit from the use of a high dynamic range RF amplifier and/or passive filters to measure close-in and wideband ACLR performance when using spectrum analyzers of limited dynamic range. Treat the VDDC supply as an analog supply because the clock distribution circuitry has poor power supply rejection; therefore, noise on this supply can induce clock jitter. To ensure low noise on this sensitive supply, use a separate 1.8 V regulator powered from the 3.3 V analog supply rail that is also used to power VDDA. This supply rail can also be used to power-up VDD33 via an LC filter network. The digital 1.8 V supply, VDD, can be supplied via a well-filtered switching regulator. Data Sheet AD9739 Upon power-up of the AD9739, a host processor is required to initialize and configure the AD9739 via its SPI port. Figure 74 shows a flowchart of the sequential steps required, while Table 31 and Table 32 provides more detail on the SPI register write/read operations required to implement the flowchart steps. Note the following: • • • • • A software reset is optional because the AD9739 has both an internal POR circuit and a RESET pin. The SYNC controller is optional because it is only required to synchronize two or more devices. If synchronization is CONFIGURE SPI PORT SOFTWARE RESET SET CLK INPUT CMV CONFIGURE MU CONT. NO CONFIGURE SYNC CONT. • NO required, validate that DCI_DEL values between devices are sufficiently matched. The mu controller must be first enabled (and in track mode) before the data receiver controller is enabled because the DCO output signal is derived from this circuitry. A wait period is related to fDATA periods. Limit the number of attempts to lock the controllers to three; locks typically occur on the first attempt. Hardware or software interrupts can be used to monitor the status of the controllers. CONFIGURE Rx DATA CONT. NO COMPARE DCI_DEL VALUES WAIT A FEW 100µs WAIT A FEW 100µs WAIT A FEW 100µs RECONFIGURE TxDAC FROM DEFAULT SETTING MU CONT. LOCKED? SYNC CONT. VALID? Rx DATA CONT. LOCKED? OPTIONAL YES YES YES Figure 74. Flowchart for Initialization and Configuration of the AD9739 Rev. E | Page 47 of 50 SYNC. ONLY 07851-075 RECOMMENDED START-UP SEQUENCE AD9739 Data Sheet Table 31. Recommended SPI Initialization with SYNC Controller Disabled Step 1 Address (Hex) 0x00 Write Value 0x00 2 3 4 5 6 7 8 9 10 11 12 13 14 0x00 0x00 0x22 0x23 0x24 0x25 0x27 0x28 0x29 0x26 0x26 Not applicable 0x2A 0x20 0x00 0x0F 0x0F 0x30 0x80 0x44 0x6C 0xCB 0x02 0x03 Not applicable 15 16 17 18 19 20 21 Not applicable 0x13 0x10 0x10 0x10 Not applicable 0x21 Not applicable 0x72 0x00 0x02 0x03 Not applicable 22 23 0x06, 0x07 0x08 0x00, 0x02 0x00 Comments Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto Bits[2:0] because the MSB/LSB format can be unknown at power-up. Software reset to default SPI values. Clear the reset bit. Set the common-mode voltage of DACCLK_P and DACCLK_N inputs. Configure the mu controller. Refer to Table 28 for recommended target mu slope and phase settings vs. clock rate. Enable the mu controller search and track mode. Wait for 160k × 1/fDATA cycles. Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop is locked. If it is not locked, proceed to Step 10 and repeat. Limit attempts to three before breaking out of the loop and reporting a mu lock failure. Ensure that the AD9739 is fed with DCI clock input from the data source. Set FINE_DEL_SKEW to 2. Disable the data Rx controller before enabling it. Enable the data Rx controller for loop and IRQ. Enable the data Rx controller for search and track mode. Wait for 135 K × 1/fDATA cycles. Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop is locked and tracking. If it is not locked and tracking, advance the CLKDIVPH[1:0] phase in Register 0x14, Bit[7:6] before proceeding to Step 17 to repeat attempt. Limit attempts to three before breaking out of the loop and reporting an Rx data lock failure. Optional: modify the TxDAC IOUTFS setting (the default is 20 mA). Optional: modify the TxDAC operation mode (the default is normal mode). Rev. E | Page 48 of 50 Data Sheet AD9739 Table 32. Recommended SPI Initialization with SYNC Controller Enabled Step 1 Address (Hex) 0x00 Write Value 0x00 2 3 4 5 6 7 8 9 10 11 12 13 14 0x00 0x00 0x22 0x23 0x24 0x25 0x27 0x28 0x29 0x26 0x26 Not applicable 0x2A 0x20 0x00 0x0F 0x0F 0x30 0x80 0x44 0x6C 0xCB 0x02 0x03 Not applicable 15 16 17 0x15 0x10 0x10 0x42 0x00 0x60 or 0x40 18 0x10 0x70 or 0x50 19 20 Not applicable 0x21 Not applicable 21 0x0D 22 23 24 Not applicable 0x13 0x10 Not applicable 0x72 0x70 or 0x50 25 0x10 0x72 or 0x52 26 0x10 0x73 or 0x53 27 28 0x21 29 Not applicable Not applicable 30 31 0x06, 0x07 0x08 0x00, 0x02 0x00 Comments Configure for the 4-wire SPI mode with MSB. Note that Bits[7:5] must be mirrored onto Bits[2:0] because the MSB/LSB format can be unknown at power-up. Software reset to default SPI values. Clear the reset bit. Set the common-mode voltage of DACCLK_P and DACCLK_N inputs. Configure the mu controller. Refer to Table 28 for recommended target mu slope and phase settings vs. clock rate. Enable the mu controller search and track mode. Wait for 160k × 1/fDATA cycles. Read back Register 0x2A and confirm that it is equal to 0x01 to ensure that the DLL loop is locked. If it is not locked, proceed to Step 10 and repeat. Limit attempts to three before breaking out of the loop and reporting a mu lock failure. Configure sync controller. Disable sync controller before enabling it. Enable sync controller for loop and IRQ. 0x60 = master mode. 0x40 = slave mode. Enable sync controller: 0x70 = master mode. 0x50 = slave mode. Wait for 160k × 1/fDATA for DLL to lock. Read back Register 0x21 to confirm proper operation: 0x90 = master mode. 0x00 = slave mode. If not, proceed to Step 15 and repeat. Limit to three attempts before breaking out of loop and reporting sync lock failure. Read back Register 0x0D and confirm Bits[5:4] = 10. If not, proceed to Step 2 and repeat. Limit to three attempts before breaking out of loop and reporting sync lock failure. Ensure that the AD9739 is fed with DCI clock input from the data source. Set FINE_DEL_SKEW to 2. Disable the data Rx controller before enabling it. 0x70 = master mode. 0x50 = slave mode. Enable the data Rx controller for loop and IRQ. 0x72 = master mode. 0x52 = slave mode. Enable the data Rx controller for search and track mode. 0x73 = master mode. 0x53 = slave mode. Wait for 135k × 1/fDATA cycles. Read back Register 0x21 and confirm that it is equal to 0x09 to ensure that the DLL loop is locked and tracking. If it is not locked and tracking, proceed to Step 16 and repeat. Limit attempts to three before breaking out of the loop and reporting an Rx data lock failure. Readback DCI_DEL value in Register 0x13 and Register 0x14 for master and slave. If slave devices are not within 40 codes of each other, re-specify target DCI_DEL value to be average between master and readback DCI_DEL value. Optional: modify the TxDAC IOUTFS setting (the default is 20 mA). Optional: modify the TxDAC operation mode (the default is normal mode). Rev. E | Page 49 of 50 AD9739 Data Sheet OUTLINE DIMENSIONS 14 13 12 11 10 9 8 7 6 5 4 3 2 A1 BALL CORNER 1 A B C D E F G H J K L M N P 10.40 BSC SQ 0.80 BSC BOTTOM VIEW TOP VIEW DETAIL A 0.43 MAX 0.25 MIN 1.40 MAX SEATING PLANE DETAIL A 1.00 MAX 0.85 MIN 0.55 0.50 0.45 BALL DIAMETER COPLANARITY 0.12 COMPLIANT WITH JEDEC STANDARDS MO-275-GGAA-1. 11-18-2011-A A1 BALL CORNER 12.10 12.00 SQ 11.90 Figure 75. 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-160-1) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9739BBCZ AD9739BBCZRL AD9739BBC AD9739BBCRL AD9739-R2-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 160-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board Z = RoHS Compliant Part. ©2009–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07851-0-6/18(E) Rev. E | Page 50 of 50 Package Option BC-160-1 BC-160-1 BC-160-1 BC-160-1