12-Bit, 210 MSPS
TxDAC® D/A Converter
AD9742
FEATURES
APPLICATIONS
High performance member of pin-compatible
TxDAC product family
Excellent spurious-free dynamic range performance
SNR @ 5 MHz output, 125 MSPS: 70 dB
Twos complement or straight binary data format
Differential current outputs: 2 mA to 20 mA
Power dissipation: 135 mW @ 3.3 V
Power-down mode: 15 mW @ 3.3 V
On-chip 1.2 V Reference
CMOS compatible digital interface
28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP
packages
Edge-triggered latches
Wideband communication transmit channel:
Direct IF
Base stations
Wireless local loops
Digital radio links
Direct digital synthesis (DDS)
Instrumentation
FUNCTIONAL BLOCK DIAGRAM
3.3V
REFIO
FS ADJ
RSET
3.3V
CURRENT
SOURCE
ARRAY
DVDD
DCOM
CLOCK
AVDD
150pF
ACOM
AD9742
IOUTA
SEGMENTED
SWITCHES
CLOCK
LSB
SWITCHES
IOUTB
LATCHES
MODE
DIGITAL DATA INPUTS (DB11–DB0)
SLEEP
02913-B-001
0.1µF
REFLO
1.2V REF
Figure 1.
GENERAL DESCRIPTION
The AD97421 is a 12-bit resolution, wideband, third generation
member of the TxDAC series of high performance, low power
CMOS digital-to-analog converters (DACs). The TxDAC family,
consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is
specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface
options, small outline package, and pinout, providing an upward
or downward component selection path based on performance,
resolution, and cost. The AD9742 offers exceptional ac and dc
performance while supporting update rates up to 210 MSPS.
The AD9742’s low power dissipation makes it well suited for
portable and low power applications. Its power dissipation can
be further reduced to a mere 60 mW with a slight degradation
in performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 15 mW. A segmented current source architecture
is combined with a proprietary switching technique to reduce
spurious components and enhance dynamic performance.
Edge-triggered input latches and a 1.2 V temperature compensated band gap reference have been integrated to provide a
complete monolithic DAC solution. The digital inputs support
3 V CMOS logic families.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
1
The AD9742 is the 12-bit member of the pin-compatible
TxDAC family, which offers excellent INL and DNL
performance.
Data input supports twos complement or straight binary
data coding.
High speed, single-ended CMOS clock input supports
210 MSPS conversion rate.
Low power: Complete CMOS DAC function operates on
135 mW from a 2.7 V to 3.6 V single supply. The DAC fullscale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
On-chip voltage reference: The AD9742 includes a 1.2 V
temperature compensated band gap voltage reference.
Industry-standard 28-lead SOIC, 28-lead TSSOP, and
32-lead LFCSP packages.
Protected by U.S. Patent Numbers 5568145, 5689257, and 5703519.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9742
TABLE OF CONTENTS
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
Dynamic Specifications ............................................................... 4
Digital Specifications ................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Functional Description .................................................................. 12
Reference Operation .................................................................. 12
Reference Control Amplifier..................................................... 13
DAC Transfer Function ............................................................. 13
Analog Outputs........................................................................... 13
Digital Inputs .............................................................................. 14
Clock Input.................................................................................. 14
DAC Timing................................................................................ 15
Power Dissipation....................................................................... 15
Applying the AD9742 ................................................................ 16
Differential Coupling Using a Transformer................................ 16
Differential Coupling Using an Op Amp ................................ 16
Single-Ended, Unbuffered Voltage Output ............................. 17
Single-Ended, Buffered Voltage Output Configuration ........ 17
REVISION HISTORY
6/04—Data Sheet Changed from Rev. A to Rev. B
Changes to the Title.................................................................................1
Changes to General Description............................................................1
Changes to Product Highlights..............................................................1
Changes to Dynamic Specifications......................................................4
Changes to Figures 6 and 10...................................................................9
Changes to Figures 12 to 15 .................................................................10
Changes to the Functional Description Section................................12
Changes to the Digital Inputs Section ................................................14
Changes to Figure 29.............................................................................15
Changes to Figure 30.............................................................................16
5/03—Data Sheet Changed from Rev. 0 to Rev. A
Added 32-Lead LFCSP Package ........................................... Universal
Edits to Features..................................................................................... 1
Edits to Product Highlights.................................................................. 1
Edits to DC Specifications.................................................................... 2
Edits to Dynamic Specifications.......................................................... 3
Edits to Digital Specifications .............................................................. 4
Edits to Absolute Maximum Ratings.................................................. 5
Edits to Thermal Characteristics......................................................... 5
Edits to Ordering Guide ....................................................................... 5
Edits to Pin Configuration ................................................................... 6
Edits to Pin Function Descriptions..................................................... 6
Edits to Figure 2 ..................................................................................... 7
Replaced TPCs 1, 4, 7, and 8 ................................................................ 8
Edits to Figure 3 ................................................................................... 10
Edits to Functional Description Section .......................................... 10
Added Clock Input Section................................................................ 12
Added Figure 7..................................................................................... 12
Edits to DAC Timing Section ............................................................ 12
Edits to Sleep Mode Operation Section............................................ 13
Edits to Power Dissipation Section................................................... 13
Renumbered Figures 8 to 26 .............................................................. 13
Added Figure 11................................................................................... 13
Added Figures 27 to 35 ....................................................................... 21
Updated Outline Dimensions............................................................ 26
5/02—Revision 0: Initial Version
Power and Grounding Considerations, Power Supply
Rejection ...................................................................................... 17
Evaluation Board ............................................................................ 19
General Description................................................................... 19
Outline Dimensions ....................................................................... 29
Ordering Guide........................................................................... 30
Rev. B | Page 2 of 32
AD9742
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (Ext. Reference)
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
CLKVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)4
Clock Supply Current (ICLKVDD)
Supply Current Sleep Mode (IAVDD)
Power Dissipation4
Power Dissipation5
Power Supply Rejection Ratio—AVDD6
Power Supply Rejection Ratio—DVDD6
OPERATING RANGE
Min
12
Typ
Max
Unit
Bits
−2.5
−1.3
±0.5
±0.4
+2.5
+1.3
LSB
LSB
+0.02
+0.5
+0.5
20
+1.25
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
1.26
V
nA
1.25
1
0.5
V
MΩ
MHz
0
±50
±100
±50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
−0.02
−0.5
−0.5
2
−1
±0.1
±0.1
100
5
1.14
1.20
100
0.1
2.7
2.7
2.7
−1
−0.04
−40
1
3.3
3.3
3.3
33
8
5
5
135
145
3.6
3.6
3.6
36
9
6
6
145
+1
+0.04
+85
Measured at IOUTA, driving a virtual ground.
Nominal full-scale current, IOUTFS, is 32 times the IREF current.
3
An external buffer amplifier with input bias current 100 kΩ).
AD9742
REFERENCE CONTROL AMPLIFIER
VOUTA = IOUTA× RLOAD
(5)
The AD9742 contains a control amplifier that is used to regulate
the full-scale output current, IOUTFS. The control amplifier is
configured as a V-I converter, as shown in Figure 24, so that its
current output, IREF, is determined by the ratio of the VREFIO and
an external resistor, RSET, as stated in Equation 4. IREF is copied to
the segmented current sources with the proper scale factor to
set IOUTFS, as stated in Equation 3.
VOUTB = IOUTB × RLOAD
(6)
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5 µA and 625 µA. The wide adjustment span of IOUTFS
provides several benefits. The first relates directly to the power
dissipation of the AD9742, which is proportional to IOUTFS
(see the Power Dissipation section). The second relates to the
20 dB adjustment, which is useful for system gain control
purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency small
signal multiplying applications.
DAC TRANSFER FUNCTION
Both DACs in the AD9742 provide complementary current
outputs, IOUTA and IOUTB. IOUTA provides a near full-scale
current output, IOUTFS, when all bits are high (i.e., DAC CODE =
4095), while IOUTB, the complementary output, provides no
current. The current output appearing at IOUTA and IOUTB is
a function of both the input code and IOUTFS and can be
expressed as:
IOUTA = (DAC CODE / 4096 )× I OUTFS
(1)
IOUTB = (4095 − DAC CODE )/4096 × I OUTFS
(2)
where DAC CODE = 0 to 4095 (i.e., decimal representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage, VREFIO,
and external resistor, RSET. It can be expressed as:
I OUTFS = 32 × I REF
(3)
where
I REF = VREFIO / RSET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note that
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply
Note that the full-scale value of VOUTA and VOUTB should not
exceed the specified output compliance range to maintain
specified distortion and linearity performance.
VDIFF = (IOUTA − IOUTB) × RLOAD
(7)
Substituting the values of IOUTA, IOUTB, IREF, and VDIFF can be
expressed as:
V DIFF = {(2 × DAC CODE − 4095)/ 4096}
(32 × RLOAD / RSET )× VREFIO
(8)
Equations 7 and 8 highlight some of the advantages of operating the AD9742 differentially. First, the differential operation
helps cancel common-mode error sources associated with
IOUTA and IOUTB, such as noise, distortion, and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the
AD9742 can be enhanced by selecting temperature tracking
resistors for RLOAD and RSET due to their ratiometric relationship,
as shown in Equation 8.
ANALOG OUTPUTS
The complementary current outputs in each DAC, IOUTA, and
IOUTB may be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a
load resistor, RLOAD, as described in the DAC Transfer Function
section by Equations 5 through 8. The differential voltage, VDIFF,
existing between VOUTA and VOUTB, can also be converted to a
single-ended voltage via a transformer or differential amplifier
configuration. The ac performance of the AD9742 is optimum
and specified using a differential transformer-coupled output in
which the voltage swing at IOUTA and IOUTB is limited to
±0.5 V.
The distortion and noise performance of the AD9742 can be
enhanced when it is configured for differential operation. The
common-mode error sources of both IOUTA and IOUTB can
be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed waveform increases and/or its amplitude decreases. This is due to the
first-order cancellation of various dynamic common-mode
distortion mechanisms, digital feedthrough, and noise.
Rev. B | Page 13 of 32
AD9742
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the
reconstructed signal power to the load (assuming no source
termination). Since the output currents of IOUTA and IOUTB
are complementary, they become additive when processed differentially. A properly selected transformer will allow the
AD9742 to provide the required power and voltage levels to
different loads.
The output impedance of IOUTA and IOUTB is determined
by the equivalent parallel combination of the PMOS switches
associated with the current sources and is typically 100 kΩ in
parallel with 5 pF. It is also slightly dependent on the output
voltage (i.e., VOUTA and VOUTB) due to the nature of a PMOS
device. As a result, maintaining IOUTA and/or IOUTB at a
virtual ground via an I-V op amp configuration will result in
the optimum dc linearity. Note that the INL/DNL specifications
for the AD9742 are measured with IOUTA maintained at a virtual ground via an op amp.
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the
AD9742.
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from its
nominal 1.2 V for an IOUTFS = 20 mA to 1 V for an IOUTFS = 2 mA.
The optimum distortion performance for a single-ended or
differential output is achieved when the maximum full-scale
signal at IOUTA and IOUTB does not exceed 0.5 V.
DIGITAL INPUTS
The AD9742 digital section consists of 12 input bit channels
and a clock input. The 12-bit parallel data inputs follow standard positive binary coding, where DB11 is the most significant
bit (MSB) and DB0 is the least significant bit (LSB). IOUTA
produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the
full-scale current split between the two outputs as a function of
the input code.
DVDD
02912-B-024
DIGITAL
INPUT
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC output updates on the rising edge
of the clock and is designed to support a clock rate as high as
210 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock.
CLOCK INPUT
SOIC/TSSOP Packages
The 28-lead package options have a single-ended clock input
(CLOCK) that must be driven to rail-to-rail CMOS levels. The
quality of the DAC output is directly related to the clock quality,
and jitter is a key concern. Any noise or jitter in the clock will
translate directly into the DAC output. Optimal performance
will be achieved if the CLOCK input has a sharp rising edge,
since the DAC latches are positive edge triggered.
LFCSP Package
A configurable clock input is available in the LFCSP package,
which allows for one single-ended and two differential modes.
The mode selection is controlled by the CMODE input, as
summarized in Table 6. Connecting CMODE to CLKCOM
selects the single-ended clock input. In this mode, the CLK+
input is driven with rail-to-rail swings and the CLK− input is
left floating. If CMODE is connected to CLKVDD, the differential receiver mode is selected. In this mode, both inputs are high
impedance. The final mode is selected by floating CMODE.
This mode is also differential, but internal terminations for
positive emitter-coupled logic (PECL) are activated. There is no
significant performance difference between any of the three
clock input modes.
Table 6. Clock Mode Selection
CMODE Pin
CLKCOM
CLKVDD
Float
Clock Input Mode
Single-Ended
Differential
PECL
The single-ended input mode operates in the same way as the
CLOCK input in the 28-lead packages, as described previously.
In the differential input mode, the clock input functions as a
high impedance differential pair. The common-mode level of
the CLK+ and CLK− inputs can vary from 0.75 V to 2.25 V, and
the differential voltage can be as low as 0.5 V p-p. This mode
can be used to drive the clock with a differential sine wave since
the high gain bandwidth of the differential inputs will convert
the sine wave into a single-ended square wave internally.
Figure 25. Equivalent Digital Input
Rev. B | Page 14 of 32
AD9742
The final clock mode allows for a reduced external component
count when the DAC clock is distributed on the board using
PECL logic. The internal termination configuration is shown in
Figure 26. These termination resistors are untrimmed and can
vary up to ±20%. However, matching between the resistors
should generally be better than ±1%.
CLOCK
RECEIVER
•
•
•
•
TO DAC CORE
02912-B-025
50Ω
VTT = 1.3V NOM
Figure 26. Clock Termination in PECL Mode
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship between the position of the clock edges and the time at
which the input data changes. The AD9742 is rising edge
triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the goal
when applying the AD9742 is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 27 shows the relationship of SFDR
to clock placement with different sample rates. Note that at the
lower sample rates, more tolerance is allowed in clock placement, while at higher rates, more care must be taken.
The power supply voltages (AVDD, CLKVDD, and DVDD)
The full-scale current output IOUTFS
The update rate fCLOCK
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD. IAVDD
is directly proportional to IOUTFS, as shown in Figure 28, and is
insensitive to fCLOCK. Conversely, IDVDD is dependent on both the
digital input waveform, fCLOCK, and digital supply DVDD. Figure
29 shows IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
35
30
25
IAVDD (mA)
CLK+
50Ω
POWER DISSIPATION
The power dissipation, PD, of the AD9742 is dependent on
several factors that include:
AD9742
CLK–
active pull-down circuit that ensures that the AD9742 remains
enabled if this input is left disconnected. The AD9742 takes less
than 50 ns to power down and approximately 5 µs to power
back up.
20
15
75
65
0
dB
2
20MHz SFDR
60
4
6
8
10
12
IOUTFS (mA)
14
16
18
20
02912-B-027
10
70
Figure 28. IAVDD vs. IOUTFS
55
50MHz SFDR
20
50
18
45
16
40
210MSPS
14
0
ns
1
2
3
Figure 27. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz
12
8
Sleep Mode Operation
6
The AD9742 has a power-down function that turns off the
output current and reduces the supply current to less than 6 mA
over the specified supply range of 2.7 V to 3.6 V and temperature range. This mode can be activated by applying a Logic
Level 1 to the SLEEP pin. The SLEEP pin logic threshold is
equal to 0.5 Ω AVDD. This digital input also contains an
4
Rev. B | Page 15 of 32
165MSPS
10
125MSPS
65MSPS
2
0
0.01
0.1
RATIO (fOUT/fCLOCK)
Figure 29. IDVDD vs. Ratio @ DVDD = 3.3 V
1
02912-B-028
–1
IDVDD (mA)
–2
02912-B-026
50MHz SFDR
35
–3
AD9742
12
for impedance matching purposes. Note that the transformer
provides ac coupling only.
10
MINI-CIRCUITS
T1-1T
IOUTA 22
8
PECL
RLOAD
AD9742
6
IOUTB 21
02912-B-030
OPTIONAL RDIFF
4
SE
Figure 31. Differential Output Using a Transformer
0
0
50
100
150
200
fCLOCK (MSPS)
250
02912-B-029
2
Figure 30. ICLKVDD vs. fCLOCK and Clock Mode
APPLYING THE AD9742
Output Configurations
The following sections illustrate some typical output
configurations for the AD9742. Unless otherwise noted, it is
assumed that IOUTFS is set to a nominal 20 mA. For applications
requiring the optimum dynamic performance, a differential
output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential
op amp configuration. The transformer configuration provides
the optimum high frequency performance and is recommended
for any application that allows ac coupling. The differential op
amp configuration is suitable for applications requiring dc
coupling, a bipolar output, signal gain, and/or level shifting
within the bandwidth of the chosen op amp.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if IOUTA and/or IOUTB are connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This
configuration may be more suitable for a single-supply system
requiring a dc-coupled, ground-referred output voltage. Alternatively, an amplifier could be configured as an I-V converter,
thus converting IOUTA or IOUTB into a negative unipolar
voltage. This configuration provides the best dc linearity since
IOUTA or IOUTB is maintained at a virtual ground.
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing
symmetrically around ACOM and should be maintained with
the specified output compliance range of the AD9742. A differential resistor, RDIFF, may be inserted in applications where the
output of the transformer is connected to the load, RLOAD, via a
passive reconstruction filter or cable. RDIFF is determined by the
transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF.
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 32. The AD9742 is
configured with two equal load resistors, RLOAD, of 25 Ω. The
differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp’s distortion
performance by preventing the DAC’s high slewing output from
overloading the op amp’s input.
500Ω
AD9742
225Ω
IOUTA 22
225Ω
IOUTB 21
AD8047
COPT
500Ω
25Ω
25Ω
DIFFERENTIAL COUPLING USING A TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 31. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content lies within the transformer’s pass band. An RF transformer,
such as the Mini-Circuits T1–1T, provides excellent rejection of
common-mode distortion (i.e., even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios may also be used
02912-B-031
ICLKVDD (mA)
DIFF
Figure 32. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8047 is configured to provide
some additional signal gain. The op amp must operate off a dual
supply since its output is approximately ±1 V. A high speed
amplifier capable of preserving the differential performance of
the AD9742 while meeting other system level objectives (e.g.,
cost or power) should be selected. The op amp’s differential gain,
gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit.
Rev. B | Page 16 of 32
AD9742
500Ω
AD9742
225Ω
IOUTA 22
COPT
25Ω
1kΩ
25Ω
AVDD
1kΩ
02912-B-032
AD8041
225Ω
IOUTB 21
Figure 33. Single-Supply DC Differential Coupled Circuit
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 34 shows the AD9742 configured to provide a unipolar
output range of approximately 0 V to 0.5 V for a doubly terminated 50 Ω cable since the nominal full-scale current, IOUTFS, of
20 mA flows through the equivalent RLOAD of 25 Ω. In this case,
RLOAD represents the equivalent load resistance seen by IOUTA
or IOUTB. The unused output (IOUTA or IOUTB) can be
connected to ACOM directly or via a matching RLOAD. Different
values of IOUTFS and RLOAD can be selected as long as the positive
compliance range is adhered to. One additional consideration in
this mode is the integral nonlinearity (INL), discussed in the
Analog Outputs section. For optimum INL performance, the
single-ended, buffered voltage output configuration is
suggested.
AD9742
IOUTFS = 20mA
VOUTA = 0V TO 0.5V
IOUTA 22
50Ω
25Ω
Figure 34. 0 V to 0.5 V Unbuffered Voltage Output
02912-B-033
50Ω
IOUTB 21
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 35 shows a buffered single-ended output configuration
in which the op amp U1 performs an I-V conversion on the
AD9742 output current. U1 maintains IOUTA (or IOUTB) at a
virtual ground, minimizing the nonlinear output impedance
effect on the DAC’s INL performance as described in the
Analog Outputs section. Although this single-ended configuration typically provides the best dc linearity performance, its ac
distortion performance at higher DAC update rates may be
limited by U1’s slew rate capabilities. U1 provides a negative
unipolar output voltage, and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be
set within U1’s voltage output swing capabilities by scaling IOUTFS
and/or RFB. An improvement in ac distortion performance may
result with a reduced IOUTFS since U1 will be required to sink less
signal current.
COPT
RFB
200Ω
IOUTFS = 10mA
AD9742
IOUTA 22
U1
VOUT = IOUTFS × RFB
IOUTB 21
200Ω
02912-B-034
The differential circuit shown in Figure 33 provides the
necessary level shifting required in a single-supply system. In
this case, AVDD, which is the positive analog supply for both
the AD9742 and the op amp, is also used to level shift the
differential output of the AD9742 to midsupply (i.e., AVDD/2).
The AD8041 is a suitable op amp for this application.
Figure 35. Unipolar Buffered Voltage Output
POWER AND GROUNDING CONSIDERATIONS,
POWER SUPPLY REJECTION
Many applications seek high speed and high performance
under less than ideal operating conditions. In these application
circuits, the implementation and construction of the printed
circuit board is as important as the circuit design. Proper RF
techniques must be used for device selection, placement, and
routing as well as power supply bypassing and grounding to
ensure optimum performance. Figure 40 to Figure 43
illustrate the recommended printed circuit board ground,
power, and signal plane layouts implemented on the AD9742
evaluation board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is generated by a switching power supply. Typically, switching power
supply noise will occur over the spectrum from tens of kHz to
several MHz. The PSRR versus frequency of the AD9742 AVDD
supply over this frequency range is shown in Figure 36.
Rev. B | Page 17 of 32
AD9742
85
appear as current noise superimposed on the DAC’s full-scale
current, IOUTFS, one must determine the PSRR in dB using Figure 36
at 250 kHz. To calculate the PSRR for a given RLOAD, such that the
units of PSRR are converted from A/V to V/V, adjust the curve in
Figure 36 by the scaling factor 20 Ω log (RLOAD). For instance, if
RLOAD is 50 Ω, the PSRR is reduced by 34 dB (i.e., PSRR of the DAC
at 250 kHz, which is 85 dB in Figure 36, becomes 51 dB VOUT/VIN).
75
PSRR (dB)
70
65
60
55
50
40
0
2
4
6
8
FREQUENCY (MHz)
10
12
02912-B-035
45
Figure 36. Power Supply Rejection Ratio (PSRR)
Note that the ratio in Figure 36 is calculated as amps out/volts
in. Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. The
voltage noise on AVDD, therefore, will be added in a nonlinear
manner to the desired IOUT. Due to the relative different size
of these switches, the PSRR is very code dependent. This can
produce a mixing effect that can modulate low frequency power
supply noise to higher frequencies. Worst-case PSRR for either
one of the differential DAC outputs will occur when the fullscale current is directed toward that output. As a result, the
PSRR measurement in Figure 36 represents a worst-case condition in which the digital inputs remain static and the full-scale
output current of 20 mA is directed to the DAC output being
measured.
Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9742
features separate analog and digital supplies and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, AVDD, the analog supply, should be
decoupled to ACOM, the analog common, as close to the chip
as physically possible. Similarly, DVDD, the digital supply,
should be decoupled to DCOM as close to the chip as physically
possible.
For those applications that require a single 3.3 V supply for both
the analog and digital supplies, a clean analog supply may be
generated using the circuit shown in Figure 37. The circuit consists of a differential LC filter with separate power supply and
return lines. Lower noise can be attained by using low ESR type
electrolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s sake (ignoring harmonics), all of this noise is concentrated
at 250 kHz. To calculate how much of this undesired noise will
Rev. B | Page 18 of 32
AVDD
100µF
ELECT.
10µF–22µF
TANT.
0.1µF
CER.
ACOM
3.3V
POWER SUPPLY
Figure 37. Differential LC Filter for Single 3.3 V Applications
02912-B-036
80
AD9742
EVALUATION BOARD
GENERAL DESCRIPTION
The TxDAC family evaluation boards allow for easy setup and
testing of any TxDAC product in the SOIC and LFCSP packages. Careful attention to layout and circuit design, combined
with a prototyping area, allows the user to evaluate the AD9742
easily and effectively in any application where high resolution,
high speed conversion is required.
This board allows the user the flexibility to operate the AD9742
in various configurations. Possible output configurations
include transformer coupled, resistor terminated, and single and
differential outputs. The digital inputs are designed to be driven
from various word generators, with the on-board option to add
a resistor network for proper load termination. Provisions are
also made to operate the AD9742 with either the internal or
external reference or to exercise the power-down feature.
JP3
CKEXTX
L2
BEAD
RED
TP2
DVDD
TB1 1
C7
0.1µF
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
BLK
TP4
+ C4
10µF
25V
C6
0.1µF
BLK
TP7
1 DCOM
2 R1
3 R2
4 R3
5 R4
6 R5
7 R6
8 R7
9 R8
10 R9
RP3
RP3
RP3
RP3
RP3
RP3
RP3
RP3
RP4
RP4
RP4
RP4
RP4
RP4
RP4
8 RP4
CKEXTX
RIBBON
RP5
OPT
RP1
OPT
22Ω 16
22Ω 15
22Ω 14
22Ω 13
22Ω 12
22Ω 11
22Ω 10
22Ω 9
22Ω 16
22Ω 15
22Ω 14
22Ω 13
22Ω 12
22Ω 11
22Ω 10
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
22Ω 9
RP6
OPT
CKEXT
DCOM 1
R1 2
R2 3
R3 4
R4 5
R5 6
R6 7
R7 8
R8 9
R9 10
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
1
2
3
4
5
6
7
8
9
10
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
DCOM 1
R1 2
R2 3
R3 4
R4 5
R5 6
R6 7
R7 8
R8 9
R9 10
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
DCOM
R1
R2
R3
R4
R5
R6
R7
R8
R9
J1
RP2
OPT
BLK
TP8
TB1 2
L3
BEAD
RED
TP5
C9
0.1µF
BLK
TP6
+ C5
10µF
25V
C8
0.1µF
BLK
TP10
BLK
TP9
TB1 4
Figure 38. SOIC Evaluation Board—Power Supply and Digital Inputs
Rev. B | Page 19 of 32
02912-B-037
AVDD
TB1 3
AD9742
AVDD
+ C14
10µF
16V
C16
0.1µF
CUT
UNDER DUT
C17
0.1µF
JP6
DVDD
C18
0.1µF
DVDD
C19
0.1µF
R5
OPT
CKEXT
3
R11
50Ω
S5
JP4
AVDD
JP10
A B
2
S2
IOUTA
CLOCK
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
IX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLOCK
DVDD
DCOM
MODE
AVDD
RESERVED
IOUTA
U1
AD9742 IOUTB
ACOM
NC
FS ADJ
REFIO
REFLO
SLEEP
2
A B
3
1
JP5
INT
EXT
REF
28
27
26
25
24
23
22
21
20
19
18
17
16
15
CLOCK
TP1
WHT
DVDD
R4
50Ω
R2
10kΩ
C13
OPT
DVDD
JP8
JP2
IOUT
MODE
AVDD
3
T1
2
R6
OPT
4
5
1
S3
6
T1-1T
REF
R1
2kΩ
TP3
WHT
C11
0.1µF
C1
0.1µF
C2
0.1µF
C12
OPT
JP9
AVDD
SLEEP
TP11
WHT
R10
50Ω
S1
IOUTB
R3
10kΩ
IY
Figure 39. SOIC Evaluation Board—Output Signal Conditioning
Rev. B | Page 20 of 32
1
2
A B
3
JP11
02912-B-038
+ C15
10µF
16V
02912-B-039
AD9742
02912-B-040
Figure 40. SOIC Evaluation Board—Primary Side
Figure 41. SOIC Evaluation Board—Secondary Side
Rev. B | Page 21 of 32
02912-B-041
AD9742
02912-B-042
Figure 42. SOIC Evaluation Board—Ground Plane
Figure 43. SOIC Evaluation Board—Power Plane
Rev. B | Page 22 of 32
02912-B-043
AD9742
02912-B-044
Figure 44. SOIC Evaluation Board Assembly—Primary Side
Figure 45. SOIC Evaluation Board Assembly—Secondary Side
Rev. B | Page 23 of 32
AD9742
RED
TP12
TB1
CVDD
1
C3
0.1µF
TB1
BLK
C2
10µF
6.3V
TP2
C10
0.1µF
2
2
4
1
3
6
5
8
7
DB10X
10
9
DB9X
11
DB8X
13
DB7X
15
DB6X
17
DB5X
19
DB4X
21
DB3X
23
DB2X
25
DB1X
27
DB0X
12
L2 BEAD
TB3
16
DVDD
1
C7
0.1µF
TB3
14
RED
TP13
18
20
BLK
C4
10µF
6.3V
TP4
C6
0.1µF
22
24
26
2
28
RED
TP5
L3 BEAD
C9
0.1µF
TB4
32
AVDD
1
BLK
C5
10µF
6.3V
TP6
34
36
C8
0.1µF
38
40
2
DB13X
DB12X
DB11X
29
31
33
35
JP3
CKEXTX
37
39
J1
R3
100Ω
R4
100Ω
R15
100Ω
R16
100Ω
R17
100Ω
R18
100Ω
R19
100Ω
DB13X
DB12X
DB11X
DB10X
DB9X
DB8X
DB7X
DB6X
DB5X
DB4X
DB3X
DB2X
DB1X
DB0X
CKEXTX
R21
100Ω
R24
100Ω
R25
100Ω
R26
100Ω
R27
100Ω
R20
100Ω
1 RP3
22Ω 16
2 RP3
22Ω 15
3 RP3
22Ω 14
4 RP3
22Ω 13
5 RP3
22Ω 12
6 RP3
22Ω 11
7 RP3
22Ω 10
8 RP3
22Ω 9
1 RP4
22Ω 16
2 RP4
22Ω 15
3 RP4
22Ω 14
4 RP4
22Ω 13
5 RP4
22Ω 12
6 RP4
7 RP4
22Ω 11
22Ω 10
8 RP4
22Ω 9
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CKEXT
R28
100Ω
02912-B-045
TB4
30
HEADER STRAIGHT UP MALE NO SHROUD
L1 BEAD
Figure 46. LFCSP Evaluation Board Schematic—Power Supply and Digital Inputs
Rev. B | Page 24 of 32
AD9742
AVDD
DVDD
CVDD
C19
0.1
0.1µF
C17
0.1µF
C32
0.1µF
SLEEP
TP11
WHT
R29
10kΩ
DB7
DB6
DVDD
DB5
DB4
DB3
DB2
DB1
DB0
CVDD
CLK
CLKB
CMODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DB7
DB6
DVDD
DB5
DB4
DB3
DB2
DB1
DB0
DCOM
U1
CVDD
CLK
CLKB
CCOM
CMODE
MODE
DB8
DB9
DB10
DB11
DB12
DB13
DCOM1
SLEEP
FS ADJ
REFIO
ACOM
IA
IB
ACOM1
AVDD
AVDD1
32
31
30
29
28
27
DB8
DB9
DB10
DB11
DB12
DB13
R11
50Ω
DNP
C13
26
25
24
23
22
TP3
TP1
WHT
WHT
JP8
IOUT
3
21
20
19
18
17
TP7
4
S3
AGND: 3, 4, 5
5
2
6
1
AVDD
T1 – 1T
C11
0.1µF
JP9
AD9744LFCSP
WHT
T1
DNP
C12
R30
10kΩ
R10
50Ω
CVDD
R1
2kΩ
0.1%
JP1
02912-B-046
MODE
Figure 47. LFCSP Evaluation Board Schematic—Output Signal Conditioning
CVDD
1
7
U4
C20
10µF
16V
2
AGND: 5
CVDD: 8
C35
0.1µF
CVDD
R5
120Ω
3
JP2
CKEXT
CLK
U4
6
S5
AGND: 3, 4, 5
4
AGND: 5
CVDD: 8
R2
120Ω
C34
0.1µF
R6
50Ω
02912-B-047
CLKB
Figure 48. LFCSP Evaluation Board Schematic—Clock Input
Rev. B | Page 25 of 32
02912-B-048
AD9742
02912-B-049
Figure 49. LFCSP Evaluation Board Layout—Primary Side
Figure 50. LFCSP Evaluation Board Layout—Secondary Side
Rev. B | Page 26 of 32
02912-B-050
AD9742
02912-B-051
Figure 51. LFCSP Evaluation Board Layout—Ground Plane
Figure 52. LFCSP Evaluation Board Layout—Power Plane
Rev. B | Page 27 of 32
02912-B-052
AD9742
02912-B-053
Figure 53. LFCSP Evaluation Board Layout Assembly—Primary Side
Figure 54. LFCSP Evaluation Board Layout Assembly—Secondary Side
Rev. B | Page 28 of 32
AD9742
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
0.15
0.05
COPLANARITY
0.10
0.30
0.19
1.20 MAX
8°
0°
0.20
0.09
SEATING
PLANE
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 55. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
18.10 (0.7126)
17.70 (0.6969)
28
15
7.60 (0.2992)
7.40 (0.2913)
1
14
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
0.75 (0.0295)
× 45°
0.25 (0.0098)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
8°
1.27 (0.0500) 0.51 (0.0201) SEATING
0°
0.32 (0.0126)
BSC
0.33 (0.0130) PLANE
0.23 (0.0091)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AE
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
Figure 56. 28-Lead Standard Small Outline Package [SOIC]
Wide Body (R-28)
Dimensions shown in millimeters and (inches)
Rev. B | Page 29 of 32
AD9742
5.00
BSC SQ
0.60 MAX
32
25
24
PIN 1
INDICATOR
0.50
BSC
4.75
BSC SQ
TOP
VIEW
0.50
0.40
0.30
12° MAX
PIN 1
INDICATOR
0.60 MAX
1
3.25
3.10 SQ
2.95
BOTTOM
VIEW
17
16
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
1.00
0.85
0.80
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body (CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Models
AD9742AR
AD9742ARRL
AD9742ARZ2
AD9742ARZRL2
AD9742ARU
AD9742ARURL7
AD9742ARUZ2
AD9742ARUZRL72
AD9742ACP
AD9742ACPRL7
AD9742ACPZ2
AD9742ACPZRL72
AD9742-EB
AD9742ACP-PCB
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
28-Lead 300-Mil SOIC
28-Lead 300-Mil SOIC
28-Lead 300-Mil SOIC
28-Lead 300-Mil SOIC
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
28-Lead TSSOP
32-Lead LFCSP
32-Lead LFCSP
32-Lead LFCSP
32-Lead LFCSP
Evaluation Board (SOIC)
Evaluation Board (LFCSP)
R = Small Outline IC; RU = Thin Shrink Small Outline Package; CP = Lead Frame Chip Scale Package.
Z = Pb-free part.
Rev. B | Page 30 of 32
Package Options 1
R-28
R-28
R-28
R-28
RU-28
RU-28
RU-28
RU-28
CP-32-2
CP-32-2
CP-32-2
CP-32-2
AD9742
NOTES
Rev. B | Page 31 of 32
AD9742
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
C02912–0–6/04(B)
Rev. B | Page 32 of 32
工商网监
湘ICP备2023018690号
