AD9750-EB

a 10-Bit, 125 MSPS High Performance TxDAC® D/A Converter AD9750 FEATURES High Performance Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 5 MHz Output: 76 dBc Differential Current Outputs: 2 mA to 20 mA Power Dissipation: 190 mW @ 5 V Power-Down Mode: 20 mW @ 5 V On-Chip 1.20 V Reference CMOS-Compatible +2.7 V to +5.5 V Digital Interface Packages: 28-Lead SOIC and TSSOP Edge-Triggered Latches APPLICATIONS Wideband Communication Transmit Channel: Direct IF Basestations Wireless Local Loop Digital Radio Link Direct Digital Synthesis (DDS) Instrumentation PRODUCT DESCRIPTION The AD9750 is a 10-bit resolution, wideband, second generation member of the TxDAC series of high performance, low power CMOS digital-to-analog-converters (DACs). The TxDAC family, which consists of pin compatible 8-, 10-, 12-, and 14-bit DACs, is specifically optimized for the transmit signal path of communication systems. All of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. The AD9750 offers exceptional ac and dc performance while supporting update rates up to 125 MSPS. The AD9750’s flexible single-supply operating range of 4.5 V to 5.5 V and low power dissipation are well suited for portable and low power applications. Its power dissipation can be further reduced to a mere 65 mW, without a significant degradation in performance, by lowering the full-scale current output. Also, a power-down mode reduces the standby power dissipation to apprixmatley 20 mW. The AD9750 is manufactured on an advanced CMOS process. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Edge-triggered input latches and a 1.2 V temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solution. The digital inputs support +2.7 V and +5 V CMOS logic families. TxDAC is a registered trademark of Analog Devices, Inc. *Protected by U.S. Patents Numbers 5450084, 5568145, 5689257, 5612697 and 5703519. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM +5V REFLO 0.1mF RSET +5V ACOM AD9750 CURRENT SOURCE ARRAY DVDD DCOM CLOCK AVDD 150pF +1.20V REF REFIO FS ADJ SEGMENTED SWITCHES CLOCK LSB SWITCH ICOMP 0.1mF IOUTA IOUTB LATCHES SLEEP DIGITAL DATA INPUTS (DB9–DB0) The AD9750 is a current-output DAC with a nominal full-scale output current of 20 mA and > 100 kΩ output impedance. Differential current outputs are provided to support singleended or differential applications. Matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. The current outputs may be tied directly to an output resistor to provide two complementary, single-ended voltage outputs or fed directly into a transformer. The output voltage compliance range is 1.25 V. The on-chip reference and control amplifier are configured for maximum accuracy and flexibility. The AD9750 can be driven by the on-chip reference or by a variety of external reference voltages. The internal control amplifier, which provides a wide (>10:1) adjustment span, allows the AD9750 full-scale current to be adjusted over a 2 mA to 20 mA range while maintaining excellent dynamic performance. Thus, the AD9750 may operate at reduced power levels or be adjusted over a 20 dB range to provide additional gain ranging capabilities. The AD9750 is available in 28-lead SOIC and TSSOP packages. It is specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS 1. The AD9750 is a member of the wideband TxDAC high performance product family that provides an upward or downward component selection path based on resolution (8 to 14 bits), performance and cost. The entire family of TxDACs is available in industry standard pinouts. 2. Manufactured on a CMOS process, the AD9750 uses a proprietary switching technique that enhances dynamic performance beyond that previously attainable by higher power/cost bipolar or BiCMOS devices. 3. On-chip, edge-triggered input CMOS latches interface to +2.7 V to +5 V CMOS logic families. The AD9750 can support update rates up to 125 MSPS. 4. A flexible single-supply operating range of +4.5 V to +5.5 V, and a wide full-scale current adjustment span of 2 mA to 20 mA, allows the AD9750 to operate at reduced power levels. 5. The current output(s) of the AD9750 can be easily configured for various single-ended or differential circuit topologies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9750–SPECIFICATIONS DC SPECIFICATIONS (T MIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted) Parameter Min RESOLUTION 10 DC ACCURACY1 Integral Linearity Error (INL) Differential Nonlinearity (DNL) –1.0 –0.5 ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance REFERENCE OUTPUT Reference Voltage Reference Output Current3 REFERENCE INPUT Input Compliance Range Reference Input Resistance Small Signal Bandwidth Typ OPERATING RANGE Units Bits ± 0.1 ± 0.1 –0.02 –2 –5 2.0 –1.0 +1.0 +0.5 LSB LSB +0.02 +2 +5 20.0 1.25 % of FSR % of FSR % of FSR mA V kΩ pF 1.26 V nA 1.25 1 0.5 V MΩ MHz 0 ± 50 ± 100 ± 50 ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm/°C ± 0.5 ± 1.5 100 5 1.14 1.20 100 0.1 TEMPERATURE COEFFICIENTS Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift POWER SUPPLY Supply Voltages AVDD DVDD Analog Supply Current (IAVDD)4 Digital Supply Current (IDVDD)5 Supply Current Sleep Mode (IAVDD)6 Power Dissipation5 (5 V, IOUTFS = 20 mA) Power Supply Rejection Ratio7—AVDD Power Supply Rejection Ratio7—DVDD Max 4.5 2.7 5.0 5.0 33 5.0 4.0 190 –0.4 –0.025 5.5 5.5 39 7 8 230 +0.4 +0.025 V V mA mA mA mW % of FSR/V % of FSR/V –40 +85 °C NOTES 1 Measured at IOUTA, driving a virtual ground. 2 Nominal full-scale current, I OUTFS, is 32 × the IREF current. 3 Use an external buffer amplifier to drive any external load. 4 Requires +5 V supply. 5 Measured at fCLOCK = 50 MSPS and IOUT = static full scale (20 mA). 6 Logic level for SLEEP pin must be referenced to AVDD. Min V IH = 3.5 V. 7 ± 5% Power supply variation. Specifications subject to change without notice. –2– REV. 0 AD9750 (TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output, DYNAMIC SPECIFICATIONS 50 ⍀ Doubly Terminated, unless otherwise noted) Parameter Min DYNAMIC PERFORMANCE Maximum Output Update Rate (fCLOCK) Output Settling Time (tST) (to 0.1%)1 Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA) Output Noise (IOUTFS = 2 mA) 125 AC LINEARITY Spurious-Free Dynamic Range to Nyquist fCLOCK = 50 MSPS; fOUT = 1.00 MHz 0 dBFS Output TA = +25°C fCLOCK = 50 MSPS; fOUT = 2.51 MHz fCLOCK = 50 MSPS; fOUT = 5.02 MHz fCLOCK = 50 MSPS; fOUT = 20.2 MHz fCLOCK = 100 MSPS; fOUT = 2.51 MHz fCLOCK = 100 MSPS; fOUT = 5.04 MHz fCLOCK = 100 MSPS; fOUT = 20.2 MHz fCLOCK = 100 MSPS; fOUT = 40.4 MHz Spurious-Free Dynamic Range within a Window fCLOCK = 50 MSPS; fOUT = 1.00 MHz fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span fCLOCK = 100 MSPS; fOUT = 5.04 MHz; 4 MHz Span Total Harmonic Distortion fCLOCK = 50 MSPS; fOUT = 1.00 MHz TA = +25°C fCLOCK = 50 MHz; fOUT = 2.00 MHz fCLOCK = 100 MHz; fOUT = 2.00 MHz NOTES 1 Measured single ended into 50 Ω load. Specifications subject to change without notice. REV. 0 Typ –3– Max Units 35 1 5 2.5 2.5 50 30 MSPS ns ns pV-s ns ns pA/√Hz pA/√Hz 71 82 79 76 60 78 77 69 63 dBc dBc dBc dBc dBc dBc dBc dBc 80 87 86 86 dBc dBc dBc –80 –76 –76 dBc dBc dBc AD9750 DIGITAL SPECIFICATIONS (T MIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted) Parameter DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V1 Logic “1” Voltage @ DVDD = +3 V Logic “0” Voltage @ DVDD = +5 V1 Logic “0” Voltage @ DVDD = +3 V Logic “1” Current Logic “0” Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW) Min Typ 3.5 2.1 5 3 0 0 Max Units V V V V µA µA pF ns ns ns 1.3 0.9 +10 +10 –10 –10 5 2.0 1.5 3.5 NOTES 1 When DVDD = +5 V, and Logic 1 voltage ≈3.5 V and Logic 0 voltage ≈1.3 V, IVDD can increase by up to 10 mA depending on f CLOCK. Specifications subject to change without notice. DB0–DB11 tS tH CLOCK tLPW tPD tST IOUTA OR IOUTB 0.1% 0.1% Figure 1. Timing Diagram ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD ACOM AVDD CLOCK, SLEEP Digital Inputs IOUTA, IOUTB ICOMP REFIO, FSADJ REFLO Junction Temperature Storage Temperature Lead Temperature (10 sec) ORDERING GUIDE With Respect to Min Max Units Model ACOM DCOM DCOM DVDD DCOM DCOM ACOM ACOM ACOM ACOM –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –1.0 –0.3 –0.3 –0.3 +6.5 +6.5 +0.3 +6.5 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +0.3 +150 +150 V V V V V V V V V V °C °C AD9750AR –40°C to +85°C 28-Lead 300 Mil SOIC R-28 AD9750ARU –40°C to +85°C 28-Lead TSSOP RU-28 AD9750-EB Evaluation Board +300 °C –65 Temperature Ranges Package Descriptions Package Options* *R = Small Outline IC; RU = Thin Shrink Small Outline Package. THERMAL CHARACTERISTICS Thermal Resistance 28-Lead 300 Mil SOIC θJA = 71.4°C/W θJC = 23°C/W 28-Lead TSSOP θJA = 97.9°C/W θJC = 14.0°C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9750 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. 0 AD9750 PIN CONFIGURATION (MSB) DB9 1 28 CLOCK DB8 2 27 DVDD DB7 3 26 DCOM DB6 4 25 NC DB5 5 24 AVDD DB4 6 AD9750 TOP VIEW 23 ICOMP DB3 7 (Not to Scale) 22 IOUTA DB2 8 21 IOUTB DB1 9 20 ACOM DB0 10 19 NC NC 11 18 FS ADJ NC 12 17 REFIO NC 13 16 REFLO NC 14 15 SLEEP NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1 2–9 10 11–14, 19, 25 15 DB9 DB8–DB1 DB0 NC SLEEP 16 REFLO 17 REFIO 18 20 21 22 23 24 26 27 28 FS ADJ ACOM IOUTB IOUTA ICOMP AVDD DCOM DVDD CLOCK Most Significant Data Bit (MSB). Data Bits 1–8. Least Significant Data Bit (LSB). No Internal Connection. Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if not used. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Analog Common. Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor. Analog Supply Voltage (+4.5 V to +5.5 V). Digital Common. Digital Supply Voltage (+2.7 V to +5.5 V). Clock Input. Data latched on positive edge of clock. REV. 0 –5– AD9750 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Settling Time Differential Nonlinearity (or DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Monotonicity Glitch Impulse A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. Offset Error The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Spurious-Free Dynamic Range Gain Error THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Total Harmonic Distortion The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. Multitone Power Ratio Output Compliance Range The spurious-free dynamic range for an output containing multiple carrier tones of equal amplitude. It is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. +5V REFLO AVDD 150pF +1.20V REF 0.1mF REFIO RSET 2kV +5V DVDD CLOCK 50V 0.1mF MINI-CIRCUITS T1-1T LSB SWITCH 100V IOUTB LATCHES 50V SLEEP RETIMED CLOCK OUTPUT* LECROY 9210 PULSE GENERATOR ICOMP IOUTA SEGMENTED SWITCHES FOR DB9–DB1 DCOM DVDD DCOM AD9750 PMOS CURRENT SOURCE ARRAY FS ADJ ACOM 50V CLOCK OUTPUT TO HP3589A SPECTRUM/ NETWORK ANALYZER 50V INPUT 20pF 20pF DIGITAL DATA TEKTRONIX AWG-2021 W/OPTION 4 * AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. Figure 2. Basic AC Characterization Test Set-Up –6– REV. 0 AD9750 Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted) 90 90 90 0dBFS 0dBFS 25MSPS 80 –6dBFS 80 80 70 60 SFDR – dBc SFDR – dBc SFDR – dBc 100MSPS 70 –12dBFS 60 70 –6dBFS 60 65MSPS –12dBFS 50 50 50 125MSPS 40 40 10 fOUT – MHz 1 Figure 3. SFDR vs. fOUT @ 0 dBFS 0 2 4 6 fOUT – MHz 8 10 Figure 4. SFDR vs. fOUT @ 25 MSPS 90 40 12 0 5 10 15 fOUT – MHz 20 25 30 Figure 5. SFDR vs. fOUT @ 65 MSPS 90 90 80 80 20mAFS 0dBFS 80 –12dBFS 60 50 40 70 0dBFS 60 –12dBFS –6dBFS 50 0 10 20 30 fOUT – MHz 40 40 50 Figure 6. SFDR vs. fOUT @ 100 MSPS SFDR – dBc SFDR – dBc SFDR – dBc –6dBFS 70 0 40 10 20 10mAFS 60 5mAFS 50 30 40 fOUT – MHz 50 60 Figure 7. SFDR vs. fOUT @125 MSPS 0 2 4 6 8 fOUT – MHz 10 12 Figure 8. SFDR vs. fOUT and IOUTFS @ 25 MSPS and 0 dBFS 70 90 90 70 455kHz/5MSPS 1MHz/5MHz 66 80 80 70 SNR – dB SFDR – dBc SFDR – dBc 5.91/65MSPS 5MHz/25MHz 70 62 IOUTFS = 20mA 58 2.27MHz/25MHz 13MHz/65MHz 60 60 54 50 –25 –20 –15 –10 AOUT – dBFS –5 0 Figure 9. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/11 REV. 0 IOUTFS = 5mA 25MHz/125MHz 11.37MHz/125MSPS 50 –25 –20 –15 –10 AOUT – dBc –5 IOUTFS = 10mA 0 Figure 10. Single-Tone SFDR vs. AOUT @ fOUT = fCLOCK/5 –7– 50 0 10 20 30 40 fCLOCK – MSPS 50 60 Figure 11. SNR vs. fCLOCK and IOUTFS @ fOUT = 2 MHz and 0 dBFS AD9750 0.2 0.08 0.15 90 fOUT = 2.5MHz 0.04 ERROR – LSB ERROR – LSB 0.1 0.05 0 SFDR – dBc 80 0 –0.04 70 fOUT = 10MHz fOUT = 40MHz 60 –0.08 –0.05 –0.1 0 200 400 600 CODE 1000 800 –0.12 0 Figure 12. Typical INL 400 600 CODE 800 1000 50 –60 –40 –20 0 20 40 60 TEMPERATURE – 8C 80 100 Figure 14. SFDR vs. Temperature @ 125 MSPS, 0 dBFS Figure 13. Typical DNL –10 0 –20 –30 –40 –50 –60 –70 fCLOCK = 65MSPS fOUT1 = 6.25MHz fOUT2 = 6.75MHz fOUT3 = 7.25MHz fOUT4 = 7.75MHz AMPLITUDE = 0dBFS SFDR = 70dBc –20 –30 AMPLITUDE – dBm fCLOCK = 125MSPS fOUT1 = 13.5MHz fOUT2 = 14.5MHz AMPLITUDE = 0dBFS SDFR = 75dBc –10 AMPLITUDE – dBm 200 –40 –50 –60 –70 –80 –80 –90 –90 –100 –100 4 6 8 10 12 14 16 18 fOUT – MHz 20 22 24 Figure 15. Two-Tone SFDR 0 5 10 15 20 fOUT – MHz 25 30 Figure 16. Four-Tone SFDR –8– REV. 0 AD9750 IOUTB = (1023 – DAC CODE)/1024 × IOUTFS FUNCTIONAL DESCRIPTION Figure 17 shows a simplified block diagram of the AD9750. The AD9750 consists of a large PMOS current source array that is capable of providing up to 20 mA of total current. The array is divided into 31 equal currents that make up the five most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an MSB current source. The remaining LSB is a binary weighted fractions of the middle-bits current sources. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC’s high output impedance (i.e., >100 kΩ). where DAC CODE = 0 to 1023 (i.e., Decimal Representation). As mentioned previously, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage VREFIO and external resistor RSET. It can be expressed as: IOUTFS = 32 × IREF (3) where IREF = VREFIO/RSET (4) The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, which are tied to analog common, ACOM. Note, RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply : All of these current sources are switched to one or the other of the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. This new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. VOUTA = IOUTA × RLOAD (5) VOUTB = IOUTB × RLOAD (6) Note the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. The analog and digital sections of the AD9750 have separate power supply inputs (i.e., AVDD and DVDD). The digital section, which is capable of operating up to a 125 MSPS clock rate and over a +2.7 V to +5.5 V operating range, consists of edge-triggered latches and segment decoding logic circuitry. The analog section, which can operate over a +4.5 V to +5.5 V range, includes the PMOS current sources, the associated differential switches, a 1.20 V bandgap voltage reference and a reference control amplifier. The differential voltage, VDIFF, appearing across IOUTA and IOUTB is: VDIFF = (IOUTA – IOUTB) × RLOAD (7) Substituting the values of IOUTA, IOUTB, and IREF; VDIFF can be expressed as: VDIFF = {(2 DAC CODE – 1023)/1024} × (32 RLOAD/RSET) × VREFIO The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET. The external resistor, in combination with both the reference control amplifier and voltage reference VREFIO, sets the reference current IREF, which is mirrored over to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is thirty-two times the value of IREF. The AD9750 provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 1023) while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as: Note, the gain drift temperature performance for a single-ended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9750 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship as shown in Equation 8. (1) +5V REFLO AVDD 150pF +1.20V REF VREFIO 0.1mF RSET 2kV REFIO IREF FS ADJ +5V DVDD DCOM CLOCK CLOCK ACOM AD9750 PMOS CURRENT SOURCE ARRAY ICOMP 0.1mF VDIFF = VOUTA – VOUTB IOUTA IOUTA SEGMENTED SWITCHES FOR DB9–DB1 LSB SWITCH IOUTB LATCHES SLEEP DIGITAL DATA INPUTS (DB9–DB0) Figure 17. Functional Block Diagram REV. 0 (8) These last two equations highlight some of the advantages of operating the AD9750 differentially. First, the differential operation will help cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion and dc offsets. Second, the differential code dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal power to the load. DAC TRANSFER FUNCTION IOUTA = (DAC CODE/1024) × IOUTFS (2) –9– IOUTB VOUTA VOUTB RLOAD 50V RLOAD 50V AD9750 REFERENCE OPERATION REFERENCE CONTROL AMPLIFIER The AD9750 contains an internal 1.20 V bandgap reference that can easily be disabled and overridden by an external reference. REFIO serves as either an input or output depending on whether the internal or an external reference is selected. If REFLO is tied to ACOM, as shown in Figure 18, the internal reference is activated and REFIO provides a 1.20 V output. In this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 µF or greater from REFIO to REFLO. Also, REFIO should be buffered with an external amplifier having an input bias current less than 100 nA if any additional loading is required. The AD9750 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter as shown in Figure 19, such that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied over to the segmented current sources with the proper scaling factor to set IOUTFS as stated in Equation 3. The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 µA and 625 µA. The wide adjustment span of IOUTFS provides several application benefits. The first benefit relates directly to the power dissipation of the AD9750, which is proportional to IOUTFS (refer to the Power Dissipation section). The second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes. +5V OPTIONAL EXTERNAL REF BUFFER REFLO AVDD 150pF +1.2V REF REFIO ADDITIONAL LOAD 0.1mF CURRENT SOURCE ARRAY FS ADJ 2kV AD9750 Figure 18. Internal Reference Configuration The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied to REFIO as shown in Figure 19. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 µF compensation capacitor is not required since the internal reference is disabled, and the high input impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the external reference. AVDD REFLO AVDD 150pF AVDD +1.2V REF VREFIO EXTERNAL REF REFIO RSET IREF = VREFIO/RSET REFERENCE CONTROL AMPLIFIER AD9750 There are two methods in which IREF can be varied for a fixed RSET. The first method is suitable for a single-supply system in which the internal reference is disabled, and the common-mode voltage of REFIO is varied over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply amplifier or DAC, thus allowing IREF to be varied for a fixed RSET. Since the input impedance of REFIO is approximately 1 MΩ, a simple, low cost R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown in Figure 20 using the AD7524 and an external 1.2 V reference, the AD1580. The second method may be used in a dual-supply system in which the common-mode voltage of REFIO is fixed and IREF is varied by an external voltage, VGC, applied to RSET via an amplifier. An example of this method is shown in Figure 21, in which the internal reference is used to set the common-mode voltage of the control amplifier to 1.20 V. The external voltage, VGC, is referenced to ACOM and should not exceed 1.2 V. The value of RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µA CURRENT SOURCE ARRAY FS ADJ The small signal bandwidth of the reference control amplifier is approximately 0.5 MHz. The output of the control amplifier is internally compensated via a 150 pF capacitor that limits the control amplifier small-signal bandwidth and reduces its output impedance. Since the –3 dB bandwidth corresponds to the dominant pole, and hence the time constant, the settling time of the control amplifier to a stepped reference input response can be approximated. In this case, the time constant can be approximated to be 320 ns. Figure 19. External Reference Configuration AVDD AVDD REFLO RFB 1.2V AD1580 OUT1 AD7524 VREF 150pF 0.1V TO 1.2V OUT2 REFIO FS ADJ AGND AVDD +1.2V REF VDD RSET IREF = VREF/RSET CURRENT SOURCE ARRAY AD9750 DB7–DB0 Figure 20. Single-Supply Gain Control Circuit –10– REV. 0 AD9750 and 625 µA, respectively. The associated equations in Figure 21 can be used to determine the value of RSET. AVDD REFLO AVDD 150pF +1.2V REF REFIO RSET VGC CURRENT SOURCE ARRAY FS ADJ 1mF IREF AD9750 IREF = (1.2–VGC)/RSET WITH VGC < VREFIO AND 62.5mA # IREF # 625A Figure 21. Dual-Supply Gain Control Circuit ANALOG OUTPUTS The AD9750 produces two complementary current outputs, IOUTA and IOUTB, which may be configured for single-end or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. Figure 22 shows the equivalent analog output circuit of the AD9750 consisting of a parallel combination of PMOS differential current switches associated with each segmented current source. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches and is typically 100 kΩ in parallel with 5 pF. Due to the nature of a PMOS device, the output impedance is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) and, to a lesser extent, the analog supply voltage, AVDD, and full-scale current, IOUTFS. Although the output impedance’s signal dependency can be a source of dc nonlinearity and ac linearity (i.e., distortion), its effects can be limited if certain precautions are noted. AVDD IOUTA IOUTB RLOAD RLOAD Figure 22. Equivalent Analog Output IOUTA and IOUTB also have a negative and positive voltage compliance range. The negative output compliance range of –1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9750. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA. Operation beyond the positive compliance range will induce clipping of the output signal which severely degrades the AD9750’s linearity and distortion performance. REV. 0 For applications requiring the optimum dc linearity, IOUTA and/or IOUTB should be maintained at a virtual ground via an I-V op amp configuration. Maintaining IOUTA and/or IOUTB at a virtual ground keeps the output impedance of the AD9750 fixed, significantly reducing its effect on linearity. However, it does not necessarily lead to the optimum distortion performance due to limitations of the I-V op amp. Note that the INL/DNL specifications for the AD9750 are measured in this manner using IOUTA. In addition, these dc linearity specifications remain virtually unaffected over the specified power supply range of 4.5 V to 5.5 V. Operating the AD9750 with reduced voltage output swings at IOUTA and IOUTB in a differential or single-ended output configuration reduces the signal dependency of its output impedance thus enhancing distortion performance. Although the voltage compliance range of IOUTA and IOUTB extends from –1.0 V to +1.25 V, optimum distortion performance is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed approximately 0.5 V. A properly selected transformer with a grounded center-tap will allow the AD9750 to provide the required power and voltage levels to different loads while maintaining reduced voltage swings at IOUTA and IOUTB. DC-coupled applications requiring a differential or single-ended output configuration should size RLOAD accordingly. Refer to Applying the AD9750 section for examples of various output configurations. The most significant improvement in the AD9750’s distortion and noise performance is realized using a differential output configuration. The common-mode error sources of both IOUTA and IOUTB can be substantially reduced by the common-mode rejection of a transformer or differential amplifier. These common-mode error sources include even-order distortion products and noise. The enhancement in distortion performance becomes more significant as the reconstructed wave-form’s frequency content increases and/or its amplitude decreases. The distortion and noise performance of the AD9750 is also slightly dependent on the analog and digital supply as well as the full-scale current setting, IOUTFS. Operating the analog supply at 5.0 V ensures maximum headroom for its internal PMOS current sources and differential switches leading to improved distortion performance. Although IOUTFS can be set between 2 mA and 20 mA, selecting an IOUTFS of 20 mA will provide the best distortion and noise performance also shown in Figure 8. The noise performance of the AD9750 is affected by the digital supply (DVDD), output frequency, and increases with increasing clock rate as shown in Figure 11. Operating the AD9750 with low voltage logic levels between 3 V and 3.3 V will slightly reduce the amount of on-chip digital noise. In summary, the AD9750 achieves the optimum distortion and noise performance under the following conditions: (1) Differential Operation. (2) Positive voltage swing at IOUTA and IOUTB limited to +0.5 V. (3) IOUTFS set to 20 mA. (4) Analog Supply (AVDD) set at 5.0 V. (5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appropriate logic levels. Note that the ac performance of the AD9750 is characterized under the above mentioned operating conditions. –11– AD9750 resistors should be considered to maintain “clean” digital inputs. Also, operating the AD9750 with reduced logic swings and a corresponding digital supply (DVDD) will also reduce data feedthrough. DIGITAL INPUTS The AD9750’s digital input consists of 10 data input pins and a clock input pin. The 10-bit parallel data inputs follow standard positive binary coding where DB9 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. The external clock driver circuitry should provide the AD9750 with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform. Thus, the clock input should be driven by the fastest logic family suitable for the application. The digital interface is implemented using an edge-triggered master slave latch. The DAC output is updated following the rising edge of the clock as shown in Figure 1 and is designed to support a clock rate as high as 125 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met; although the location of these transition edges may affect digital feedthrough and distortion performance. Best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock. Note, the clock input could also be driven via a sine wave, which is centered around the digital threshold (i.e., DVDD/2), and meets the min/max logic threshold. This will typically result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. Also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and subsequently cut into the required data setup and hold times. The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD set to approximately half the digital positive supply (DVDD) or INPUT CLOCK/DATA TIMING RELATIONSHIP VTHRESHOLD = DVDD/2 (± 20%) The internal digital circuitry of the AD9750 is capable of operating over a digital supply range of 2.7 V to 5.5 V. As a result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage of the TTL drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure proper compatibility with most TTL logic families. Figure 23 shows the equivalent digital input circuit for the data and clock inputs. The sleep mode input is similar with the exception that it contains an active pull-down circuit, thus ensuring that the AD9750 remains enabled if this input is left disconnected. SNR in a DAC is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. The AD9750 is positive edge triggered, and so exhibits SNR sensitivity when the data transition is close to this edge. In general, the goal when applying the AD9750 is to make the data transitions shortly after the rising edge. This becomes more important as the sample rate increases. Figure 24 shows the relationship of SNR to clock placement with different sample rates and different frequencies out. Note that at the lower sample rates, much more tolerance is allowed in clock placement, while at higher rates, much more care must be taken. 60 56 DVDD SNR – dB FS = 65MSPS DIGITAL INPUT 52 FS = 125MSPS 48 44 Figure 23. Equivalent Digital Input Since the AD9750 is capable of being updated up to 125 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9750 as well as its required min/ max input logic level thresholds. Typically, the selection of the slowest logic family that satisfies the above conditions will result in the lowest data feedthrough and noise. Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 20 Ω to 100 Ω) between the AD9750 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. For longer run lengths and high data update rates, strip line techniques with proper termination 40 –10 –5 0 5 10 TIME OF DATA CHANGE RELATIVE TO RISING CLOCK EDGE – ns 15 Figure 24. SNR vs. Clock Placement 2 fOUT = 10 MHz SLEEP MODE OPERATION The AD9750 has a power-down function which turns off the output current and reduces the supply current to less than 8.5 mA over the specified supply range of 2.7 V to 5.5 V and temperature range. This mode can be activated by applying a logic level “1” to the SLEEP pin. This digital input also contains an active pull-down circuit that ensures the AD9750 remains enabled if this input is left disconnected. The AD9750 takes less than 50 ns to power down and approximately 5 µs to power back up. –12– REV. 0 AD9750 POWER DISSIPATION 8 125MSPS The power dissipation, PD, of the AD9750 is dependent on several factors which include: (1) AVDD and DVDD, the power supply voltages; (2) IOUTFS, the full-scale current output; (3) fCLOCK, the update rate; (4) and the reconstructed digital input waveform. The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS as shown in Figure 25 and is insensitive to fCLOCK. IDVDD – mA 6 100MSPS 4 50MSPS Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figures 26 and 27 show IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 5 V and DVDD = 3 V, respectively. Note, how IDVDD is reduced by more than a factor of 2 when DVDD is reduced from 5 V to 3 V. 2 25MSPS 0 0.01 5MSPS 0.1 RATIO (fCLOCK/fOUT) 1 Figure 27. IDVDD vs. Ratio @ DVDD = 3 V 35 APPLYING THE AD9750 OUTPUT CONFIGURATIONS 30 IAVDD – mA 25 20 15 10 5 2 4 6 8 10 12 IOUTFS – mA 14 16 18 20 A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. Note, IOUTA provides slightly better performance than IOUTB. Figure 25. IAVDD vs. IOUTFS 18 125MSPS 16 14 100MSPS 12 IDVDD – mA The following sections illustrate some typical output configurations for the AD9750. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. 10 8 50MSPS 6 DIFFERENTIAL COUPLING USING A TRANSFORMER 4 25MSPS 2 5MSPS 0 0.01 0.1 RATIO (fCLOCK/fOUT) Figure 26. IDVDD vs. Ratio @ DVDD = 5 V REV. 0 1 An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 28. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s passband. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only. –13– AD9750 MINI-CIRCUITS T1-1T 500V IOUTA AD9750 RLOAD AD9750 225V IOUTA AD8041 225V IOUTB IOUTB OPTIONAL RDIFF Figure 28. Differential Output Using a Transformer 25V The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9750. A differential resistor, RDIFF, may be inserted in applications in which the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer’s impedance ratio and provides the proper source termination which results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. DIFFERENTIAL USING AN OP AMP An op amp can also be used to perform a differential to singleended conversion as shown in Figure 29. The AD9750 is configured with two equal load resistors, RLOAD, of 25 Ω. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amps distortion performance by preventing the DACs high slewing output from overloading the op amp’s input. 1kV 25V AVDD 1kV Figure 30. Single-Supply DC Differential Coupled Circuit SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT Figure 31 shows the AD9750 configured to provide a unipolar output range of approximately 0 V to +0.5 V for a doubly terminated 50 Ω cable since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 Ω. In this case, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL) as discussed in the ANALOG OUTPUT section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. AD9750 IOUTFS = 20mA VOUTA = 0 TO +0.5V IOUTA 50V 50V IOUTB 25V 500V AD9750 COPT Figure 31. 0 V to +0.5 V Unbuffered Voltage Output 225V IOUTA 225V IOUTB SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT CONFIGURATION AD8055 COPT 500V 25V 25V Figure 29. DC Differential Coupling Using an Op Amp The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit is configured to provide some additional signal gain. The op amp must operate off of a dual supply since its output is approximately ± 1.0 V. A high speed amplifier such as the AD8055 or AD8057 capable of preserving the differential performance of the AD9750 while meeting other system level objectives (i.e., cost, power) should be selected. The op amps differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. Figure 32 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9750 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, thus minimizing the nonlinear output impedance effect on the DAC’s INL performance as discussed in the ANALOG OUTPUT section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by U1’s slewing capabilities. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1’s voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since the signal current U1 will be required to sink will be subsequently reduced. The differential circuit shown in Figure 30 provides the necessary level-shifting required in a single supply system. In this case, AVDD which is the positive analog supply for both the AD9750 and the op amp is also used to level-shift the differential output of the AD9750 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. –14– REV. 0 AD9750 different sizes of these switches, PSRR is very code-dependent. This can produce a mixing effect which can modulate low frequency power supply noise to higher frequencies. Worst case PSRR for either one of the differential DAC outputs will occur when the full-scale current is directed towards that output. As a result, the PSRR measurement in Figure 33 represents a worst case condition in which the digital inputs remain static and the full-scale output current of 20 mA is directed to the DAC output being measured. COPT RFB 200V IOUTFS = 10mA AD9750 IOUTA U1 VOUT = IOUTFS 3 RFB IOUTB 200V An example serves to illustrate the effect of supply noise on the analog supply. Suppose a switching regulator with a switching frequency of 250 kHz produces 10 mV rms of noise and, for simplicity sake (i.e., ignore harmonics), all of this noise is concentrated at 250 kHz. To calculate how much of this undesired noise will appear as current noise superimposed on the DAC’s full-scale current, IOUTFS, one must determine the PSRR in dB using Figure 33 at 250 kHz. To calculate the PSRR for a given RLOAD, such that the units of PSRR are converted from A/V to V/V, adjust the curve in Figure 33 by the scaling factor 20 × Log (RLOAD). For instance, if RLOAD is 50 Ω, the PSRR is reduced by 34 dB (i.e., PSRR of the DAC at 1 MHz, which is 74 dB in Figure 33 becomes 40 dB VOUT/VIN). Figure 32. Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS, POWER SUPPLY REJECTION Many applications seek high speed and high performance under less than ideal operating conditions. In these circuits, the implementation and construction of the printed circuit board design are as important as the circuit design. To ensure optimum performance, proper RF techniques must be used for device selection, placement and routing as well as power supply bypassing and grounding. Figures 39–44 illustrate the recommended printed circuit board ground, power and signal plane layouts which are implemented on the AD9750 evaluation board. Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9750 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM as close as physically as possible. One factor that can measurably affect system performance is the ability of the DAC output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution (i.e., AVDD, DVDD). This is referred to as Power Supply Rejection Ratio (PSRR). For dc variations of the power supply, the resulting performance of the DAC directly corresponds to a gain error associated with the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. Typically, switching power supply noise will occur over the spectrum from tens of kHz to several MHz. PSRR vs. frequency of the AD9750 AVDD supply, over this frequency range, is given in Figure 33. For those applications that require a single +5 V or +3 V supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 34. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESR type electrolytic and tantalum capacitors. 90 FERRITE BEADS TTL/CMOS LOGIC CIRCUITS AVDD 100mF ELECT. 10-22mF TANT. 0.1mF CER. ACOM PSRR – dB 80 +5V OR +3V POWER SUPPLY 70 Figure 34. Differential LC Filter for Single +5 V or +3 V Applications 60 0.26 0.5 0.75 FREQUENCY – MHz 1.0 Figure 33. Power Supply Rejection Ratio of AD9750 Note that the units in Figure 33 are given in units of (amps out)/ (volts in). Noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. The voltage noise on the dc power will be added in a nonlinear manner to the desired IOUT. Due to the relatively REV. 0 Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the AD9750. If properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current transport, etc. In mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. –15– AD9750 All analog ground pins of the DAC, reference and other analog components should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal and the supply feeders. The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing some “free” capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all connections be short, direct and as physically close to the package as possible in order to minimize the sharing of conduction paths between different currents. When runs exceed an inch in length, strip line techniques with proper termination resistor should be considered. The necessity and value of this resistor will be dependent upon the logic family used. For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to Analog Devices’ application notes AN-280 and AN-333. A common and traditional implementation of a QAM modulator is shown in Figure 35. The modulation is performed in the analog domain in which two DACs are used to generate the baseband I and Q components, respectively. Each component is then typically applied to a Nyquist filter before being applied to a quadrature mixer. The matching Nyquist filters shape and limit each component’s spectral envelope while minimizing intersymbol interference. The DAC is typically updated at the QAM symbol rate or possibly a multiple of it if an interpolating filter precedes the DAC. The use of an interpolating filter typically eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. A quadrature mixer modulates the I and Q components with in-phase and quadrature phase carrier frequency and then sums the two outputs to provide the QAM signal. 12 AD9750 DSP OR ASIC CARRIER FREQUENCY 0 90 S TO MIXER 12 AD9750 NYQUIST FILTERS QUADRATURE MODULATOR Figure 35. Typical Analog QAM Architecture APPLICATIONS Using the AD9750 for Quadrature Amplitude Modulation (QAM) QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in FDM as well as spreadspectrum (i.e., CDMA) based systems. A QAM signal is a carrier frequency that is modulated in both amplitude (i.e., AM modulation) and phase (i.e., PM modulation). It can be generated by independently modulating two carriers of identical frequency but with a 90° phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90° phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. In this implementation, it is much more difficult to maintain proper gain and phase matching between the I and Q channels. The circuit implementation shown in Figure 36 helps improve upon the matching and temperature stability characteristics between the I and Q channels, as well as showing a path for upconversion using the AD8346 quadrature modulator. Using a single voltage reference derived from U1 to set the gain for both the I and Q channels will improve the gain matching and stability. RCAL can be used to compensate for any mismatch in gain between the two channels. This mismatch may be attributed to the mismatch between RSET1 and RSET2, effective load resistance of each channel, and/or the voltage offset of the control amplifier in each DAC. The differential voltage outputs of U1 and U2 are fed into the respective differential inputs of the AD8346 via matching networks. –16– REV. 0 AD9750 +5V 1.82V 634V DVDD 100W REFLO REFIO FSADJ RSET1 2kV 500V 500V AVDD 0.1mF VPBF AD9750 (“I DAC”) U1 DAC BBIP 500V IOUTA CFILTER LATCHES IOUTB I DATA INPUT + BBIN 500V VOUT 100V AVDD CLK LOIP 100V AVDD REFLO QOUTA LATCHES Q DATA INPUT REFIO BBQP LOIN 500V BBQN AD8346 100V SLEEP 500mV p-p WITH VCM=1.2V RSET2 1.9kV 0.1mF PHASE SPLITTER CFILTER QOUTB FSADJ 500V 500V U2 DAC AD9750 (“Q DAC”) 500V RCAL 220V DCOM NOTE: 500V RESISTOR NETWORK - OHMTEK ORN5000D 100V RESISTOR NETWORK - TOMC1603-100D ACOM Figure 36. Baseband QAM Implementation Using Two AD9750s It is also possible to generate a QAM signal completely in the digital domain via a DSP or ASIC, in which case only a single DAC of sufficient resolution and performance is required to reconstruct the QAM signal. Also available from several vendors are Digital ASICs which implement other digital modulation schemes such as PSK and FSK. This digital implementation has the benefit of generating perfectly matched I and Q components in terms of gain and phase, which is essential in maintaining optimum performance in a communication system. In this implementation, the reconstruction DAC must be operating at a sufficiently high clock rate to accommodate the highest specified QAM carrier frequency. Figure 37 shows a block diagram of such an implementation using the AD9750. 12 12 I DATA STEL-1130 QAM 12 LPF Q DATA AD9750 12 SIN CARRIER 12 FREQUENCY 50V 12 COS TO MIXER 50V AD9750 EVALUATION BOARD General Description The AD9750-EB is an evaluation board for the AD9750 10-bit D/A converter. Careful attention to layout and circuit design combined with a prototyping area allow the user to easily and effectively evaluate the AD9750 in any application where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9750 in various configurations. Possible output configurations include transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. The digital inputs are designed to be driven directly from various word generators, with the on-board option to add a resistor network for proper load termination. Provisions are also made to operate the AD9750 with either the internal or external reference, or to exercise the power-down feature. Refer to the application note AN-420 for a thorough description and operating instructions for the AD9750 evaluation board. STEL-1177 NCO CLOCK Figure 37. Digital QAM Architecture REV. 0 –17– 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 –18– A J4 A J3 P1 R1 A R38 49.9V A OUT2 R20 49.9V OUT1 R2 C13 22pF R14 0 C12 22pF A 6 5 4 T1 1 2 3 4 5 6 7 8 9 10 10 9 8 7 6 5 4 3 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 1 1 3 R5 C4 10mF TP4 B3 R6 A J7 JP6B C20 0 JP6A A C30 C31 C32 C33 C34 C35 C36 C19 C1 C2 C25 C26 C27 C28 C29 A AGND R13 OPEN A R12 OPEN DVDD 1 2 3 4 5 6 7 8 9 10 AVDD 10 9 8 7 6 5 4 3 2 1 DVDD TP2 TP3 C3 10mF B2 DGND B1 DVDD 16 15 14 13 12 11 10 9 A B JP7B 1 2 3 4 5 6 7 R9 1kV 16 15 14 13 12 11 10 16 PINDIP RES PK 1 2 3 4 5 6 7 8 JP9 A R3 C6 10mF TP7 B6 R4 B A A B R10 1kV A R35 1kV A B JP8 R18 1kV 2 3 R7 U4 7 AVCC R8 AVEE 4 A A C23 0.1mF R36 1kV 6 C21 0.1mF C24 1mF R37 49.9V C22 1mF A J6 DVDD 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 J1 2 3 4 5 6 7 8 9 10 EXTCLK 10 9 8 7 6 5 4 3 2 1 DVDD A AD8047 1 2 3 4 5 6 7 8 9 10 A AVCC 10 9 8 7 6 5 4 3 2 1 C5 10mF TP6 B5 JP7A AVEE 16 PINDIP RES PK TP5 TP18 TP19 B4 A C18 0.1mF TP12 A 28 27 26 25 24 23 22 21 20 19 18 17 16 15 2 CLK JP1 A C16 1mF TP11 U7 A A 4 GND R44 50V VOUT REF43 A 3 2 1 AVDD JP2 VIN A C7 1mF AVDD EXTREFIN J5 2 PDIN J2 A 3 B AVCC R17 49.9V CLOCK DVDD DCOM NC AVDD COMP2 IOUTA IOUTB ACOM COMP1 FS ADJ REFIO REFLO SLEEP CT1 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AD975x U1 1 R15 49.9V TP1 C14 1mF 6 A R45 1kV R43 5kV R42 1kV A A JP4 A R46 1kV 2 3 7 A 3 4 A AD8047 U6 JP3 1 AVEE A C15 0.1mF 2 JP5 6 C17 0.1mF AVCC C10 0.1mF TP9 OUT 2 TP8 OUT 1 C9 0.1mF AVDD CW TP14 R16 2kV TP10 AVDD C11 0.1mF C8 0.1mF 1 2 3 A B TP13 AD9750 Figure 38. Evaluation Board Schematic REV. 0 AD9750 Figure 39. Silkscreen Layer—Top Figure 40. Component Side PCB Layout (Layer 1) REV. 0 –19– AD9750 Figure 41. Ground Plane PCB Layout (Layer 2) Figure 42. Power Plane PCB Layout (Layer 3) –20– REV. 0 AD9750 Figure 43. Solder Side PCB Layout (Layer 4) Figure 44. Silkscreen Layer—Bottom REV. 0 –21– AD9750 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 28 C3377–8–1/99 0.7125 (18.10) 0.6969 (17.70) 15 0.2992 (7.60) 0.2914 (7.40) 0.4193 (10.65) 0.3937 (10.00) 14 1 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 0.0118 (0.30) 0.0040 (0.10) 0.0291 (0.74) 3 458 0.0098 (0.25) 88 0.0500 (1.27) 0.0192 (0.49) 08 0.0157 (0.40) SEATING 0.0125 (0.32) 0.0138 (0.35) PLANE 0.0091 (0.23) 28-Lead TSSOP (RU-28) 0.386 (9.80) 0.378 (9.60) 15 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) 28 1 14 PIN 1 0.006 (0.15) 0.002 (0.05) 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 88 08 0.028 (0.70) 0.020 (0.50) PRINTED IN U.S.A. SEATING PLANE 0.0433 (1.10) MAX –22– REV. 0