a
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
10-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 40 MHz Output: 52 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Basestations
Set Top Boxes
Digital Radio Link
Direct Digital Synthesis (DDS)
Instrumentation
PRODUCT DESCRIPTION
The AD9760 and AD9760-50 are the 10-bit resolution members
of the TxDAC series of high performance, low power CMOS
digital-to-analog converters (DACs). The AD9760-50 is a lower
performance option that is guaranteed and specified for 50 MSPS
operation. The TxDAC family that consists of pin compatible 8-,
10-, 12- and 14-bit DACs is specifically optimized for the transmit signal path of communication systems. All of the devices
share the same interface options, small outline package and
pinout, thus providing an upward or downward component
selection path based on performance, resolution and cost. Both
the AD9760 and AD9760-50 offer exceptional ac and dc
performance while supporting update rates up to 125 MSPS
and 60 MSPS respectively.
The AD9760’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.
The AD9760 is manufactured on an advanced CMOS process. A
segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and
enhance dynamic performance. Edge-triggered input latches and a
1.2 V temperature compensated bandgap reference have been integrated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
10-Bit, 125 MSPS
TxDAC® D/A Converter
AD9760
FUNCTIONAL BLOCK DIAGRAM
+5V
0.1F
REFLO
COMP1
AVDD
+1.20V REF
0.1F
CURRENT
SOURCE
ARRAY
FS ADJ
RSET
+5V
DVDD
DCOM
CLOCK
AD9760
50pF
REFIO
SEGMENTED
SWITCHES
CLOCK
ACOM
LSB
SWITCHES
COMP2
0.1F
IOUTA
IOUTB
LATCHES
SLEEP
DIGITAL DATA INPUTS (DB9–DB0)
The AD9760 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
Differential current outputs are provided to support singleended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complementary, single-ended voltage outputs or fed directly into a transformer. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9760 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier that provides a wide
(>10:1) adjustment span allows the AD9760 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9760 may operate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9760 is available in a 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9760 is a member of the TxDAC product family that
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
2. Manufactured on a CMOS process, the AD9760 uses a proprietary switching technique that enhances dynamic performance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.
3. On-chip, edge-triggered input CMOS latches interface readily
to +3 V and +5 V CMOS logic families. The AD9760 can
support update rates up to 125 MSPS.
4. A flexible single-supply operating range of 2.7 V to 5.5 V and
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9760 to operate at reduced power levels.
5. The current output(s) of the AD9760 can be easily configured for various single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
AD9760/AD9760-50–SPECIFICATIONS
DC SPECIFICATIONS (T
MIN
to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
Parameter
Min
RESOLUTION
Typ
Max
10
Units
Bits
1
DC ACCURACY
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
–1.0
–0.5
MONOTONICITY
Guaranteed Over Specified Temperature Range
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth (w/o CCOMP1)4
± 0.5
± 0.25
–0.025
–10
–10
2.0
–1.0
1.08
OPERATING RANGE
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
1.32
V
nA
1.25
1
1.4
V
MΩ
MHz
0
± 50
± 100
± 50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
1.20
100
0.1
2.7
2.7
LSB
LSB
+0.025
+10
+10
20.0
1.25
±2
±1
100
5
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD5
DVDD
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD)6
Supply Current Sleep Mode (IAVDD)
Power Dissipation6 (5 V, IOUTFS = 20 mA)
Power Dissipation7 (5 V, IOUTFS = 20 mA)
Power Dissipation7 (3 V, IOUTFS = 2 mA)
Power Supply Rejection Ratio—AVDD
Power Supply Rejection Ratio—DVDD
+1.0
+0.5
5.0
5.0
25
3
–0.04
–0.025
+0.04
+0.025
V
V
mA
mA
mA
mW
mW
mW
% of FSR/V
% of FSR/V
–40
+85
°C
140
190
45
5.5
5.5
30
5
8.5
175
NOTES
1
Measured at I OUTA, driving a virtual ground.
2
Nominal full-scale current, I OUTFS, is 32 × the IREF current.
3
Use an external buffer amplifier to drive any external load.
4
Reference bandwidth is a function of external cap at COMP1 pin and signal level. Refer to Figure 41.
5
For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6
Measured at f CLOCK = 50 MSPS and f OUT = 1.0 MHz.
7
Measured as unbuffered voltage output into 50 Ω RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
Specifications subject to change without notice.
–2–
REV. B
AD9760
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer Coupled Output,
DYNAMIC SPECIFICATIONS 50 ⍀ Doubly Terminated, unless otherwise noted)
Model
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLOCK)
Output Settling Time (tST) (to 0.1%)1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (10% to 90%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
TA = +25°C
TMIN to TMAX
fCLOCK = 50 MSPS; fOUT = 2.51 MHz
fCLOCK = 50 MSPS; fOUT = 5.02 MHz
fCLOCK = 50 MSPS; fOUT = 20.2 MHz
fCLOCK = 100 MSPS; fOUT = 2.51 MHz
fCLOCK = 100 MSPS; fOUT = 5.04 MHz
fCLOCK = 100 MSPS; fOUT = 20.2 MHz
fCLOCK = 100 MSPS; fOUT = 40.4 MHz
Spurious-Free Dynamic Range within a Window
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
TA = +25°C
TMIN to TMAX
fCLOCK = 50 MSPS; fOUT = 5.02 MHz; 2 MHz Span
fCLOCK = 100 MSPS; fOUT = 5.04 MHz; 4 MHz Span
Total Harmonic Distortion
fCLOCK = 50 MSPS; fOUT = 1.00 MHz
TA = +25°C
TMIN to TMAX
fCLOCK = 50 MHz; fOUT = 2.00 MHz
fCLOCK = 100 MHz; fOUT = 2.00 MHz
Min
Max
125
Min
70
68
73
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
68
66
73
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
73
68
55
N/A
N/A
N/A
N/A
78
72
70
76
76
–76
–71
–71
–3–
78
dBc
dBc
dBc
dBc
76
N/A
–73
–71
Units
60
35
1
5
2.5
2.5
50
30
73
68
55
74
68
60
52
74
72
AD9760-50
Typ
Max
50
35
1
5
2.5
2.5
50
30
NOTES
1
Measured single ended into 50 Ω load.
Specifications subject to change without notice.
REV. B
AD9760
Typ
–76
–71
N/A
–70
–68
dBc
dBc
dBc
dBc
AD9760
DIGITAL SPECIFICATIONS (T
MIN
to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted)
Parameter
DIGITAL INPUTS
Logic “1” Voltage @ DVDD = +5 V
Logic “1” Voltage @ DVDD = +3 V
Logic “0” Voltage @ DVDD = +5 V
Logic “0” Voltage @ DVDD = +3 V
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup Time (tS)
Input Hold Time (tH)
Latch Pulsewidth (tLPW)
Min
Typ
3.5
2.1
5
3
0
0
Max
Units
V
V
V
V
µA
µA
pF
ns
ns
ns
1.3
0.9
+10
+10
–10
–10
5
2.0
1.5
3.5
Specification subject to change without notice.
DB0–DB9
tH
tS
CLOCK
tLPW
tPD
IOUTA OR
IOUTB
tST
0.1%
0.1%
Figure 1. Timing Diagram
ORDERING GUIDE
ABSOLUTE MAXIMUM RATINGS*
Parameter
AVDD
DVDD
ACOM
AVDD
CLOCK, SLEEP
Digital Inputs
IOUTA, IOUTB
COMP1, COMP2
REFIO, FSADJ
REFLO
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
With
Respect to
Min
Max
Units
Model
Temperature
Range
Package
Descriptions
Package
Options
ACOM
DCOM
DCOM
DVDD
DCOM
DCOM
ACOM
ACOM
ACOM
ACOM
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–1.0
–0.3
–0.3
–0.3
+6.5
+6.5
+0.3
+6.5
DVDD + 0.3
DVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
+0.3
+150
+150
V
V
V
V
V
V
V
V
V
V
°C
°C
AD9760AR
–40°C to +85°C
R-28
AD9760ARU
–40°C to +85°C
AD9760AR50
–40°C to +85°C
28-Lead 300 mil
SOIC
28-Lead 170 mil
TSSOP
28-Lead 300 mil
SOIC
28-Lead 170 mil
TSSOP
+300
°C
28-Lead 300 mil (7.5 mm) SOIC
θJA = 71.4°C/W
θJC = 23°C/W
28-Lead 170 mil (4.4 mm) TSSOP
θJA = 97.9°C/W
θJC = 14.0°C/W
–65
AD9760ARU50 –40°C to +85°C
AD9760-EB
RU-28
R-28
RU-28
Evaluation Board
THERMAL CHARACTERISTICS
Thermal Resistance
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods may effect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9760 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. B
AD9760
PIN CONFIGURATION
(MSB) DB9 1
28 CLOCK
DB8 2
27 DVDD
DB7 3
26 DCOM
DB6 4
25 NC
DB5 5
AD9760
24 AVDD
DB4 6
TOP VIEW 23 COMP2
DB3 7 (Not to Scale) 22 IOUTA
DB2 8
21 IOUTB
DB1 9
20 ACOM
DB0 10
19 COMP1
NC 11
18 FS ADJ
NC 12
17 REFIO
NC 13
16 REFLO
NC 14
15 SLEEP
NC = NO CONNECT
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
2–9
10
11–14, 25
15
DB9
DB8–DB1
DB0
NC
SLEEP
16
17
REFLO
REFIO
18
19
20
21
22
23
24
26
27
28
FS ADJ
COMP1
ACOM
IOUTB
IOUTA
COMP2
AVDD
DCOM
DVDD
CLOCK
Most Significant Data Bit (MSB).
Data Bits 1–8.
Least Significant Data Bit (LSB).
No Internal Connection.
Power-Down Control Input. Active High. Contains active pull-down circuit, thus may be left unterminated if
not used.
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1 µF capacitor to ACOM when internal reference activated.
Full-Scale Current Output Adjust.
Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
Analog Common.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Current Output. Full-scale current when all data bits are 1s.
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
Analog Supply Voltage (+2.7 V to +5.5 V).
Digital Common.
Digital Supply Voltage (+2.7 V to +5.5 V).
Clock Input. Data latched on positive edge of clock.
REV. B
–5–
AD9760
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when the
inputs are all 0s. For IOUTB, 0 mA output is expected when all
inputs are set to 1s.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Spurious-Free Dynamic Range
Output Compliance Range
Total Harmonic Distortion
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown resulting in
nonlinear performance.
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured output signal. It is
expressed as a percentage or in decibels (dB).
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
+5V
0.1F
REFLO
COMP1
AVDD
+1.20V REF
0.1F
50pF
REFIO
PMOS
CURRENT SOURCE
ARRAY
FS ADJ
RSET
2k⍀
+5V
DVDD
DCOM
50⍀
RETIMED
CLOCK
OUTPUT*
LECROY 9210
PULSE GENERATOR
LSB
SWITCHES
SEGMENTED SWITCHES
FOR DB11–DB3
CLOCK
DVDD
DCOM
ACOM
AD9760
COMP2
0.1F
MINI-CIRCUITS
T1-1T
IOUTA
100⍀
IOUTB
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50⍀ INPUT
LATCHES
50⍀
SLEEP
20pF
50⍀
CLOCK
OUTPUT
20pF
DIGITAL
DATA
TEKTRONIX
AWG-2021
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
Figure 2. Basic AC Characterization Test Setup
–6–
REV. B
AD9760
Typical AC Characterization Curves @ +5 V Supplies
(AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted)
90
85
85
0dBFS
25MSPS
100MSPS
60
125MSPS
50
0.1
1
10
FREQUENCY – MHz
–6dBFS
SFDR – dBc
SFDR – dBc
75
–12dBFS
70
65
SFDR – dBc
–12dBFS
65
55
55
1.00
1.50
2.00
FREQUENCY – MHz
50
0.00
2.50
85
80
80
75
75
–6dBFS
–12dBFS
65
2.00
4.00 6.00 8.00 10.00 12.00
FREQUENCY – MHz
Figure 5. SFDR vs. fOUT @ 25 MSPS
85
70
0dBFS
65
60
0.50
–12dBFS
70
60
Figure 4. SFDR vs. fOUT @ 5 MSPS
85
80
70
50
0.00
100
Figure 3. SFDR vs. fOUT @ 0 dBFS
–6dBFS
SFDR – dBc
50MSPS
–6dBFS
75
75
SFDR – dBc
SFDR – dBc
80
70
80
80
5MSPS
70
–6dBFS
65
0dBFS
60
60
55
55
55
50
0.00
50
0.00
50
0.00
60
0dBFS
–12dBFS
0dBFS
10.00
15.00
20.00
FREQUENCY – MHz
25.00
Figure 6. SFDR vs. fOUT @ 50 MSPS
85
SFDR – dBc
SFDR – dBc
9.1MHz
@ 100MSPS
11.37MHz
@ 125MSPS
–20
–15
–10
AOUT – dBFS
–5
65
0.675/0.725MHz
@ 5MSPS
25MHz
@ 125MSPS
10MHz
@ 50MSPS
3.38/3.63MHz
@ 25MSPS
65
13.5/14.5MHz
@ 100MSPS
16.9/18.1MHz
@ 125MSPS
55
20MHz
@ 100MSPS
0
45
–30
–25
6.75/7.25MHz
@ 50MSPS
75
2.5MHz
@ 25MSPS
55
Figure 9. Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
REV. B
Figure 8. SFDR vs. fOUT @ 125 MSPS
85
75
65
–25
10.00 20.00 30.00 40.00 50.00 60.00
FREQUENCY – MHz
1MHz
@ 5MSPS
2.27MHz
@ 25MSPS
45
–30
50.00
85
4.55MHz
@ 50MSPS
55
20.00
30.00
40.00
FREQUENCY – MHz
Figure 7. SFDR vs. fOUT @100 MSPS
455kHz
@ 5MSPS
75
10.00
SFDR – dBc
5.00
–20
–15
–10
AOUT – dBFS
–5
0
Figure 10. Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/5
–7–
45
–30
–25
–20
–15
–10
AOUT – dBFS
–5
0
Figure 11. Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
AD9760
80
–70
75
IDIFF @ 0dBFS
2.5MHz
75
–75
70
2ND
HARMONIC
10MHz
dBc
3RD
HARMONIC
–85
–90
60
28.6MHz
55
IOUTA @ 0dBFS
60
55
50
4TH
HARMONIC
65
65
SFDR – dBc
SFDR – dBc
–80
IDIFF @ –6dBFS
70
IOUTA @ –6dBFS
40MHz
50
45
–95
40
0
20
40
60
80 100
FREQUENCY – MSPS
2
120 140
Figure 12. THD vs. fCLOCK @
fOUT = 2 MHz
4
6
8
10 12 14
IOUTFS – mA
16
18
45
1
20
Figure 13. SFDR vs. fOUT and IOUTFS
@ 100 MSPS, 0 dBFS
80
0.4
75
0.3
2.5MHz
0.3
0.1
0
–0.1
70
SFDR – dBc
ERROR – LSB
0.2
ERROR – LSB
100
Figure 14. Differential vs. SingleEnded SFDR vs. fOUT @ 100 MSPS
0.5
0.5
0.4
10
OUTPUT FREQUENCY – MHz
0.2
0.1
0
–0.2
–0.1
–0.3
–0.4
65
10MHz
60
55
40MHz
–0.2
–0.5
0
0
125 250 375 500 625 750 875 1000
CODE
Figure 15. Typical INL
125 250 375 500 625 750 875 1000
CODE
Figure 16. Typical DNL
0
0
Figure 18. Single-Tone SFDR
Figure 17. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
SFDR = 70dBc
AMPLITUDE = 0dBFS
10dB – Div
10dB – Div
10dB – Div
STOP: 62.5MHz
80
0
20
40
60
TEMPERATURE – ⴗC
–10
–100
START: 0.3MHz
–20
fCLOCK = 100MSPS
fOUT1 = 13.5MHz
fOUT2 = 14.5MHz
SFDR = 61dBc
AMPLITUDE = 0dBFS
fCLOCK = 125MSPS
fOUT = 9.95MHz
SFDR = 62dBc
AMPLITUDE = 0dBFS
–100
50
–40
START: 0.3MHz
STOP: 50.0MHz
Figure 19. Dual-Tone SFDR
–8–
–110
START: 0.3MHz
STOP: 25.0MHz
Figure 20. Four-Tone SFDR
REV. B
AD9760
Typical AC Characterization Curves @ +3 V Supplies
(AVDD = +3 V, DVDD = +3 V, IOUTFS = 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, SFDR up to Nyquist, unless otherwise noted)
85
90
85
0dBFS
5MSPS
80
80
–6dBFS
75
25MSPS
70
100MSPS
50MSPS
60
125MSPS
50
0.1
1
10
FREQUENCY – MHz
Figure 21. SFDR vs. fOUT @ 0 dBFS
–12dBFS
65
70
–12dBFS
65
60
60
55
55
0.50
1.00
1.50
2.00
FREQUENCY – MHz
50
0.00
2.50
Figure 22. SFDR vs. fOUT @ 5 MSPS
85
80
80
80
75
75
SFDR – dBc
–12dBFS
70
65
60
0dBFS
SFDR – dBc
85
–6dBFS
–6dBFS
70
–12dBFS
65
0dBFS
2.00
4.00 6.00 8.00 10.00 12.00
FREQUENCY – MHz
Figure 23. SFDR vs. fOUT @ 25 MSPS
85
75
SFDR – dBc
70
50
0.00
100
–6dBFS
75
SFDR – dBc
SFDR – dBc
SFDR – dBc
80
60
70
–6dBFS
–12dBFS
65
60
0dBFS
55
55
5.00
10.00 15.00
20.00
FREQUENCY – MHz
50
0.00
25.00
Figure 24. SFDR vs. fOUT @ 50 MSPS
80
90
455kHz
@ 5MSPS
9.1MHz
@ 100MSPS
11.37MHz
@ 125MSPS
60
50
3.38/3.63MHz
@ 25MSPS
1MHz
@ 5MSPS
80
4.55MHz
@ 50MSPS
SFDR – dBc
SFDR – dBc
Figure 26. SFDR vs. fOUT @ 125 MSPS
90
2.27MHz
@ 25MSPS
0dBFS
50
0.00 10.00 20.00 30.00 40.00 50.00 60.00
FREQUENCY – MHz
50.00
Figure 25. SFDR vs. fOUT @ 100 MSPS
90
70
10.00 20.00
30.00
40.00
FREQUENCY – MHz
80
2.5MHz
@ 25MSPS
70
SFDR – dBc
50
0.00
55
10MHz
@ 50MSPS
20MHz
@ 100MSPS
60
6.75/7.25MHz
@ 50MSPS
60
13.5/14.5MHz
@ 100MSPS
25MHz
@ 125MSPS
50
70
0.675/0.725MHz
@ 5MSPS
50
16.9/18.1MHz
@ 125MSPS
40
–30
–25
–20
–15
–10
AOUT – dBFS
–5
0
Figure 27. Single-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/11
REV. B
40
–30
–25
–20
–15
–10
AOUT – dBFS
–5
0
Figure 28. Single-Tone SFDR vs.
AOUT @ fOUT = fCLOCK/5
–9–
40
–30
–25
–20
–15
–10
AOUT – dBFS
–5
0
Figure 29. Dual-Tone SFDR vs. AOUT
@ fOUT = fCLOCK/7
AD9760
–70
80
75
2.5MHz
IOUTA @
75
–75
70
2ND
HARMONIC
60
22.4MHz
55
IDIFF @
–6dBFS
65
65
SFDR – dBc
dBc
–85
SFDR – dBc
10MHz
3RD
HARMONIC
–80
60
IDIFF @
0dBFS
55
28.6MHz
50
–90
4TH
HARMONIC
–95
–6dBFS
70
0
20
50
45
40
60
80 100
FREQUENCY – MSPS
40
120 140
Figure 30. THD vs. fCLOCK
fOUT = 2 MHz
IOUTA @
0dBFS
2
4
6
8
10 12 14
IREF – mA
16
18
Figure 31. SFDR vs. fOUT and IOUTFS
@ 100 MSPS, 0 dBFS
0.5
0.4
45
1
20
10
OUTPUT FREQUENCY – MHz
100
Figure 32. Differential vs. Single
Ended SFDR vs. fOUT @ 100 MSPS
0.5
80
0.4
75
0.3
70
0.2
65
2.5MHz
ERROR – LSB
ERROR – LSB
0.2
0.1
0
–0.1
0.1
–0.2
0
–0.3
–0.1
–0.4
–0.2
–0.5
SFDR – dBc
0.3
10MHz
60
28.6MHz
55
50
45
0
0
125 250 375 500 625 750 875 1000
CODE
Figure 33. Typical INL
125 250 375 500 625 750 875 1000
CODE
Figure 34. Typical DNL
0
Figure 36. Single-Tone SFDR
80
Figure 35. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
fCLOCK = 50MSPS
fOUT1 = 6.25MHz
fOUT2 = 6.75MHz
fOUT3 = 7.25MHz
fOUT4 = 7.75MHz
SFDR = 71dBc
AMPLITUDE = 0dBFS
10dB – Div
10dB – Div
10dB – Div
STOP: 62.5MHz
0
20
40
60
TEMPERATURE – ⴗC
fCLOCK = 100MSPS
fOUT1 = 13.5MHz
fOUT2 = 14.5MHz
SFDR = 59.0dBc
AMPLITUDE = 0dBFS
–110
–100
START: 0.3MHz
–20
–10
0
fCLOCK = 125MSPS
fOUT = 9.95MHz
SFDR = 62dBc
AMPLITUDE = 0dBFS
–100
40
–40
START: 0.3MHz
STOP: 50.0MHz
Figure 37. Dual-Tone SFDR
–10–
START: 0.3MHz
STOP: 25.0MHz
Figure 38. Four-Tone SFDR
REV. B
AD9760
FUNCTIONAL DESCRIPTION
DAC TRANSFER FUNCTION
Figure 39 shows a simplified block diagram of the AD9760.
The AD9760 consists of a large PMOS current source array that
is capable of providing up to 20 mA of total current. The array
is divided into 31 equal currents that make up the 5 most significant bits (MSBs). The next 4 bits or middle bits consist
of 15 equal current sources whose value is 1/16th of an MSB
current source. The remaining LSBs is a binary weighted fraction of the middle-bits current sources. Implementing the
middle and lower bits with current sources, instead of an R-2R
ladder, enhances its dynamic performance for multitone or low
amplitude signals and helps maintain the DAC’s high output
impedance (i.e., >100 kΩ).
The AD9760 provides complementary current outputs, IOUTA
and IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 1023) while
IOUTB, the complementary output, provides no current. The
current output appearing at IOUTA and IOUTB is a function of
both the input code and IOUTFS and can be expressed as:
IOUTA = (DAC CODE/1024) × IOUTFS
(1)
IOUTB = (1023 – DAC CODE)/1024 × IOUTFS
(2)
where DAC CODE = 0 to 1023 (i.e., Decimal Representation).
As mentioned previously, IOUTFS is a function of the reference
current IREF, which is nominally set by a reference voltage,
VREFIO and external resistor RSET. It can be expressed as:
All of these current sources are switched to one or the other of
the two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. The switches are based on a new architecture that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the differential current switches.
IOUTFS = 32 × IREF
(3)
where IREF = VREFIO/RSET
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, that are tied to analog common, ACOM. Note,
RLOAD may represent the equivalent load resistance seen by
IOUTA or IOUTB as would be the case in a doubly terminated
50 Ω or 75 Ω cable. The single-ended voltage output appearing
at the IOUTA and IOUTB nodes is simply:
The analog and digital sections of the AD9760 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 2.7 volt to 5.5 volt range. The digital
section, which is capable of operating up to a 125 MSPS clock
rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V bandgap
voltage reference and a reference control amplifier.
VOUTA = IOUTA × RLOAD
(5)
VOUTB = IOUTB × RLOAD
(6)
Note the full-scale value of VOUTA and VOUTB should not exceed
the specified output compliance range to maintain specified
distortion and linearity performance.
The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET. The external resistor, in combination with
both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is mirrored over to
the segmented current sources with the proper scaling factor.
The full-scale current, IOUTFS, is thirty-two times the value of IREF.
+5V
0.1F
REFLO
+1.20V REF
VREFIO
0.1F
RSET
2k⍀
REFIO
IREF
FS ADJ
+5V
DVDD
DCOM
CLOCK
CLOCK
COMP1
AVDD
ACOM
AD9760
50pF
PMOS
CURRENT SOURCE
ARRAY
SEGMENTED SWITCHES
FOR DB9–DB1
LSB
SWITCH
COMP2 0.1F
VDIFF = VOUTA – VOUTB
IOUTA
IOUTB
LATCHES
SLEEP
DIGITAL DATA INPUTS (DB9–DB0)
Figure 39. Functional Block Diagram
REV. B
–11–
IOUTA
IOUTB
VOUTA
VOUTB
RLOAD
50⍀
RLOAD
50⍀
AD9760
The differential voltage, VDIFF, appearing across IOUTA and
IOUTB is:
VDIFF = (IOUTA – IOUTB) × RLOAD
REFERENCE CONTROL AMPLIFIER
(7)
Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be
expressed as:
VDIFF = {(2 DAC CODE – 1023)/1024} ×
(32 RLOAD/RSET) × VREFIO
(8)
These last two equations highlight some of the advantages of
operating the AD9760 differentially. First, the differential operation will help cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion and dc offsets.
Second, the differential code dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (i.e., VOUTA or VOUTB), thus providing twice the signal
power to the load.
The AD9760 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a V-I converter as shown
in Figure 41, so that its current output, IREF, is determined by
the ratio of the VREFIO and an external resistor, RSET, as stated
in Equation 4. IREF is copied over to the segmented current
sources with the proper scaling factor to set IOUTFS as stated in
Equation 3.
AVDD
0.1F
REFLO
AVDD
COMP1
AVDD
+1.2V REF
Note, the gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the AD9760
can be enhanced by selecting temperature tracking resistors for
RLOAD and RSET due to their ratiometric relationship as shown
in Equation 8.
50pF
VREFIO
EXTERNAL
REF
REFIO
FS ADJ
RSET
IREF =
VREFIO/RSET
AD9760
CURRENT
SOURCE
ARRAY
REFERENCE
CONTROL
AMPLIFIER
Figure 41. External Reference Configuration
REFERENCE OPERATION
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5 µA and 625 µA. The wide adjustment span of IOUTFS provides several application benefits. The first benefit relates
directly to the power dissipation of the AD9760, which is
proportional to IOUTFS (refer to the Power Dissipation section).
The second benefit relates to the 20 dB adjustment, which is
useful for system gain control purposes.
The AD9760 contains an internal 1.20 V bandgap reference
that can be easily disabled and overridden by an external reference. REFIO serves as either an input or output depending on
whether the internal or an external reference is selected. If
REFLO is tied to ACOM, as shown in Figure 40, the internal
reference is activated and REFIO provides a 1.20 V output. In
this case, the internal reference must be compensated externally
with a ceramic chip capacitor of 0.1 µF or greater from REFIO
to REFLO. Also, REFIO should be buffered with an external
amplifier having an input bias current less than 100 nA if any
additional loading is required.
The small signal bandwidth of the reference control amplifier is
approximately 1.4 MHz and can be reduced by connecting an
external capacitor between COMP1 and AVDD. The output of
the control amplifier, COMP1, is internally compensated via a
50 pF capacitor that limits the control amplifier small-signal
bandwidth and reduces its output impedance. Any additional
external capacitance further limits the bandwidth and acts as a
filter to reduce the noise contribution from the reference amplifier. Figure 42 shows the relationship between the external
capacitor and the small signal –3 dB bandwidth of the reference amplifier. Since the –3 dB bandwidth corresponds to the
dominant pole, and hence the time constant, the settling time of
the control amplifier to a stepped reference input response can
be approximated.
+5V
0.1F
OPTIONAL
EXTERNAL
REF BUFFER
REFLO
+1.2V REF
REFIO
ADDITIONAL
LOAD
0.1F
2k⍀
FS ADJ
COMP1
AVDD
50pF
CURRENT
SOURCE
ARRAY
AD9760
Figure 40. Internal Reference Configuration
1000
BANDWIDTH – kHz
The internal reference can be disabled by connecting REFLO to
AVDD. In this case, an external reference may be applied to
REFIO as shown in Figure 41. The external reference may
provide either a fixed reference voltage to enhance accuracy and
drift performance or a varying reference voltage for gain control.
Note that the 0.1 µF compensation capacitor is not required
since the internal reference is disabled, and the high input impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the
external reference.
10
0.1
0.1
1
10
100
COMP1 CAPACITOR – nF
1000
Figure 42. External COMP1 Capacitor vs. –3 dB Bandwidth
–12–
REV. B
AD9760
AVDD
OPTIONAL
BANDLIMITING
CAPACITOR
AVDD
REFLO
RFB
1.2V
VDD
OUT1
AD7524
VREF
REFIO
CURRENT
SOURCE
ARRAY
FS ADJ
AGND
AVDD
50pF
0.1V TO 1.2V
OUT2
AD1580
COMP1
+1.2V REF
RSET
IREF =
VREF/RSET
AD9760
DB7–DB0
Figure 43. Single-Supply Gain Control Circuit
The optimum distortion performance for any reconstructed
waveform is obtained with a 0.1 µF external capacitor installed.
Thus, if IREF is fixed for an application, a 0.1 µF ceramic chip
capacitor is recommended. Also, since the control amplifier is
optimized for low power operation, multiplying applications
requiring large signal swings should consider using an external
control amplifier to enhance the application’s overall large signal
multiplying bandwidth and/or distortion performance.
There are two methods in which IREF can be varied for a fixed
RSET. The first method is suitable for a single-supply system in
which the internal reference is disabled, and the common-mode
voltage of REFIO is varied over its compliance range of 1.25 V
to 0.10 V. REFIO can be driven by a single-supply amplifier or
DAC, allowing IREF to be varied for a fixed RSET. Since the
input impedance of REFIO is approximately 1 MΩ, a simple,
low cost R-2R ladder DAC configured in the voltage mode
topology may be used to control the gain. This circuit is shown
in Figure 43 using the AD7524 and an external 1.2 V reference,
the AD1580.
The second method may be used in a dual-supply system in
which the common-mode voltage of REFIO is fixed and IREF is
varied by an external voltage, VGC, applied to RSET via an amplifier. An example of this method is shown in Figure 44 where
the internal reference is used to set the common-mode voltage
of the control amplifier to 1.20 V. The external voltage, VGC, is
referenced to ACOM and should not exceed 1.2 V. The value
of RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µA
and 625 µA, respectively. The associated equations in Figure 44
can be used to determine the value of RSET.
OPTIONAL
BANDLIMITING
CAPACITOR
COMP1 AVDD
REFLO
+1.2V REF
50pF
REFIO
FS ADJ
1F
RSET
VGC
IREF
AVDD
CURRENT
SOURCE
ARRAY
AD9760
IREF = (1.2 – VGC)/RSET
WITH VGC < VREFIO AND 62.5A
IREF
625A
Figure 44. Dual-Supply Gain Control Circuit
REV. B
In some applications, the user may elect to use an external control amplifier to enhance the multiplying bandwidth, distortion
performance and/or settling time. External amplifiers capable of
driving a 50 pF load such as the AD817 are suitable for this
purpose. It is configured in such a way that it is in parallel with
the weaker internal reference amplifier as shown in Figure 45.
In this case, the external amplifier simply overdrives the weaker
reference control amplifier. Also, since the internal control
amplifier has a limited current output, it will sustain no damage
if overdriven.
EXTERNAL
CONTROL AMPLIFIER
AVDD
VREF
INPUT
REFLO
50pF COMP1 AVDD
+1.2V REF
REFIO
FS ADJ
RSET
CURRENT
SOURCE
ARRAY
AD9760
Figure 45. Configuring an External Reference Control
Amplifier
ANALOG OUTPUTS
The AD9760 produces two complementary current outputs,
IOUTA and IOUTB, which may be configured for single-ended or
differential operation. IOUTA and IOUTB can be converted into
complementary single-ended voltage outputs, VOUTA and VOUTB,
via a load resistor, RLOAD, as described in the DAC Transfer
Function section by Equations 5 through 8. The differential
voltage, VDIFF, existing between VOUTA and VOUTB can also be
converted to a single-ended voltage via a transformer or differential amplifier configuration. The ac performance of the AD9760
is optimum and specified using a differential transformer
coupled output in which the voltage swing at IOUTA and IOUTB is
limited to ± 0.5 V. If a single-ended unipolar output is desirable,
IOUTA should be selected.
The distortion and noise performance of the AD9760 can be
enhanced when the AD9760 is configured for differential operation. The common-mode error sources of both IOUTA and IOUTB
can be significantly reduced by the common-mode rejection of a
transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
–13–
AD9760
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed waveform increases. This is due to the first order cancellation of
various dynamic common-mode distortion mechanisms, digital feedthrough and noise.
clock cycle as long as the specified minimum times are met
although the location of these transition edges may affect digital
feedthrough and distortion performance. Best performance is
typically achieved when the input data transitions on the falling edge
of a 50% duty cycle clock.
Performing a differential-to-single-ended conversion via a
transformer also provides the ability to deliver twice the reconstructed signal power to the load (i.e., assuming no source
termination). Since the output currents of IOUTA and IOUTB are
complementary, they become additive when processed differentially. A properly selected transformer will allow the AD9760
to provide the required power and voltage levels to different
loads. Refer to Applying the AD9760 section for examples of
various output configurations.
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD set to approximately half the digital positive supply
(DVDD) or
VTHRESHOLD = DVDD/2 (± 20%)
The internal digital circuitry of the AD9760 is capable of operating over a digital supply range of 2.7 V to 5.5 V. As a result,
the digital inputs can also accommodate TTL levels when
DVDD is set to accommodate the maximum high level voltage
VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure proper
compatibility with most TTL logic families. Figure 46 shows the
equivalent digital input circuit for the data and clock inputs.
The sleep mode input is similar with the exception that it contains an active pull-down circuit, ensuring that the AD9760
remains enabled if this input is left disconnected.
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ in parallel
with 5 pF. It is also slightly dependent on the output voltage
(i.e., VOUTA and VOUTB) due to the nature of a PMOS device.
As a result, maintaining IOUTA and/or IOUTB at a virtual ground
via an I-V op amp configuration will result in the optimum dc
linearity. Note the INL/DNL specifications for the AD9760 are
measured with IOUTA maintained at a virtual ground via an
op amp.
DVDD
DIGITAL
INPUT
IOUTA and IOUTB also have a negative and positive voltage compliance range that must be adhered to in order to achieve optimum performance. The negative output compliance range of
–1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9760.
Figure 46. Equivalent Digital Input
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from
its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an
IOUTFS = 2 mA. The optimum distortion performance for a
single-ended or differential output is achieved when the maximum
full-scale signal at IOUTA and IOUTB does not exceed 0.5 V. Applications requiring the AD9760’s output (i.e., VOUTA and/or
VOUTB) to extend its output compliance range should size RLOAD
accordingly. Operation beyond this compliance range will adversely affect the AD9760’s linearity performance and subsequently degrade its distortion performance.
DIGITAL INPUTS
The AD9760’s digital input consists of 10 data input pins and a
clock input pin. The 10-bit parallel data inputs follow standard
positive binary coding where DB9 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at
Logic 1. IOUTB produces a complementary output with the fullscale current split between the two outputs as a function of the
input code.
The digital interface is implemented using an edge-triggered
master slave latch. The DAC output is updated following the
rising edge of the clock as shown in Figure 1 and is designed to
support a clock rate as high as 125 MSPS. The clock can be
operated at any duty cycle that meets the specified latch pulsewidth. The setup and hold times can also be varied within the
Since the AD9760 is capable of being updated up to 125 MSPS,
the quality of the clock and data input signals are important in
achieving the optimum performance. The drivers of the digital
data interface circuitry should be specified to meet the minimum setup and hold times of the AD9760 as well as its required
min/max input logic level thresholds. Typically, the selection of
the slowest logic family that satisfies the above conditions will
result in the lowest data feedthrough and noise.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low value resistor network (i.e., 20 Ω to 100 Ω) between the
AD9760 digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough. For longer run lengths and high
data update rates, strip line techniques with proper termination
resistors should be considered to maintain “clean” digital inputs. Also, operating the AD9760 with reduced logic swings and
a corresponding digital supply (DVDD) will also reduce data
feedthrough.
The external clock driver circuitry should provide the AD9760
with a low jitter clock input meeting the min/max logic levels
while providing fast edges. Fast clock edges will help minimize
any jitter that will manifest itself as phase noise on a reconstructed waveform. Thus, the clock input should be driven by
the fastest logic family suitable for the application.
–14–
REV. B
AD9760
Note, the clock input could also be driven via a sine wave that is
centered around the digital threshold (i.e., DVDD/2), and
meets the min/max logic threshold. This will typically result in a
slight degradation in the phase noise, that becomes more noticeable at higher sampling rates and output frequencies. Also, at
higher sampling rates, the 20% tolerance of the digital logic
threshold should be considered since it will affect the effective
clock duty cycle and subsequently cut into the required data
setup and hold times.
Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figures 48 and 49
show IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 5 V and
DVDD = 3 V, respectively. Note how IDVDD is reduced by more
than a factor of 2 when DVDD is reduced from 5 V to 3 V.
18
125MSPS
16
SLEEP MODE OPERATION
14
The AD9760 has a power-down function that turns off the output current and reduces the supply current to less than 8.5 mA
over the specified supply range of 2.7 V to 5.5 V and temperature range. This mode can be activated by applying a logic level
“1” to the SLEEP pin. This digital input also contains an active
pull-down circuit that ensures that the AD9760 remains enabled
if this input is left disconnected. The SLEEP input with active
pull-down requires
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