10-/12-/14-Bit, 125 MSPS
Dual TxDAC+ Digital-to-Analog Converters
AD9763/AD9765/AD9767
FEATURES
FUNCTIONAL BLOCK DIAGRAM
10-/12-/14-bit dual transmit digital-to-analog converters (DACs)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 75 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual-port or interleaved data
On-chip 1.2 V reference
5 V or 3.3 V operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
DVDD1/ DCOM1/
DVDD2 DCOM2
WRT2/IQSEL
GENERAL DESCRIPTION
The AD9763/AD9765/AD9767 are dual-port, high speed,
2-channel, 10-/12-/14-bit CMOS DACs. Each part integrates
two high quality TxDAC+® cores, a voltage reference, and digital
interface circuitry into a small 48-lead LQFP. The AD9763/
AD9765/AD9767 offer exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.
The AD9763/AD9765/AD9767 have been optimized for
processing I and Q data in communications applications. The
digital interface consists of two double-buffered latches as well
as control logic. Separate write inputs allow data to be written to
the two DAC ports independent of one another. Separate clocks
control the update rate of the DACs.
A mode control pin allows the AD9763/AD9765/AD9767 to
interface to two separate data ports, or to a single interleaved
high speed data port. In interleaving mode, the input data
stream is demuxed into its original I and Q data and then
latched. The I and Q data is then converted by the two DACs
and updated at half the input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor. See the
Gain Control Mode section for important date code
information on this feature.
DIGITAL
INTERFACE
AD9763/
AD9765/
AD9767
2
LATCH
PORT2
MODE
CLK1
1
DAC
IOUTA1
IOUTB1
REFERENCE
REFIO
FSADJ1
FSADJ2
GAINCTRL
BIAS
GENERATOR
SLEEP
2
DAC
IOUTA2
IOUTB2
CLK2/IQ RESET
00617-001
WRT1/IQWRT
ACOM
1
LATCH
PORT1
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound
AVDD
Figure 1.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
glitch energy and maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or differential applications. Both DACs of the AD9763, AD9765, or
AD9767 can be simultaneously updated and can provide a
nominal full-scale current of 20 mA. The full-scale currents
between each DAC are matched to within 0.1%.
The AD9763/AD9765/AD9767 are manufactured on an
advanced, low cost CMOS process. They operate from a single
supply of 3.3 V to 5 V and consume 380 mW of power.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
The AD9763/AD9765/AD9767 are members of a pincompatible family of dual TxDACs providing 8-, 10-, 12-,
and 14-bit resolution.
Dual 10-/12-/14-Bit, 125 MSPS DACs. A pair of high
performance DACs for each part is optimized for low
distortion performance and provides flexible transmission
of I and Q information.
Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
Low Power. Complete CMOS dual DAC function operates on
380 mW from a 3.3 V to 5 V single supply. The DAC full-scale
current can be reduced for lower power operation, and a sleep
mode is provided for low power idle periods.
On-Chip Voltage Reference. The AD9763/AD9765/AD9767
each include a 1.20 V temperature-compensated band gap
voltage reference.
Dual 10-/12-/14-Bit Inputs. The AD9763/AD9765/AD9767
each feature a flexible dual-port interface, allowing dual or
interleaved input data.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD9763/AD9765/AD9767
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Outputs .......................................................................... 23
Applications....................................................................................... 1
Digital Inputs .............................................................................. 24
General Description ......................................................................... 1
DAC Timing................................................................................ 24
Functional Block Diagram .............................................................. 1
Sleep Mode Operation............................................................... 26
Product Highlights ........................................................................... 1
Power Dissipation....................................................................... 26
Revision History ............................................................................... 3
Applying the AD9763/AD9765/AD9767 .................................... 28
Specifications..................................................................................... 5
Output Configurations .............................................................. 28
DC Specifications ......................................................................... 5
Differential Coupling Using a Transformer............................ 28
Dynamic Specifications ............................................................... 6
Differential Coupling Using an Op Amp................................ 28
Digital Specifications ................................................................... 7
Single-Ended, Unbuffered Voltage Output............................. 29
Absolute Maximum Ratings............................................................ 8
Single-Ended, Buffered Voltage Output Configuration........ 29
Thermal Resistance ...................................................................... 8
Power and Grounding Considerations.................................... 29
ESD Caution.................................................................................. 8
Applications..................................................................................... 31
Pin Configuration and Function Descriptions............................. 9
VDSL Example Applications
Using the AD9765 and AD9767............................................... 31
Typical Performance Characteristics ........................................... 11
AD9763 ........................................................................................ 11
AD9765 ........................................................................................ 14
AD9767 ........................................................................................ 17
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 21
Functional Description.............................................................. 21
Reference Operation .................................................................. 22
Gain Control Mode .................................................................... 22
Setting the Full-Scale Current................................................... 22
Quadrature Amplitude Modulation (QAM) Example
Using the AD9763 ...................................................................... 32
CDMA ......................................................................................... 33
Evaluation Board ............................................................................ 34
General Description................................................................... 34
Schematics................................................................................... 34
Evaluation Board Layout........................................................... 37
Outline Dimensions ....................................................................... 40
Ordering Guide............................................................................... 40
DAC Transfer Function ............................................................. 23
Rev. E | Page 2 of 40
AD9763/AD9765/AD9767
REVISION HISTORY
Revision History: AD9763/AD9765/AD9767
Revision History: AD9765
1/08—Revision E: Initial Combined Version
1/08—Rev. C to Rev. E
Combined with AD9763 and AD9767 Data Sheets ...... Universal
Changes to Figure 1 ..........................................................................1
Changes to Applications Section.....................................................1
Changes to Timing Diagram Section .............................................7
Change to Absolute Maximum Ratings .........................................8
Added Figure 3 and Figure 5 ...........................................................9
Changes to Table 6 ..........................................................................10
Added Figure 6 to Figure 22 ..........................................................11
Added Figure 40 to Figure 56 ........................................................17
Added Note to Figure 58 ................................................................20
Changes to Functional Description Section................................22
Changes to Reference Operation Section ....................................22
Changes to Figure 59 and Figure 60 .............................................22
Changes to Gain Control Mode Section ......................................22
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section .................................................22
Changes to DAC Transfer Section ................................................23
Changes to Interleaved Mode Timing Section............................25
Added Figure 64 ..............................................................................25
Changes to Power and Grounding Considerations Section............30
Added Figure 80 and Figure 82 .....................................................31
Changes to Quadrature Amplitude Modulation (QAM)
Example Using the AD9763 Section........................................32
Changes to Figure 83 and Figure 84 .............................................32
Changes to CDMA Section............................................................33
Changes to Figure 85 Caption .......................................................33
Changes to Figure 86 ......................................................................34
Changes to Figure 88 ......................................................................36
Changes to Ordering Guide...........................................................40
Revision History: AD9763
1/08—Rev. D to Rev. E
Combined with AD9765 and AD9767 Data Sheets ...... Universal
Changes to Figure 1...........................................................................1
Changes to Applications Section.....................................................1
Changes to Timing Diagram Section .............................................7
Added Figure 4 and Figure 5 ...........................................................9
Changes to Table 6 ..........................................................................10
Change to Typical Performance Characteristics Section
Conditions Statement ................................................................11
Added Figure 23 to Figure 56 ........................................................14
Added Note to Figure 58 ................................................................20
Changes to Functional Description Section ................................22
Changes to Figure 59 and Figure 60 .............................................22
Changes to Gain Control Mode Section ......................................22
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section..................................................22
Changes to DAC Transfer Section ................................................23
Change to Analog Outputs Section ..............................................24
Changes to Dual-Port Mode Timing............................................24
Changes to Interleaved Mode Timing Section ............................25
Added Figure 64 ..............................................................................25
Change to Differential Coupling Using a Transformer Section .....28
Changes to Power and Grounding Considerations Section............30
Added VDSL Example Applications Using the AD9765 and
AD9767 Section..........................................................................31
Added Figure 79 to Figure 82 ........................................................31
Changes to Figure 84 ......................................................................32
Changes to CDMA Section............................................................33
Changes to Figure 85 Caption .......................................................33
Changes to Figure 86 ......................................................................34
Changes to Figure 88 ......................................................................36
Changes to Ordering Guide...........................................................40
10/01—Rev. B to Rev. C
Changes to Figure 29 ......................................................................21
9/06—Rev. B to Rev. C
Updated Format ................................................................. Universal
Changes to Figure 2 ..........................................................................5
Changes to Figure 3 ..........................................................................7
Changes to Functional Description Section................................12
Changes to Figure 25 and Figure 26 .............................................15
Changes to Figure 28 and Figure 29 .............................................16
Changes to Power Dissipation Section.........................................17
Changes to Power and Grounding Considerations Section......19
Changes to Figure 39 ......................................................................19
Changes to Figure 45 ......................................................................22
Changes to Evaluation Board Section ..........................................24
Changes to Figure 47 ......................................................................24
Updated Outline Dimensions........................................................30
Changes to Ordering Guide...........................................................30
2/00—Rev. A to Rev. B
2/00—Rev. A to Rev. B
12/99—Rev. 0 to Rev. A
12/99—Rev. 0 to Rev. A
9/06—Rev. C to Rev. D
Updated Format.................................................................. Universal
Renumbered Figures.......................................................... Universal
Changes to Specifications Section...................................................3
Changes to Applications Section...................................................21
Updated Outline Dimensions........................................................32
Changes to Ordering Guide...........................................................32
8/99—Revision 0: Initial Version
Rev. E | Page 3 of 40
AD9763/AD9765/AD9767
Revision History: AD9767
1/08—Rev. C to Rev. E
Combined with AD9763 and AD9765 Data Sheets.......Universal
Changes to Figure 1.......................................................................... 1
Changes to Features Section............................................................ 1
Changes to Applications Section .................................................... 1
Changes to Timing Diagram Section............................................. 7
Change to Absolute Maximum Ratings......................................... 8
Added Figure 3 and Figure 4........................................................... 9
Changes to Table 6.......................................................................... 10
Added Figure 6 to Figure 39.......................................................... 11
Added Note to Figure 58 ............................................................... 20
Changes to Functional Description Section ............................... 22
Changes to Reference Operation Section.................................... 22
Changes to Figure 59 and Figure 60............................................. 22
Changes to Gain Control Mode Section...................................... 22
Replaced Reference Control Amplifier Section with Setting
the Full-Scale Current Section................................................. 22
Changes to DAC Transfer Section................................................ 23
Changes to Dual-Port Mode Timing ........................................... 24
Changes to Interleaved Mode Timing Section ........................... 25
Added Figure 64.............................................................................. 25
Change to Differential Coupling Using a Transformer Section......28
Changes to Power and Grounding Considerations Section............30
Added Figure 79 and Figure 81..................................................... 31
Added to Quadrature Amplitude Modulation (QAM)
Example Using the AD9763 Section ....................................... 32
Added Figure 83 and Figure 84 .................................................... 32
Changes to CDMA Section ........................................................... 33
Changes to Figure 85 Caption ...................................................... 33
Changes to Figure 86...................................................................... 34
Changes to Figure 88...................................................................... 36
Changes to Ordering Guide .......................................................... 40
10/06—Rev. B to Rev. C
Updated Format..................................................................Universal
Changes to Figure 2...........................................................................5
Changes to Figure 3...........................................................................7
Changes to Functional Description Section ............................... 12
Changes to Figure 25 and Figure 26............................................. 15
Changes to Figure 28 and Figure 29............................................. 16
Changes to Power Dissipation Section ........................................ 18
Changes to Figure 39...................................................................... 19
Changes to Power and Grounding Considerations Section ..... 19
Changes to Figure 45...................................................................... 22
Changes to Figure 47...................................................................... 24
Updated Outline Dimensions....................................................... 28
Changes to Ordering Guide .......................................................... 28
2/00—Rev. A to Rev. B
12/99—Rev. 0 to Rev. A
8/99—Revision 0: Initial Version
Rev. E | Page 4 of 40
AD9763/AD9765/AD9767
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
AD9763
Parameter
RESOLUTION
DC ACCURACY 1
Integral Linearity Error (INL)
TA = 25°C
TMIN to TMAX
Differential Nonlinearity (DNL)
TA = 25°C
TMIN to TMAX
ANALOG OUTPUT
Offset Error
Gain Error Without Internal Reference
Gain Error with Internal Reference
Gain Match
Full-Scale Output Current 2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current 3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small-Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift Without Internal Reference
Gain Drift with Internal Reference
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD1, DVDD2
Analog Supply Current (IAVDD)
Digital Supply Current (IDVDD) 4
Digital Supply Current (IDVDD) 5
Supply Current Sleep Mode (IAVDD)
Power Dissipation4 (5 V, IOUTFS = 20 mA)
Power Dissipation5 (5 V, IOUTFS = 20 mA)
Power Dissipation 6 (5 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio 7 —AVDD
Power Supply Rejection Ratio7—DVDD
OPERATING RANGE
AD9765
Min
10
Typ
Max
−1
±0.1
+1
−0.5
−0.02
−2
−5
−1.6
−0.14
2.0
−1.0
±0.07
±0.25
±1
±0.1
Typ
Max
Min
14
Typ
Max
−1.5
−2.0
±0.4
+1.5
+2.0
−3.5
−4.0
±1.5
+3.5
+4.0
+0.5
−0.75
−1.0
±0.3
+0.75
+1.0
−2.5
−3.0
±1.0
+2.5
+3.0
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
−0.02
−2
−5
−1.6
−0.14
2.0
−1.0
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
−0.02
−2
−5
−1.6
−0.14
2.0
−1.0
±0.25
±1
±0.1
100
5
1.14
1.20
100
0.1
3
2.7
AD9767
Min
12
100
5
1.26
1.14
1.25
0.1
1.20
100
±0.25
±1
±0.1
1.14
1.25
0.1
1.20
100
LSB
LSB
LSB
LSB
LSB
LSB
+0.02
+2
+5
+1.6
+0.14
20.0
+1.25
% of FSR
% of FSR
% of FSR
% of FSR
dB
mA
V
kΩ
pF
1.26
V
nA
1.25
100
5
1.26
Unit
Bits
1
0.5
1
0.5
1
0.5
V
MΩ
MHz
0
±50
±100
±50
0
±50
±100
±50
0
±50
±100
±50
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
5
5
71
5
8
380
5.5
5.5
75
7
15
12.0
410
420
450
3
2.7
5
5
71
5
450
8
380
5.5
5.5
75
7
15
12.0
410
420
450
3
2.7
450
5
5
71
5
8
380
5.5
5.5
75
7
15
12.0
410
420
450
mW
–0.4
–0.025
+0.4
+0.025
–0.4
–0.025
+0.4
+0.025
–0.4
–0.025
+0.4
+0.025
mW
% of FSR/V
% of FSR/V
–40
+85
–40
+85
–40
+85
°C
1
450
V
V
mA
mA
mA
mA
mW
Measured at IOUTA, driving a virtual ground.
Nominal full-scale current, IOUTFS, is 32 times the IREF current.
An external buffer amplifier with input bias current 100 kΩ).
All of these current sources are switched to one of the two
output nodes (that is, IOUTA or IOUTB) via the PMOS differential
current switches. The switches are based on a new architecture
that drastically improves distortion performance. This new
switch architecture reduces various timing errors and provides
matching complementary drive signals to the inputs of the
differential current switches.
B
The analog and digital sections of the AD9763/AD9765/AD9767
have separate power supply inputs (that is, AVDD and DVDD1/
DVDD2) that can operate independently at 3.3 V or 5 V. The
digital section, which is capable of operating up to a 125 MSPS
clock rate, consists of edge-triggered latches and segment decoding
logic circuitry. The analog section includes the PMOS current
sources, the associated differential switches, a 1.20 V band gap
voltage reference, and two reference control amplifiers.
Rev. E | Page 21 of 40
AD9763/AD9765/AD9767
The full-scale output current of each DAC is regulated by
separate reference control amplifiers and can be set from
2 mA to 20 mA via an external network connected to the full
scale adjust (FSADJ) pin. The external network, in combination
with both the reference control amplifier and voltage reference
(VREFIO) sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current (IOUTFS) is 32 × IREF.
REFERENCE OPERATION
The AD9763/AD9765/AD9767 contain an internal 1.20 V band
gap reference. This can easily be overridden by a low noise external
reference with no effect on performance. REFIO serves as either
an input or output, depending on whether the internal or an
external reference is used. To use the internal reference, simply
decouple the REFIO pin to ACOM with a 0.1 μF capacitor. The
internal reference voltage is present at REFIO. If the voltage at
REFIO is used elsewhere in the circuit, an external buffer amplifier
with an input bias current of less than 100 nA should be used. An
example of the use of the internal reference is shown in Figure 59.
GAINCTRL
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
AD9763/
AD9765/
AD9767
1.2V
REF
REFIO
ADDITIONAL
EXTERNAL
LOAD
AVDD
CURRENT
SOURCE
ARRAY
RSET
256Ω
FSADJ1/
FSADJ2
ACOM
22nF
00617-059
IREF
The AD9763/AD9765/AD9767 allow the gain of each channel
to be set independently by connecting one RSET resistor network
to FSADJ1 and another RSET resistor network to FSADJ2. To add
flexibility and reduce system cost, a single RSET resistor can be
used to set the gain of both channels simultaneously. If this RSET
resistor is 2 kΩ or less, the 22 nF capacitor and 256 Ω resistor
are not required on either FSADJ pin.
When GAINCTRL is low (that is, connected to analog ground), the
independent channel gain control mode using two resistors is
enabled. In this mode, individual RSET resistor networks must be
connected to FSADJ1 and FSADJ2. When GAINCTRL is high
(that is, connected to AVDD), the master/slave channel gain
control mode using one network is enabled. In this mode, a single
network is connected to FSADJ1, and the FSADJ2 pin must be
left unconnected.
Note that only parts with a date code of 9930 or later have the
master/slave gain control function. For parts with a date code
before 9930, Pin 42 must be connected to AGND, and the part
operates in the two-resistor, independent gain control mode.
SETTING THE FULL-SCALE CURRENT
REFERENCE
SECTION
0.1µF
GAIN CONTROL MODE
Both of the DACs in the AD9763/AD9765/AD9767 contain a
control amplifier that is used to regulate the full-scale output
current (IOUTFS). The control amplifier is configured as a V-I
converter, as shown in Figure 59, so that its current output (IREF) is
determined by the ratio of the VREFIO and an external resistor, RSET.
I REF =
Figure 59. Internal Reference Configuration
An external reference can be applied to REFIO as shown in
Figure 60. The external reference can provide either a fixed
reference voltage to enhance accuracy and drift performance
or a varying reference voltage for gain control. The 0.1 μF
compensation capacitor is not required because the internal
reference is overridden and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
GAINCTRL
1.2V
REF
REFIO
EXTERNAL
REFERENCE
256Ω
IREF
22nF
FSADJ1/
FSADJ2
REFERENCE
SECTION
CURRENT
SOURCE
ARRAY
ACOM
RSET
Figure 60. External Reference Configuration Gain Control Mode
00617-060
AVDD
AVDD
AD9763/
AD9765/
AD9767
VREFIO
RSET
The DAC full-scale current, IOUTFS, is an output current 32 times
larger than the reference current, IREF.
I OUTFS = 32 × I REF
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS from 2 mA to 20 mA by setting IREF between 62.5 μA and
625 μA. The wide adjustment range of IOUTFS provides several
benefits. The first relates directly to the power dissipation of
the AD9763/AD9765/AD9767, which is proportional to IOUTFS
(refer to the Power Dissipation section). The second relates to the
20 dB adjustment, which is useful for system gain control purposes.
It should be noted that when the RSET resistors are 2 kΩ or less,
the 22 nF capacitor and 256 Ω resistor shown in Figure 59 and
Figure 60 are not required and the reference current can be set
by the RSET resistors alone. For RSET values greater than 2 kΩ, the
22 nF capacitor and 256 Ω resistor networks are required to
ensure the stability of the reference control amplifier(s).
Regardless of the value of RSET, however, if the RSET resistor is
located more than ~10 cm away from the pin, use of the 22 nF
capacitor and 256 Ω resistor is recommended.
Rev. E | Page 22 of 40
AD9763/AD9765/AD9767
DAC TRANSFER FUNCTION
Both DACs in the AD9763/AD9765/AD9767 provide complementary current outputs, IOUTA and IOUTB. IOUTA provides a near
full-scale current output (IOUTFS) when all bits are high (that is,
DAC CODE = 1024/4095/16,384 for the AD9763/AD9765/
AD9767, respectively), while IOUTB, the complementary output,
provides no current. The current output appearing at IOUTA and
IOUTB is a function of both the input code and IOUTFS. IOUTA for the
AD9763, AD9765, and AD9767, respectively, can be expressed as
B
B
B
The gain drift temperature performance for a single-ended
(VOUTA and VOUTB) or differential output (VDIFF) of the
AD9763/AD9765/AD9767 can be enhanced by selecting
temperature tracking resistors for RLOAD and RSET due to their
ratiometric relationship.
B
ANALOG OUTPUTS
The complementary current outputs, IOUTA and IOUTB, in each
DAC can be configured for single-ended or differential
operation. IOUTA and IOUTB can be converted into complementary
single-ended voltage outputs, VOUTA and VOUTB, via a load
resistor (RLOAD) as described in Equation 5 through Equation 7.
The differential voltage (VDIFF) existing between VOUTA and VOUTB
can be converted to a single-ended voltage via a transformer or
differential amplifier configuration. The ac performance of the
AD9763/AD9765/AD9767 is optimum and specified using a
differential transformer-coupled output in which the voltage
swing at IOUTA and IOUTB is limited to ±0.5 V. If a single-ended
unipolar output is desired, select IOUTA.
B
B
IOUTA = (DAC CODE/1024) × IOUTFS
(1)
IOUTA = (DAC CODE/4096) × IOUTFS
IOUTA = (DAC CODE/16,384) × IOUTFS
IOUTB for the AD9763, AD9765, and AD9767, respectively, can be
expressed as
B
IOUTB = (1023 − DAC CODE/1024) × IOUTFS
(2)
B
IOUTB = (1023 − DAC CODE/4096) × IOUTFS
IOUTB = (1023 − DAC CODE/16,384) × IOUTFS
where DAC CODE = 0 to 1024, 0 to 4095, or 0 to 16,384 (decimal
representation).
IOUTFS is a function of the reference current (IREF). This is nominally
set by a reference voltage (VREFIO) and an external resistor (RSET).
It can be expressed as
IOUTFS = 32 × IREF
(3)
where IREF is set as discussed in the Setting the Full-Scale
Current section.
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTA and IOUTB
should be directly connected to matching resistive loads (RLOAD)
that are tied to the analog common (ACOM). Note that RLOAD
can represent the equivalent load resistance seen by IOUTA or IOUTB,
as is the case in a doubly terminated 50 Ω or 75 Ω cable. The singleended voltage output appearing at the IOUTA and IOUTB nodes is
B
VOUTA = IOUTA × RLOAD
(5)
VOUTB = IOUTB × RLOAD
(6)
Note that the full-scale value of VOUTA and VOUTB must not
exceed the specified output compliance range to maintain the
specified distortion and linearity performance.
VDIFF = (IOUTA − IOUTB) × RLOAD
(7)
Equation 7 highlights some of the advantages of operating the
AD9763/AD9765/AD9767 differentially. First, the differential
operation helps cancel common-mode error sources associated
with IOUTA and IOUTB such as noise, distortion, and dc offsets.
Second, the differential code-dependent current and subsequent
voltage, VDIFF, is twice the value of the single-ended voltage
output (that is, VOUTA or VOUTB), thus providing twice the signal
power to the load.
The distortion and noise performance of the AD9763/AD9765/
AD9767 can be enhanced when it is configured for differential
operation. The common-mode error sources of both IOUTA and
IOUTB can be significantly reduced by the common-mode rejection
of a transformer or differential amplifier. These common-mode
error sources include even-order distortion products and noise.
The enhancement in distortion performance becomes more
significant as the frequency content of the reconstructed waveform
increases. This is due to the first-order cancellation of various
dynamic common-mode distortion mechanisms, digital feedthrough, and noise.
Performing a differential-to-single-ended conversion via a transformer also provides the ability to deliver twice the reconstructed
signal power to the load, assuming no source termination. Because
the output currents of IOUTA and IOUTB are complementary, they
become additive when processed differentially. A properly selected
transformer allows the AD9763/AD9765/AD9767 to provide the
required power and voltage levels to different loads.
B
The output impedance of IOUTA and IOUTB is determined by the
equivalent parallel combination of the PMOS switches associated
with the current sources and is typically 100 kΩ in parallel with
5 pF. It is also slightly dependent on the output voltage (that is,
VOUTA and VOUTB) due to the nature of a PMOS device. As a result,
maintaining IOUTA and/or IOUTB at a virtual ground via an I-V
op amp configuration results in the optimum dc linearity. Note that
the INL/DNL specifications for the AD9763/AD9765/AD9767 are
measured with IOUTA maintained at a virtual ground via an op amp.
B
B
Rev. E | Page 23 of 40
B
B
AD9763/AD9765/AD9767
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. When IOUTFS is decreased
from 20 mA to 2 mA, the positive output compliance range
degrades slightly from its nominal 1.25 V to 1.00 V. The optimum
distortion performance for a single-ended or differential output
is achieved when the maximum full-scale signal at IOUTA and IOUTB
does not exceed 0.5 V. Applications requiring the AD9763/
AD9765/AD9767 output (that is, VOUTA and/or VOUTB) to extend its
output compliance range must size RLOAD accordingly. Operation
beyond this compliance range adversely affects the linearity
performance of the AD9763/AD9765/AD9767 and
subsequently degrades its distortion performance.
DIGITAL INPUTS
The digital inputs of the AD9763/AD9765/AD9767 consist of
two independent channels. For the dual-port mode, each DAC has
its own dedicated 10-/12-/14-bit data port: WRT line and CLK line.
In the interleaved timing mode, the function of the digital control
pins changes as described in the Interleaved Mode Timing section.
The 10-/12-/14-bit parallel data inputs follow straight binary
coding, where the most significant bits (MSBs) are DB9P1 and
DB9P2 for the AD9763, DB11P1 and DB11P2 for the AD9765, and
DB13P1 and DB13P2 for the AD9767, and the least significant bits
(LSBs) are DB0P1 and DB0P2 for all three parts. IOUTA produces a
full-scale output current when all data bits are at Logic 1. IOUTB
produces a complementary output with the full-scale current
split between the two outputs as a function of the input code.
PORT 1
INPUT
LATCH
INTERLEAVED
DATA IN, PORT 1
DAC1
LATCH
DAC1
DEINTERLEAVED
DATA OUT
PORT 2
INPUT
LATCH
IQWRT
IQSEL
IQCLK
IQRESET
DAC2
LATCH
00617-061
IOUTA and IOUTB also have a negative and positive voltage
compliance range that must be adhered to in order to achieve
optimum performance. The negative output compliance range
of −1.0 V is set by the breakdown limits of the CMOS process.
Operation beyond this maximum limit may result in a breakdown
of the output stage and affect the reliability of the
AD9763/AD9765/AD9767.
DAC2
÷2
Figure 61. Latch Structure in Interleaved Mode
Dual-Port Mode Timing
When the MODE pin is at Logic 1, the AD9763/AD9765/AD9767
operates in dual-port mode (refer to Figure 57). The AD9763/
AD9765/AD9767 functions as two distinct DACs. Each DAC
has its own completely independent digital input and control lines.
The AD9763/AD9765/AD9767 features a double-buffered data
path. Data enters the device through the channel input latches.
This data is then transferred to the DAC latch in each signal
path. After the data is loaded into the DAC latch, the analog
output settles to its new value.
For general consideration, the WRT lines control the channel
input latches, and the CLK lines control the DAC latches. Both
sets of latches are updated on the rising edge of their respective
control signals.
The rising edge of CLK must occur before or simultaneously
with the rising edge of WRT. If the rising edge of CLK occurs
after the rising edge of WRT, a minimum delay of 2 ns must be
maintained from the rising edge of WRT to the rising edge of CLK.
Timing specifications for dual-port mode are shown in Figure 62
and Figure 63.
tS
tH
B
WRT1/WRT2
tLPW
CLK1/CLK2
tCPW
IOUTA
OR
IOUTB
00617-062
The digital interface is implemented using an edge-triggered
master/slave latch. The DAC outputs are updated following
either the rising edge or every other rising edge of the clock,
depending on whether dual or interleaved mode is used. The
DAC outputs are designed to support a clock rate as high as
125 MSPS. The clock can be operated at any duty cycle that
meets the specified latch pulse width. The setup and hold times
can also be varied within the clock cycle as long as the specified
minimum times are met, although the location of these transition
edges may affect digital feedthrough and distortion performance.
Best performance is typically achieved when the input data
transitions on the falling edge of a 50% duty cycle clock.
DATA IN
tPD
Figure 62. Dual-Port Mode Timing
DATA IN
D1
D2
D3
D4
D5
WRT1/WRT2
CLK1/CLK2
The AD9763/AD9765/AD9767 can operate in two timing
modes, dual and interleaved, which are described in the
following sections. The block diagram in Figure 61 represents
the latch architecture in the interleaved timing mode.
Rev. E | Page 24 of 40
IOUTA
OR
IOUTB
XX
D1
D2
Figure 63. Dual-Port Mode Timing
D3
D4
00617-063
DAC TIMING
AD9763/AD9765/AD9767
tS
Interleaved Mode Timing
DATA IN
IQSEL
Data enters the device on the rising edge of IQWRT. The logic level
of IQSEL steers the data to either Channel Latch 1 (IQSEL = 1) or
to Channel Latch 2 (IQSEL = 0). For proper operation, IQSEL
must change state only when IQWRT and IQCLK are low.
tLPW
When IQRESET is high, IQCLK is disabled. When IQRESET
goes low, the next rising edge on IQCLK updates both DAC
latches with the data present at their inputs. In the interleaved
mode, IQCLK is divided by 2 internally. Following this first
rising edge, the DAC latches are only updated on every other
rising edge of IQCLK. In this way, IQRESET can be used to
synchronize the routing of the data to the DACs.
IQCLK
tPD
IOUTA
OR
IOUTB
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
Figure 65. 5 V Only Interleaved Mode Timing
Similar to the order of CLK and WRT in dual-port mode,
IQCLK must occur before or simultaneously with IQWRT.
INTERLEAVED
DATA
Timing specifications for interleaved mode are shown in Figure 64
and Figure 66.
xx
D1
D2
D3
D4
D5
IQSEL
The digital inputs are CMOS compatible with logic thresholds,
VTHRESHOLD, set to approximately half the digital positive supply
(DVDDx), or
IQWRT
IQCLK
VTHRESHOLD = DVDDx/2(±20%)
IQRESET
tH
DAC OUTPUT
PORT 1
DATA IN
xx
xx
DAC OUTPUT
PORT 2
500 ps
D3
D1
D4
D2
00617-066
tS
tH*
IQWRT
00617-065
When the MODE pin is at Logic 0, the AD9763/AD9765/AD9767
operate in interleaved mode (refer to Figure 61). In addition,
WRT1 functions as IQWRT, CLK1 functions as IQCLK, WRT2
functions as IQSEL, and CLK2 functions as IQRESET.
tH
Figure 66. Interleaved Mode Timing
IQSEL
IQWRT
tH *
tLPW
IQCLK
500 ps
tPD
*APPLIES TO FALLING EDGE OF IQCLK/IQWRT AND IQSEL ONLY.
00617-064
IOUTA
OR
IOUTB
The internal digital circuitry of the AD9763/AD9765/AD9767
is capable of operating at a digital supply of 3.3 V or 5 V. As a
result, the digital inputs can also accommodate TTL levels when
DVDD1/DVDD2 is set to accommodate the maximum high
level voltage (VOH(MAX)) of the TTL drivers. A DVDD1/DVDD2
of 3.3 V typically ensures proper compatibility with bipolar TTL
logic families. Figure 67 shows the equivalent digital input
circuit for the data and clock inputs. The sleep mode input is
similar, with the exception that it contains an active pull-down
circuit, thus ensuring that the AD9763/AD9765/AD9767
remains enabled if this input is left disconnected.
DVDD1
Figure 64. 5 V or 3.3 V Interleaved Mode Timing
DIGITAL
INPUT
00617-067
At 5 V it is permissible to drive IQWRT and IQCLK together as
shown in Figure 65, but at 3.3 V the interleaved data transfer is
not reliable.
Figure 67. Equivalent Digital Input
Rev. E | Page 25 of 40
AD9763/AD9765/AD9767
80
Because the AD9763/AD9765/AD9767 is capable of being clocked
up to 125 MSPS, the quality of the clock and data input signals
are important in achieving the optimum performance. Operating
the AD9763/AD9765/AD9767 with reduced logic swings and a
corresponding digital supply (DVDD1/DVDD2) results in the
lowest data feedthrough and on-chip digital noise. The drivers of
the digital data interface circuitry should be specified to meet the
minimum setup and hold times of the AD9763/AD9765/AD9767
as well as its required minimum and maximum input logic level
thresholds.
The external clock driver circuitry provides the AD9763/AD9765/
AD9767 with a low-jitter clock input meeting the minimum
and maximum logic levels while providing fast edges. Fast clock
edges help minimize jitter manifesting itself as phase noise on a
reconstructed waveform. Therefore, the clock input should be
driven by the fastest logic family suitable for the application.
Note that the clock input can also be driven via a sine wave, which
is centered around the digital threshold (that is, DVDDx/2) and
meets the minimum and maximum logic threshold. This
typically results in a slight degradation in the phase noise, which
becomes more noticeable at higher sampling rates and output
frequencies. In addition, at higher sampling rates, the 20%
tolerance of the digital logic threshold should be considered,
because it affects the effective clock duty cycle and,
subsequently, cuts into the required data setup and hold times.
Input Clock and Data Timing Relationship
SNR in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9763/AD9765/AD9767 are rising
edge triggered and therefore exhibit SNR sensitivity when the
data transition is close to this edge. The goal when applying the
AD9763/AD9765/AD9767 is to make the data transition close
to the falling clock edge. This becomes more important as the
sample rate increases. Figure 68 shows the relationship of SNR
to clock placement with different sample rates. Note that at the
lower sample rates, much more tolerance is allowed in clock
placement; much more care must be taken at higher rates.
AD9763
AD9765
AD9767
SNR (dBc)
60
50
40
30
20
10
0
–4
–3
–2
–1
0
1
2
TIME OF DATA CHANGE RELATIVE TO
RISING CLOCK EDGE (ns)
3
4
00617-068
Digital signal paths should be kept short, and run lengths should be
matched to avoid propagation delay mismatch. The insertion
of a low value (that is, 20 Ω to 100 Ω) resistor network between
the AD9763/AD9765/AD9767 digital inputs and driver outputs
can be helpful in reducing any overshooting and ringing at the
digital inputs that contribute to digital feedthrough. For longer
board traces and high data update rates, stripline techniques
with proper impedance and termination resistors should be
considered to maintain “clean” digital inputs.
70
Figure 68. SNR vs. Clock Placement @ fOUT = 20 MHz and fCLK = 125 MSPS
SLEEP MODE OPERATION
The AD9763/AD9765/AD9767 has a power-down function that
turns off the output current and reduces the supply current to less
than 8.5 mA over the specified supply range of 3.3 V to 5 V and
over the full operating temperature range. This mode can be
activated by applying a Logic Level 1 to the SLEEP pin. The
SLEEP pin logic threshold is equal to 0.5 × AVDD. This digital
input also contains an active pull-down circuit that ensures the
AD9763/AD9765/AD9767 remains enabled if this input is left
disconnected. The AD9763/AD9765/AD9767 require less than
50 ns to power down and approximately 5 μs to power back up.
POWER DISSIPATION
The power dissipation (PD) of the AD9763/AD9765/AD9767 is
dependent on several factors, including
•
•
•
•
the power supply voltages (AVDD and DVDD1/DVDD2)
the full-scale current output (IOUTFS)
the update rate (fCLK)
the reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current (IAVDD) and the digital supply current (IDVDD).
IAVDD is directly proportional to IOUTFS, as shown in Figure 69,
and is insensitive to fCLK.
Conversely, IDVDD is dependent on the digital input waveform,
the fCLK, and the digital supply (DVDD1/DVDD2). Figure 70
and Figure 71 show IDVDD as a function of full-scale sine wave
output ratios (fOUT/fCLK) for various update rates with DVDD1 =
DVDD2 = 5 V and DVDD1 = DVDD2 = 3.3 V, respectively. Note
that IDVDD is reduced by more than a factor of 2 when
DVDD1/DVDD2 is reduced from 5 V to 3.3 V.
Rev. E | Page 26 of 40
AD9763/AD9765/AD9767
18
80
125MSPS
16
70
14
100MSPS
90
IDVDD (mA)
IAVDD (mA)
12
50
40
10
65MSPS
8
6
30
25MSPS
4
0
5
10
15
20
25
IOUTFS
00617-069
10
Figure 69. IAVDD vs. IOUTFS
30
125MSPS
25
65MSPS
15
25MSPS
5
5MSPS
0
0.1
0.2
0.3
0.4
RATIO (fOUT/fCLK)
0.5
00617-070
IDVDD (mA)
100MSPS
20
10
0
0
0.1
0.2
0.3
0.4
RATIO (fOUT/fCLK)
Figure 71. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 3.3 V
35
0
5MSPS
2
Figure 70. IDVDD vs. Ratio @ DVDD1 = DVDD2 = 5 V
Rev. E | Page 27 of 40
0.5
00617-071
20
AD9763/AD9765/AD9767
APPLYING THE AD9763/AD9765/AD9767
OUTPUT CONFIGURATIONS
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically
around ACOM and must be maintained with the output compliance range of the AD9763/AD9765/AD9767 to achieve the
specified performance. A differential resistor (RDIFF) can be
inserted in applications where the output of the transformer is
connected to the load (RLOAD) via a passive reconstruction filter
or cable. RDIFF is determined by the transformer’s impedance
ratio and provides the proper source termination that results in a
low VSWR. Approximately half the signal power will be dissipated
across RDIFF.
B
A single-ended output is suitable for applications requiring
a unipolar voltage output. A positive unipolar output voltage
results if IOUTA and/or IOUTB is connected to an appropriately
sized load resistor (RLOAD) referred to as ACOM. This configuration
may be more suitable for a single-supply system requiring a
dc-coupled, ground-referred output voltage. Alternatively, an
amplifier can be configured as an I-V converter, thus converting
IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity because IOUTA or IOUTB is
maintained at a virtual ground. Note that IOUTA provides slightly
better performance than IOUTB.
B
B
DIFFERENTIAL COUPLING USING AN OP AMP
An op amp can also be used as shown in Figure 73 to perform a
differential-to-single-ended conversion. The AD9763/AD9765/
AD9767 is configured with two equal load resistors (RLOAD) of
25 Ω each. The differential voltage developed across IOUTA and
IOUTB is converted to a single-ended signal via the differential
op amp configuration. An optional capacitor can be installed
across IOUTA and IOUTB, forming a real pole in a low-pass filter.
The addition of this capacitor often enhances the op amp’s
distortion performance by preventing the DAC’s high-slewing
output from overloading the op amp’s input.
B
B
500Ω
IOUTA
Mini-Circuits
T1-1T
AD9763/
AD9765/
AD9767
225Ω
IOUTB
An RF transformer can be used as shown in Figure 72 to
perform a differential-to-single-ended signal conversion. A
differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the pass band of the transformer. An RF transformer
such as the Mini-Circuits® T1-1T provides excellent rejection of
common-mode distortion (that is, even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios can also be used
for impedance matching purposes. Note that the transformer
provides ac coupling only.
RLOAD
IOUTB
OPTIONAL
RDIFF
00617-072
IOUTA
225Ω
AD9763/
AD9765/
AD9767
DIFFERENTIAL COUPLING USING A
TRANSFORMER
Figure 72. Differential Output Using a Transformer
The center tap on the primary side of the transformer must be
connected to ACOM to provide the necessary dc current path
AD8047
COPT
500Ω
25Ω
25Ω
00617-073
The following sections illustrate some typical output configurations
for the AD9763/AD9765/AD9767, with IOUTFS set to a nominal
20 mA, unless otherwise noted. For applications requiring the
optimum dynamic performance, a differential output configuration
is suggested. A differential output configuration can consist of
either an RF transformer or a differential op amp configuration.
The transformer configuration provides the optimum high
frequency performance and is recommended for any application
allowing for ac coupling. The differential op amp configuration
is suitable for applications requiring dc coupling, bipolar
output, signal gain, and/or level shifting within the bandwidth
of the chosen op amp.
Figure 73. DC Differential Coupling Using an Op Amp
The common-mode rejection of this configuration is typically
determined by the resistor matching. In this circuit, the
differential op amp circuit using the AD8047 is configured to
provide some additional signal gain. The op amp must operate
from a dual supply because its output is approximately ±1.0 V.
Select a high speed amplifier capable of preserving the
differential performance of the AD9763/AD9765/AD9767
while meeting other system level objectives (that is, cost or
power). Consider the op amp’s differential gain, gain setting
resistor values, and full-scale output swing capabilities when
optimizing this circuit.
The differential circuit shown in Figure 74 provides the
necessary level shifting required in a single-supply system.
In this case, AVDD, which is the positive analog supply for both
the AD9763/AD9765/AD9767 and the op amp, is used to level
shift the differential output of the AD9763/AD9765/AD9767 to
midsupply (that is, AVDD/2). The AD8055 is a suitable op amp
for this application.
Rev. E | Page 28 of 40
AD9763/AD9765/AD9767
COPT
500Ω
IOUTA
225Ω
COPT
25Ω
1kΩ
25Ω
IOUTFS = 10mA
IOUTA
AVDD
500Ω
AD9763/
AD9765/
AD9767
Figure 76. Unipolar Buffered Voltage Output
SINGLE-ENDED, UNBUFFERED VOLTAGE OUTPUT
Figure 75 shows the AD9763/AD9765/AD9767 configured to
provide a unipolar output range of approximately 0 V to 0.5 V
for a doubly terminated 50 Ω cable, because the nominal fullscale current (IOUTFS) of 20 mA flows through the equivalent
RLOAD of 25 Ω. In this case, RLOAD represents the equivalent load
resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected directly to ACOM or via a matching RLOAD.
Different values of IOUTFS and RLOAD can be selected as long as the
positive compliance range is adhered to. One additional
consideration in this mode is the INL (see the Analog Outputs
section). For optimum INL performance, the single-ended,
buffered voltage output configuration is suggested.
B
IOUTFS = 20mA
AD9763/
AD9765/
AD9767
VOUTA = 0V TO 0.5V
50Ω
50Ω
00617-075
IOUTB
25Ω
VOUT = IOUTFS × RFB
200Ω
IOUTB
Figure 74. Single-Supply DC Differential-Coupled Circuit
IOUTA
U1
00617-076
225Ω
IOUTB
RFB
200Ω
AD8055
00617-074
AD9763/
AD9765/
AD9767
Figure 75. 0 V to 0.5 V Unbuffered Voltage Output
SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT
CONFIGURATION
Figure 76 shows a buffered single-ended output configuration
in which the U1 op amp performs an I-V conversion on the
AD9763/AD9765/AD9767 output current. U1 maintains IOUTA
(or IOUTB) at a virtual ground, thus minimizing the nonlinear
output impedance effect on the INL performance of the DAC,
as described in the Analog Outputs section. Although this singleended configuration typically provides the best dc linearity
performance, its ac distortion performance at higher DAC update
rates may be limited by the slewing capabilities of U1. U1
provides a negative unipolar output voltage, and its full-scale
output voltage is simply the product of RFB and IOUTFS. Set the
full-scale output within U1’s voltage output swing capabilities
by scaling IOUTFS and/or RFB. An improvement in ac distortion
performance may result with a reduced IOUTFS because the signal
current U1 has to sink will be subsequently reduced.
POWER AND GROUNDING CONSIDERATIONS
Power Supply Rejection
Many applications seek high speed and high performance under
less than ideal operating conditions. In these applications, the
implementation and construction of the printed circuit board is
as important as the circuit design. Proper RF techniques must
be used for device selection, placement, and routing as well as
power supply bypassing and grounding to ensure optimum
performance. Figure 89 to Figure 94 illustrate recommended
printed circuit board ground, power, and signal plane layouts
that are implemented on the AD9763/AD9765/AD9767
evaluation board.
One factor that can measurably affect system performance is
the ability of the DAC output to reject dc variations or ac noise
superimposed on the analog or digital dc power distribution.
This is referred to as the power supply rejection ratio (PSRR).
For dc variations of the power supply, the resulting performance
of the DAC directly corresponds to a gain error associated with
the DAC’s full-scale current, IOUTFS. AC noise on the dc supplies
is common in applications where the power distribution is
generated by a switching power supply. Typically, switching
power supply noise occurs over the spectrum of tens of
kilohertz to several megahertz. The PSRR vs. frequency of the
AD9763/AD9765/AD9767 AVDD supply over this frequency
range is shown in Figure 77.
B
90
80
75
70
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
FREQUENCY (MHz)
Figure 77. AVDD Power Supply Rejection Ratio vs. Frequency
Rev. E | Page 29 of 40
00617-077
PSRR (dB)
85
AD9763/AD9765/AD9767
An example serves to illustrate the effect of supply noise on the
analog supply. Suppose a switching regulator with a switching
frequency of 250 kHz produces 10 mV of noise and, for simplicity’s
sake, all of this noise is concentrated at 250 kHz (that is, ignore
harmonics). To calculate how much of this undesired noise will
appear as current noise superimposed on the DAC full-scale
current, IOUTFS, one must determine the PSRR in decibels using
Figure 77 at 250 kHz. To calculate the PSRR for a given RLOAD,
such that the units of PSRR are converted from A/V to V/V,
adjust the curve in Figure 77 by the scaling factor 20 × log(RLOAD).
For example, if RLOAD is 50 Ω, the PSRR is reduced by 34 dB (that
is, the PSRR of the DAC at 250 kHz, which is 85 dB in Figure 77,
becomes 51 dB VOUT/VIN).
Proper grounding and decoupling are primary objectives in any
high speed, high resolution system. The AD9763/AD9765/AD9767
features separate analog and digital supply and ground pins to
optimize the management of analog and digital ground currents
in a system. In general, decouple the analog supply (AVDD) to
the analog common (ACOM) as close to the chip as physically
possible. Similarly, decouple the digital supply (DVDD1/DVDD2)
to the digital common (DCOM1/DCOM2) as close to the chip
as possible.
For those applications that require a single 5 V or 3.3 V supply
for both the analog and digital supplies, a clean analog supply
can be generated using the circuit shown in Figure 78. The
circuit consists of a differential LC filter with separate power
supply and return lines. Lower noise can be attained by using
low-ESR type electrolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
Rev. E | Page 30 of 40
ELECTROLYTIC
100µF
CERAMIC
10µF
TO
22µF
AVDD
0.1µF
ACOM
TANTALUM
5V
POWER SUPPLY
Figure 78. Differential LC Filter for Single 5 V and 3.3 V Applications
00617-078
Note that the data in Figure 77 is given in terms of current out
vs. voltage in. Noise on the analog power supply has the effect
of modulating the internal current sources and therefore the
output current. The voltage noise on AVDD, therefore, is added
in a nonlinear manner to the desired IOUT. PSRR is very code
dependent, thus producing mixing effects that can modulate
low frequency power supply noise to higher frequencies. Worstcase PSRR for either one of the differential DAC outputs occurs
when the full-scale current is directed toward that output. As a
result, the PSRR measurement in Figure 77 represents a worstcase condition in which the digital inputs remain static and the
full-scale output current of 20 mA is directed to the DAC
output being measured.
AD9763/AD9765/AD9767
APPLICATIONS
–20
VDSL EXAMPLE APPLICATIONS USING THE
AD9765 AND AD9767
–30
–50
(dBm)
–60
–70
–80
–90
–100
–120
0.665
0.685
0.705
0.725
0.745
0.765
0.785
0.805
0.825
FREQUENCY (MHz)
00617-080
–110
Figure 80. AD9767 Notch in Missing Bin at 750 kHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
4.85
4.90
4.95
5.00
5.05
5.10
5.15
FREQUENCY (MHz)
–20
00617-081
As with other multitone applications, each VDSL tone is
capable of transmitting a given number of bits, depending on
the signal-to-noise ratio (SNR) in a narrow band around that
tone. For a typical VDSL application, the tones are evenly
spaced over the range of several kHz to 10 MHz. At the high
frequency end of this range, performance is generally limited by
cable characteristics and environmental factors such as external
interferers. Performance at the lower frequencies is much more
dependent on the performance of the components in the signal
chain. In addition to in-band noise, intermodulation from other
tones can also potentially interfere with the data recovery for
a given tone. The two graphs in Figure 79 and Figure 81
represent a 500-tone missing bin test vector, with frequencies
evenly spaced from 400 Hz to 10 MHz. This test is very
commonly done to determine if distortion limits the number of
bits that can be transmitted in a tone. The test vector has a
series of missing tones around 750 kHz, which is represented in
Figure 79, and a series of missing tones around 5 MHz, which is
represented in Figure 81. In both cases, the spurious-free
dynamic range (SFDR) between the transmitted tones and the
empty bins is greater than 60 dB.
–40
(dBm)
Very high frequency digital subscriber line (VDSL) technology is
growing rapidly in applications requiring data transfer over
relatively short distances. By using quadrature amplitude
modulation (QAM) and transmitting the data in discrete multiple
tones (DMT), high data rates can be achieved.
Figure 81. AD9765 Notch in Missing Bin at 5 MHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–30
–40
–20
–50
(dBm)
–60
–40
–70
–80
(dBm)
–60
–90
–100
–80
0.685
0.705
0.725
0.745
0.765
FREQUENCY (MHz)
0.785
0.805
0.825
Figure 79. AD9765 Notch in Missing Bin at 750 kHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
–100
–120
4.85
4.90
4.95
5.00
5.05
5.10
5.15
FREQUENCY (MHz)
Figure 82. AD9767 Notch in Missing Bin at 5 MHz Is Down >60 dB
(Peak Amplitude = 0 dBm)
Rev. E | Page 31 of 40
00617-082
–120
0.665
00617-079
–110
AD9763/AD9765/AD9767
baseband channels. A quadrature mixer modulates the I and Q
components with the in-phase and quadrature carrier
frequency and then sums the two outputs to provide the QAM
signal.
QAM is one of the most widely used digital modulation
schemes in digital communications systems. This modulation
technique can be found in FDM as well as spread spectrum
(that is, CDMA) based systems. A QAM signal is a carrier
frequency that is modulated in both amplitude (that is, AM
modulation) and phase (that is, PM modulation). It can be
generated by independently modulating two carriers of
identical frequency but with a 90° phase difference. This results
in an in-phase (I) carrier component and a quadrature (Q) carrier
component at a 90° phase shift with respect to the I component.
The I and Q components are then summed to provide a QAM
signal at the specified carrier frequency.
10
DAC
DSP
OR
ASIC
0°
CARRIER
FREQUENCY
10
TO
MIXER
Σ
90°
DAC
NYQUIST
FILTERS
00617-083
QUADRATURE AMPLITUDE MODULATION (QAM)
EXAMPLE USING THE AD9763
QUADRATURE
MODULATOR
Figure 83. Typical Analog QAM Architecture
In this implementation, it is much more difficult to maintain
proper gain and phase matching between the I and Q channels.
The circuit implementation shown in Figure 84 helps improve the
matching between the I and Q channels, and it shows a path for
upconversion using the AD8346 quadrature modulator.
The AD9763 provides both I and Q DACs a common reference
that improves the gain matching and stability. RCAL can be used
to compensate for any mismatch in gain between the two
channels. The mismatch can be attributed to the mismatch
between RSET1 and RSET2, the effective load resistance of each
channel, and/or the voltage offset of the control amplifier in
each DAC. The differential voltage outputs of both DACs in the
AD9763 are fed into the respective differential inputs of the
AD8346 via matching networks.
A common and traditional implementation of a QAM
modulator is shown in Figure 83. The modulation is performed
in the analog domain in which two DACs are used to generate
the baseband I and Q components. Each component is then
typically applied to a Nyquist filter before being applied to
a quadrature mixer. The matching Nyquist filters shape and
limit each component’s spectral envelope while minimizing
intersymbol interference. The DAC is typically updated at the
QAM symbol rate, or at a multiple of the QAM symbol rate if an
interpolating filter precedes the DAC. The use of an
interpolating filter typically eases the implementation and
complexity of the analog filter, which can be a significant
contributor to mismatches in gain and phase between the two
AVDD
ROHDE & SCHWARZ
FSEA30B
OR EQUIVALENT
SPECTRUM ANALYZER
0.1µF
ACOM AVDD
PORT Q
CLK1/IQCLK
RL
LA
IOUTA
I DAC
LATCH
I
DAC
AD9763/
AD9765/
AD9767
Q DAC
LATCH
RL
CB
CA
RL LA
IOUTA
RL LA RL
IOUTB
WRT2/IQSEL
RL
LA
BBIP
VOUT
RB
RA
256Ω
22nF
MODE
FSADJ1
2kΩ
20kΩ
FSADJ2
256Ω
22nF
NOTES
1. DAC FULL-SCALE OUTPUT CURRENT = IOUTFS.
2. RA, RB, AND RL ARE THIN FILM RESISTOR NETWORKS
WITH 0.1% MATCHING, 1% ACCURACY AVAILABLE
FROM OHMTEK ORNXXXXD SERIES OR EQUIVALENT.
2kΩ
20kΩ
+
BBQP
RB
RB
LOIP
RA
PHASE
SPLITTER
LOIN
CFILTER
BBQN
RL
VDIFF = 1.82V p-p
SLEEP
VPBF
RL
CB
CA
RA
BBIN
IOUTB
Q
DAC
RA
RB
AD8346
REFIO
DIFFERENTIAL
RLC FILTER
0.1µF RL = 200Ω
RA = 2500Ω
RB = 500Ω
RP = 200Ω
CA = 280pF
CB = 45pF
LA = 10µH
IOUTFS = 11mA
AVDD = 5.0V
VCM = 1.2V
ROHDE & SCHWARZ
SIGNAL GENERATOR
AVDD
AD976x
RB
0 TO IOUTFS
Figure 84. Baseband QAM Implementation Using an AD9763 and an AD8346
Rev. E | Page 32 of 40
RL
VDAC
RA
AD8346
VMOD
00617-084
WRT1/IQWRT
DIGITAL INTERFACE
TEKTRONIX
AWG2021
WITH
OPTION 4
PORT I
DCOM1/ DVDD1/
DCOM2 DVDD2
AD9763/AD9765/AD9767
I and Q digital data can be fed into the AD9763 in two ways. In
dual-port mode, the digital I information drives one input port,
and the digital Q information drives the other input port. If no
interpolation filter precedes the DAC, the symbol rate is the rate
at which the system clock drives the CLK and WRT pins on the
AD9763. In interleaved mode, the digital input stream at Port 1
contains the I and the Q information in alternating digital words.
Using IQSEL and IQRESET, the AD9763 can be synchronized to
the I and Q data streams. The internal timing of the AD9763 routes
the selected I and Q data to the correct DAC output. In interleaved
mode, if no interpolation filter precedes the AD9763, the symbol
rate is half that of the system clock driving the digital data stream
and the IQWRT and IQCLK pins on the AD9763.
out-of-band is often referred to as adjacent channel power (ACP).
This is a regulatory issue due to the possibility of interference with
other signals being transmitted by air. Regulatory bodies define a
spectral mask outside of the transmit band, and the ACP must fall
under this mask. If distortion in the transmit path causes the
ACP to be above the spectral mask, filtering or different
component selection is needed to meet the mask requirements.
Figure 85 shows the results of using the AD9763/AD9765/
AD9767 with the AD8346 to reconstruct a wideband CDMA
signal centered at 2.4 GHz. The baseband signal is sampled at
65 MSPS and has a chip rate of 8 MHz.
–30
–40
CDMA
–50
–60
==
–70
(dB)
–80
–90
–100
–110
c11
c11
cu1
–120
cu1
C0
C0
–130
CENTER 2.4GHz
3MHz
FREQUENCY
SPAN 30MHz
00617-085
Code division multiple access (CDMA) is an air transmit/receive
scheme in which the signal in the transmit path is modulated
with a pseudorandom digital code (sometimes referred to as the
spreading code). The effect of this is to spread the transmitted
signal across a wide spectrum. Similar to a discrete multitone
(DMT) waveform, a CDMA waveform containing multiple
subscribers can be characterized as having a high peak to average
ratio (that is, crest factor), thus demanding highly linear
components in the transmit signal path. The bandwidth of the
spectrum is defined by the CDMA standard being used, and in
operation it is implemented by using a spreading code with
particular characteristics.
Figure 85. CDMA Signal, 8 MHz Chip Rate Sampled at 65 MSPS, Recreated at
2.4 GHz, Adjacent Channel Power >60 dBm
Distortion in the transmit path can lead to power being transmitted
out of the defined band. The ratio of power transmitted in-band to
Rev. E | Page 33 of 40
AD9763/AD9765/AD9767
EVALUATION BOARD
This board allows the user the flexibility to operate the AD9763/
AD9765/AD9767 in various configurations. Possible output
configurations include transformer coupled, resistor terminated,
and single-ended and differential outputs. The digital inputs can be
used in dual-port or interleaved mode and are designed to be
driven from various word generators, with the on-board option
to add a resistor network for proper load termination. When
operating the AD9763/AD9765/AD9767, best performance is
obtained by running the digital supply (DVDD1/DVDD2) at
3.3 V and the analog supply (AVDD) at 5 V.
GENERAL DESCRIPTION
The AD9763/AD9765/AD9767-EB is an evaluation board
for the AD9763/AD9765/AD9767 10-/12-/14-bit dual DAC.
Careful attention to layout and circuit design, combined with a
prototyping area, allow the user to easily and effectively evaluate
the AD9763/AD9765/AD9767 in any application where a high
resolution, high speed conversion is required.
SCHEMATICS
DVDDIN
B3
L1
DVDD
BEAD
BAN-JACK
AVDDIN
1
C9
10µF
2 25V
B2
BLK
TP37
BAN-JACK
BLK
TP38
BAN-JACK
BLK
TP39
TP43
BLK
DVDD
L2
AVDD
BEAD
1
C10
10µF
BLK
TP40
2 25V
B4
BAN-JACK
DGND
WHT
TP29
2
1
3
A B
JP16
JP5
A 2B
1
2
1
DVDD
WHT
TP31
JP4
A 2B
1
I
DGND; 3, 4, 5
WHT
TP32
1
DGND; 3, 4, 5
1
2
1
R1
50Ω
2
1
R2
50Ω
2
R3
50Ω
1
2
JP1
I
J
1
AGND
10
U1
Q
K
CLR
15
3
5
11
13
CLK
2
DVDD
C
JP3
A2 B
2 0.01µF
3
PRE
3
3
1 C8
2 0.1µF
A B
JP2
C
I
DGND; 3, 4, 5
WRT2 S4
IQSEL
1 C7
4
WHT
TP30
CLK2 S3
RESET
BLK
TP42
JP6
DCLKIN2
DGND; 3, 4, 5
CLK1 S2
IQCLK
BLK
TP41
TP44
BLK
JP9
DCLKIN1
WRT1 S1
IQWRT
RED
TP11
Q
6
12
PRE
J
9
Q
U2
CLK
K
74HC112
14
DGND; 8
DVDD; 16
7
Q
CLR
74HC112
DGND; 8
DVDD; 16
A B
DVDD
1
3
2
JP7
/2 CLOCK DIVIDER
3
WRT1
C
R4
50Ω
CLK1
CLK2
WHT
TP33
WRT2
SLEEP
1
2
SLEEP
R13
50Ω
RP16
R1
22Ω
RCOM
1
2
INP1
R2
22Ω
3
INP2
R3
22Ω
4
INP3
R4
22Ω
5
INP4
R5
22Ω
6
INP5
R6
22Ω
7
INP6
R7
22Ω
8
INP7
R8
22Ω
9
R9
22Ω
RP9
R1
22Ω
RCOM
10
1
INP8
2
R2
22Ω
3
R3
22Ω
4
R4
22Ω
5
R5
22Ω
6
R6
22Ω
7
R7
22Ω
8
INP9 INP10 INP11 INP12 INP13 INP14
R8
22Ω
9
R1
22Ω
1
2
R2
22Ω
3
R3
22Ω
4
R4
22Ω
5
R5
22Ω
6
R6
22Ω
7
R7
22Ω
8
R8
22Ω
9
R9
22Ω
10
10
INCK1
RP10
RCOM
R9
22Ω
RP15
R1
22Ω
RCOM
1
INP23 INP24 INP25 INP26 INP27 INP28 INP29 INP30
2
R2
22Ω
3
R3
22Ω
4
R4
22Ω
5
R5
22Ω
6
R6
22Ω
7
INP31 INP32 INP33 INP34 INP35 INP36
Figure 86. Power Decoupling and Clocks on AD9763/AD9765/AD9767 Evaluation Board
Rev. E | Page 34 of 40
R7
22Ω
8
R8
22Ω
9
INCK2
R9
22Ω
10
00617-086
RED
TP10
B1
AD9763/AD9765/AD9767
RP3
RP1
RCOM R1
R9
22Ω
P1
P1 1
4
P1
P1 3
6
P1
P1 5
8
P1
P1 7
10
P1
P1 9
12
P1
P1 11
14
P1
P1 13
16
P1
P1 15
18
P1
P1 17
20
P1
P1 19
22
P1
P1 21
24
P1
P1 23
26
P1
P1 25
28
P1
P1 27
30
P1
P1 29
32
P1
P1 31
34
P1
P1 33
36
P1
P1 35
38
P1
P1 37
40
P1
P1 39
INP2
INP3
INP4
INP5
INP6
INP7
INP8
INP9
INP10
INP11
INP12
INP13
INP14
1
16
RP5, 10Ω
3
14
RP5, 10Ω
5
12
RP5, 10Ω
7
10
RP6, 10Ω
1
16
RP6, 10Ω
3
14
RP6, 10Ω
5
12
2
DUTP2
15
DUTP3
RP5, 10Ω
4
DUTP4
13
DUTP5
RP5, 10Ω
6
DUTP6
11
DUTP7
RP5, 10Ω
8
DUTP8
9
DUTP9
RP6, 10Ω
2
DUTP10
15
DUTP11
RP6, 10Ω
4
DUTP12
13
DUTP13
RP6, 10Ω
DUTP14
11
RP6, 10Ω
INCK1
8
DCLKIN1
9
RP2
R9
1
P2 1
P2
P2 3
6
P2
P2 5
8
P2
P2 7
10
P2
P2 9
12
P2
P2 11
14
P2
P2 13
16
P2
P2 15
18
P2
P2 17
20
P2
P2 19
22
P2
P2 21
24
P2
P2 23
26
P2
P2 25
28
P2
P2 27
30
P2
P2 29
32
P2
P2 31
34
P2
P2 33
36
P2
P2 35
38
P2
P2 37
40
P2
P2 39
INP24
INP25
INP26
INP27
INP28
INP29
INP30
INP31
INP32
INP33
INP34
INP35
INP36
1
16
RP7, 10Ω
3
14
RP7, 10Ω
5
12
RP7, 10Ω
7
10
RP8, 10Ω
1
16
RP8, 10Ω
3
14
RP8, 10Ω
5
12
2 3 4 5 6 7 8 9 10
1
2
2 3 4 5 6 7 8 9 10
1
2 3 4 5 6 7 8 9 10
DUTP26
13
DUTP27
DUTP28
11
DUTP29
DUTP30
9
DUTP31
DUTP32
15
DUTP33
DUTP34
13
DUTP35
RP8, 10Ω
DUTP36
11
RP8, 10Ω
8
1
DUTP25
RP8, 10Ω
4
2 3 4 5 6 7 8 9 10
DUTP24
15
RP8, 10Ω
2
R9
33Ω
DUTP23
RP7, 10Ω
8
RCOM R1
DVDD
RP7, 10Ω
6
R9
33Ω
RP7, 10Ω
4
RP12
RCOM R1
RP7, 10Ω
6
INCK2
R9
22Ω
DVDD
RP7, 10Ω
RP14
RCOM R1
22Ω
P2
2 3 4 5 6 7 8 9 10
1
DUTP1
RCOM R1
4
2 3 4 5 6 7 8 9 10
1
R9
33Ω
DVDD
RP4
2
RCOM R1
RP5, 10Ω
6
INP23
R9
33Ω
2 3 4 5 6 7 8 9 10
1
RP11
RCOM R1
DCLKIN2
9
SPARES
RP5, 10Ω
7
10
RP8, 10Ω
7
10
Figure 87. Digital Input Signal Conditioning
Rev. E | Page 35 of 40
00617-087
2
DVDD
RP5, 10Ω
R9
22Ω
2 3 4 5 6 7 8 9 10
1
INP1
RP13
RCOM R1
AD9763/AD9765/AD9767
BL1
TP34
WHT
C1
2 VAL
1
C2
2 0.01µF
ACOM
JP15
DVDD
C3
2 0.1µF
AVDD
1
2
1
NC = 5
3
2
R11
VAL
3
A B
1
1:1
1
DB13P1 (MSB)
MODE 48
DUTP2
2
DB12P1
AVDD 47
DUTP3
3
DB11P1
IOUTA1 46
DUTP4
4
DB10P1
IOUTB1 45
DUTP5
5
DB9P1
DUTP6
6
DB8P1
REFIO 43
DUTP7
7
DB7P1
GAINCTRL 42
6
BL2
3
1
2
C4 2
10pF 1
DB6P1
FSADJ2 41
DUTP9
9
DB5P1
IOUTB2 40
DUTP10
10
DB4P1
IOUTA2 39
2
R6
50Ω
C5 2
10pF 1
TP45
WHT
R9
1.92kΩ
1
C16
22nF
1
C17
22nF
2
R10
1.92kΩ
2
11
DB3P1
DUTP12
12
DB2P1
SLEEP 37
SLEEP
DUTP13
13
DB1P1
DB0P2 36
DUTP36
DUTP14
14
DB0P1
DB1P2 35
DUTP35
15
DCOM1
DB2P2
34
DUTP34
16
DVDD1
DB3P2 33
DUTP33
17
WRT1/IQWRT
DB4P2 32
DUTP32
U2
2
1
DUTP11
WRT1
1
R5
50Ω
FSADJ1 44
8
S6
OUT1
T1
A B
DUTP1
DUTP8
2
AGND; 3, 4, 5
1
MODE
JP8
DVDD
4
ACOM 38
CLK1
18
CLK1/IQCLK
DB5P2 31
DUTP31
CLK2
19
CLK2/IQRESET
DB6P2
30
DUTP30
WRT2
20
WRT2/IQSEL
DB7P2 29
DUTP29
21
DCOM2
DB8P2 28
DUTP28
22
DVDD2
DB9P2 27
DUTP27
DUTP23
23
DB13P2 (MSB)
DB10P2 26
DUTP26
DUTP24
24
DB12P2
DB11P2 25
DUTP25
1
2
C15
10pF 1
C6
10pF 1
1
2
1
R7
50Ω
2
R8
50Ω
2
R15
256Ω
1
REFIO
TP36
WHT
2
R14
256Ω
1
1
2
2
C14
0.1µF
JP10
2
WHT
TP46
BL3
TP35
WHT
3
R12
VAL
2
NC = 5
4
AGND; 3, 4, 5
1:1
1
S11
OUT2
6
T2
BL4
AVDD
1
C11
2 1µF
1
C12
2 0.01µF
1
C13
2 0.1µF
Figure 88. AD9767 and Output Signal Conditioning
Rev. E | Page 36 of 40
00617-088
1
AD9763/AD9765/AD9767
00617-089
EVALUATION BOARD LAYOUT
00617-090
Figure 89. Assembly, Top Side
Figure 90. Assembly, Bottom Side
Rev. E | Page 37 of 40
00617-091
AD9763/AD9765/AD9767
00617-092
Figure 91. Layer 1, Top Side
Figure 92. Layer 2, Ground Plane
Rev. E | Page 38 of 40
00617-093
AD9763/AD9765/AD9767
00617-094
Figure 93. Layer 3, Power Plane
Figure 94. Layer 4, Bottom Side
Rev. E | Page 39 of 40
AD9763/AD9765/AD9767
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
24
0.27
0.22
0.17
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
051706-A
0.75
0.60
0.45
Figure 95. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9763AST
AD9763ASTRL
AD9763ASTZ 1
AD9763ASTZRL1
AD9765AST
AD9765ASTRL
AD9765ASTZ1
AD9765ASTZRL1
AD9767AST
AD9767ASTRL
AD9767ASTZ1
AD9767ASTZRL1
AD9763-EB
AD9765-EB
AD9767-EB
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
48-Lead Low Profile Quad Flat Package [LQFP]
Evaluation Board
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00617-0-1/08(E)
Rev. E | Page 40 of 40
Package Option
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
ST-48
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ST-48