AD9774ASZ

a FEATURES Single 3 V or 5 V Supply 14-Bit DAC Resolution and Input Data Width 32 MSPS Input Data Rate at 5 V 13.5 MHz Reconstruction Bandwidth 12 ENOBS @ 1 MHz 77 dBc SFDR @ 5 MHz 4ⴛ Interpolation Filter 69 dB Image Rejection 84% Passband to Nyquist Ratio 0.002 dB Passband Ripple 23 3/4 Cycle Latency Internal 4ⴛ Clock Multiplier On-Chip 1.20 V Reference 44-Lead MQFP Package APPLICATIONS Communication Transmit Channel: Wireless Basestations ADSL/HFC Modems Direct Digital Synthesis (DDS) PRODUCT DESCRIPTION The AD9774 is a single supply, oversampling, 14-bit digital-toanalog converter (DAC) optimized for waveform reconstruction applications requiring exceptional dynamic range. Manufactured on an advanced CMOS process, it integrates a complete, low distortion 14-bit DAC with a 4× digital interpolation filter and clock multiplier. The two-stage, 4× digital interpolation filter provides more than a six-fold reduction in the complexity of the analog reconstruction-filter. It does so by multiplying the input data rate by a factor of four while simultaneously suppressing the original inband images by more than 69 dB. The on-chip clock multiplier provides all the necessary clocks. The AD9774 can reconstruct full-scale waveforms having bandwidths as high as 13.5 MHz when operating at an input data rate of 32 MSPS and a DAC output rate of 128 MSPS. The 14-bit DAC provides differential current outputs to support differential or single-ended applications. A segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. Matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. The differential current outputs may be fed into a transformer or tied directly to an output resistor to provide two complementary, single-ended voltage outputs. A differential op amp topology can also be used to obtain a single-ended output voltage. The output voltage compliance range is nominally 1.25 V. TxDAC+ is a trademark of Analog Devices, Inc. 14-Bit, 32 MSPS TxDAC+™ with 4ⴛ Interpolation Filters AD9774 FUNCTIONAL BLOCK DIAGRAM CLK43IN PLL ENABLE PLLLOCK PLL DIVIDE VCO IN/EXT PLLCOM AD9774 PLL CLOCK MULTIPLIER CLK IN/OUT 13 23 43 43 DATA INPUTS (DB13-DB0) 14 EDGE TRIGGERED LATCHES 14 14 23 SNOOZE 14 23 14-BIT DAC +1.2V REFERENCE AND CONTROL AMP SLEEP DCOM DVDD LPF PLLVDD IOUTA IOUTB REFIO FSADJ ICOMP ACOM AVDD REFLO REFCOMP Edge-triggered input latches, a 4× clock multiplier, and a temperature compensated bandgap reference have also been integrated to provide a complete monolithic DAC solution. Flexible supply options support +3 V and +5 V CMOS logic families. TTL logic levels can also be accommodated by reducing the AD9774 digital supply. The on-chip reference and control amplifier are configured for maximum accuracy and flexibility. The AD9774 can be driven by the on-chip reference or by a variety of external reference voltages. The full-scale current of the AD9774 can be adjusted over a 2 mA to 20 mA range, thus providing additional gain ranging capabilities. The AD9774 is available in a 44-lead MQFP package. It is specified for operation over the industrial temperature range. PRODUCT HIGHLIGHTS 1. On-Chip 4× interpolation filter eases analog reconstruction filter requirements by suppressing the first three images by 69 dB. 2. Low glitch and fast settling time provide outstanding dynamic performance for waveform reconstruction or digital synthesis requirements, including communications. 3. On-chip, edge-triggered input CMOS latches interface readily to CMOS and TTL logic families. The AD9774 can support input data rates up to 32 MSPS. 4. A temperature compensated, 1.20 V bandgap reference is included on-chip, providing a complete DAC solution. An external reference may also be used. 5. The current output(s) of the AD9774 can easily be configured for various single-ended or differential circuit topologies. 6. On-chip clock multiplier generates all the high-speed clocks required by the internal interpolation filters. Both 2× and 4× clocks are generated from the lower rate data clock supplied by the user. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 AD9774–SPECIFICATIONS DC SPECIFICATIONS (T MIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted) Parameter Min RESOLUTION Typ Max 14 Units Bits 1 DC ACCURACY Integral Linearity Error (INL) TA = +25°C TMIN to TMAX Differential Nonlinearity (DNL) TA = +25°C TMIN to TMAX Monotonicity (12-Bit) ±4 LSB ±3 LSB GUARANTEED OVER RATED SPECIFICATION TEMPERATURE RANGE ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance –0.025 –7 +7.5 REFERENCE OUTPUT Reference Voltage Reference Output Current3 1.14 REFERENCE INPUT Input Compliance Range Reference Input Resistance 0.1 TEMPERATURE COEFFICIENTS Unipolar Offset Drift Gain Drift (Without Internal Reference) Gain Drift (With Internal Reference) Reference Voltage Drift +0.025 +7 +7.5 % of FSR % of FSR % of FSR mA V kΩ pF 1.26 V µA 1.25 1 V MΩ 0 ± 50 ± 100 ± 100 ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ±1 ±1 20 1.25 100 5 1.20 1 POWER SUPPLY AVDD Voltage Range4 Analog Supply Current (IAVDD) Analog Supply Current in SLEEP Mode (IAVDD) PLLVDD Voltage Range Clock Multiplier Supply Current (IPLLVDD) DVDD Voltage Range Digital Supply Current at 5 V (IDVDD)5 Digital Supply Current at 5 V in SNOOZE Mode (IDVDD) Digital Supply Current at 3 V (IDVDD)5 Nominal Power Dissipation AVDD and DVDD at 3 V6 AVDD and DVDD at 5 V6 Power Supply Rejection Ratio (PSRR)7 – AVDD Power Supply Rejection Ratio (PSRR)7 – PLLVDD Power Supply Rejection Ratio (PSRR)7 – DVDD –0.2 –0.025 –0.025 +0.2 +0.025 +0.025 mW mW % of FSR/V % of FSR/V % of FSR/V OPERATING RANGE –40 +85 °C 2.7 5.0 26.5 3.2 5.5 32 5 V mA mA 2.7 5.0 13 5.5 17 V mA 2.7 5.0 123.0 42.0 62.0 5.5 140.0 50.0 V mA mA mA 415 1125 NOTES 1 Measured at IOUTA driving a virtual ground. 2 Nominal full-scale current, IOUTFS, is 32 × the IREF current. 3 Use an external amplifier to drive any external load. 4 For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance. 5 Measured at fCLOCK = 25 MSPS and fOUT = 1.01 MHz. 6 Measured as unbuffered voltage output into 50 Ω RLOAD at IOUTA and IOUTB, f CLOCK = 32 MSPS and f OUT = 12.8 MHz. 7 ± 5% power supply variation. Specifications subject to change without notice. –2– REV. B AD9774 (TMIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Differential Transformer DYNAMIC SPECIFICATIONS Coupled Output, 50 ⍀ Doubly Terminated, unless otherwise noted) Parameter Min DYNAMIC PERFORMANCE Maximum Output Update Rate w/DVDD = 5 V Maximum Output Update Rate w/DVDD = 3 V Output Settling Time (tST) (to 0.025%) Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%)1 Output Fall Time (10% to 90%)1 Output Noise (IOUTFS = 20 mA) Typ 128 100 AC LINEARITY TO NYQUIST Spurious-Free Dynamic Range (SFDR) to Nyquist fCLOCK = 25 MSPS; fOUT = 1.01 MHz 0 dBFS Output –6 dBFS Output –12 dBFS Output –18 dBFS Output fCLOCK = 32 MSPS; fOUT = 1.01 MHz fCLOCK = 32 MSPS; fOUT = 5.01 MHz fCLOCK = 32 MSPS; fOUT = 10.01 MHz fCLOCK = 32 MSPS; fOUT = 13.01 MHz Total Harmonic Distortion (THD) fCLOCK = 25 MSPS; fOUT = 1.01 MHz; 0 dBFS Signal-to-Noise Ratio (SNR) fCLOCK = 25 MSPS; fOUT = 1.01 MHz; 0 dBFS Max Units 128 35 55 5 2.5 2.5 50 MSPS MSPS ns Clocks1 pV-s ns ns pA/√Hz2 79 86 75 75 78 77 79 78 dB dB dB dB dB dB dB dB –75 dB 76 dB NOTES 1 Propagation delay is delay from data input to DAC update. 2 Measured single-ended into 50 Ω load. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (T MIN to TMAX, AVDD = +5 V, PLLVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted) Parameter DIGITAL INPUTS Logic “1” Voltage @ DVDD = +5 V Logic “1” Voltage @ DVDD = +3 V Logic “0” Voltage @ DVDD = +5 V Logic “0” Voltage @ DVDD = +3 V Logic “1” Current Logic “0” Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) Latch Pulsewidth (tLPW) Min Typ 3.5 2.1 5 3 0 0 –10 –10 5 2.5 1.5 4 DB0–DB11 tS tH CLOCK tLPW tPD tST IOUTA OR IOUTB 0.025% 0.025% REV. B Figure 1. Timing Diagram –3– Max 1.3 0.9 +10 +10 Units V V V V µA µA pF ns ns ns AD9774–SPECIFICATIONS (TMIN to TMAX, AVDD = +2.7 V to +5.5 V, DVDD = +2.7 V to +5.5 V, IOUTFS = 20 mA unless DIGITAL FILTER SPECIFICATIONS otherwise noted) Parameter Min Typ MAXIMUM INPUT CLOCK RATE (fCLOCK) DVDD = 5 V DVDD = 3 V 32 25 32 MSPS MSPS 0.410 0.414 0.420 0.482 fOUT/fCLOCK fOUT/fCLOCK fOUT/fCLOCK fOUT/fCLOCK STOPBAND REJECTION 0.591 fCLOCK to 3.419 fCLOCK 0.591 fCLOCK to 1.409 fCLOCK –69.5 –79.5 dB dB GROUP DELAY2 38 Input Clocks IMPULSE RESPONSE DURATION –40 dB –60 dB 53 62 Input Clocks Input Clocks DIGITAL FILTER CHARACTERISTICS Passband Width1: 0.005 dB Passband Width: 0.01 dB Passband Width: 0.1 dB Passband Width: –3 dB Max Units LINEAR PHASE (FIR IMPLEMENTATION) NOTES 1 Excludes sinx/x characteristic of DAC. 2 Defined as the number of data clock cycles between impulse input and peak of output response. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD PLLVDD ACOM PLLCOM PLLCOM AVDD PLLVDD PLLVDD CLKIN, CLK4×IN SLEEP, SNOOZE Digital Inputs PLL DIVIDE, LPF PLLLOCK VCO IN/EXT IOUTA/IOUTB REFIO, FSADJ FSADJ ICOMP REFCOM Junction Temperature Storage Temperature Lead Temperature (10 sec) ORDERING GUIDE With Respect to Min Max Units ACOM DCOM PLLCOM DCOM ACOM DCOM DVDD DVDD AVDD DVDD DCOM DCOM ACOM ACOM ACOM ACOM ACOM ACOM ACOM ACOM –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +6.5 +6.5 +6.5 +0.3 +0.3 +0.3 +6.5 +6.5 +6.5 +6.5 DVDD + 0.3 DVDD + 0.3 PLLVDD + 0.3 PLLVDD + 0.3 PLLVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +0.3 +150 +150 +300 V V V V V V V V V V V V V V V V V V V V °C °C °C Model –65 AD9774AS AD9774EB Temperature Range Package Description Package Option* –40°C to +85°C 44-Lead MQFP S-44 Evaluation Board *S = Metric Quad Flatpack. THERMAL CHARACTERISTIC Thermal Resistance 44-Lead MQFP θJA = 53.2°C/W θJC = 19°C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability. –4– REV. B AD9774 0 Table I. Integer Filter Coefficients for First Stage Interpolation Filter (55-Tap Halfband FIR Filter) –20 –40 OUTPUT – dBFS –60 –80 –100 –120 –140 –160 –180 0 1.0 0.5 2.0 1.5 FREQUENCY – DC TO 23 fCLOCK Figure 2a. FIR Filter Frequency Response 1.0 NORMALIZED OUTPUT 0.8 0.6 0.4 0.2 0.0 –0.2 –0.4 0 10 20 30 40 50 TIME – Samples 60 70 80 Figure 2b. FIR Filter Impulse Response Lower Coefficient Upper Coefficient Integer Value H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(23) H(24) H(25) H(26) H(27) H(28) H(55) H(54) H(53) H(52) H(51) H(50) H(49) H(48) H(47) H(46) H(45) H(44) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) –1 0 3 0 –7 0 15 0 –28 0 49 0 –81 0 128 0 –196 0 295 0 –447 0 706 0 –1274 0 3976 6276 Table II. Integer Filter Coefficients for Second Stage Interpolation Filter (23-Tap Halfband FIR Filter) Lower Coefficient Upper Coefficient Integer Value H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(23) H(22) H(21) H(20) H(19) H(18) H(17) H(16) H(15) H(14) H(13) –6 0 37 0 –125 0 316 0 –736 0 2562 4096 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9774 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. B –5– WARNING! ESD SENSITIVE DEVICE AD9774 PIN FUNCTION DESCRIPTIONS Pin No. Name Description 1, 19, 40, 44 2 3–14 15 16, 17, 42 18, 41 20 DCOM DB13 DB12–DB1 DB0 NC DVDD CLK IN/OUT 21 22 23 PLLLOCK CLK4×IN PLLDIVIDE 24 VCO IN/EXT 25 26 27 28 29 30 LPF PLLVDD PLLCOM PLLENABLE UNUSED REFLO 31 REFIO 32 33 34 35 36 37 38 39 43 FSADJ REFCOMP ACOM AVDD IOUTB IOUTA ICOMP SLEEP SNOOZE Digital Common. Most Significant Data Bit (MSB). Data Bits 1–12. Least Significant Data Bit (LSB). No Internal Connection. Digital Supply Voltage (+2.7 V to +5.5 V). Clock Input when PLL Clock Multiplier enabled. Clock Output when PLL Clock Multiplier disabled. Data latched on rising edge. Phase Lock Loop Lock Signal. Active High indicates PLL is locked to input clock. External 4× Clock Input when PLL is disabled. No Connect when internal PLL is active. PLL Range Control Pin. Connect to PLLCOM if CLKIN is above 10 MSPS. Connect to PLLVDD if CLKIN is between 10 MSPS and 5.5 MSPS. Internal Voltage Controlled Oscillator (VCO) Enable/Disable Pin. Connect to PLLVDD to enable VCO. Connect to PLLCOM to disable VCO and drive CLK4×IN with external VCO output. PLL Loop Filter Node. Connect to external VCO control input if internal VCO disabled. Phase Lock Loop (PLL) Supply Voltage (+2.7 V to +5.5 V). Must be set to similar voltage as DVDD. Phase Lock Loop Common. Phase Lock Loop Enable. Connect to PLLVDD to enable. Connect to PLLCOM to disable. Factory Test. Leave Open. Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. Reference Input/Output. Serves as reference input when internal reference disabled (i.e., tie REFLO to AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., tie REFLO to ACOM). Requires 0.1 µF capacitor to ACOM when internal reference activated. Full-Scale Current Output Adjust. Noise Reduction Node. Add 0.1 µF to AVDD. Analog Common. Analog Supply Voltage (+2.7 V to +5.5 V). Complementary DAC Current Output. Full-scale current when all data bits are 0s. DAC Current Output. Full-scale current when all data bits are 1s. Internal bias node for switch driver circuitry. Decouple to ACOM with 0.1 µF capacitor. Power-Down Control Input. Active High. Connect to DCOM if not used. SNOOZE Control Input. Deactivates 4× interpolation filter to reduce digital power consumption only. Active High. Connect to DCOM if not used. ACOM AVDD IOUTB ICOMP IOUTA SLEEP DVDD DCOM SNOOZE NC DCOM PIN CONFIGURATION 44 43 42 41 40 39 38 37 36 35 34 DCOM 1 DB13 2 DB12 3 33 REFCOMP PIN 1 IDENTIFIER 32 FSADJ 31 REFIO 30 REFLO DB11 4 DB10 5 AD9774 DB9 6 TOP VIEW (Not to Scale) DB8 7 29 UNUSED 28 PLLENABLE 27 PLLCOM DB7 8 26 PLLVDD DB6 9 25 LPF DB5 10 24 VCO IN/EXT DB4 11 23 PLLDIVIDE –6– CLK43IN PLLLOCK CLK IN/OUT DCOM NC NC = NO CONNECT DVDD NC DB0 DB1 DB2 DB3 12 13 14 15 16 17 18 19 20 21 22 REV. B AD9774 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Glitch Impulse DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified the net area of the glitch in pV-s. Monotonicity Spurious-Free Dynamic Range A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Offset Error Total Harmonic Distortion The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. It is expressed as a percentage or in decibels (dB). Gain Error The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s, minus the output when all inputs are set to 0s. S/N is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Output Compliance Range Passband The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Frequency band in which any input applied therein passes unattenuated to the DAC output. Differential Nonlinearity (or DNL) Signal-to-Noise Ratio (SNR) Stopband Rejection The amount of attenuation of a frequency outside the passband applied to the DAC, relative to a full-scale signal applied at the DAC input within the passband. Temperature Drift Temperature drift is specified as the maximum change from the ambient (+25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per degree C. For reference drift, the drift is reported in ppm per degree C. Group Delay Number of input clocks between an impulse applied at the device input and peak DAC output current. Impulse Response Power Supply Rejection Response of the device to an impulse applied to the input. The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. +3VD CLK IN/OUT CLK43IN PLLLOCK PLL VCO ENABLE IN/EXT PLL DIVIDE PLLCOM PLL CLOCK MULTIPLIER 1.5kV TEKTRONIX AWG-2021 OPTION 4 0.01mF 13 DIGITAL DATA 14 EDGE TRIGGERED LATCHES 23 14 43 14 23 14 14-BIT DAC AD9774 0.1mF 0.1mF +1.2V REFERENCE AND CONTROL AMP DCOM DVDD ICOMP ACOM AVDD REFCOMP +3VD 100V IOUTB REFIO FSADJ REFLO 1.91kV 0.1mF +5VA Figure 3. Basic AC Characterization Test Setup –7– MINI-CIRCUITS T1-1T +3VD PLLVDD IOUTA 43 23 SNOOZE SLEEP REV. B TO HP3589A SPECTRUM / NETWORK ANALYZER 50V INPUT LPF 50V 20pF 50V 20pF AD9774 Typical AC Characterization Curves (AVDD = +5 V, PLLVDD = +3 V, DVDD = +3 V, IOUTFS = 20 mA, 50 ⍀ Doubly Terminated Load, Differential Output, TA = +25ⴗC, unless otherwise noted. Note: PLLVDD = +5 V and DVDD = +5 V for Figures 4, 5 and 6.) “INBAND” 10 90 85 0 80 85 –10 75 0dBFS 70 80 –30 –40 –50 –6dBFS SFDR – dBc SFDR – dBc 10dB – DIV –20 75 –12dBFS 65 60 0dBFS 55 –6dBFS 70 –60 50 –18dBFS –70 –12dBFS 45 65 –18dBFS –80 40 –90 60 0 25.6 51.2 76.8 102.4 128.0 0 2 4 MHz 6 8 10 35 14 12 0 2 4 fOUT – MHz Figure 4. Single Tone Spectral Plot @ 32 MSPS w/fOUT = 12.8 MHz (DC to 4 × CLKIN) 6 8 10 12 14 fOUT – MHz Figure 5. “Inband” SFDR vs. fOUT @ 32 MSPS (DC to CLKIN/2) Figure 6. “Out-of-Band” SFDR vs. fOUT @ 32 MSPS (CLKIN/2 to 3 1/2 CLKIN) “INBAND” 10 85 90 0 80 85 –10 75 –30 –40 –50 –6dBFS 75 –12dBFS 0dBFS 70 –60 65 –6dBFS 60 –12dBFS 55 –18dBFS 50 –18dBFS –70 45 65 –80 40 –90 0 12.8 25.6 38.4 MHz 51.2 60 64.0 0 1 2 3 4 5 35 7 6 0 1 2 Figure 8. “Inband” SFDR vs. fOUT @ 16 MSPS (DC to CLKIN/2) 10 70 80 SFDR – dBc SFDR – dBc –50 7 75 0dBFS –20 –6dBFS 75 –12dBFS 70 –60 6 –6dBFS 0dBFS 80 85 –40 5 85 90 –30 4 Figure 9. “Out-of-Band” SFDR vs. fOUT @ 16 MSPS (CLKIN/2 to 3 1/2 CLKIN) 0 –10 3 fOUT – MHz fOUT – MHz Figure 7. Single Tone Spectral Plot @ 16 MSPS w/fOUT = 6.4 MHz (DC to 4 × CLKIN) 10dB – DIV 0dBFS 70 80 SFDR – dBc SFDR – dBc 10dB – DIV –20 –12dBFS 65 –18dBFS 60 55 50 –18dBFS –70 45 65 –80 40 –90 0 6.4 12.8 19.2 MHz 25.6 32.0 Figure 10. Single Tone Spectral Plot fOUT @ 8 MSPS w/fOUT = 3.2 MHz (DC to 4 × CLKIN) 60 0 0.5 1 1.5 2 2.5 3 3.5 fOUT – MHz Figure 11. “Inband” SFDR vs. fOUT @ 8 MSPS (DC to CLKIN/2) –8– 35 0 0.5 1 1.5 2 2.5 3 3.5 fOUT – MHz Figure 12. “Out-of-Band” SFDR vs. fOUT @ 8 MSPS (CLKIN/2 to 3 1/2 CLKIN) REV. B AD9774 10 85 90 0 80 –30 –40 –50 75 70 80 0dBFS SFDR – dBc SFDR – dBc –20 10dB – DIV 0dBFS 85 –10 –6dBFS 75 –12dBFS –18dBFS 55 50 –18dBFS –70 45 65 –80 –90 –12dBFS 60 70 –60 –6dBFS 65 40 0 1.0 2.0 3.0 4.0 5.0 MHz 6.0 7.0 60 0.1 8.0 35 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 0.2 Figure 13. Single Tone Spectral Plot @ 2 MSPS w/fOUT = 800 kHz (DC to 4 × CLKIN) Figure 14. “Inband” SFDR vs. fOUT @ 2 MSPS (DC to CLKIN/2) 90 0.3 0.4 0.5 0.6 0.7 0.8 fOUT – MHz fOUT – MHz Figure 15. “Out-of-Band” SFDR vs. fOUT @ 2 MSPS (CLKIN/2 to 3 1/2 CLKIN) 85 80 80 85 75 363kHz @ 4MSPS 70 727kHz @ 8MSPS 2.9MHz @ 32MSPS 75 75 70 1.45MHz @ 16MSPS 60 55 50 363kHz @ 4MSPS 1.45MHz @ 16MSPS DVDD = 3.3V 65 SNR – dB 727kHz @ 8MSPS SFDR – dBc SFDR – dBc 80 2.9MHz @ 32MSPS DVDD = 5.0V 70 65 45 65 40 60 –18 –16 –14 –12 –10 –8 –6 AIN – dBFS –4 –2 0 Figure 16. “In-Band” Single Tone SFDR vs. AIN @ fOUT = fCLOCK/7 (DC to CLKIN/2) 75 5.6/6.4MHz @ 16MSPS –10 –20 1.4/1.6MHz @ 4MSPS –30 –40 1.4/1.6MHz @ 4MSPS 65 –4 –2 Figure 19. “In-Band” Two Tone SFDR vs. AOUT @ fOUT = fCLOCK/2.7 (DC to CLKIN/2) 0 5.6/6.4MHz @ 16MSPS 55 50 55 50 –18 –16 –14 –12 –10 –8 –6 AOUT – dBFS 2.8/3.2MHz @ 8MSPS 60 30 Figure 18. SNR vs. fCLKIN @ fOUT = 2 MHz (DC to CLKIN/2) 70 65 20 fCLK – MSPS 80 SFDR – dBc SFDR – dBc 60 10 0 85 2.8/3.2MHz @ 8MSPS 11.2/12.8MHz @ 32MSPS 70 REV. B –2 Figure 17. Out-of-Band Single Tone SFDR vs. AIN @ fOUT = fCLOCK/7 (DC to 3 1/2 CLKIN) 75 60 –4 10dB – DIV 80 35 –18 –16 –14 –12 –10 –8 –6 AIN – dBFS 11.2/12.8MHz @ 32MSPS –50 –60 –70 –80 45 –90 40 –100 35 –18 –16 –14 –12 –10 –8 –6 AOUT – dBFS –110 –4 –2 0 Figure 20. “Out-of-Band” Two Tone SFDR vs. AOUT @ fOUT = fCLOCK/2.7 (DC to 3 1/2 CLKIN) –9– 0 25.6 51.2 76.8 102.4 128.0 Figure 21. Multitone Spectral Plot @ 32 MSPS (DC to 4 × CLKIN) AD9774 coefficients for each of the filter stages. The interpolation filters essentially multiply the input data rate to the DAC by a factor of four relative to its original input data rate while simultaneously reducing the magnitude of the images associated with the original input data rate. FUNCTIONAL DESCRIPTION Figure 22 shows a simplified block diagram of the AD9774. The AD9774 is a complete, 4× oversampling, 14-bit DAC that includes two cascaded 2× interpolation filters, a phase-locked loop (PLL) clock multiplier, and a 1.20 Volt bandgap voltage reference. The 14-bit DAC provides two complementary current outputs whose full-scale current is determined by an external resistor. Input data that is latched into the edge-triggered input latches is first interpolated by a factor of four by the interpolation filters before updating the 14-bit DAC. A PLL clock multiplier produces the necessary internally synchronized 1×, 2× and 4× clocks from an external reference. The AD9774 can support input data rates as high as 32 MSPS, corresponding to a DAC update rate of 128 MSPS. The benefits of an interpolation filter are clearly seen in Figure 23, which shows an example of the frequency and time domain representation of a discrete time sine wave signal before and after it is applied to a digital interpolation filter. Images of the sine wave signal appear around multiples of the DAC’s input data rate as predicted by sampling theory. These undesirable images will also appear at the output of a reconstruction DAC, although modified by the DAC’s sin(x)/(x) roll-off response. In many bandlimited applications, these images must be suppressed by an analog filter following the DAC. The complexity of this analog filter is typically determined by the proximity of the desired fundamental to the first image and the required amount of image suppression. Adding to the complexity of this analog filter may be the requirement of compensating for the DAC’s sin(x)/x response. The analog and digital sections of the AD9774 have separate power supply inputs (i.e., AVDD and DVDD) that can operate over a 2.7 V to 5.5 V range. A separate supply input (i.e., PLLVDD) having a similar operating range is also provided for the PLL clock multiplier. To maintain optimum noise and distortion performance, PLLVDD should be maintained at the same voltage level as DVDD. CLK43IN PLLLOCK PLL ENABLE PLLCOM AD9774 PLL CLOCK MULTIPLIER CLK IN/OUT 13 23 DATA INPUTS (DB13–DB0) EDGE TRIGGERED LATCHES 14 14 23 14 14-BIT DAC 23 SNOOZE +1.2V REFERENCE AND CONTROL AMP SLEEP LPF 43 43 14 Referring to Figure 23, the “new” first image associated with the DAC’s higher data rate after interpolation is “pushed” out further relative to the input signal. The “old” first image associated with the lower DAC data rate before interpolation is suppressed by the digital filter. As a result, the transition band for the analog reconstruction filter is increased, thus reducing the complexity of the analog filter. Furthermore, the sin(x)/x roll-off over the effective passband (i.e., dc to fCLOCK/2) is significantly reduced. PLL DIVIDE VCO IN/EXT PLLVDD The AD9774 includes a PLL clock multiplier that produces the necessary internally synchronized 1×, 2× and 4× clocks for the edge triggered latches, interpolation filters and DACs. The PLL clock multiplier typically accepts an input data clock, CLK IN/OUT, as its reference source. Alternatively, it can also be configured using an external 4× clock via CLK4×IN. The PLLDIVIDE, VCO IN/EXT, PLLENABLE, and PLLLOCK are control inputs/outputs used in the PLL clock generator. Refer to the PLL CLOCK MULTIPLIER OPERATION section for a detailed discussion on its operation. IOUTA IOUTB REFIO FSADJ DCOM DVDD ICOMP ACOM AVDD REFCOMP REFLO Figure 22. Functional Block Diagram Preceding the 14-bit DAC are two cascaded 2× digital interpolation filter stages based on a 55- and 23-tap halfband symmetric FIR topology. Edge triggered latches are used to latch the input data on the rising edge of CLK IN/OUT. The composite frequency and impulse response of both filters are shown in Figures 2a and 2b. Table I and Table II list the idealized filter The digital section of the AD9774 also includes several other control inputs and outputs. The SLEEP and SNOOZE inputs provide different power-saving modes as discussed in the SLEEP and SNOOZE section. 1 4fCLOCK TIME DOMAIN 1 fCLOCK FUNDAMENTAL 1ST IMAGE FUNDAMENTAL "NEW" 1ST IMAGE DIGITAL FILTER DACs "SINX" X FREQUENCY DOMAIN 2fCLOCK 4fCLOCK INPUT DATA LATCH SUPPRESSED "OLD" 1ST IMAGE 2fCLOCK 4fCLOCK 4x INTERPOLATION FILTER 2fCLOCK 4fCLOCK DAC 4x fCLOCK 43fCLOCK Figure 23. Time and Frequency Domain Example of Digital Interpolation Filter –10– REV. B AD9774 PLL CLOCK MULTIPLIER OPERATION The Phase Lock Loop (PLL) Clock Multiplier is intrinsic to the operation of the AD9774 in that it produces the necessary internally synchronized 1×, 2× and 4× clocks for the edge triggered latches, interpolation filters and DACs. Figure 24 shows a functional block diagram of the PLL Clock Multiplier, which consists of a phase detector, a charge pump, a voltage controlled oscillator (VCO), a divide-by-N circuit and some control inputs/ outputs. It produces the required internal clocks for the AD9774 by using one of two possible externally applied reference clock sources applied to either CLKIN or CLK4×IN. PLLENABLE and VCO IN/EXT are active HIGH control inputs used to enable the charge pump and VCO respectively. To maintain optimum noise and distortion performance, PLLVDD and DVDD should be set to similar voltage levels. If a separate supply cannot be provided for PLLVDD, PLLVDD can be tied to DVDD using an LC filter network similar to that shown in Figure 41. Many applications will select a reference clock operating at the data input rate as shown in Figure 24. In this case, the external clock source is applied to CLKIN and the PLL Clock Multiplier is fully enabled by tying PLLENABLE and VCO IN/EXT to PLLVDD. Note, CLKIN must adhere to the timing requirements shown in Figure 1. A 1.5 kΩ resistor and 0.01 µF ceramic capacitor connected in series from LPF to PLLVDD are required to optimize the phase noise vs. settling/acquisition time characteristics of the PLL. PLLLOCK is a control output, active HIGH, which may be monitored upon system power-up to indicate that the PLL is successfully “locked” to CLKIN. Note, applications employing multiple AD9774 devices will benefit from the PLL Clock Multiplier’s ability to ensure precise simultaneous updating/phase synchronization of these devices when driven by the same input clock source. There are two cases in which a user may consider or be required to disable the internal PLL Clock Multiplier and supply the AD9774 with an external 4× system clock. Applications already containing a system clock operating at four (i.e., 4×) the input data rate may consider using it as the master clock source. Applications with input data rates less than 5.5 MSPS must use a master 4× clock. In any of these cases, the clock source is applied to CLK4×IN and the PLL is partially disabled by typing PLLENABLE and VCO IN/EXT to PLLCOM as shown in Figure 25. LPF may remain open since this portion of the PLL circuitry is disabled. The divide-by-N circuit still remains enabled providing a 1× or 2× internal clock at CLOCK IN/OUT depending on the state of PLLDIVIDE. Since the digital input data is latched into the AD9774 on the rising edge of the 1× clock, PLLDIVIDE should be tied to PLLCOM such that the 1× clock appears as an output at CLOCK IN/OUT. The input data should be stable 5 ns (i.e., data set-up) before the rising edge of the 1× clock appearing at CLOCK IN/OUT and remain stable for 1 ns after the rising edge (i.e., data hold) to ensure proper latching. Note, the rising edge of the 1× clock occurs approximately 9 ns to 15 ns relative to the falling edge of the CLK4× input. If a data timing issue exists between the AD9774 and its external driver device, the CLK4× input can be inverted via an external gate to ensure proper set-up and hold time. PLLLOCK CLK PLL DIVIDE IN/OUT PLL ENABLE PHASE DETECTOR PLLDIVIDE is used to preset the “lock-in” range of the PLL. It should be tied to PLLCOM if CLKIN is greater than 10 MHz and to PLLVDD if CLKIN is between 5.5 MHz and 10 MHz. For operation below 5.5 MHz (i.e., input data rates less than 5.5 MSPS), the internal charge pump and VCO should be disabled by tying PLLENABLE and VCO IN/EXT LOW. In this case, the user MUST supply a system clock operating at 4× the input data rate as discussed below. CHARGE PUMP AD9774 48 44 DIVIDE42 BY-N 41 DCOM CLK DVDD 43IN LPF PLL VDD VCO VCO +2.7 TO +5.5 VD PLL COM VCO IN/EXT +2.7 TO +5.5 VD CONNECT TO PLLCOM CLK IN/OUT Figure 25. Clock Divider with PLL Disabled CONNECT TO PLLVDD PLLLOCK PLL DIVIDE DAC OPERATION PLL ENABLE LPF PHASE DETECTOR CHARGE PUMP 1.5kV AD9774 48 44 DIVIDE42 BY-N 41 DCOM CLK DVDD 43IN 0.01mF PLL VDD VCO VCO PLL COM +2.7 TO +5.5 VD VCO IN/EXT +2.7 TO +5.5 VD Figure 24. Clock Multiplier with PLL Enabled REV. B The 14-bit DAC along with the 1.2 V reference and reference control amplifier is shown in Figure 26. The DAC consists of a large PMOS current source array capable of providing up to 20 mA of full-scale current, IOUTFS. The array is divided into 31 equal currents which make up the five most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose values are 1/16th of an MSB current source. The remaining LSBs are binary weighted fractions of the middle-bits current sources. All of these current sources are switched to one or the other of two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. Implementing the middle and lower bits with current sources, instead of an R-2R ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the DAC’s high output impedance (i.e., > 100 kΩ). –11– AD9774 Substituting the values of IOUTA, IOUTB and IREF; VDIFF can be expressed as: +2.7 TO +5.5VA 0.1mF REFLO REFCOMP AVDD ACOM VDIFF = {(2 DAC CODE – 16383)/16384} × VDIFF = {(32 RLOAD/RSET) × VREFIO 50pF 1.20V REF CURRENT SOURCE ARRAY REFIO 1.91kV ICOMP 0.1mF FS ADJ IOUTA SEGMENTED SWITCHES 0.1mF LSB SWITCHES IOUTB AD9774 Figure 26. Block Diagram of Internal DAC, 1.2 V Reference, and Reference Control Circuits The full-scale output current is regulated by the reference control amplifier and can be set from 2 mA to 20 mA via an external resistor, RSET. The external resistor,␣ in combination with both the reference control amplifier and voltage reference, REFIO, sets the reference current, IREF, which is mirrored over to the segmented current sources with the proper scaling factor. The full-scale current, IOUTFS, is exactly thirty-two times the value of IREF. Note that the gain drift temperature performance for a singleended (VOUTA and VOUTB) or differential output (VDIFF) of the AD9774 can be enhanced by selecting temperature tracking resistors for RLOAD and RSET due to their ratiometric relationship as shown in Equation 8. REFERENCE OPERATION DAC TRANSFER FUNCTION The AD9774 provides complementary current outputs, IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 16383) while IOUTB, the complementary output, provides no current. The current output appearing at IOUTA and IOUTB is a function of both the input code and IOUTFS and can be expressed as: IOUTA = (DAC CODE/16384) × IOUTFS (1) IOUTB = (16383 – DAC CODE)/16384 × IOUTFS (2) The AD9774 contains an internal 1.20 V bandgap reference that can be easily disabled and overridden by an external reference. REFIO serves as either an input or output, depending on whether the internal or external reference is selected. If REFLO is tied to ACOM, as shown in Figure 27, the internal reference is activated, and REFIO provides a 1.20 V output. In this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 µF or greater from REFIO to REFLO. If any additional loading is required, REFIO should be buffered with an external amplifier having an input bias current less than 100 nA. +2.7 TO +5.5VA OPTIONAL EXTERNAL REF BUFFER where DAC CODE = 0 to 16383 (i.e., Decimal Representation). As previously mentioned, IOUTFS is a function of the reference current IREF, which is nominally set by a reference voltage VREFIO and external resistor RSET. It can be expressed as: IOUTFS = 32 × IREF where IREF = VREFIO/RSET (8) These last two equations highlight some of the advantages of operating the AD9774 differentially. First, the differential operation will help cancel common-mode error sources associated with IOUTA and IOUTB such as noise, distortion and dc offsets. Second, the differential code-dependent current and subsequent voltage, VDIFF, is twice the value of the single-ended voltage output (i.e., VOUTA or VOUTB), thus providing twice the signal power to the load. 0.1mF REFLO +1.2V REF REFIO ADDITIONAL LOAD (3) (4) The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, that are tied to analog common, ACOM. Note that RLOAD may represent the equivalent load resistance seen by IOUTA or IOUTB as would be the case in a doubly terminated 50 Ω or 75 Ω cable. The single-ended voltage output appearing at the IOUTA and IOUTB nodes is simply: 0.1mF 2kV FSADJ REFCOMP AVDD 50pF CURRENT SOURCE ARRAY AD9774 Figure 27. Internal Reference Configuration VOUTA = IOUTA × RLOAD (5) VOUTB = IOUTB × RLOAD (6) Note that the full-scale value of VOUTA and VOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. The internal reference can be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied to REFIO as shown in Figure 28. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 µF compensation capacitor is not required since the internal reference is disabled, and the high input impedance (i.e., 1 MΩ) of REFIO minimizes any loading of the external reference. The differential voltage, VDIFF, appearing across IOUTA and IOUTB is: VDIFF = (IOUTA – IOUTB) × RLOAD (7) –12– REV. B AD9774 +2.7 TO +5.5VA varied by an external voltage, VGC, applied to RSET via an amplifier. An example of this method is shown in Figure 29 in which the internal reference is used to set the common-mode voltage of the control amplifier to 1.20 V. The external voltage, VGC, is referenced to ACOM and should not exceed 1.2 V. The value of RSET is such that IREFMAX and IREFMIN do not exceed 62.5 µA and 625 µA, respectively. The associated equations in Figure 29 can be used to determine the value of RSET. 0.1mF REFCOMP REFLO AVDD AVDD +1.2V REF VREFIO EXTERNAL REF 50pF REFIO CURRENT SOURCE ARRAY FS ADJ RSET IREF = VREFIO/RSET +2.7 TO +5.5VA REFERENCE CONTROL AMPLIFIER AD9774 0.1mF REFLO Figure 28. External Reference Configuration REFCOMP +1.2V REF REFIO REFERENCE CONTROL AMPLIFIER The AD9774 also contains an internal control amplifier that is used to regulate the DAC’s full-scale output current, IOUTFS. The control amplifier is configured as a V-I converter, as shown in Figure 28, such that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied over to the segmented current sources with the proper scaling factor to set IOUTFS as stated in Equation 3. The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 2 mA to 20 mA range by setting IREF between 62.5 µA and 625 µA. The wide adjustment span of IOUTFS provides several application benefits. The first benefit relates directly to the power dissipation of the AD9774, which is proportional to IOUTFS (refer to the Power Dissipation section). The second benefit relates to the 20 dB adjustment, which is useful for system gain control purposes. There are two methods by which IREF can be varied for a fixed RSET. The first method is suitable for a single-supply system in which the internal reference is disabled, and the common-mode voltage of REFIO is varied over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply amplifier or DAC, thus allowing IREF to be varied for a fixed RSET. Since the input impedance of REFIO is approximately 1 MΩ, a simple, low cost R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown in Figure 30 using the AD7524 and an external 1.2 V reference, the AD1580. The second method may be used in a dual-supply system in which the common-mode voltage of REFIO is fixed, and IREF is RSET VGC IREF AD9774 IREF = (1.2–VGC)/RSET WITH VGC , VREFIO AND 62.5 mA # IREF # 625A Figure 29. Dual Supply Gain Control Circuit ANALOG OUTPUTS The AD9774 produces two complementary current outputs, IOUTA and IOUTB, which may be configured for single-end or differential operation. IOUTA and IOUTB can be converted into complementary single-ended voltage outputs, VOUTA and VOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VDIFF, existing between VOUTA and VOUTB, can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. Figure 31 shows the equivalent analog output circuit of the AD9774 consisting of a parallel combination of PMOS differential current switches associated with each segmented current source. The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches and is typically 100 kΩ in parallel with 5 pF. Due to the nature of a PMOS device, the output impedance is also slightly dependent on the output voltage (i.e., VOUTA and VOUTB) and, to a lesser extent, the analog supply voltage, AVDD, and full-scale current, IOUTFS. Although the output impedance’s signal dependency can be a source of dc nonlinearity and ac linearity (i.e., distortion), its effects can be limited if certain precautions are noted. +2.7 TO +5.5VA AVDD 0.1mF REFLO RFB 1.2V AD7524 AD1580 VREF REFCOMP 50pF 0.1V TO 1.2V OUT2 REFIO FSADJ AGND RSET IREF = VREF/RSET AD9774 DB7–DB0 Figure 30. Single Supply Gain Control Circuit REV. B AVDD +1.2V REF VDD OUT1 50pF CURRENT SOURCE ARRAY FSADJ 1mF AVDD –13– CURRENT SOURCE ARRAY AD9774 AD9774 AVDD IOUTA IOUTB RLOAD RLOAD The distortion and noise performance of the AD9774 is also slightly dependent on the analog and digital supply as well as the full-scale current setting, IOUTFS. Operating the analog supply at 5.0 V ensures maximum headroom for its internal PMOS current sources and differential switches leading to improved distortion performance. Although IOUTFS can be set between 2 mA and 20 mA, selecting an IOUTFS of 20 mA will provide the best distortion and noise performance. The noise performance of the AD9774 is affected by the digital supply (DVDD), output frequency, and increases with increasing clock rate. Operating the AD9774 with low voltage logic levels between 3 V and 3.3 V will slightly reduce the amount of on-chip digital noise. In summary, the AD9774 achieves the optimum distortion and noise performance under the following conditions: Figure 31. Equivalent Analog Output Circuit IOUTA and IOUTB also have a negative and positive voltage compliance range. The negative output compliance range of –1.0 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage and affect the reliability of the AD9774. The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 20 mA to 1.00 V for an IOUTFS = 2 mA. Operation beyond the positive compliance range will induce clipping of the output signal, which severely degrades the AD9774’s linearity and distortion performance. For applications requiring the optimum dc linearity, IOUTA and/or IOUTB should be maintained at a virtual ground via an I-V op amp configuration. Maintaining IOUTA and/or IOUTB at a virtual ground keeps the output impedance of the AD9774 fixed, significantly reducing its effect on linearity. However, it does not necessarily lead to the optimum distortion performance due to limitations of the I-V op amp. Note that the INL/DNL specifications for the AD9774 are measured in this manner using IOUTA. In addition, these dc linearity specifications remain virtually unaffected over the specified power supply range of 2.7 V to 5.5 V. Operating the AD9774 with reduced voltage output swings at IOUTA and IOUTB in a differential or single-ended output configuration reduces the signal dependency of its output impedance thus enhancing distortion performance. Although the voltage compliance range of IOUTA and IOUTB extends from –1.0 V to +1.25 V, optimum distortion performance is achieved when the maximum full-scale signal at IOUTA and IOUTB does not exceed approximately 0.5 V. A properly selected transformer with a grounded center-tap will allow the AD9774 to provide the required power and voltage levels to different loads while maintaining reduced voltage swings at IOUTA and IOUTB. DC-coupled applications requiring a differential or single-ended output configuration should size RLOAD accordingly. Refer to Applying the AD9774 section for examples of various output configurations. (1) Differential Operation. (2) Positive voltage swing at IOUTA and IOUTB limited to +0.5 V. (3) IOUTFS set to 20 mA. (4) Analog Supply (AVDD) set at 5.0 V. (5) Digital Supply (DVDD) and Phase Lock Loop Supply (PLLVDD) set at 3.0 V to 3.3 V with appropriate logic levels. Note that the ac performance of the AD9774 is characterized under the above-mentioned operating conditions. DIGITAL INPUTS/OUTPUTS The digital input of the AD9774 consists of 14 data input pins and a clock input pin, and several control input pins. Since some of the internal logic is operated from DVDD and PLLVDD, they must be set to the same or similar levels to ensure proper compatibility with any external logic/drivers. The two digital outputs of the AD9774, PLL LOCK and CLK OUT originate from the internal PLL circuitry and thus its output logic levels will be set by PLLVDD. The 14-bit parallel data inputs follow standard positive binary coding where DB13 is the most significant bit (MSB), and DB0 is the least significant bit (LSB). IOUTA produces a full-scale output current when all data bits are at Logic 1. IOUTB produces a complementary output with the full-scale current split between the two outputs as a function of the input code. The digital interface is implemented using an edge-triggered master slave latch and is designed to support a clock and input data rate as high as 32 MSPS. The clock can be operated at any duty cycle that meets the specified latch pulsewidth as shown in Figure 1. The setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met. The digital inputs are CMOS-compatible with logic thresholds, VTHRESHOLD, set to approximately half the digital positive supply (i.e., DVDD or PLLVDD) or VTHRESHOLD = DVDD/2 (± 20%) The most significant improvement in the AD9774’s distortion The internal digital circuitry of the AD9774 is capable of operating and noise performance is realized using a differential output over a digital supply range of 2.7 V to 5.5 V. As a result, the configuration. The common-mode error sources of both IOUTA digital inputs can also accommodate TTL levels when DVDD is and IOUTB can be substantially reduced by the common-mode set to accommodate the maximum high level voltage of the TTL rejection of a transformer or differential amplifier. These drivers VOH(MAX). A DVDD of 3 V to 3.3 V will typically ensure common-mode error sources include even-order distortion proper compatibility with most TTL logic families. Figure 32 products and noise. The enhancement in distortion performance shows the equivalent digital input circuit for the data and clock becomes more significant as the reconstructed waveform’s inputs. frequency content increases and/or its amplitude decreases. REV. B –14– AD9774 DVDD DVDD = 3 V, respectively. Note, how IDVDD is reduced by more than a factor of 2 when DVDD is reduced from 5 V to 3 V. 30 DIGITAL INPUT 25 IAVDD – mA 20 Figure 32. Equivalent Digital Input Since the AD9774 is capable of being updated up to 32 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. Operating the AD9774 with reduced logic swings and a corresponding digital supply (DVDD) will result in the lowest data feedthrough and on-chip digital noise. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9774 as well as its required min/max input logic level thresholds. 15 10 5 0 2 4 6 8 10 12 14 IOUTFS – mA 16 18 20 Figure 33. IAVDD vs. IOUTFS Digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 20 Ω to 100 Ω) between the AD9774 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs that contribute to data feedthrough. 200 180 32MSPS 160 140 IDVDD – mA The external clock driver circuitry should provide the AD9774 with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter that will manifest itself as phase noise on a reconstructed waveform. Thus, the clock input should be driven by the fastest logic family suitable for the application. 120 100 80 16MSPS 60 8MSPS 40 4MSPS 20 SLEEP AND SNOOZE MODE OPERATION 0 0.01 The AD9774 has a SLEEP function that turns off the output current and reduces the supply current to less than 5 mA over the specified supply range of 2.7 V to 5.5 V and temperature range. This mode can be activated by applying a logic level “1” to the SLEEP pin. The AD9774 takes less than 0.1 µs to power down and approximately 6.4 µs to power back up. 100 90 32MSPS 80 IDVDD – mA 70 60 50 40 16MSPS 30 POWER DISSIPATION The power dissipation, PD, of the AD9774 is dependent on several factors, including: (1) AVDD, PLLVDD, and DVDD, the power supply voltages; (2) IOUTFS, the full-scale current output; (3) fCLOCK, the update rate; and (4) the reconstructed digital input waveform. The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 33, and is insensitive to fCLOCK. REV. B 1.0 Figure 34. IDVDD vs. Ratio @ DVDD = 5 V The SNOOZE mode should be considered as an alternative power-savings option if the power-up characteristics of the SLEEP mode are unsuitable. This mode, which is also activated by applying a logic level “1” to the SNOOZE pin, disables the AD9774’s digital filters only, resulting in significant power savings. Both the SLEEP and SNOOZE pins should be tied to DCOM if power savings is not required. Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply DVDD. Figures 34 and 35 show IDVDD as a function of full-scale sine wave output ratios (fOUT/fCLOCK) for various update rates with DVDD = 5 V and 0.10 RATIO – fOUT/fCLOCK 20 8MSPS 10 4MSPS 0 0.01 0.10 RATIO – fOUT/fCLOCK 1.0 Figure 35. IDVDD vs. Ratio @ DVDD = 3 V For those applications requiring the AD9774 to operate under the following conditions: (1) AVDD, PLLVDD and DVDD = +5 V; (2) fCLOCK > 25 MSPS; and (3) ambient temperatures > 70°C; proper thermal management via a heatsink or thermal epoxy is recommended. –15– AD9774 APPLYING THE AD9774 DIFFERENTIAL USING AN OP AMP OUTPUT CONFIGURATIONS An op amp can also be used to perform a differential-to-singleended conversion as shown in Figure 37. The AD9774 is configured with two equal load resistors, RLOAD, of 25 Ω. The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB, forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp’s distortion performance by preventing the DAC’s high slewing output from overloading the op amp’s input. The following sections illustrate some typical output configurations for the AD9774. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 20 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an approximately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. AD8055 225V IOUTB 21 COPT 500V 25V 25V Figure 37. DC Differential Coupling Using an Op Amp An RF transformer can be used to perform a differential-tosingle-ended signal conversion as shown in Figure 36. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer’s passband. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only. MINI-CIRCUITS T1-1T The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8055 is configured to provide some additional signal gain. The op amp must operate from a dual supply since its output is approximately ± 1.0 V. A high speed amplifier capable of preserving the differential performance of the AD9774 while meeting other system level objectives (i.e., cost, power) should be selected. The op amps differential gain, its gain setting resistor values and full-scale output swing capabilities should all be considered when optimizing this circuit. The differential circuit shown in Figure 38 provides the necessary level-shifting required in a single supply system. In this case, AVDD, which is the positive analog supply for both the AD9774 and the op amp, is also used to level-shift the differential output of the AD9774 to midsupply (i.e., AVDD/2). The AD8041 is a suitable op amp for this application. 500 RLOAD AD9774 IOUTB 225V IOUTA 22 DIFFERENTIAL COUPLING USING A TRANSFORMER IOUTA 22 500V AD9774 AD9774 225 IOUTA 22 21 OPTIONAL RDIFF AD8041 225 IOUTB 21 COPT 1k AVDD Figure 36. Differential Output Using a Transformer 25 The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9774. A differential resistor, RDIFF, may be inserted in applications in which the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable. RDIFF is determined by the transformer’s impedance ratio and provides the proper source termination that results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. 25 1k Figure 38. Single-Supply DC Differential Coupled Circuit SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT Figure 39 shows the AD9774 configured to provide a unipolar output range of approximately 0 V to +0.5 V for a doubly terminated 50 Ω cable since the nominal full-scale current, IOUTFS, of 20 mA flows through the equivalent RLOAD of 25 Ω. In this case, RLOAD represents the equivalent load resistance seen by IOUTA. The unused output (IOUTB) can be connected to ACOM directly. Different values of IOUTFS and RLOAD can be selected as –16– REV. B AD9774 to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply, should be decoupled to DCOM and PLLVDD, the Phase Lock Loop Supply, should be decoupled to PLLCOM. long as the positive compliance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL) as discussed in the Analog Output section of this data sheet. For optimum INL performance, the single-ended, buffered voltage output configuration is suggested. AD9774 IOUTFS = 20mA For those applications requiring a single +5 V or +3 V supply for both the analog, digital supply and Phase Lock Loop supply, a clean AVDD and/or PLLVDD may be generated using the circuit shown in Figure 41. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESR type electrolytic and tantalum capacitors. VOUTA = 0 TO +0.5V IOUTA 22 50V 50V IOUTB 21 FERRITE BEADS Figure 39. 0 V to +0.5 V Unbuffered Voltage Output TTL/CMOS LOGIC CIRCUITS SINGLE-ENDED BUFFERED VOLTAGE OUTPUT CONFIGURATION RFB 200V IOUTFS = 10mA IOUTA 22 VOUT = IOUTFS 3 RFB IOUTB 21 200V Figure 40. Unipolar Buffered Voltage Output POWER AND GROUNDING CONSIDERATIONS In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection, placement and routing and supply bypassing and grounding. Figures 44–49 illustrate the recommended printed circuit board ground, power and signal plane layouts that are implemented on the AD9774 evaluation board. Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9774 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled REV. B 0.1mF CER. +5V OR +3V POWER SUPPLY Figure 41. Differential LC Filter for Single +5 V or +3 V Applications Maintaining low noise on power supplies and ground is critical to obtain optimum results from the AD9774. If properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding current transport, etc. In mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. All analog ground pins of the DAC, reference and other analog components should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal and the supply feeders. COPT U1 10-22mF TANT. ACOM Figure 40 shows a buffered single-ended output configuration in which the op amp U1 performs an I-V conversion on the AD9774 output current. U1 maintains IOUTA (or IOUTB) at a virtual ground, thus minimizing the nonlinear output impedance effect on the DAC’s INL performance as discussed in the Analog Output section. Although this single-ended configuration typically provides the best dc linearity performance, its ac distortion performance at higher DAC update rates may be limited by U1’s slewing capabilities. U1 provides a negative unipolar output voltage and its full-scale output voltage is simply the product of RFB and IOUTFS. The full-scale output should be set within U1’s voltage output swing capabilities by scaling IOUTFS and/or RFB. An improvement in ac distortion performance may result with a reduced IOUTFS since the signal current U1 will be required to sink will be subsequently reduced. AD9774 AVDD 100mF ELECT. The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing some “free” capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all connections be short, direct and as physically close to the package as possible in order to minimize the sharing of conduction paths between different currents. When runs exceed an inch in length, strip line techniques with proper termination resistors should be considered. The necessity and value of this resistor will be dependent upon the logic family used. For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to Analog Devices’ application notes AN-280 and AN-333. –17– AD9774 MULTITONE PERFORMANCE CONSIDERATIONS AND CHARACTERIZATION The frequency domain performance of high speed DACs has traditionally been characterized by analyzing the spectral output of a reconstructed full-scale (i.e., 0 dBFS), single-tone sine wave at a particular output frequency and update rate. Although this characterization data is useful, it is often insufficient to reflect a DAC’s performance for a reconstructed multitone or spreadspectrum waveform. In fact, evaluating a DAC’s spectral performance using a full-scale, single tone at the highest specified frequency (i.e., fH) of a bandlimited waveform is typically indicative of a DAC’s “worst-case” performance for that given waveform. In the time domain, this full-scale sine wave represents the lowest peak-to-rms ratio or crest factor (i.e., VPEAK/ V rms) that this bandlimited signal will encounter. 0 –10 –20 10dB – DIV –30 –40 –50 –60 –70 –80 –90 –100 0 2 4 6 8 10 12 14 16 Figure 42a. Multitone Spectral Plot 1.0000 0.8000 0.6000 0.4000 VOLTS 0.2000 0.0000 –0.2000 –0.4000 –0.6000 –0.8000 –1.0000 TIME Figure 42b. Time Domain “Snapshot” of the Multitone Waveform However, the inherent nature of a multitone, spread spectrum, or QAM waveform, in which the spectral energy of the waveform is spread over a designated bandwidth, will result in a higher peak-to-rms ratio when compared to the case of a simple sine wave. As the reconstructed waveform’s peak-to-average ratio increases, an increasing amount of the signal energy is concentrated around the DAC’s midscale value. Figure 42a is just one example of a bandlimited multitone vector (i.e., eight tones) centered around one-half the Nyquist bandwidth (i.e., fCLOCK/4). This particular multitone vector, has a peak-to-rms ratio of 13.5 dB compared to a sine waves peak-to-rms ratio of 3 dB. A “snapshot” of this reconstructed multitone vector in the time domain as shown in Figure 43b reveals the higher signal content around the midscale value. As a result, a DAC’s “smallscale” dynamic and static linearity becomes increasingly critical in obtaining low intermodulation distortion and maintaining sufficient carrier-to-noise ratios for a given modulation scheme. A DAC’s small-scale linearity performance is also an important consideration in applications where additive dynamic range is required for gain control purposes or “predistortion” signal conditioning. For instance, a DAC with sufficient dynamic range can be used to provide additional gain control of its reconstructed signal. In fact, the gain can be controlled in 6 dB increments by simply performing a shift left or right on the DAC’s digital input word. Other applications may intentionally predistort a DAC’s digital input signal to compensate for nonlinearities associated with the subsequent analog components in the signal chain. For example, the signal compression associated with a power amplifier can be compensated for by predistorting the DAC’s digital input with the inverse nonlinear transfer function of the power amplifier. In either case, the DAC’s performance at reduced signal levels should be carefully evaluated. A full-scale single tone will induce all of the dynamic and static nonlinearities present in a DAC that contribute to its distortion and hence SFDR performance. As the frequency of this reconstructed full-scale, single-tone waveform increases, the dynamic nonlinearities of any DAC (i.e., AD9774) tend to dominate thus contributing to the roll-off in its SFDR performance. However, unlike most DACs, which employ an R-2R ladder for the lower bit current segmentation, the AD9774 (as well as other TxDAC members) exhibits an improvement in distortion performance as the amplitude of a single tone is reduced from its full-scale level. This improvement in distortion performance at reduced signal levels is evident if one compares the SFDR performance vs. frequency at different amplitudes (i.e., 0 dBFS, –6 dBFS and –12 dBFS) and sample rates as shown in Figures 4 through 15. Maintaining decent “small-scale” linearity across the full span of a DAC transfer function is also critical in maintaining excellent multitone performance. Although characterizing a DAC’s multitone performance tends to be application-specific, much insight into the potential performance of a DAC can also be gained by evaluating the DAC’s swept power (i.e., amplitude) performance for single, dual and multitone test vectors at different clock rates and carrier frequencies. The DAC is evaluated at different clock rates when reconstructing a specific waveform whose amplitude is decreased in 3 dB increments from full-scale (i.e., 0 dBFS). For each specific waveform, a graph showing the SFDR (over Nyquist) performance vs. amplitude can be generated at the different tested clock rates as shown in Figures 19 and 20. Note that the carrier(s)-to-clock ratio remains constant in each figure. –18– REV. B AD9774 This particular test vector was centered around one-half the Nyquist bandwidth (i.e., fCLOCK/4) with a passband of fCLOCK/16. Centering the tones at a much lower region (i.e., fCLOCK/10) would lead to an improvement in performance while centering the tones at a higher region (i.e., fCLOCK/2.5) would result in a degradation in performance. Figure 43a shows the SFDR vs. amplitude at 32 MSPS up to the Nyquist frequency while Figure 43b shows the SFDR vs. amplitude within the passband of the test vector. In assessing a DAC’s multitone performance, it is also recommended that several units be tested under exactly the same conditions to determine any performance variability. 80 75 70 SFDR – dBc A multitone test vector may consist of several equal amplitude, spaced carriers each representative of a channel within a defined bandwidth as shown in Figure 42a. In many cases, one or more tones are removed so the intermodulation distortion performance of the DAC can be evaluated. Nonlinearities associated with the DAC will create spurious tones of which some may fall back into the “empty” channel thus limiting a channel’s carrier-to-noise ratio. Other spurious components falling outside the band of interest may also be important, depending on the system’s spectral mask and filtering requirements. 65 60 55 50 45 40 –18 –16 –14 –12 –10 –8 AOUT – dBFS –6 –2 0 Figure 43a. Multitone SFDR vs. AOUT @ 32 MSPS (Up to Nyquist) 80 8MSPS 75 16MSPS 32MSPS The AD9774-EB is an evaluation board for the AD9774 14-bit DAC converter. Careful attention to layout and circuit design, combined with a prototyping area, allows the user to easily and effectively evaluate the AD9774 in signal reconstruction applications, where high resolution, high speed conversion is required. This board allows the user the flexibility to operate the AD9774 in various configurations. The digital inputs are designed to be driven directly from various word generators with the onboard option to add a resistor network for proper load termination. Provisions are also made to operate the AD9774 with either the internal or external reference or to exercise the SLEEP or SNOOZE power-savings feature. –19– SFDR – dBc 70 AD9774 EVALUATION BOARD General Description REV. B –4 65 60 55 50 –18 –16 –14 –12 –10 –8 AOUT – dBFS –6 –4 –2 0 Figure 43b. Multitone SFDR vs. AOUT @ 32 MSPS (Within Multitone Passband) AD9774 TP DVDD DGND TP TP TP14 DGND C3 10mF AVDD TP17 TP15 AGND C2 10mF TP16 C1 0.1mF R2 50V IA C4 20pF IDIFF 3 4 C12 0.1mF U3 50V TP 50V TP R10 100V TP ACOM 39 AVDD 40 IOUTB SLEEP 41 ICOMP DGND 42 IOUTA NC 43 38 37 36 35 34 C6 0.1mF TP AGND TP TP REFCOMP 33 DCOM 1 DB13 2 32 FSADJ DB12 3 31 REFIO DB11 4 30 REFLO DB10 5 29 UNUSED PLLENABLE 28 AD9774 TOP VIEW (Not to Scale) DB9 6 DB8 7 27 DB7 8 26 TP J4 PLLCOM 15 16 17 18 19 20 21 22 DVDD DGND CLK IN/OUT PLLLOCK CLK43IN DB3 14 NC 23 PLLDIVIDE NC DB4 11 DB0 24 VCO IN/EXT DB1 DB5 10 13 C11 0.1mF TP19 PLLVDD C8 0.01mF C9 10mF S3 TP18 PLLGND S2 P S1 TP P PLLGND TP TP AVDD DGND J1 C10 0.1mF P DVDD EXT CLK C7 0.1mF P R5 25 LPF TP 1.5kV 12 R1 1.91kV PLLVDD DB6 9 DB2 EDGE_40 1 C5 20pF R3 IB 50V DCOM SNOOZE DCOM 44 33 2 C13 0.1mF TP U2,U4 33 5 6 TP 1 X9 U7 PLLVDD J2 P J8 TP13 R4 50V 40 NC = NO CONNECT U8 U6 Figure 44. Evaluation Board Schematic –20– REV. B AD9774 Figure 45. Silkscreen Layer—Top Figure 46. Component Side PCB Layout (Layer 1) REV. B –21– AD9774 Figure 47. Ground Plane PCB Layout (Layer 2) Figure 48. Power Plane PCB Layout (Layer 3) –22– REV. B AD9774 Figure 49. Solder Side PCB Layout (Layer 4) Figure 50. Silkscreen Layer—Bottom REV. B –23– AD9774 OUTLINE DIMENSIONS Dimensions shown in millimeters and (inches). 13.45 (0.529) 12.95 (0.510) 2.45 (0.096) MAX 1.03 (0.041) 0.73 (0.029) C3198b–0–11/98 44-Lead Metric Quad Flatpack (S-44) 10.10 (0.398) 9.90 (0.390) 0° MIN 44 34 1 33 SEATING PLANE 8.45 (0.333) 8.30 (0.327) TOP VIEW (PINS DOWN) 11 0.25 (0.01) MIN 0.23 (0.009) 0.13 (0.005) 23 12 0.80 (0.031) BSC 0.45 (0.018) 0.30 (0.012) PRINTED IN U.S.A. 2.10 (0.083) 1.95 (0.077) 22 –24– REV. B