Dual 12-/14-/16-Bit,
LVDS Interface, 500 MSPS DACs
AD9780/AD9781/AD9783
Data Sheet
FEATURES
GENERAL DESCRIPTION
High dynamic range, dual DAC parts
Low noise and intermodulation distortion
Single carrier W-CDMA ACLR = 80 dBc at 61.44 MHz IF
Innovative switching output stage permits usable outputs
beyond Nyquist frequency
LVDS inputs with dual-port or optional interleaved singleport operation
Differential analog current outputs are programmable from
8.6 mA to 31.7 mA full scale
Auxiliary 10-bit current DACs with source/sink capability for
external offset nulling
Internal 1.2 V precision reference voltage source
Operates from 1.8 V and 3.3 V supplies
315 mW power dissipation
Small footprint, RoHS compliant, 72-lead LFCSP
The AD9780/AD9781/AD9783 include pin-compatible, high
dynamic range, dual digital-to-analog converters (DACs) with
12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS.
The devices include specific features for direct conversion transmit
applications, including gain and offset compensation, and they
interface seamlessly with analog quadrature modulators such as
the ADL5370.
A proprietary, dynamic output architecture permits synthesis
of analog outputs even above Nyquist by shifting energy away
from the fundamental and into the image frequency.
Full programmability is provided through a serial peripheral
interface (SPI) port. Some pin-programmable features are also
offered for those applications without a controller.
PRODUCT HIGHLIGHTS
APPLICATIONS
1.
Wireless infrastructure
W-CDMA, CDMA2000, TD-SCDMA, WiMAX
Wideband communications
LMDS/MMDS, point-to-point
RF signal generators, arbitrary waveform generators
2.
3.
Low noise and intermodulation distortion (IMD) enable
high quality synthesis of wideband signals.
Proprietary switching output for enhanced dynamic
performance.
Programmable current outputs and dual auxiliary DACs
provide flexibility and system enhancements.
FUNCTIONAL BLOCK DIAGRAM
AD9783 DUAL LVDS DAC
CLKP
16-BIT
I DAC
IOUT1P
16-BIT
Q DAC
IOUT2P
IOUT1N
INTERFACE LOGIC
IOUT2N
GAIN
DAC
GAIN
DAC
OFFSET
DAC
AUX1P
OFFSET
DAC
AUX2P
AUX1N
AUX2N
06936-001
RESET
CSB
SCLK
SDO
SDIO
SERIAL
PERIPHERAL
INTERFACE
INTERNAL
REFERENCE
AND
BIAS
REFIO
LVDS
INTERFACE
D[15:0]
VIA, VIB
DEINTERLEAVING
LOGIC
CLKN
Figure 1.
Rev. C
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Tel: 781.329.4700 ©2007–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9780/AD9781/AD9783
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
General Operation of the Serial Interface ............................... 19
Applications ....................................................................................... 1
Instruction Byte .......................................................................... 19
General Description ......................................................................... 1
MSB/LSB Transfers .................................................................... 20
Product Highlights ........................................................................... 1
Serial Interface Port Pin Descriptions ..................................... 20
Functional Block Diagram .............................................................. 1
SPI Register Map ............................................................................ 21
Table of Contents .............................................................................. 2
SPI Register Descriptions .............................................................. 22
Revision History ............................................................................... 2
SPI Port, RESET, and Pin Mode ............................................... 24
Specifications..................................................................................... 3
Parallel Data Port Interface ........................................................... 25
DC Specifications ......................................................................... 3
Optimizing the Parallel Port Timing ....................................... 25
Digital Specifications ................................................................... 4
BIST Operation........................................................................... 27
AC Specifications.......................................................................... 5
Driving the CLK Input .............................................................. 27
Absolute Maximum Ratings............................................................ 6
Full-Scale Current Generation ................................................. 28
Thermal Resistance ...................................................................... 6
DAC Transfer Function ............................................................. 28
ESD Caution .................................................................................. 6
Analog Modes of Operation ..................................................... 28
Pin Configurations and Function Descriptions ........................... 7
Power Dissipation....................................................................... 30
Typical Performance Characteristics ........................................... 10
Outline Dimensions ....................................................................... 31
Terminology .................................................................................... 18
Ordering Guide .......................................................................... 31
Theory of Operation ...................................................................... 19
Serial Peripheral Interface ......................................................... 19
REVISION HISTORY
8/2017—Rev. B to Rev. C
Changes to Table 12 ........................................................................ 22
6/2012—Rev. A to Rev. B
Changes to Table 2 ............................................................................ 4
Changes to Pins 25, 26, 29, and 30 Description, Table 6 ............. 7
Changes to Pins 9 to 24, 31 to 42, 25, 26, 29, and 30 Description,
Table 7 ................................................................................................ 8
Changes to Pins 25, 26, 29, and 30 Description, Table 7 ............. 9
Changes to SEEK Bit Function Description, Table 12 ............... 22
Changes to Parallel Data Port Interface Section......................... 25
Changed fDACCLK from 600 MHz to 500 MHz .............................. 26
Added BIST Operation Section .................................................... 27
Changes to Driving the CLK Input Section and Figure 59 ....... 27
Removed Evaluation Board Schematics Section ........................ 31
Updated Outline Dimensions ....................................................... 31
Changes to Ordering Guide .......................................................... 31
6/2008—Rev. 0 to Rev. A
Changed Maximum Sample Rate to 500 MHz Throughout .......1
Changes to Table 3.............................................................................4
Changes to Building the Array Section ....................................... 25
Changes to Determining the SMP Value Section ...................... 25
Added Evaluation Board Schematics Section ............................. 30
Updated Outline Dimensions ....................................................... 35
11/2007—Revision 0: Initial Version
Rev. C | Page 2 of 32
AD9780/AD9781/AD9783
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
MAIN DAC OUTPUTS
Offset Error
Gain Error (with Internal Reference)
Full-Scale Output Current 1
Output Compliance Range
Output Resistance
Main DAC Monotonicity Guaranteed
MAIN DAC TEMPERATURE DRIFT
Offset
Gain
Reference Voltage
AUX DAC OUTPUTS
Resolution
Full-Scale Output Current
Output Compliance Range (Source)
Output Compliance Range (Sink)
Output Resistance
AUX DAC Monotonicity Guaranteed
REFERENCE
Internal Reference Voltage
Output Resistance
ANALOG SUPPLY VOLTAGES
AVDD33
CVDD18
DIGITAL SUPPLY VOLTAGES
DVDD33
DVDD18
POWER CONSUMPTION
fDAC = 500 MSPS, IF = 20 MHz
fDAC = 500 MSPS, IF = 10 MHz
Power-Down Mode
SUPPLY CURRENTS 2
AVDD33
CVDD18
DVDD33
DVDD18
1
2
Min
AD9780
Typ
Max
12
Min
±0.13
±0.25
–0.001
8.66
–1.0
0
±2
20.2
AD9781
Typ
Max
14
Min
±0.5
±1
+0.001
–0.001
31.66
+1.0
8.66
–1.0
±2
±4
+0.001
–0.001
31.66
+1.0
8.66
–1.0
LSB
LSB
10
10
10
0.04
100
30
0.04
100
30
0.04
100
30
ppm/°C
ppm/°C
ppm/°C
+0.001
31.66
+1.0
1
1
1
Bits
mA
V
V
MΩ
1.2
5
1.2
5
1.2
5
V
kΩ
–2
0
0.8
10
0
±2
20.2
Unit
Bits
% FSR
% FSR
mA
V
MΩ
10
0
±2
20.2
AD9783
Typ
Max
16
+2
1.6
1.6
–2
0
0.8
10
+2
1.6
1.6
–2
0
0.8
+2
1.6
1.6
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
V
V
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
3.13
1.70
3.3
1.8
3.47
1.90
V
V
V×I
440
3
V×I
V×I
5
V×I
440
3
V×I
5
V×I
440
3
35
mW
mW
mW
55
34
13
68
58
38
15
85
55
34
13
68
58
38
15
85
55
34
13
68
58
38
15
85
mA
mA
mA
mA
Based on a 10 kΩ external resistor.
fDAC = 500 MSPS, fOUT = 20 MHz.
Rev. C | Page 3 of 32
AD9780/AD9781/AD9783
Data Sheet
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless
otherwise noted.
Table 2.
Parameter
DAC CLOCK INPUT (CLKP, CLKN)
Differential Peak-to-Peak Voltage (CLKP − CLKN)
Common-Mode Voltage
Maximum Clock Rate
DAC CLOCK TO ANALOG OUTPUT DATA LATENCY
SERIAL PERIPHERAL INTERFACE (CMOS INTERFACE)
Maximum Clock Rate (SCLK)
Minimum Pulse Width High
Minimum Pulse Width Low
Setup Time, SDI to SCLK (tDS)
Hold Time , SDI to to SCLK (tDH)
Data Valid ,SDO to SCLK, (tDV)
Setup time, CSB to SCLK (tDCSB)
SERIAL PERIPHERAL INTERFACE LOGIC LEVELS
Input Logic High
Input Logic Low
DIGITAL INPUT DATA (LVDS INTERFACE)
Input Voltage Range, VIA or VIB
Input Differential Threshold, VIDTH
Input Differential Hysteresis, VIDTHH to VIDTHL
Input Differential Input Impedance, RIN
Maximum LVDS Input Rate (per DAC)
Min
Typ
Max
Unit
400
300
500
800
400
1600
500
mV
mV
MSPS
Cycles
7
40
12.5
12.5
2.0
0.2
2.3
1.4
2.0
0.8
800
−100
1600
+100
20
80
500
Rev. C | Page 4 of 32
120
MHz
ns
ns
ns
ns
ns
ns
V
V
mV
mV
mV
Ω
MSPS
Data Sheet
AD9780/AD9781/AD9783
AC SPECIFICATIONS
TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless
otherwise noted.
Table 3.
Parameter
SPURIOUS FREE DYNAMIC RANGE (SFDR)
fDAC = 500 MSPS, fOUT = 20 MHz
fDAC = 500 MSPS, fOUT = 120 MHz
fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode)
fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode)
TWO-TONE INTERMODULATION DISTORTION (IMD)
fDAC = 500 MSPS, fOUT = 20 MHz
fDAC = 500 MSPS, fOUT = 120 MHz
fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode)
fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode)
ONE-TONE NOISE SPECTRAL DENSITY (NSD)
fDAC = 500 MSPS, fOUT = 40 MHz
fDAC = 500 MSPS, fOUT = 120 MHz
fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode)
fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode)
W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR),
SINGLE CARRIER
fDAC = 491.52 MSPS, fOUT = 20 MHz
fDAC = 491.52 MSPS, fOUT = 80 MHz
fDAC = 491.52 MSPS, fOUT = 411.52 MHz
fDAC = 491.52 MSPS, fOUT = 471.52 MHz
Min
AD9780
Typ
Max
Min
AD9781
Typ
Max
Min
AD9783
Typ
Max
Unit
79
67
55
58
78
66
58
62
80
68
62
59
dBc
dBc
dBc
dBc
91
80
69
60.5
93
75
70
61.5
86
79
64
66
dBc
dBc
dBc
dBc
−157
−154.5
−153
−152
−162
−156.5
−153
−152
−165
−157
−154
−153
dBc
dBc
dBc
dBc
−81
−80
−71
−69
−82.5
−82.5
−68
−69
−82
−81
−69
−70
dBc
dBc
dBc
dBc
Rev. C | Page 5 of 32
AD9780/AD9781/AD9783
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
AVDD33, DVDD33
DVDD18, CVDD18
AGND
DGND
CGND
REFIO
With
Respect to
AGND, DGND, CGND
AGND, DGND, CGND
DGND, CGND
AGND, CGND
AGND, DGND
AGND
AGND
IOUT1P, IOUT1N,
IOUT2P, IOUT2N,
AUX1P, AUX1N,
AUX2P, AUX2N
D15 to D0
DGND
CLKP, CLKN
CGND
CSB, SCLK, SDIO, SDO
DGND
Junction Temperature
Storage Temperature
Rating
−0.3 V to +3.6 V
−0.3 V to +1.98 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to
AVDD33 + 0.3 V
−1.0 V to
AVDD33 + 0.3 V
−0.3 V to
DVDD33 + 0.3 V
−0.3 V to
CVDD18 + 0.3 V
–0.3 V to
DVDD33 + 0.3 V
+125°C
−65°C to +150°C
Thermal resistance is tested using a JEDEC standard 4-layer
thermal test board with no airflow.
Table 5.
Package Type
CP-72-1 (Exposed Pad Soldered to PCB)
θJA
25
Unit
°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 6 of 32
Data Sheet
AD9780/AD9781/AD9783
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
AVSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
AVSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
AVDD33
AVDD33
REFIO
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PIN 1
INDICATOR
AD9780
(TOP VIEW)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FS ADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
NC
NC
NC
NC
NC
NC
NC
NC
D0N
D0P
D6P
D6N
D5P
D5N
D4P
D4N
DCOP
DCON
DVDD33
DVSS
DCIP
DCIN
D3P
D3N
D2P
D2N
D1P
D1N
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
D11P
D11N
D10P
D10N
D9P
D9N
D8P
D8N
D7P
D7N
06936-002
NOTES
1. NC = NO CONNECT
2. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.
Figure 2. AD9780 Pin Configuration
Table 6. AD9780 Pin Function Descriptions
Pin No.
1, 6
2, 5
3, 4
7, 28, 48
8, 47
9 to 24, 31 to 38
25, 26
27
29, 30
39 to 46
49
50
51
52
53
54
55
56, 57, 71, 72
58, 61, 64, 67, 70
59
60
62, 63
65, 66
68
69
Heat Sink Pad
Mnemonic
CVDD18
CVSS
CLKP, CLKN
DVSS
DVDD18
D11P, D11N to D0P, D0N
DCOP, DCON
DVDD33
DCIP, DCIN
NC
SDO
SDIO
SCLK
CSB
RESET
FS ADJ
REFIO
AVDD33
AVSS
IOUT2P
IOUT2N
AUX2P, AUX2N
AUX1N, AUX1P
IOUT1N
IOUT1P
N/A
Description
Clock Supply Voltage (1.8 V).
Clock Supply Return.
Differential DAC Sampling Clock Input.
Digital Common.
Digital Supply Voltage (1.8 V).
LVDS Data Inputs. D11 is the MSB, D0 is the LSB.
Differential Data Clock Output. Clock at the DAC sample rate.
Digital Input and Output Pad Ring Supply Voltage (3.3 V).
Differential Data Clock Input. Clock aligned with input data.
No Connection. Leave these pins floating.
Serial Port Data Output.
Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
Serial Port Clock Input.
Serial Port Chip Select (Active Low).
Chip Reset (Active High).
Full-Scale Current Output Adjust.
Analog Reference Input/Output (1.2 V Nominal).
Analog Supply Voltage (3.3 V).
Analog Common.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Differential Auxiliary DAC Current Output (Channel 2).
Differential Auxiliary DAC Current Output (Channel 1).
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
The heat sink pad on the bottom of the package must be soldered to the PCB plane that
carries AVSS.
Rev. C | Page 7 of 32
Data Sheet
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
AVSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
AVSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
AVDD33
AVDD33
REFIO
AD9780/AD9781/AD9783
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PIN 1
INDICATOR
AD9781
(TOP VIEW)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FS ADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
NC
NC
NC
NC
D0N
D0P
D1N
D1P
D2N
D2P
D8P
D8N
D7P
D7N
D6P
D6N
DCOP
DCON
DVDD33
DVSS
DCIP
DCIN
D5P
D5N
D4P
D4N
D3P
D3N
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
D13P
D13N
D12P
D12N
D11P
D11N
D10P
D10N
D9P
D9N
06936-003
NOTES
1. NC = NO CONNECT
2. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.
Figure 3. AD9781 Pin Configuration
Table 7. AD9781 Pin Function Descriptions
Pin No.
1, 6
2, 5
3, 4
7, 28, 48
8, 47
9 to 24, 31 to 42
25, 26
27
29, 30
43 to 46
49
50
51
52
53
54
55
56, 57, 71, 72
58, 61, 64, 67, 70
59
60
62, 63
65, 66
68
69
Heat Sink Pad
Mnemonic
CVDD18
CVSS
CLKP, CLKN
DVSS
DVDD18
D13P, D13N to D0P, D0N
DCOP, DCON
DVDD33
DCIP, DCIN
NC
SDO
SDIO
SCLK
CSB
RESET
FS ADJ
REFIO
AVDD33
AVSS
IOUT2P
IOUT2N
AUX2P, AUX2N
AUX1N, AUX1P
IOUT1N
IOUT1P
N/A
Description
Clock Supply Voltage (1.8 V).
Clock Supply Return.
Differential DAC Sampling Clock Input.
Digital Common.
Digital Supply Voltage (1.8 V).
Data Inputs. D13 is the MSB, D0 is the LSB.
Differential Data Clock Output. Clock at the DAC sample rate.
Digital Input and Output Pad Ring Supply Voltage (3.3 V).
Differential Data Clock Input. Clock aligned with input data.
No Connection. Leave these pins floating.
Serial Port Data Output.
Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
Serial Port Clock Input.
Serial Port Chip Select (Active Low).
Chip Reset (Active High).
Full-Scale Current Output Adjust.
Analog Reference Input/Output (1.2 V Nominal).
Analog Supply Voltage (3.3 V).
Analog Common.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Differential Auxiliary DAC Current Output (Channel 2).
Differential Auxiliary DAC Current Output (Channel 1).
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
The heat sink pad on the bottom of the package must be soldered to the PCB plane that
carries AVSS.
Rev. C | Page 8 of 32
AD9780/AD9781/AD9783
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD33
AVDD33
AVSS
IOUT1P
IOUT1N
AVSS
AUX1P
AUX1N
AVSS
AUX2N
AUX2P
AVSS
IOUT2N
IOUT2P
AVSS
AVDD33
AVDD33
REFIO
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
PIN 1
INDICATOR
AD9783
(TOP VIEW)
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FS ADJ
RESET
CSB
SCLK
SDIO
SDO
DVSS
DVDD18
D0N
D0P
D1N
D1P
D2N
D2P
D3N
D3P
D4N
D4P
D10P
D10N
D9P
D9N
D8P
D8N
DCOP
DCON
DVDD33
DVSS
DCIP
DCIN
D7P
D7N
D6P
D6N
D5P
D5N
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CVDD18
CVSS
CLKP
CLKN
CVSS
CVDD18
DVSS
DVDD18
D15P
D15N
D14P
D14N
D13P
D13N
D12P
D12N
D11P
D11N
06936-004
NOTES
1. EXPOSED PAD MUST BE
SOLDERED TO PCB AND
CONNECTED TO AVSS.
Figure 4. AD9783 Pin Configuration
Table 8. AD9783 Pin Function Descriptions
Pin No.
1, 6
2, 5
3, 4
7, 28, 48
8, 47
9 to 24, 31 to 46
25, 26
27
29, 30
49
50
51
52
53
54
55
56, 57, 71, 72
58, 61, 64, 67, 70
59
60
62, 63
65, 66
68
69
Heat Sink Pad
Mnemonic
CVDD18
CVSS
CLKP, CLKN
DVSS
DVDD18
D15P, D15N to D0P, D0N
DCOP, DCON
DVDD33
DCIP, DCIN
SDO
SDIO
SCLK
CSB
RESET
FS ADJ
REFIO
AVDD33
AVSS
IOUT2P
IOUT2N
AUX2P, AUX2N
AUX1N, AUX1P
IOUT1N
IOUT1P
N/A
Description
Clock Supply Voltage (1.8 V).
Clock Supply Return.
Differential DAC Sampling Clock Input.
Digital Common.
Digital Supply Voltage (1.8 V).
LVDS Data Inputs. D15 is the MSB, D0 is the LSB.
Differential Data Clock Output. Clock at the DAC sample rate.
Digital Input and Output Pad Ring Supply Voltage (3.3 V).
Differential Data Clock Input Clock aligned with input data.
Serial Port Data Output.
Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode).
Serial Port Clock Input.
Serial Port Chip Select (Active Low).
Chip Reset (Active High).
Full-Scale Current Output Adjust.
Analog Reference Input/Output (1.2 V Nominal).
Analog Supply Voltage (3.3 V).
Analog Common.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
Differential Auxiliary DAC Current Output (Channel 2).
Differential Auxiliary DAC Current Output (Channel 1).
Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s.
DAC Current Output. Full-scale current is sourced when all data bits are 1s.
The heat sink pad on the bottom of the package must be soldered to the PCB plane that
carries AVSS.
Rev. C | Page 9 of 32
AD9780/AD9781/AD9783
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.4
1.5
0.2
1.0
0
0.5
–0.2
–0.4
LSB
LSB
0
–0.5
–0.6
–0.8
–1.0
–1.0
–1.5
–1.2
–2.0
0
16,384
32,768
49,152
65,535
CODE
–1.6
06936-005
–2.5
0
16,384
32,768
49,152
65,535
CODE
Figure 5. AD9783 INL, TA = 85°C, FS = 20 mA
06936-008
–1.4
Figure 8. AD9783 DNL, TA = 85°C, FS = 20 mA
5
0.4
4
0.2
0
3
–0.2
–0.4
LSB
LSB
2
1
–0.6
–0.8
0
–1.0
–1
–1.2
–2
0
16,384
32,768
49,152
65,535
CODE
–1.6
0
16,384
32,768
49,152
65,535
CODE
Figure 6. AD9783 INL, TA = 25°C, FS = 20 mA
06936-009
–3
06936-006
–1.4
Figure 9. AD9783 DNL, TA = 25°C, FS = 20 mA
5
1.0
4
0.8
0.6
3
0.4
LSB
0.2
1
0
–0.2
0
–0.4
–1
–0.6
–2
0
16,384
32,768
49,152
CODE
65,535
Figure 7. AD9783 INL, TA = −40°C, FS = 20 mA
–1.0
0
16,384
32,768
49,152
CODE
Figure 10. AD9783 DNL, TA = −40°C, FS = 20 mA
Rev. C | Page 10 of 32
65,535
06936-010
–0.8
–3
06936-007
LSB
2
Data Sheet
AD9780/AD9781/AD9783
0.4
0.059
0.3
0.2
–0.060
0.1
LSB
LSB
0
–0.1
–0.179
–0.2
–0.3
–0.297
–0.4
0
4096
8192
12,288
16,383
CODE
–0.416
0
4096
8192
12,288
16,383
CODE
Figure 11. AD9781 INL, TA = 85°C, FS = 20 mA
06936-014
–0.6
06936-011
–0.5
Figure 14. AD9781 DNL, TA = 85°C, FS = 20 mA
0.6
0.1
0.4
0
0.2
–0.1
LSB
LSB
0
–0.2
–0.2
–0.4
–0.3
–0.6
4096
8192
12288
16,383
CODE
–0.5
0
0.1
0
0
–0.1
–0.1
LSB
0.1
–0.2
–0.3
–0.4
–0.4
–0.5
–0.5
2048
3072
CODE
16,383
–0.2
–0.3
4096
06936-013
LSB
0.2
1024
12,288
Figure 15. AD9781 DNL, TA = −40°C, FS = 20 mA
0.2
0
8192
CODE
Figure 12. AD9781 INL, TA = −40°C, FS = 20 mA
–0.6
4096
Figure 13. AD9780 INL, TA = −40°C, FS = 20 mA
–0.6
0
1024
2048
3072
CODE
Figure 16. AD9780 INL, TA = 85°C, FS = 20 mA
Rev. C | Page 11 of 32
4096
06936-016
0
06936-012
–1.0
06936-015
–0.4
–0.8
AD9780/AD9781/AD9783
Data Sheet
90
100
85
95
80
90
250MSPS
85
400MSPS
75
+25°C
70
SFDR (dBc)
SFDR (dBc)
80
65
60
–40°C
75
70
65
+85°C
60
55
500MSPS
55
50
50
45
50
100
150
200
250
300
350
400
450
500
fOUT (MHz)
40
0
25
50
75
100
125
150
175
200
225
250
fOUT (MHz)
Figure 17. AD9783 SFDR vs. fOUT Over fDAC in Baseband and Mix Modes,
FS = 20 mA
06936-020
0
06936-017
45
40
Figure 20. AD9783 SFDR vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA
100
100
95
95
90
90
250MSPS
85
85
20mA
80
30mA
IMD (dBc)
75
70
65
55
10mA
500MSPS
50
50
45
40
40
0
25
50
75
100
125
150
175
200
225
250
fOUT (MHz)
06936-018
45
0
50
100
150
100
95
95
90
90
85
350
400
450
500
10mA
85
–3dBFS
80
IMD (dBc)
75
70
–6dBFS
60
300
Figure 21. AD9783 IMD vs. fOUT Over fDAC in Baseband and Mix Modes,
FS = 20 mA
100
65
250
fOUT (MHz)
Figure 18. AD9783 SFDR vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS
80
200
06936-021
55
20mA
75
70
30mA
65
60
0dBFS
55
55
50
50
45
45
0
25
50
75
100
125
150
175
200
225
fOUT (MHz)
Figure 19. AD9783 SFDR vs. fOUT Over Digital Input Level,
TA = 25°C, at 500 MSPS, FS = 20 mA
250
40
06936-019
40
400MSPS
65
60
60
SFDR (dBc)
75
70
0
25
50
75
100
125
150
fOUT (MHz)
175
200
225
250
06936-022
SFDR (dBc)
80
Figure 22. AD9783 IMD vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS
Rev. C | Page 12 of 32
Data Sheet
AD9780/AD9781/AD9783
–140
100
95
–143
–6dBFS
90
–146
–3dBFS
85
–149
NSD (dBm/Hz)
IMD (dBc)
80
75
70
0dBFS
65
60
–152
–155
250MSPS
–158
–161
55
–164
500MSPS
50
30
60
90
120
150
180
210
240
fOUT (MHz)
–170
06936-023
0
50
100
150
200
250
300
350
400
450
500
fOUT (MHz)
Figure 26. AD9783 Eight-Tone NSD vs. fOUT Over fDAC Baseband and
Mix Modes, FS = 20 mA
Figure 23. AD9783 IMD vs. fOUT Over Digital Input Level, TA = 25°C, at
500 MSPS, FS = 20 mA
100
–140
95
–143
90
–146
85
+85°C
–149
75
NSD (dBm/Hz)
80
IMD (dBc)
0
06936-026
45
40
400MSPS
–167
+25°C
70
–40°C
65
60
+85°C
–152
+25°C
–155
–158
–40°C
–161
55
–164
50
0
30
60
90
120
150
180
210
240
fOUT (MHz)
–170
06936-024
40
–140
–143
–143
–146
–146
75
100
125
150
175
200
225
250
–149
250MSPS
NSD (dBm/Hz)
NSD (dBm/Hz)
50
Figure 27. AD9783 One-Tone NSD vs. fOUT Over Temperature, at 500 MSPS,
FS = 20 mA
–140
–152
500MSPS
–155
25
fOUT (MHz)
Figure 24. AD9783 IMD vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA
–149
0
06936-027
–167
45
–158
–152
–155
–158
+85°C
–161
–161
400MSPS
–164
–167
–167
0
50
100
150
200
250
300
fOUT (MHz)
350
400
450
500
–170
06936-025
–170
Figure 25. AD9783 One-Tone NSD vs. fOUT Over fDAC Baseband and Mix Modes,
FS = 20 mA
+25°C
–40°C
0
25
50
75
100
125
150
fOUT (MHz)
175
200
225
250
06936-028
–164
Figure 28. AD9783 Eight-Tone NSD vs. fOUT Over Temperature, at 500 MSPS,
FS = 20 mA
Rev. C | Page 13 of 32
Data Sheet
–50
–50
–55
–55
–60
–60
245.76MSPS
–70
–80
–80
–85
–85
–90
100
200
300
400
500
fOUT (MHz)
Figure 29. AD9783 ACLR for First Adjacent Band One-Carrier W-CDMA
Baseband and Mix Modes, FS = 20 mA
–55
–55
–60
–60
–65
–65
ACLR (dBc)
–50
245.76MSPS
491.52MSPS
–70
–75
–75
–80
–80
–85
–85
300
400
500
–3dB
0dB
0
100
200
300
400
500
fOUT (MHz)
–90
Figure 30. AD9783 ACLR for Second Adjacent Band One-Carrier W-CDMA
Baseband and Mix Modes, FS = 20 mA
–55
–60
–60
–65
–65
ACLR (dBc)
–55
491.52MSPS
300
400
500
Figure 33. AD9783 ACLR for Second Adjacent Channel Two-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
–50
245.76MSPS
200
fOUT (MHz)
–50
–70
100
0
06936-033
–90
200
Figure 32. AD9783 ACLR for First Adjacent Channel Two-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
–50
–70
100
0
fOUT (MHz)
06936-030
ACLR (dBc)
–3dB
–75
0
0dB
–70
–75
–90
ACLR (dBc)
–65
06936-032
ACLR (dBc)
491.52MSPS
–65
06936-029
ACLR (dBc)
AD9780/AD9781/AD9783
–70
–75
–75
–80
–80
–85
–85
–3dB
0
100
200
300
fOUT (MHz)
400
500
–90
06936-031
–90
Figure 31. AD9783 ACLR for Third Adjacent Band One-Carrier W-CDMA
Baseband and Mix Modes, FS = 20 mA
06936-034
0dB
0
100
200
300
400
500
fOUT (MHz)
Figure 34. AD9783 ACLR for Third Adjacent Channel Two-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
Rev. C | Page 14 of 32
Data Sheet
AD9780/AD9781/AD9783
–50
1.0
0.5
–55
0
–0.5
0dB
AMPLITUDE (dBm)
ACLR (dBc)
–60
–65
–70
–3dB
–75
–80
–1.0
NORMAL MODE
–1.5
–2.0
–2.5
–3.0
MIX MODE
–3.5
–4.0
–85
200
300
400
500
fOUT (MHz)
0.8
–55
0.6
–60
0.4
–3dB
LSB
0dB
–75
300
360
420
480
540
600
–0.2
–0.4
–85
–0.6
100
240
0
–80
0
180
0.2
–70
–90
120
Figure 38. Nominal Power in the Fundamental, FS = 20 mA, at 500 MSPS,
FS = 20 mA
–50
–65
60
fOUT (MHz)
200
300
400
500
fOUT (MHz)
–0.8
06936-036
ACLR (dBc)
Figure 35. AD9783 ACLR for First Adjacent Channel Four-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
0
0
4096
8192
12,288
16,383
CODE
06936-039
100
06936-035
0
–5.0
06936-038
–4.5
–90
Figure 39. AD9781 INL, FS = 20 mA
Figure 36. AD9783 ACLR for Second Adjacent Channel Four-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
0.1
–50
–55
0
–60
–3dB
LSB
ACLR (dBc)
–0.1
–65
–70
–75
0dB
–0.2
–0.3
–80
–0.4
0
100
200
300
fOUT (MHz)
400
500
Figure 37. AD9783 ACLR for Third Adjacent Channel Four-Carrier W-CDMA
Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS,
FS = 20 mA
Rev. C | Page 15 of 32
–0.5
0
4096
8192
12,288
CODE
Figure 40. AD9781 DNL, FS = 20 mA
16,383
06936-040
–90
06936-037
–85
AD9780/AD9781/AD9783
Data Sheet
100
–50
95
–55
90
85
–60
FIRST
ADJACENT
CHANNEL
75
70
65
60
55
–65
–70
–75
SECOND
ADJACENT
CHANNEL
–85
45
0
50
100
150
200
250
300
350
400
450
500
fOUT (MHz)
–90
06936-041
40
THIRD
ADJACENT
CHANNEL
–80
50
100
200
300
400
500
fOUT (MHz)
Figure 41. AD9781 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS,
FS = 20 mA
Figure 44. AD9781 ACLR for One-Carrier W-CDMA Baseband and Mix Modes,
at 491.52 MSPS, FS = 20 mA
100
0.2
IMD @ 500MSPS
95
0
06936-044
ACLR (dBc)
SFDR (dBc)
80
0.1
90
85
0
–0.1
75
LSB
IMD (dBc)
80
70
–0.2
65
60
–0.3
55
–0.4
50
0
60
120
180
240
300
360
420
480
540
600
fOUT (MHz)
06936-042
40
–0.6
0
1024
2048
3072
4096
CODE
Figure 42. AD9781 IMD vs. fOUT in Baseband and Mix Modes, at 500 MSPS,
FS = 20 mA
06936-045
–0.5
45
Figure 45. AD9780 INL, FS = 20 mA
0.04
–140
–142
0.02
–144
–146
0
–148
1-TONE
–0.02
–152
–154
LSB
NSD (dBm/Hz)
–150
–156
–0.04
8-TONE
–158
–0.06
–160
–162
–0.08
–164
–166
–0.10
0
50
100
150
200
250
300
fOUT (MHz)
350
400
450
500
Figure 43. AD9781 One-Tone, Eight-Tone NSD vs. fOUT in Baseband and Mix
Modes, at 500 MSPS, FS = 20 mA
Rev. C | Page 16 of 32
–0.12
0
1024
2048
3072
CODE
Figure 46. AD9780 DNL, FS = 20 mA
4096
06936-046
–170
06936-043
–168
Data Sheet
AD9780/AD9781/AD9783
–140
100
–142
95
–144
90
–146
85
–148
–150
NSD (dBm/Hz)
SFDR (dBc)
80
75
70
65
1-TONE
–152
–154
–156
–158
–160
60
8-TONE
–162
55
–166
45
–168
0
50
100
150
200
250
300
350
400
450
500
fOUT (MHz)
–170
06936-047
40
0
50
100
150
200
250
300
350
400
450
500
fOUT (MHz)
Figure 47. AD9780 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS,
FS = 20 mA
06936-049
–164
50
Figure 49. AD9780 One-Tone, Eight-Tone NSD vs. fOUT in Baseband and Mix
Modes, at 500 MSPS, FS = 20 mA
100
–50
95
–55
90
85
–60
80
ACLR (dBc)
IMD (dBc)
75
70
65
60
55
FIRST
ADJACENT
CHANNEL
–65
–70
–75
50
SECOND
ADJACENT
CHANNEL
–80
45
40
–85
THIRD
ADJACENT
CHANNEL
0
50
100
150
200
250
300
fOUT (MHz)
350
400
450
500
–90
06936-048
30
0
100
200
300
fOUT (MHz)
Figure 48. AD9780 IMD vs. fOUT in Baseband and Mix Modes, at 500 MSPS,
FS = 20 mA
400
500
06936-050
35
Figure 50. AD9780 ACLR for One-Carrier W-CDMA Baseband and Mix Modes,
at 491.52 MSPS, FS = 20 mA
Rev. C | Page 17 of 32
AD9780/AD9781/AD9783
Data Sheet
TERMINOLOGY
Linearity Error or Integral Nonlinearity (INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero scale to full scale.
Power Supply Rejection
Power supply rejection is the maximum change in the full-scale
output as the supplies are varied from minimum to maximum
specified voltages.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Settling Time
Settling time is the time required for the output to reach and
remain within a specified error band around its final value,
measured from the start of the output transition.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Offset Error
Offset error is the deviation of the output current from the ideal
of zero. For IOUTA, 0 mA output is expected when the inputs are
all 0s. For IOUTB, 0 mA output is expected when all inputs are
set to 1s.
Gain Error
Gain error is the difference between the actual and ideal output
span. The actual span is determined by the difference between
the output when all inputs are set to 1s and the output when all
inputs are set to 0s.
Output Compliance Range
Output compliance range is the range of allowable voltage at
the output of a current-output DAC. Operation beyond the
maximum compliance limits can cause either output stage
saturation or breakdown, resulting in nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from
the ambient (25°C) value to the value at either TMIN or TMAX.
For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the
drift is reported in ppm per degree Celsius.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels, between the peak amplitude
of the output signal and the peak spurious signal between dc
and the frequency equal to half the input data rate.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
Adjacent Channel Leakage Ratio (ACLR)
ACLR is the ratio in dBc between the measured power within a
channel relative to its adjacent channel.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images usually waste
transmitter power and system bandwidth. By placing the real
part of a second complex modulator in series with the first
complex modulator, either the upper or lower frequency image
near the second IF can be rejected.
Rev. C | Page 18 of 32
Data Sheet
AD9780/AD9781/AD9783
THEORY OF OPERATION
The AD9780/AD9781/AD9783 have a combination of features
that make them very attractive for wired and wireless communications systems. The dual DAC architecture facilitates easy
interface to common quadrature modulators when designing
single sideband transmitters. In addition, the speed and
performance of the devices allow wider bandwidths and more
carriers to be synthesized than in previously available products.
All features and options are software programmable through
the SPI port.
SERIAL PERIPHERAL INTERFACE
SDO
SCLK
AD9783
SPI
PORT
CSB
06936-051
SDIO
Figure 51. SPI Port
The serial peripheral interface (SPI) port is a flexible, synchronous serial communications port allowing easy interface to many
industry-standard microcontrollers and microprocessors. The
port is compatible with most synchronous transfer formats,
including both the Motorola SPI and Intel® SSR protocols.
The interface allows read and write access to all registers that
configure the AD9780/AD9781/AD9783. Single or multiple
byte transfers are supported as well as MSB-first or LSB-first
transfer formats. Serial data input/output can be accomplished
through a single bidirectional pin (SDIO) or through two
unidirectional pins (SDIO/SDO).
The serial port configuration is controlled by Register 0x00,
Bits[7:6]. It is important to note that any change made to the
serial port configuration occurs immediately upon writing to
the last bit of this byte. Therefore, it is possible with a multibyte
transfer to write to this register and change the configuration in
the middle of a communication cycle. Care must be taken to
compensate for the new configuration within the remaining
bytes of the current communication cycle.
The Phase 1 instruction byte defines whether the upcoming
data transfer is a read or write, the number of bytes in the data
transfer, and a reference register address for the first byte of the
data transfer. A logic high on the CSB pin followed by a logic
low resets the SPI port to its initial state and defines the start of
the instruction cycle. From this point, the next eight rising
SCLK edges define the eight bits of the instruction byte for the
current communication cycle.
The remaining SCLK edges are for Phase 2 of the communication
cycle, which is the data transfer between the serial port controller
and the system controller. Phase 2 can be a transfer of one, two,
three, or four data bytes as determined by the instruction byte.
Using multibyte transfers is usually preferred, although singlebyte data transfers are useful to reduce CPU overhead or when
only a single register access is required.
All serial port data is transferred to and from the device in
synchronization with the SCLK pin. Input data is always latched
on the rising edge of SCLK, whereas output data is always valid
after the falling edge of SCLK. Register contents change immediately upon writing to the last bit of each transfer byte.
Anytime synchronization is lost, the device has the ability to
asynchronously terminate an I/O operation whenever the CSB pin
is taken to logic high. Any unwritten register content data is lost
if the I/O operation is aborted. Taking CSB low then resets the
serial port controller and restarts the communication cycle.
INSTRUCTION BYTE
The instruction byte contains the information shown in Table 9.
Table 9.
MSB
B7
R/W
B6
N1
B5
N0
B4
A4
B3
A3
B2
A2
B1
A1
LSB
B0
A0
Bit 7, R/W, determines whether a read or a write data transfer
occurs after the instruction byte write. Logic 1 indicates a read
operation. Logic 0 indicates a write operation.
Use of a single-byte transfer when changing the serial port
configuration is recommended to prevent unexpected device
behavior.
Bits[6:5], N1 and N0, determine the number of bytes to be
transferred during the data transfer cycle. The bits decode as
shown in Table 10.
GENERAL OPERATION OF THE SERIAL INTERFACE
Table 10. Byte Transfer Count
There are two phases to any communication cycle with the
AD9780/AD9781/AD9783: Phase 1 and Phase 2. Phase 1 is the
instruction cycle, which writes an instruction byte into the device.
This byte provides the serial port controller with information
regarding Phase 2 of the communication cycle: the data transfer
cycle.
N1
0
0
1
1
Rev. C | Page 19 of 32
N0
0
1
0
1
Description
Transfer one byte
Transfer two bytes
Transfer three bytes
Transfer four bytes
AD9780/AD9781/AD9783
Data Sheet
Serial Port Data I/O (SDIO)
Data is always written into the device on this pin. However,
SDIO can also function as a bidirectional data output line. The
configuration of this pin is controlled by Register 0x00, Bit 7.
The default is Logic 0, which configures the SDIO pin as
unidirectional.
Serial Port Data Output (SDO)
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. The configuration of this
pin is controlled by Register 0x00, Bit 7. If this bit is set to a
Logic 1, the SDO pin does not output data and is set to a high
impedance state.
MSB/LSB TRANSFERS
When using MSB-first format (LSBFIRST = 0), the instruction
and data bit must be written from MSB to LSB. Multibyte data
transfers in MSB-first format start with an instruction byte that
includes the register address of the most significant data byte.
Subsequent data bytes are loaded into sequentially lower address
locations. In MSB-first mode, the serial port internal address
generator decrements for each byte of the multibyte data
transfer.
When using LSB-first format (LSBFIRST = 1), the instruction
and data bit must be written from LSB to MSB. Multibyte data
transfers in LSB-first format start with an instruction byte that
includes the register address of the least significant data byte.
Subsequent data bytes are loaded into sequentially higher
address locations. In LSB-first mode, the serial port internal
address generator increments for each byte of the multibyte
data transfer.
DATA TRANSFER CYCLE
INSTRUCTION CYCLE
CSB
SCLK
SDIO
R/W N1
N0
A4 A3
A2 A1
A0
SDO
D7 D6N D5N
D30 D20 D10 D00
D7 D6N D5N
D30 D20 D10 D00
06936-052
The serial port can support both MSB-first and LSB-first data
formats. This functionality is controlled by Register 0x00, Bit 6.
The default is Logic 0, which is MSB-first format.
Figure 52. Serial Register Interface Timing Diagram, MSB First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CSB
SCLK
SDIO
A0
A1
A2
A3 A4
N0 N1 R/W D00 D10 D20
D4N D5N D6N D7N
D00 D10 D20
D4N D5N D6N D7N
SDO
06936-053
Bits[4:0], A4, A3, A2, A1, and A0, determine which register is
accessed during the data transfer of the communication cycle.
For multibyte transfers, this address is a starting or ending
address depending on the current data transfer mode. For
MSB-first format, the specified address is an ending address
or the most significant address in the current cycle. Remaining
register addresses for multiple byte data transfers are generated
internally by the serial port controller by decrementing from
the specified address. For LSB-first format, the specified address
is a beginning address or the least significant address in the
current cycle. Remaining register addresses for multiple byte
data transfers are generated internally by the serial port
controller by incrementing from the specified address.
Figure 53. Serial Register Interface Timing Diagram, LSB First
Use of a single-byte transfer when changing the serial port data
format is recommended to prevent unexpected device behavior.
tS
fSCLK –1
CSB
SERIAL INTERFACE PORT PIN DESCRIPTIONS
tPWH
Chip Select Bar (CSB)
tPWL
tDS
SDIO
tDH
INSTRUCTION BIT 7
INSTRUCTION BIT 6
06936-054
SCLK
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communication lines. CSB must stay low during the entire
communication cycle. Incomplete data transfers are aborted
anytime the CSB pin goes high. SDO and SDIO pins go to a
high impedance state when this input is high.
Figure 54. Timing Diagram for SPI Write Register
CSB
Serial Clock (SCLK)
SCLK
tDV
SDIO
SDO
Rev. C | Page 20 of 32
DATA BIT N
DATA BIT N – 1
Figure 55. Timing Diagram for SPI Read Register
06936-055
The serial clock pin is used to synchronize data to and from the
device and to run the internal state machines. The maximum
frequency of SCLK is 40 MHz. All data input is registered on
the rising edge of SCLK. All data is driven out on the falling
edge of SCLK.
Data Sheet
AD9780/AD9781/AD9783
SPI REGISTER MAP
Table 11.
Register Name
SPI Control
Data Control
Power-Down
Setup and Hold
Timing Adjust
Seek
Mix Mode
DAC1 FSC
DAC1 FSC MSBs
AUXDAC1
AUXDAC1 MSB
DAC2 FSC
DAC2 FSC MSBs
AUXDAC2
AUXDAC2 MSB
BIST Control
BIST Result 1 Low
BIST Result 1 High
BIST Result 2 Low
BIST Result 2 High
Hardware Version
Addr
0x00
0x02
0x03
0x04
0x05
0x06
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
Default
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xF9
0x01
0x00
0x00
0xF9
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
N/A
Bit 7
SDIO_DIR
DATA
PD_DCO
Bit 6
LSBFIRST
AUX1SGN
AUX1DIR
AUX2SGN
BISTEN
AUX2DIR
BISTRD
Bit 5
RESET
PD_INPT
PD_AUX2
SET[3:0]
Bit 4
Bit 3
Bit 2
Bit 1
INVDCO
PD_AUX1
PD_BIAS
PD_CLK
PD_DAC2
PD_DAC1
HLD[3:0]
SAMP_DLY[4:0]
LVDS low
LVDS high SEEK
DAC1MIX[1:0]
DAC2MIX[1:0]
DAC1FSC[7:0]
DAC1FSC[9:8]
AUXDAC1[7:0]
AUXDAC1[9:8]
DAC2FSC[7:0]
DAC2FSC[9:8]
AUXDAC2[7:0]
AUXDAC2[9:8]
BISTCLR
BISTRES1[7:0]
BISTRES1[15:8]
BISTRES2[7:0]
BISTRES2[15:8]
VERSION[3:0]
Rev. C | Page 21 of 32
Bit 0
DEVICE[3:0]
AD9780/AD9781/AD9783
Data Sheet
SPI REGISTER DESCRIPTIONS
Reading these registers returns previously written values for all defined register bits, unless otherwise noted.
Table 12.
Register
SPI Control
Address
0x00
Data Control
0x02
Power-Down
0x03
Setup and Hold
0x04
Timing Adjust
Seek
0x05
0x06
Mix Mode
DAC1 FSC
0x0A
0x0B
0x0C
Bit
7
Name
SDIO_DIR
6
LSBFIRST
5
RESET
7
DATA
4
7
6
5
4
3
2
1
0
7:4
3:0
4:0
2
INVDCO
PD_DCO
PD_INPT
PD_AUX2
PD_AUX1
PD_BIAS
PD_CLK
PD_DAC2
PD_DAC1
SET[3:0]
HLD[3:0]
SAMP_DLY[4:0]
LVDS low
1
LVDS high
0
SEEK
3:2
DAC1MIX[1:0]
1:0
DAC2MIX[1:0]
7:0
1:0
DAC1FSC[9:0]
Function
0, operate SPI in 4-wire mode. The SDIO pin operates as an input only pin.
1, operate SPI in 3-wire mode. The SDIO pin operates as a bidirectional data line.
0, MSB first per SPI standard.
1, LSB first per SPI standard.
Only change LSB/MSB order in single-byte instructions to avoid erratic behavior
due to bit order errors.
0, execute software reset of SPI and controllers, reload default register values
except Register 0x00.
1, set software reset, write 0 on the next (or any following) cycle to release the reset.
0, DAC input data is twos complement binary format.
1, DAC input data is unsigned binary format.
1, inverts the data clock output. Used for adjusting timing of input data.
1, power down data clock output driver circuit.
1, power down input.
1, power down AUX2 DAC
1, power down AUX1 DAC.
1, power down voltage reference bias circuit.
1, power down DAC clock input circuit.
1, power down DAC2.
1, power down DAC1.
4-bit value used to determine input data setup timing.
4-bit value used to determine input data hold timing.
5-bit value used to optimally position input data relative to internal sampling clock.
One of the LVDS inputs is above the input voltage limits of the IEEE reduced link
specification.
One of the LVDS inputs is below the input voltage limits of the IEEE reduced link
specification.
Indicator bit used with LVDS_SET and LVDS HLD to determine input data timing
margin.
00, selects Normal Mode.
01, selects Mix Mode.
10, selects RZ Mode.
11, selects RZ Mode.
00, selects Normal Mode.
01, selects Mix Mode.
10, selects RZ Mode.
11, selects RZ Mode.
DAC1 full-scale 10-bit adjustment word.
0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA.
0x200, sets DAC full-scale output current to the nominal value of 20.0 mA.
0x000, sets DAC full-scale output current to the minimum value of 8.66 mA.
Rev. C | Page 22 of 32
Data Sheet
Register
AUXDAC1
AD9780/AD9781/AD9783
Address
0x0D
0x0E
Bit
7:0
1:0
Name
AUXDAC1[9:0]
DAC2 FSC
0x0F
0x10
7:0
1:0
DAC2FSC[9:0]
AUXDAC2
0x11
0x12
7:0
1:0
AUXDAC2[9:0]
0x12
7
AUX2SGN
6
AUX2DIR
7
6
5
7:0
7:0
7:0
7:0
7:4
3:0
BISTEN
BISTRD
BISTCLR
BISTRES1[15:0]
Function
AUXDAC1 output current adjustment word.
0x3FF, sets AUXDAC1 output current to 2.0 mA.
0x200, sets AUXDAC1 output current to 1.0 mA.
0x000, sets AUXDAC1 output current to 0.0 mA.
0, AUX1P output pin is active.
1, AUX1N output pin is active.
0, configures AUXDAC1 output to source current.
1, configures AUXDAC1 output to sink current.
DAC2 full-scale 10-bit adjustment word.
0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA.
0x200, sets DAC full-scale output current to the nominal value of 20.0 mA.
0x000, sets DAC full-scale output current to the minimum value of 8.66 mA.
AUXDAC2 output current adjustment word.
0x3FF, sets AUXDAC2 output current to 2.0 mA.
0x200, sets AUXDAC2 output current to 1.0 mA.
0x000, sets AUXDAC2 output current to 0.0 mA.
0, AUX2P output pin is active.
1, AUX2N output pin is active.
0, configures AUXDAC2 output to source current.
1, configures AUXDAC2 output to sink current.
1, enables and starts built-in self-test.
1, transfers BIST result registers to SPI for readback.
1, reset BIST logic and clear BIST result registers.
16-bit result generated by BIST 1.
0x0E
7
AUX1SGN
6
AUX1DIR
BISTRES2[15:0]
16-bit result generated by BIST 2.
VERSION[3:0]
DEVICE[3:0]
Read only register; indicates the version of the chip.
Read only register; indicates the device type.
BIST Control
0x1A
BIST Result 1
0x1B
0x1C
0x1D
0x1E
0x1F
BIST Result 2
Hardware Version
Rev. C | Page 23 of 32
AD9780/AD9781/AD9783
Data Sheet
SPI PORT, RESET, AND PIN MODE
Table 13. SPI Pin Functions (Pin Mode)
In general, when the AD9780/AD9781/AD9783 are powered
up, an active high pulse applied to the RESET pin follows. This
ensures the default state of all control register bits. In addition,
once the RESET pin goes low, the SPI port can be activated;
thus, CSB must be held high.
Pin
Name
SDIO
For applications without a controller, the AD9780/AD9781/
AD9783 also supports pin mode operation, which allows some
functional options to be pin selected without the use of the SPI
port. Pin mode is enabled anytime the RESET pin is held high.
In pin mode, the four SPI port pins take on secondary
functions, as shown in Table 13.
SDO
CSB
Rev. C | Page 24 of 32
Pin Mode Function
DATA (Register 0x02, Bit 7), bit value (1/0) equals pin
state (high/low).
Enable mix mode. If CSB is high, Register 0x0A is set
to 0x05, putting both DAC1 and DAC2 into mix mode.
Enable full power-down. If SDO is high, Register 0x03
is set to 0xFF.
Data Sheet
AD9780/AD9781/AD9783
PARALLEL DATA PORT INTERFACE
The parallel port data interface consists of up to 18 differential
signals, DCO, DCI, and up to 16 data lines (D[15:0]), as shown
in Figure 56. DCO is the output clock generated by the AD9780/
AD9781/AD9783 that is used to clock out the data from the
digital data engine. The data lines transmit the multiplexed
I and Q data words for the I and Q DACs, respectively. DCI
provides timing information about the parallel data and signals
the I/Q status of the data.
OPTIMIZING THE PARALLEL PORT TIMING
As diagrammed in Figure 56, the incoming LVDS data is
latched by an internally generated clock referred to as the data
sampling signal (DSS). DSS is a delayed version of the main
DAC clock signal, CLKP/CLKN. Optimal positioning of the
rising and falling edges of DSS with respect to the incoming
data signals results in the most robust transmission of the DAC
data. Positioning the edges of DSS with respect to the data
signals is achieved by selecting the value of a programmable
delay element, SMP. A procedure for determining the optimal
value of SMP is given in the Optimizing the Parallel Port
Timing section.
The clock input signal provides timing information about the
parallel data, as well as indicating the destination (that is, I DAC
or Q DAC) of the data. A delayed version of DCI is generated
by a delay element, SET, and is referred to as DDCI. DDCI is
sampled by a delayed version of the DSS signal, labeled as DDSS
in Figure 56. DDSS is simply DSS delayed by a period of time,
HLD. The pair of delays, SET and HLD, allows accurate timing
information to be extracted from the clock input. Increasing the
delay of the HLD block results in the clock input being sampled
later in its cycle. Increasing the delay of the SET block results in
the clock input being sampled earlier in its cycle. The result of
this sampling is stored and can be queried by reading the SEEK
bit. Because DSS and the clock input signal are the same
frequency, the SEEK bit must be a constant value. By varying
the SET and HLD delay blocks and seeing the effect on the
SEEK bit, the setup-and-hold timing of DSS with respect to
clock input (and, hence, data) can be measured.
In addition to properly positioning the DSS edges, maximizing
the opening of the eye in the clock input (DCIP/DCIN) and
data signals improves the reliability of the data port interface.
The two sources of degradation that reduce the eye in the clock
input and data signals are the jitter on these signals and the
skew between them. Therefore, it is recommended that the clock
input signals be generated in the same manner as the data
signals with the same output driver and data line routing. In
other words, it must be implemented as a 17th data line with an
alternating (010101 …) bit sequence.
Before outlining the procedure for determining the delay for
SMP (that is, the positioning of DSS with respect to the data
signals), it is worthwhile to describe the simplified block
diagram of the digital data port. As can be seen in Figure 57, the
data signals are sampled on the rising and falling edges of DSS.
From there, the data is demultiplexed and retimed before being
sent to the DACs.
DATA
I0
Q0
I1
Q1
I2
Q2
DCIP/DCIN
tHLD0
I DAC
FF
FF
SET_DLY
HLD_DLY
DSS
SAMPLE 1
Q DAC
DDCI
FF
SEEK
DDSS
SMP_DLY
CLK
CLOCK
DISTRIBUTION
DCOP/DCON
Figure 56. Digital Data Port Block Diagram
SAMPLE 2
SAMPLE 3
SAMPLE 4
SAMPLE 5
SAMPLE 6
Figure 57. Timing Diagram of Parallel Interface
06936-071
DCIP/DCIN
DSS
RETIMING
AND
DEMUX
06936-072
tHLD0
D15:D0
The incremental units of SET, HLD, and SMP are in units of
real time, not fractions of a clock cycle. The nominal step size
for SET and HLD is 80 ps. The nominal step size for SMP is
160 ps. Note that the value of SMP refers to Register 0x05,
Bits[4:0], SET refers to Register 0x04, Bits[7:4], and HLD refers
to Register 0x04, Bits[3:0].
A procedure for configuring the device to ensure valid sampling
of the data signals follows. Generally speaking, the procedure
begins by building an array of setup-and-hold values as the sample
delay is swept through a range of values. Based on this information, a value of SMP is programmed to establish an optimal
sampling point. This new sampling point is then double-checked
to verify that it is optimally set.
Rev. C | Page 25 of 32
AD9780/AD9781/AD9783
Data Sheet
Building the Array
The following procedure is used to build the array:
1.
2.
3.
4.
5.
6.
Set the values of SMP, SET, and HLD to 0. Read and record
the value of the SEEK bit.
With SMP and SET set to 0, increment the HLD value until
the SEEK bit toggles, and then record the HLD value. This
measures the hold time as shown in Figure 57.
With SMP and HLD set to 0, increment the SET value until
the SEEK bit toggles, and then record the SET value. This
measures the setup time as shown in Figure 57.
Set the value of SET and HLD to 0. Increment the value of
SMP and record the value of the SEEK bit.
Increment HLD until the SEEK bit toggles, and then record
the HLD value. Set HLD to 0 and increment SET until the
SEEK bit toggles, and then record the SET value.
Repeat Step 4 and Step 5 until the procedure has been
completed for SMP values from 0 to 31.
Note that while building the table, a value for either SET or
HLD may not be found to make the SEEK bit toggle. In this
case, assume a value of 15.
fDACCLK = 400 MHz
As may be seen in Table 14, at 500 MHz the device has only two
working SMP settings. There is no way to monitor timing
margin in real time, so the output must be interrupted to check
or correct timing errors. The device must not be clocked above
500 MHz in applications where 100% up time is a requirement.
Determining the SMP Value
Once the timing data array has been built, the value of SMP can
be determined using the following procedure:
1.
2.
Table 14. Timing Data Arrays
fDACCLK = 200 MHz
Table 14 shows example arrays taken at DAC sample rates of
200 MHz, 400 MHz, and 500 MHz. It must be noted that the
delay from the DCO input to the DCI output of the data source
has a profound effect on when the SEEK bit toggles over the
range of SMP values. Therefore, the tables generated in any
particular system do not necessarily match the example timing
data arrays in Table 14.
fDACCLK = 500 MHz
SMP
SEEK
SET
HLD
SEEK
SET
HLD
SEEK
SET
HLD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
6
8
10
12
15
15
15
15
15
15
15
15
15
1
4
6
8
10
12
13
15
15
15
15
15
15
15
15
1
1
1
1
15
15
15
15
15
13
11
9
7
5
3
1
0
15
15
15
15
15
15
15
13
11
9
7
5
3
1
0
15
15
15
15
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
2
4
6
8
10
12
14
1
3
4
6
8
10
12
0
2
4
6
7
9
11
13
15
2
4
6
8
9
11
11
11
11
13
11
9
7
4
2
1
13
11
9
7
5
3
1
15
13
11
9
7
5
3
1
0
11
9
7
5
3
2
2
2
2
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
2
3
5
8
10
1
2
4
7
9
1
2
4
6
9
11
1
3
5
7
9
1
2
4
7
9
10
1
1
1
1
11
9
7
5
2
1
9
7
4
2
1
10
8
7
4
2
0
8
7
5
2
1
10
8
6
4
2
0
8
8
8
8
3.
4.
Look for the SMP value that corresponds to the 0-to-1
transition of the SEEK bit in the table. In the 500 MHz case
from Table 14, this occurs for an SMP value of 6.
Look for the SMP value that corresponds to the 1-to-0
transition of the SEEK bit in the table. In the 500 MHz case
from Table 14, this occurs for an SMP value of 11.
The same two values found in Step 1 and Step 2 indicate
the valid sampling window. In the 500 MHz case, this
occurs for an SMP value of 11.
The optimal SMP value in the valid sampling window is
where the following two conditions are true: SET < HLD
and |HLD − SET| is the smallest value.
In the 500 MHz case, the optimal SMP value is 7.
After programming the calculated value of SMP (referred to as
SMPOPTIMAL), the configuration must be tested to verify that
there is sufficient timing margin. This can be accomplished by
ensuring that the SEEK bit reads back as a 1 for SMP values
equal to SMPOPTIMAL + 1 and SMPOPTIMAL − 1. Also, it can be
noted that the sum of SET and HLD must be a minimum of 8. If
the sum is lower than this, you must check for excessive jitter on
the clock input line and check that the frequency of the clock
input does not exceed the data sheet maximum of 500 MHz (or
1000 Mbps).
As mentioned previously, low jitter and skew between the input
data bits and DCI are critical for reliable operation at the maximum input data rates. Figure 58 shows the eye diagram for the
input data signals that were used to collect the data in Table 14.
Rev. C | Page 26 of 32
Data Sheet
AD9780/AD9781/AD9783
DRIVING THE CLK INPUT
The CLK input requires a low jitter differential drive signal. It is
a PMOS input differential pair powered from the 1.8 V supply;
therefore, it is important to maintain the specified 400 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p about the 400 mV common-mode
voltage. CLK can be driven by an offset ac-coupled signal, as
shown in Figure 59.
V1: 296mV
V2: –228mV
ΔV: –524mV
1
0.1µF
P_IN
CLKP
06936-076
50Ω
VCM = 400mV
50Ω
58mV
N_IN
Over temperature, the valid sampling window shifts. Therefore,
when attempting operation of the device over 500 MHz, the
timing must be optimized again whenever the device undergoes
a temperature change of more than 20oC. Another consideration
in the timing of the digital data port is the propagation delay
variation from the clock output (DCOP/DCON) to the clock
input. If this varies significantly over time (more than 25% of
SET or HLD) due to temperature changes or other effects,
repeat this timing calibration procedure.
At sample rates of ≤400 MSPS, the interface timing margin is
sufficient to allow for a simplified procedure. In this case, the
SEEK bit can be recorded as SMP is swept through the range
from 0 to 31. The center of the first valid sampling window can
then be chosen as the optimal value of SMP. Using the 400 MHz
case from Table 14 as an example, the first valid sampling
window occurs for SMP values of 7 to 13. The center of this
window is 10, so 10 can be used as the optimal SMP value.
BIST OPERATION
CLKN
0.1µF
Figure 58. Eye Diagram of Data Source Used in Building the 500 MHz Timing
Data Array of Table 14
Figure 59. DAC CLK Drive Circuit
If a clean sine clock is available, it can be transformer-coupled
to CLKP and CLKN as shown in Figure 60. Use of a CMOS or
TTL clock is also acceptable for lower sample rates. It can then
be ac-coupled, as described in this section. Alternatively, it can
be transformer-coupled and clamped, as shown in Figure 60.
TTL OR CMOS
CLK INPUT
0.1µF
50Ω
CLKP
CLKN
50Ω BAV99ZXCT
HIGH SPEED
DUAL DIODE
VCM = 400mV
06936-057
A CH1
06936-056
125ps/DIV 2.12ns
20GSPS IT 2.5ps/PT
Figure 60. TTL or CMOS DAC CLK Drive Circuit
A simple bias network for generating the 400 mV commonmode voltage is shown in Figure 61. It is important to use
CVDD18 and CGND for the clock bias circuit. Any noise or
other signal coupled onto the clock is multiplied by the DAC
digital input signal and can degrade the DAC’s performance.
The BIST feature in the AD9780/AD9781/AD9783 is a simple
type adder and is a user synchronizable BIST feature. In
Register 0x1A, write 0x20 then 0x00 to clear the BIST registers
while writing zeros to the data bits for at least eight clock cycles
to propagate to the BIST signature module. Then enable BIST
by writing 0x80 to Register 0x1A. Next, begin writing a known
set of vectors to the data inputs. Proceed by writing zeros into
the bits after the vectors while the BIST read is being performed.
Perform a BIST read by writing 0xC0 to Register 0x1A to
receive the unique sum of rising edge data in Register 0x1B
and Register 0x1C and a unique sum of falling edge data in
Register 0x1D and Register 0x1E. These register contents must
always give the same values for the same vectors
each time they are sent.
Rev. C | Page 27 of 32
VCM = 400mV
CVDD18
1kΩ
1nF
287Ω
0.1µF
1nF
CGND
Figure 61. DAC CLK VCM Generator Circuit
06936-058
CH1 100mV
AD9780/AD9781/AD9783
Data Sheet
FULL-SCALE CURRENT GENERATION
The current output appearing at IOUTP and IOUTN is a function of
both the input code, and IFS and can be expressed as
Internal Reference
Full-scale current on the I DAC and Q DAC can be set from
8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is
used to set up a current in an external resistor connected to
FS ADJ (Pin 54). A simplified block diagram of the reference
circuitry is shown in Figure 62. The recommended value for
the external resistor is 10 kΩ, which sets up an IREFERENCE in the
resistor of 120 μA, which in turn provides a DAC output fullscale current of 20 mA. Because the gain error is a linear function
of this resistor, a high precision resistor improves gain matching
to the internal matching specification of the devices. Internal
current mirrors provide a current-gain scaling, where I DAC or
Q DAC gain is a 10-bit word in the SPI port register. The default
value for the DAC gain registers gives a full-scale current output
(IFS) of approximately 20 mA, where IFS is equal to
IFS = (86.6 + (0.220 × DAC gain)) × 1000/R
AD9783
1.2V BAND GAP
I DAC GAIN
I DAC
REFIO
DAC FULL-SCALE
REFERENCE CURRENT
CURRENT
SCALING
FS ADJ
10kΩ
Q DAC
06936-059
0.1µF
Q DAC GAIN
(1)
IOUTN = ((2N − 1) − DAC DATA)/2N × IFS
(2)
where DAC DATA = 0 to 2 − 1 (decimal representation).
N
The two current outputs typically drive a resistive load directly
or via a transformer. If dc coupling is required, IOUTP and IOUTN
must be connected to matching resistive loads (RLOAD) that are tied
to analog common (AVSS). The single-ended voltage output
appearing at the IOUTP and IOUTN pins is
VOUTP = IOUTP × RLOAD
(3)
VOUTN = IOUTN × RLOAD
(4)
Note that to achieve the maximum output compliance of 1 V at
the nominal 20 mA output current, RLOAD must be set to 50 Ω.
Also note that the full-scale value of VOUTP and VOUTN must not
exceed the specified output compliance range to maintain
specified distortion and linearity performance.
There are two distinct advantages to operating the AD9780/
AD9781/AD9783 differentially. First, differential operation
helps cancel common-mode error sources associated with IOUTP
and IOUTN, such as noise, distortion, and dc offsets. Second, the
differential code-dependent current and subsequent output
voltage (VDIFF) is twice the value of the single-ended voltage
output (VOUTP or VOUTN), providing 2× signal power to the load.
VDIFF = (IOUTP – IOUTN) × RLOAD
Figure 62. Reference Circuitry
(5)
ANALOG MODES OF OPERATION
35
The AD9780/AD9781/AD9783 use a proprietary quad-switch
architecture that lowers the distortion of the DAC by eliminating a
code-dependent glitch that occurs with conventional dual-switch
architectures. This architecture eliminates the code-dependent
glitches, but creates a constant glitch at a rate of 2 × fDAC. For
communications systems and other applications requiring good
frequency domain performance from the DAC, this is seldom
problematic.
30
25
IFS (mA)
IOUTP = (DAC DATA/2N) × IFS
20
15
5
0
256
512
DAC GAIN CODE
768
1024
06936-060
10
Figure 63. IFS vs. DAC Gain Code
DAC TRANSFER FUNCTION
Each DAC output of the AD9780/AD9781/AD9783 drives two
complementary current outputs, IOUTP and IOUTN. IOUTP provides
a near IFS when all bits are high. For example,
DAC CODE = 2N − 1
The quad-switch architecture also supports two additional
modes of operation: mix mode and return-to-zero mode. The
waveforms of these two modes are shown in Figure 64. In mix
mode, the output is inverted every other half clock cycle. This
effectively chops the DAC output at the sample rate. This chopping has the effect of frequency shifting the sinc roll-off from dc
to fDAC. Additionally, there is a second subtle effect on the output
spectrum. The shifted spectrum is also shaped by a second sinc
function with a first null at 2 × fDAC. The reason for this shaping
is that the data is not continuously varying at twice the clock
rate, but is simply repeated.
where N = 12/14/16 bits for AD9780/AD9781/AD9783
(respectively), while IOUTN provides no current.
Rev. C | Page 28 of 32
Data Sheet
AD9780/AD9781/AD9783
In return-to-zero mode, the output is set to midscale every
other half clock cycle. The output is similar to the DAC output
in normal mode except that the output pulses are half the width
and half the area. Because the output pulses have half the width,
the sinc function is scaled in frequency by two and has a first
null at 2 × fDAC. Because the area of the pulses is half that of the
pulses in normal mode, the output power is half the normal
mode output power.
INPUT DATA
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10
DAC CLK
QUAD-SWITCH
DAC OUTPUT
(fS MIX MODE)
t
Auxiliary DACs
Two auxiliary DACs are provided on the AD9780/AD9781/
AD9783. A functional diagram is shown in Figure 66. The
auxiliary DACs are current output devices with two output
pins, AUXP and AUXN. The active pin can be programmed to
either source or sink current. When either sinking or sourcing,
the full-scale current magnitude is 2 mA. The available compliance
range at the auxiliary DAC outputs depends on whether the output
is configured to sink or source current. When sourcing current,
the compliance voltage is 0 V to 1.6 V, but when sinking current,
the output compliance voltage is reduced to 0.8 V to 1.6 V. Either
output can be used, but only one output of the AUX DAC (P or
N) is active at any time. The inactive pin is always in a high
impedance state (>100 kΩ).
0mA
TO
2mA
AUXP
VBIAS
QUAD-SWITCH
DAC OUTPUT
(RETURN-TOZERO MODE)
t
POSITIVE
OR
NEGATIVE
Figure 66. Auxiliary DAC Functional Diagram
Figure 64. Mix Mode and Return-to-Zero Mode DAC Waveforms
The functions that shape the output spectrums for the three
modes of operation, normal mode, mix mode, and return-tozero mode, are shown in Figure 65. Switching between the
analog modes reshapes the sinc roll-off inherent at the DAC
output. This ability to change modes in the AD9780/AD9781/
AD9783 makes the parts suitable for direct IF applications. The
user can place a carrier anywhere in the first three Nyquist
zones depending on the operating mode selected. The performance and maximum amplitude in all three Nyquist zones is
impacted by this sinc roll-off depending on where the carrier is
placed, as shown in Figure 65.
AUXN
SINK
OR
SOURCE
06936-063
06936-061
0mA
TO
2mA
In a single sideband transmitter application, the combination of
the input referred dc offset voltage of the quadrature modulator
and the DAC output offset voltage can result in local oscillator
(LO) feedthrough at the modulator output, which degrades system
performance. The auxiliary DACs can be used to remove the dc
offset and the resulting LO feedthrough. The circuit configuration for using the auxiliary DACs for performing dc offset
correction depends on the details of the DAC and modulator
interface. An example of a dc-coupled configuration with lowpass filtering is shown in Figure 67.
QUADRATURE
MODULATOR V+
0
MIX
RETURN-TO-ZERO
AD9783
AUX
DAC1 OR
DAC2
QUAD MOD
I OR Q INPUTS
NORMAL
–20
DAC1 OR
DAC2
OPTIONAL
PASSIVE
FILTERING
–30
25Ω TO 50Ω
25Ω TO 50Ω
06936-064
AD9783
Figure 67. DAC DC-Coupled to Quadrature Modulator with a Passive DC Shift
–40
0
0.5
1.0
(fS)
1.5
2.0
06936-062
T(f) (dB)
–10
Figure 65. Transfer Function for Each Analog Operating Mode
Rev. C | Page 29 of 32
AD9780/AD9781/AD9783
Data Sheet
POWER DISSIPATION
0.50
0.45
0.45
0.40
0.40
0.35
0.35
0.30
0.25
0.20
0.25
0.20
0.15
0.15
0.10
0.10
0.05
0.05
0
0
100
200
300
400
500
CLOCK SPEED (MSPS)
0
0
100
200
300
400
500
CLOCK SPEED (MSPS)
Figure 68. Power Dissipation, I Data Only, Single DAC Mode
Figure 71. Power Dissipation, I and Q Data, Dual DAC Mode
0.200
0.200
0.175
0.175
0.150
0.150
0.125
0.125
POWER (W)
POWER (W)
0.30
06936-068
POWER (W)
0.50
06936-065
POWER (W)
Figure 68 through Figure 73 show the power dissipation of the part in single DAC and dual DAC modes.
0.100
0.075
0.100
DVDD18
0.075
DVDD18
CVDD
0.050
0.050
CVDD
100
200
300
400
500
CLOCK SPEED (MSPS)
Figure 69. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply,
I Data Only
0
0.200
0.175
0.175
0.150
0.150
AVDD33
0.100
0.075
0.050
200
0.025
300
CLOCK SPEED (MSPS)
400
500
0.125
0.100
0.075
DVDD33
0
06936-067
0
200
500
AVDD33
0.025
100
400
0.050
DVDD33
0
300
Figure 72. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply,
I and Q Data, Dual DAC Mode
0.200
0.125
100
CLOCK SPEED (MSPS)
POWER (W)
POWER (W)
0
Figure 70. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply,
I Data Only
0
100
200
300
CLOCK SPEED (MSPS)
400
500
06936-070
0
06936-066
0
06936-069
0.025
0.025
Figure 73. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply,
I and Q Data, Dual DAC Mode
Rev. C | Page 30 of 32
Data Sheet
AD9780/AD9781/AD9783
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
0.60
0.42
0.24
0.60
0.42
0.24
55
54
72 1
PIN 1
INDICATOR
PIN 1
INDICATOR
9.85
9.75 SQ
9.65
TOP VIEW
0.50
BSC
4.70
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
SEATING
PLANE
0.80 MAX
0.65 TYP
12° MAX
8.50 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.30
0.23
0.18
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4
06-07-2012-A
1.00
0.85
0.80
18
19
37
36
Figure 74. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
10 mm × 10 mm, Very Thin Quad
(CP-72-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9780BCPZ
AD9780BCPZRL
AD9781BCPZ
AD9781BCPZRL
AD9783BCPZ
AD9783BCPZRL
AD9783-DPG2-EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
72-Lead LFCSP_VQ
Evaluation Board
Z = RoHS Compliant Part.
Rev. C | Page 31 of 32
Package Option
CP-72-1
CP-72-1
CP-72-1
CP-72-1
CP-72-1
CP-72-1
AD9780/AD9781/AD9783
Data Sheet
NOTES
©2007–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06936-0-8/17(C)
Rev. C | Page 32 of 32
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