AD9806

a FEATURES Pin-Compatible with Industry Standard AD9803 18 MSPS Correlated Double Sampler (CDS) Low Noise PGA with 0 dB to 34 dB Gain Range Low Noise Clamp Circuits Analog Preblanking Function 10-Bit 18 MSPS A/D Converter AUX Input with Input Clamp and PGA Direct ADC Input with Input Clamp AUXMID Input with PGA 3-Wire Serial Interface for Digital Control Two Auxiliary 8-Bit DACs 3 V Single Supply Operation Low Power: 65 mW @ 2.7 V Supply 48-Lead LQFP Package APPLICATIONS Camcorders (8 mm and DVC) Digital Still Cameras Complete 10-Bit 18 MSPS CCD Signal Processor AD9806 PRODUCT DESCRIPTION The AD9806 is a complete analog signal processor for CCD applications. It features an 18 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area CCD arrays. The AD9806’s signal chain consists of an input clamp, correlated double sampler (CDS), digitally programmable gain amplifier (PGA), black level clamp, and 10-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input configuration, and powerdown modes. The AD9806 operates from a single 3 V power supply, typically dissipating 75 mW. Packaged in a space-saving 48-lead LQFP, the AD9806 is specified over an operating temperature range of –20°C to +85 C. FUNCTIONAL BLOCK DIAGRAM PBLK CLPOB CLAMP 0dB~34dB CCDIN CDS PGA 10 MUX CLAMP CLPDM 0dB~15dB PGA DAC1 8-BIT DAC 8-BIT DAC 10-BIT DAC CLAMP DAC2 INTF 3 3-W INTF ADCIN AUXIN AUXMID TIMING GENERATOR –4~14dB PGA VRT VRB S/H ADC DOUT AD9806 REF SHP SHD ADCCLK R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD9806–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE (For Functional Operation) Analog, Digital, Digital Driver POWER CONSUMPTION (Selected through Serial Interface D-Reg) Normal Operation (D-Reg 00) High-Speed AUX Mode (D-Reg 01) Reference Standby (D-Reg 10) Total Shut-Down Mode (D-Reg 11) MAXIMUM CLOCK RATE A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (VRT) Reference Bottom Voltage (VRB) Specifications subject to change without notice. (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.) Min –20 –65 2.7 Typ Max +85 +150 3.6 Unit °C °C V (Specified Under Each Mode of Operation) (Specified Under AUX-Mode) 5 1 (Specified Under Each Mode of Operation) 10 ± 0.5 GUARANTEED 1.0 2.0 1.0 ± 1.0 mW mW MHz Bits LSB V V V DIGITAL SPECIFICATIONS Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance (DRVDD = 2.7 V, CL = 20 pF.) Symbol VIH VIL IIH IIL CIN VOH VOL Min 2.1 0.6 10 10 10 2.2 0.5 10 10 10 10 10 Typ Max Unit V V µA µA pF V V MHz ns ns ns ns LOGIC OUTPUTS High Level Output Voltage (IOH = 2 mA) Low Level Output Voltage (IOL = 2 mA) SERIAL INTERFACE TIMING (Figure 7) Maximum SCLK Frequency SDATA to SCLK Setup SCLK to SDATA Hold SLOAD to SCLK Setup SCLK to SLOAD Hold Specifications subject to change without notice. tDS tDH tLS tLH –2– REV. 0 AD9806 CCD-MODE SPECIFICATIONS Parameter POWER CONSUMPTION VDD = 2.7 VDD = 3.0 VDD = 3.3 MAXIMUM CLOCK RATE CDS Gain Allowable CCD Reset Transient1 Max Input Range before Saturation1 PGA Gain Control Resolution Gain Range (See Figure 5a for Gain Curve) Low Gain (Code 95)2 Max Gain (1023)2 BLACK LEVEL CLAMP Clamp Level (Selected through Serial Interface E-Reg) CLP0 (E-Reg 00) CLP1 (E-Reg 01) CLP2 (E-Reg 10) CLP3 (E-Reg 11) SIGNAL-TO-NOISE RATIO3 (@ Low PGA Gain) TIMING SPECIFICATIONS Pipeline Delay Internal Clock Delay5 (tID) Inhibited Clock Period (tINHIBIT) Output Delay (tOD) Output Hold Time (tHOLD) ADCCLK, SHP, SHD Clock Period ADCCLK High-Level/Low-Level SHP, SHD Minimum Pulsewidth SHP Rising Edge to SHD Rising Edge NOTES 1 Input signal characteristics defined as follows: 4 (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = fSHP = fSHD = 18 MHz, unless otherwise noted.) Min Typ 65 75 85 18 0 500 1000 10 –1 32 0 33 +1 34 Max Unit mW mW mW MHz dB mV mV p-p Bits dB dB 32 48 64 16 74 9 3 10 14.5 6 47 20 10 20 55.6 28 14 28 16 LSB LSB LSB LSB dB Cycles ns ns ns ns ns ns ns ns 500mV TYP RESET TRANSIENT 200mV MAX OPTICAL BLACK PIXEL 2 3 4 1V MAX INPUT SIGNAL RANGE Use equations on page 8 to calculate gain. SNR = 20 log10 (Full-Scale Voltage/RMS Output Noise). 20 pF loading; timing shown in Figure 1. 5 Internal aperture delay for actual sampling edge. Specifications subject to change without notice. REV. 0 –3– AD9806–SPECIFICATIONS AUX-MODE SPECIFICATIONS Parameter POWER CONSUMPTION Normal (D-Reg 00) High-Speed (D-Reg 01) MAXIMUM CLOCK RATE Normal (D-Reg 00) High-Speed (D-Reg 01) PGA (Gain Selected through Serial Interface F-Reg) Max Input Range Max Output Range Gain Control Resolution Gain Range Min Gain (Code 128) Max Gain (Code 255) ACTIVE CLAMP Clamp Level (Selected through Serial Interface E-Reg) CLP0 (E-Reg 00) CLP1 (E-Reg 01) CLP2 (E-Reg 10) CLP3 (E-Reg 11) TIMING SPECIFICATIONS1 Pipeline Delay Internal Clock Delay (tID) Output Delay (tOD) Output Hold Time (tHOLD) NOTES 1 20 pF loading; timing shown in Figure 2. Specifications subject to change without notice. (TMIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.) Min Typ 50 95 18 28.6 700 1000 7 –2 15 Max Unit mW mW MHz MHz mV p-p mV p-p Bits dB dB 32 48 64 16 9 14.5 7 16 LSB LSB LSB LSB Cycles ns ns AUXMID-MODE SPECIFICATIONS (T Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE MIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.) Min Typ 50 18 700 1000 9 –4 14 462 512 9 14.5 7 16 562 Max Unit mW MHz mV p-p mV p-p Bits dB dB LSB Cycles ns ns PGA (Gain Selected through Serial Interface F-Reg) Max Input Range Max Output Range Gain Control Resolution Gain Range (See Figure 5b for Gain Curve) Min Gain (Code 512) Max Gain (Code 1023) MIDSCALE OFFSET LEVEL (AT MAX PGA GAIN) TIMING SPECIFICATIONS Pipeline Delay Internal Clock Delay (tID) Output Delay (tOD) Output Hold Time (tHOLD) 1 NOTES 1 20 pF loading; timing shown in Figure 2. Specifications subject to change without notice. –4– REV. 0 ADC-MODE SPECIFICATIONS (T Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE ACTIVE CLAMP TIMING SPECIFICATIONS 1 AD9806 MIN to TMAX, AVDD = DVDD = 3.0 V, fADCCLK = 18 MHz, unless otherwise noted.) Min Typ (Same as AUX-MODE) (Same as AUX-MODE) (Same as AUX-MODE) (Same as AUX-MODE) Max Unit Specifications subject to change without notice. DAC SPECIFICATIONS (DAC1 and DAC2) Parameter RESOLUTION MIN OUTPUT MAX OUTPUT MAX CURRENT LOAD MAX CAPACITIVE LOAD Specifications subject to change without notice. Min Typ 8 0.1 VDD – 0.1 1 500 Max Unit Bits V V mA pF ABSOLUTE MAXIMUM RATINGS Parameter AVDD1, AVDD2 DVDD1, DVDD2 DRVDD Digital Outputs SHP, SHD, DATACLK CLPOB, CLPDM, PBLK SCK, SL, SDATA VRT, VRB, CMLEVEL CCDIN, CLPOUT, CLPREF, CLPBYP Junction Temperature Lead Temperature (10 sec) With Respect To AVSS DVSS DRVSS DRVSS DVSS DVSS DVSS AVSS AVSS Min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Max +3.9 +3.9 +3.9 DRVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 300 Unit V V V V V V V V V °C °C ORDERING GUIDE Model AD9806KST Temperature Range –20°C to +85°C Package Description Thin Plastic Quad Flatpack (LQFP) Package Option ST-48 THERMAL CHARACTERISTICS Thermal Resistance 48-Lead LQFP Package θJA = 92°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9806 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. 0 –5– AD9806 PIN CONFIGURATION ADVSS SUBST SDATA DAC1 CMLEVEL 36 ADVDD VRB SCK VRT DAC2 48 47 46 45 44 43 42 41 40 39 38 37 NC 1 (LSB) D0 2 D1 3 D2 4 D3 5 D4 6 D5 7 D6 8 D7 9 D8 10 (MSB) D9 11 DRVDD 12 SL NC PIN 1 IDENTIFIER ADCIN AUXMID AUXIN ACVDD CLPBYP ACVSS NC NC CLPREF NC CCDIN CLPOUT 35 34 33 32 AD9806 TOP VIEW (Not to Scale) 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 NC CLPDM DRVSS ADCCLK STBY DVDD DVSS CLPOB PBLK SHP NC = NO CONNECT PIN FUNCTION DESCRIPTIONS Pin No. 1, 15, 24 2–11 12 13 14 16 17 18 19 20 21 22 23 25 26 27 28 29, 30, 38 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 47 48 Mnemonic NC D0–D9 DRVDD DRVSS DVSS ADCCLK DVDD STBY PBLK CLPOB SHP SHD CLPDM CLPOUT CCDIN NC CLPREF NC ACVSS CLPBYP ACVDD AUXIN AUXMID ADCIN CMLEVEL DAC1 DAC2 SL SCK ADVDD SDATA ADVSS SUBST VRB VRT Type DO P P P DI P DI DI DI DI DI DI AO AI AO P AO P AI AI AI AO AO AO DI DI P DI P P AO AO Description (See Figures 10 and 11 for Circuit Configurations) No Connect (Should be Left Floating or Tied to Ground) Digital Data Outputs Digital Driver Supply (3 V) Digital Driver Ground Digital Ground ADC Sample Clock Input Digital Supply (3 V) Power-Down Mode (Active High/Internal Pull-Down). Enables Reference Standby Mode. Pixel Blanking Black Level Restore Clamp CCD Reference Sample Clock Input CCD Data Sample Clock Input Input Clamp CDS Bypass (0.1 µF to Ground) CDS Input Pin (Connect to CCD Input Signal through 0.1 µF Capacitor) No Connect (Should Be Left Floating, or May Be Shorted to Pin 26) CDS Bypass (0.1 µF to Ground) No Connect (Should Be Left Floating, Tied to Ground, or Decoupled to Ground) Analog Ground CDS Bypass (0.1 µF to Ground) Analog Supply (3 V) AUX-MODE Input AUXMID-MODE Input ADC-MODE Input Common-Mode Level (0.1 µF to Ground) DAC1 Output DAC2 Output Serial I/F Load Signal Serial I/F Clock Analog Supply (3 V) Serial I/F Input Data Analog Ground Analog Ground Bottom Reference (0.1 µF to Ground and 1 µF to VRT) Top Reference (0.1 µF to Ground) NOTE Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. –6– SHD NC REV. 0 AD9806 TIMING SPECIFICATIONS CCD N N+1 N+2 N+3 N+4 SHP tID tINHIBIT SHD tID ADCCLK tOD tHOLD ADCCLK RISING EDGE PLACEMENT D0–D9 N–0 N–9 N–8 N–7 N–6 N–5 NOTES: 1. SHP AND SHD SHOULD BE OPTIMALLY ALIGNED WITH THE CCD SIGNAL. SAMPLES ARE TAKEN AT THE RISING EDGES. 2. ADCCLK RISING EDGE MUST OCCUR AT LEAST 15ns AFTER THE RISING EDGE OF SHP (tINHIBIT). 3. RECOMMENDED PLACEMENT FOR ADCCLK RISING EDGE IS BETWEEN THE RISING EDGE OF SHD AND FALLING EDGE OF SHP. 4. OUTPUT LATENCY IS 9 CYCLES. 5. ACTIVE LOW CLOCK PULSE MODE IS SHOWN. Figure 1. CCD-MODE Timing N VIDEO INPUT N+1 N+2 N+3 N+4 N+5 tOD ADCCLK tID tHOLD D0–D9 N–9 N–8 N–7 N–6 N–5 NOTE: EXAMPLE OF OUTPUT DATA LATCHED BY ADCCLK RISING EDGE. Figure 2. AUX-, AUXMID-, ADC-Mode Timing EFFECTIVE PIXELS CCD SIGNAL OPTICAL BLACK BLANKING INTERVAL DUMMY BLACK EFFECTIVE PIXELS CLPOB CLPDM PBLK NOTES: 1. CLPOB PULSEWIDTH SHOULD BE A MINIMUM OF 10 OB PIXELS WIDE, 20 OB PIXELS ARE RECOMMENDED. 2. CLPDM PULSEWIDTH SHOULD BE AT LEAST 1 s WIDE. 3. PBLK IS NOT REQUIRED, BUT RECOMMENDED IF THE CCD SIGNAL AMPLITUDE EXCEEDS 1V p-p. 4. CLPDM OVERWRITES PBLK. 5. ACTIVE LOW CLAMP PULSE MODE IS SHOWN. Figure 3. CCD-MODE Clamp Timing REV. 0 –7– AD9806 TIMING SPECIFICATIONS (Continued) VIDEO SIGNAL INPUT H SYNC INTERNAL CLAMPING OCCURS DURING SYNC CLAMP INTERVAL (AD9806 INTERNAL SIGNAL) NOTE: The AD9806 uses an “automatic” video clamp that senses the most negative in the input signal and uses this level to set the clamp voltage. As shown in the video waveform above, the SYNC level will be clamped to the black level specified in the E-Register. Figure 4. AUX-MODE and ADC-MODE Clamp Operation PGA GAIN CURVE DETAILS In CCD-Mode, the AD9806 PGA stage provides a gain range of 0 dB to 34 dB, programmable with 10-bit resolution through the serial digital interface. The PGA gain curve is divided into two separate regions. When the PGA Gain Register code is between 0, and 511, the curve follows a (1 + x)/(1 – x) shape, which is similar to a “linear-in-dB” characteristic. From Code CCD-MODE Code Range Gain Equation (dB) 0–511 Gain = 20 log10 ([658 + code]/[658 – code]) – 2.4 512–1023 Gain = (0.0354)(code) – 2.4 34 512 to Code 1023, the curve follows a “linear-in-dB” shape. In AUXMID-Mode, the PGA provides a gain range of –4 dB to +14 dB, programmable with 9-bit resolution. The exact PGA gain for either mode can be calculated for any Gain Register value by using the following equations: AUXMID-MODE Code Range Gain Equation (dB) 512–1023 Gain = 20 log10 ([146 + code]/[1170 – code]) – 4 14 28 11 PGA GAIN – dB PGA GAIN – dB 0 383 511 639 767 255 PGA GAIN REGISTER CODE 895 1023 22 8 16 5 10 2 4 –1 –2 127 –4 512 639 767 895 PGA GAIN REGISTER CODE 1023 Figure 5a. PGA Gain Curve for CCD-Mode Figure 5b. PGA Gain Curve for AUXMID-Mode 0.8V ??V 0.4V 5k –4 dB TO +14dB 0.1 F INPUT SIGNAL AUXMID PIN 35 PGA ADC MIDSCALE 0.4V 0.4V 9 PGA GAIN REGISTER Figure 6. AUXMID-Mode Circuit Block Diagram –8– REV. 0 AD9806 SERIAL INTERFACE SPECIFICATIONS SDATA A0 SELECT e0 MODES 1 0 0 CLAMP LEVEL f0 PGA 0 1 0 PGA GAIN LEVEL SELECTION g0 DAC1 1 1 0 DAC1 INPUT h0 DAC2 0 0 1 DAC2 INPUT m0 MODES21 1 1 1 DON'T CARE OPERATION AND POWER-DOWN MODES 0* j0 h1 h2 h3 h4 h5 h6 h7 g1 g2 g3 g4 g5 g6 g7 f1 e1 d0 d1 c0 CLOCK MODES f4 f5 f6 c1 b0 OUTPUT MODES f7 b1 a0 a1 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 POWER-DOWN MODES f2 f3 OPERATION MODES f8 f9 SELECT SHIFT REGISTER a0–a1 A-REG b0–b1 B-REG c0–c1 C-REG d0–d1 D-REG e0–e1 E-REG f0–f9 F-REG (a) OPERATION MODES g0–g7 G-REG (b) OUTPUT MODES h0–h7 H-REG (c) CLOCK MODES j0 J-REG (d) POWER-DOWN MODES (e) CLAMP LEVEL (f) PGA GAIN m0 M-REG (g) DAC1 INPUT (h) DAC2 INPUT (j) EVEN-ODD OFFSET CORRECTION (m) DAC1 AND DAC2 POWER-DOWN *NOTE: MODES2 REGISTER BIT D1 MUST BE SET TO ZERO Figure 7. AD9806 Internal Register Map SDATA RNW A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 RISING EDGE TRIGGERED SCK tDH tDS tLS SL tLH REGISTER LOADED ON RISING EDGE Figure 8. Serial WRITE Operation DUMMY BITS IGNORED SDATA RNW A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 XX XX SCK SL Figure 9. 16-Bit Serial WRITE Operation REV. 0 –9– AD9806 REGISTER DESCRIPTION (a) A-REGISTER: Modes of Operation (Power-On Default Value = 11) f) F-REGISTER: AUXMID-Mode PGA (Default = 00 . . . 0) f 9 f8 f 7 f 6 f5 f 4 f 3 f 2 f 1 f 0 AUXMID–Gain Gain (512) 1 0 0 0 0 0 0 0 0 0 Gain (1023) 1 1 1 1 1 1 1 1 1 1 –4 dB +14 dB a1 0 0 1 1 a0 0 1 0 1 Modes ADC-MODE AUX-MODE AUXMID-MODE CCD-MODE (Default = 00) Only the 9 LSBs of F-REG are used to adjust gain. (f) F-REGISTER: AUX-Mode PGA (Default = 00 . . . 0) f 9 f8 f 7 f 6 f5 f 4 f 3 f 2 (b) B-REGISTER: Output Modes AUX-Gain Minimum Maximum (Default = 00 . . . 0) b1 0 0 1 1 b0 0 1 0 1 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Normal 0101 1010 High Impedance 0 1 1 0 0 1 1 0 0 1 1 0 Gain (128) 1 0 0 0 0 0 0 0 Gain (255) 1 1 1 1 1 1 1 1 (g) G-REGISTER: DAC1 Input g7 g6 g5 g4 g3 g2 g1 g0 Code (0) 00000000 Code (255) 1 1 1 1 1 1 1 1 (h) H-REGISTER: DAC2 Input DAC1 Output Minimum Maximum (Default = 00 . . . 0) (c) C-REGISTER: Clock Modes (Default = 00) c1 c0 0 0 1 1 0 1 0 1 SHP-SHD Clock Pulses Active Low Active Low Active High Active High Clamp Active Pulses Active Low Active High Active Low Active High (Default = 00) h7 h6 h5 h4 h3 h2 h1 h0 Code (0) 00000000 Code (255) 1 1 1 1 1 1 1 1 DAC2 Output Minimum Maximum (Default = 0) (d) D-REGISTER: Power-Down Modes (j) J-REGISTER: Even-Odd Offset Correction Modes Normal High Speed Power-Down1 Power-Down2 d1 0 0 1 1 d0 Description 0 1 0 1 Normal Operation High-Speed AUX/ADC-MODE Reference Stand-By (Same Mode as STBY Pin 18) Total Shut-Down (Default = 00) j0 0 1 Even-Odd Offset Correction Offset Correction In Use Offset Correction Not Used (Default = 0) (m) M-REGISTER: DAC1 and DAC2 PDN m0 (e) E-REGISTER: Clamp Level Selection Power-Down of 8-Bit DACs 8-Bit DACs Powered Down 8-Bit DACs Operational e1 CLP (0) CLP (1) CLP (2) CLP (3) 0 0 1 1 e0 0 1 0 1 Clamp Level 32 LSBs 48 LSBs 64 LSBs 16 LSBs (Default = 00 . . . 0) 0 1 (f) F-REGISTER: CCD-Mode PGA f 9 f8 f 7 f6 f5 f4 f 3 f 2 f 1 f 0 Gain (0) 00 Gain (1023) 1 1 0000 1111 000 111 0 1 CCD–Gain Minimum Maximum NOTE: With the exception of a write to the PGA register during AUX-mode, all data writes must be 10 bits. During an AUX-mode write to the PGA register, only 8 bits of data are required. If more than 14 SCK rising edges are applied during a write operation, additional SCK pulses will be ignored (see Figure 9). All reads must be 10 bits to receive valid register contents. All registers default to 0s on power-up, except for the A-register which defaults to 11. Thus, on power-up, the AD9806 defaults to CCD mode with the 8-bit DACs powered down. During the power-up phase, it is recommended that SL be HIGH and SCK be LOW to prevent accidental register write operations. SDATA may be unknown. The RNW bit (“Read/Not Write”) must be LOW for all write operations to the serial interface, and HIGH when reading back from the serial interface registers. –10– REV. 0 AD9806 APPLICATION INFORMATION Grounding and Decoupling Recommendations Table I. AD9806/AD9803 Pin Differences As shown in Figure 10, a single ground plane is recommended for the AD9806. This ground plane should be as continuous as possible, particularly around Pins 25 through 37. This will ensure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. All decoupling capacitors should be located as close as possible to the package pins. A single clean power supply is recommended for the AD9806, but a separate digital driver supply may be used for DRVDD (Pin 12). DRVDD should always be decoupled to DRVSS (Pin 13), which should be connected to the analog ground plane. The advantages of using a separate digital driver supply include using a lower voltage (2.7 V) to match levels with a 2.7 V ASIC, reducing digital power dissipation, and reducing potential noise coupling. Using the AD9806 in AD9803 Sockets Pin No. 1 15 24 25 27 28 29 30 35 38 AD9803 NC ACLP NC CCDBYP2 PIN CCDBYP2 PGABYP1 PGABYP2 AUXCONT VTRBYP AD9806 NC NC NC CLPOUT NC CLPREF NC NC AUXMID NC Circuit Connection Ground Ground Ground Decoupled with 0.1 µF to Ground Shorted to Pin 26 Decoupled with 0.1 µF to Ground Decoupled with 0.1 µF to Ground Shorted to Pin 29 Ground, or decoupled with 0.1 µF to Ground Decoupled with 0.1 µF to Ground The AD9806 may be easily used in existing AD9803 designs without any circuit modifications. Most of the pin assignments are the same for both ICs. Table I outlines the differences. The circuit of Figure 10 shows the necessary connections for the AD9806 when used in an existing AD9803 socket. If the two auxiliary DACs are not used, then Pins 39 and 40 (DAC1 and DAC2) may be grounded. If the AUX or ADC modes are needed, then the input signal should be connected to either AUXIN or ADCIN through a 0.1 µF capacitor, in the same way that CCDIN is used with the input signal. Using the AD9806 in New Designs Figure 11 shows the recommended circuit for using the AD9806 in new designs. Three external decoupling capacitors have been removed from the circuit shown in Figure 9, one from Pin 29, one from Pin 38, and one from between Pins 47 and 48. Note that the decoupling capacitors for Pins 47 (VRB) and 48 (VRT) must be increased to 1.0 µF when used in this configuration. SDATA SCK SL VOUT2 VOUT1 0.1 F VDD 0.1 F 0.1 F 0.1 F 1.0 F 0.1 F 48 47 46 45 44 43 42 41 40 39 38 37 SDATA SUBST VRT ADVSS ADVDD DAC2 DAC1 VRB SCK NC SL CMLEVEL VDD ADCIN 36 AUXMID 35 AUXIN 34 ACVDD 33 CLPBYP 32 ACVSS 31 0.1 F 0.1 F 1 2 3 4 5 6 7 8 9 NC D0 (LSB) D1 D2 D3 D4 D5 D6 D7 AD9806 NC 30 NC 29 CLPREF 28 NC 27 DIN 26 CLPOUT 25 0.1 F CCD SIGNAL INPUT 0.1 F 10 D8 ADCCLK DRVSS PBLK CLPDM CLPOB DIGITAL OUTPUT DATA 11 D9 (MSB) 12 DRVDD 0.1 F DVSS DVDD STBY SHP SHD NC NC 0.1 F VDD 0.1 F VDD 13 14 15 16 17 18 19 20 21 22 23 24 0.1 F NC = NO CONNECT CLPDM SHD SHP CLPOB PBLK ADCCLK Figure 10. CCD-Mode Circuit Configuration Used in AD9803 Socket REV. 0 –11– AD9806 SDATA VDD 0.1 F 1.0 F 1.0 F 48 47 46 45 44 43 42 41 40 39 38 37 SCK SL VOUT2 VOUT1 1 2 3 4 5 6 7 8 9 NC D0 (LSB) D1 D2 D3 D4 D5 D6 D7 ADCIN 36 AUXMID 35 AUXIN 34 ACVDD 33 CLPBYP 32 ACVSS 31 0.1 F VDD 0.1 F AD9806 NC 30 NC 29 CLPREF 28 NC 27 DIN 26 CLPOUT 25 0.1 F CCD SIGNAL INPUT 0.1 F 10 D8 ADCCLK DRVSS PBLK CLPDM CLPOB DIGITAL OUTPUT DATA 11 D9 (MSB) 12 DRVDD DVSS DVDD STBY SHP SHD NC NC 0.1 F 0.1 F VDD 13 14 15 16 17 18 19 20 21 22 23 24 VDD 0.1 F NC = NO CONNECT CLPDM SHD SHP CLPOB PBLK ADCCLK Figure 11. CCD-Mode Circuit Configuration Using Minimum External Components OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead, LQFP (ST-48) 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.354 (9.00) BSC SQ 48 1 37 36 TOP VIEW (PINS DOWN) COPLANARITY 0.003 (0.08) 0.008 (0.2) 0.004 (0.09) 0 MIN 12 13 24 25 0.019 (0.5) BSC 7 0 0.011 (0.27) 0.006 (0.17) 0.057 (1.45) 0.053 (1.35) 0.006 (0.15) SEATING 0.002 (0.05) PLANE –12– REV. 0 PRINTED IN U.S.A. 0.276 (7.00) BSC SQ C02197–2.5–1/01 (rev. 0) 0.1 F SDATA SUBST VRT ADVSS ADVDD DAC2 DAC1 VRB SCK NC SL CMLEVEL