AD9826KRS

a FEATURES 16-Bit 15 MSPS A/D Converter 3-Channel 16-Bit Operation up to 15 MSPS 1-Channel 16-Bit Operation up to 12.5 MSPS 2-Channel Mode for Mono Sensors with Odd/Even Outputs Correlated Double Sampling 1~6 Programmable Gain 300 mV Programmable Offset Input Clamp Circuitry Internal Voltage Reference Multiplexed Byte-Wide Output Optional Single Byte Output Mode 3-Wire Serial Digital Interface 3 V/5 V Digital I/O Compatibility 28-Lead SSOP Package Low Power CMOS: 400 mW (Typ) Power-Down Mode Available APPLICATIONS Flatbed Document Scanners Digital Copier Multifunction Peripherals Infrared Imaging Applications Machine Vision Complete 16-Bit Imaging Signal Processor AD9826 PRODUCT DESCRIPTION The AD9826 is a complete analog signal processor for imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC, and Programmable Gain Amplifier (PGA), multiplexed to a high-performance 16-bit A/D converter. The AD9826 can operate at speeds greater than 15 MSPS with reduced performance. The CDS amplifiers may be disabled for use with sensors that do not require CDS, such as Contact Image Sensors (CIS), CMOS active pixel sensors, and Focal Plane Arrays. The 16-bit digital output is multiplexed into an 8-bit output word, which is accessed using two read cycles. There is an optional single byte output mode. The internal registers are programmed through a 3-wire serial interface, and provide adjustment of the gain, offset, and operating mode. The AD9826 operates from a single 5 V power supply, typically consumes 400 mW of power, and is packaged in a 28-lead SSOP. FUNCTIONAL BLOCK DIAGRAM AVDD AVSS CML CAPT CAPB AVDD AVSS DRVDD DRVSS VINR CDS 9-BIT DAC PGA BANDGAP REFERENCE AD9826 OEB VING CDS 9-BIT DAC PGA 3:1 MUX 16-BIT ADC 16 16:8 MUX 8 DOUT CONFIGURATION REGISTER PGA MUX REGISTER 6 RED GREEN BLUE DIGITAL CONTROL INTERFACE SCLK SLOAD SDATA VINB CDS 9-BIT DAC OFFSET INPUT CLAMP BIAS 9 RED GREEN BLUE GAIN REGISTERS OFFSET REGISTERS ADCCLK CDSCLK1 CDSCLK2 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001 AD9826–SPECIFICATIONS ANALOG SPECIFICATIONS Parameter MAXIMUM CONVERSION RATE 3-Channel Mode with CDS 2-Channel Mode with CDS 1-Channel Mode with CDS ACCURACY (ENTIRE SIGNAL PATH) ADC Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes ANALOG INPUTS Input Signal Range (Programmable)1 Allowable Reset Transient1 Input Limits2 Input Capacitance Input Bias Current AMPLIFIERS PGA Gain PGA Gain Resolution2 PGA Gain Monotonicity Programmable Offset Programmable Offset Resolution Programmable Offset Monotonicity NOISE AND CROSSTALK Total Output Noise @ PGA Minimum Total Output Noise @ PGA Maximum Channel-to-Channel Crosstalk @ 15 MSPS @ 6 MSPS POWER SUPPLY REJECTION AVDD = 5 V 0.25 V DIFFERENTIAL VREF (at 25°C) CAPT–CAPB TEMPERATURE RANGE Operating Storage POWER SUPPLIES AVDD DRVDD OPERATING CURRENT AVDD DRVDD Power-Down Mode POWER DISSIPATION 3-Channel Mode 1-Channel Mode –40 –65 4.75 3.0 5.0 5.0 75 5 200 400 300 (TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA Gain = 1, Input range = 4 V p-p, unless otherwise noted.) Min Typ 30 30 18 16 ± 16 ± 0.5 Guaranteed 2.0/4.0 1.0 AVSS – 0.3 10 10 1 64 Guaranteed –300 512 Guaranteed 3.0 9.0 70 90 0.1 2.0 +85 +150 5.25 5.25 +300 6 AVDD + 0.3 Max Unit MSPS MSPS MSPS Bits LSB LSB V p-p V V pF nA V/V Steps mV Steps LSB rms LSB rms dB dB % FSR V °C °C V V mA mA µA mW mW NOTES 1 Linear Input Signal Range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9826’s input clamp. 4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE) 1V TYP RESET TRANSIENT 4V p-p MAX INPUT SIGNAL RANGE GND 2 The PGA Gain is approximately “linear in dB” and follows the equation: Gain = 1 + 5.0 6.0  63 – G   63    where G is the register value. Specifications subject to change without notice. – 2– REV. A AD9826 DIGITAL SPECIFICATIONS Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage Low Level Output Voltage High Level Output Current Low Level Output Current LOGIC OUTPUTS (with DRVDD = 3 V) High Level Output Voltage, (IOH = 50 µA) Low Level Output Voltage (IOL = 50 µA) Specifications subject to change without notice. (TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS Mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, CL = 10 pF, unless otherwise noted.) Symbol VIH VIL IIH IIL CIN VOH VOL IOH IOL VOH VOL Min 2.0 0.8 10 10 10 4.5 0.1 50 50 2.95 0.05 Typ Max Unit V V µA µA pF V V µA µA V V TIMING SPECIFICATIONS (T Parameter MIN to TMAX, AVDD = 5 V, DRVDD = 5 V, specs are for 16-bit performance.) Symbol tPRA tPRB tADCLK tC1 tC2 tC1C2 tADC2 tC2ADR tC2ADF tC2C1 tAD fSCLK tLS tLH tDS tDH tRDV tOD tDV tHZ Min 200 80 30 8 8 0 0 5 30 5 2 10 10 10 10 10 10 6 10 10 3 (Fixed) Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns Cycles CLOCK PARAMETERS 3-Channel Pixel Rate 1-Channel Pixel Rate ADCCLK Pulsewidth CDSCLK1 Pulsewidth CDSCLK2 Pulsewidth CDSCLK1 Falling to CDSCLK2 Rising ADCCLK Falling to CDSCLK2 Rising CDSCLK2 Rising to ADCCLK Rising CDSCLK2 Falling to ADCCLK Falling CDSCLK2 Falling to CDSCLK1 Rising Aperture Delay for CDS Clocks SERIAL INTERFACE Maximum SCLK Frequency SLOAD to SCLK Set-Up Time SCLK to SLOAD Hold Time SDATA to SCLK Rising Set-Up Time SCLK Rising to SDATA Hold Time SCLK Falling to SDATA Valid DATA OUTPUTS Output Delay 3-State to Data Valid Output Enable High to 3-State Latency (Pipeline Delay) NOTES It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge. Specifications subject to change without notice. REV. A – 3– AD9826 ABSOLUTE MAXIMUM RATINGS * With Respect To Min Max AVSS AVSS AVSS DRVSS DRVSS DRVSS –0.3 –0.3 –0.5 –0.5 –0.3 –0.3 –65 AVDD + 0.3 AVDD + 0.3 +6.5 +6.5 +0.3 DRVDD + 0.3 150 +150 300 ORDERING GUIDE Parameter VIN, CAPT, CAPB Digital Inputs AVDD DRVDD AVSS Digital Outputs Junction Temperature Storage Temperature Lead Temperature (10 sec) Unit V V V V V V °C °C °C Model AD9826KRS Temperature Range –40°C to +85°C Package Description 5.3 mm SSOP Package Option RS-28 THERMAL CHARACTERISTICS Thermal Resistance 28-Lead 5.3 mm SSOP θJA = 109°C/W θJC = 39°C/W *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9826 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE –4– REV. A AD9826 PIN CONFIGURATION CDSCLK1 1 CDSCLK2 ADCCLK OEB DRVDD DRVSS (MSB) D7 D6 D5 2 3 4 5 6 7 28 AVDD 27 AVSS 26 VINR 25 OFFSET 24 VING 22 VINB TOP VIEW 8 (Not to Scale) 21 CAPT 9 20 CAPB 19 AVSS 18 AVDD 17 SLOAD 16 SCLK 15 SDATA AD9826 23 CML D4 10 D3 11 D2 12 D1 13 (LSB) D0 14 PIN FUNCTION DESCRIPTIONS Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18, 28 19, 27 20 21 22 23 24 25 26 Mnemonic CDSCLK1 CDSCLK2 ADCCLK OEB DRVDD DRVSS D7 D6 D5 D4 D3 D2 D1 D0 SDATA SCLK SLOAD AVDD AVSS CAPB CAPT VINB CML VING OFFSET VINR Type DI DI DI DI P P DO DO DO DO DO DO DO DO DI/DO DI DI P P AO AO AI AO AI AO AI Description CDS Reference Level Sampling Clock CDS Data Level Sampling Clock A/D Converter Sampling Clock Output Enable, Active Low Digital Output Driver Supply Digital Output Driver Ground Data Output MSB. ADC DB15 High Byte, ADC DB7 Low Byte Data Output. ADC DB14 High Byte, ADC DB6 Low Byte Data Output. ADC DB13 High Byte, ADC DB5 Low Byte Data Output. ADC DB12 High Byte, ADC DB4 Low Byte Data Output. ADC DB11 High Byte, ADC DB3 Low Byte Data Output. ADC DB10 High Byte, ADC DB2 Low Byte Data Output. ADC DB9 High Byte, ADC DB1 Low Byte Data Output LSB. ADC DB8 High Byte, ADC DB0 Low Byte Serial Interface Data Input/Output Serial Interface Clock Input Serial Interface Load Pulse 5 V Analog Supply Analog Ground ADC Bottom Reference Voltage Decoupling ADC Top Reference Voltage Decoupling Analog Input, Blue Channel Internal Bias Level Decoupling Analog Input, Green Channel Clamp Bias Level Decoupling Analog Input, Red Channel TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. REV. A –5– AD9826 DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) INPUT REFERRED NOISE Integral nonlinearity error refers to the deviation of each individual code from a line drawn from “zero scale” through “positive full scale.” The point used as “zero scale” occurs 1/2 LSB before the first code transition. “Positive full scale” is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. DIFFERENTIAL NONLINEARITY (DNL) The rms output noise is measured using histogram techniques. The ADC output codes’ standard deviation is calculated in LSB, and can be converted to an equivalent voltage, using the relationship 1 LSB = 4 V/65536 = 61 µV. The noise may then be referred to the input of the AD9826 by dividing by the PGA gain. CHANNEL-TO-CHANNEL CROSSTALK An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 16-bit resolution indicates that all 65536 codes, respectively, must be present over all operating ranges. OFFSET ERROR In an ideal 3-channel system, the signal in one channel will not influence the signal level of another channel. The channel-tochannel crosstalk specification is a measure of the change that occurs in one channel as the other two channels are varied. In the AD9826, one channel is grounded and the other two channels are exercised with full scale input signals. The change in the output codes from the first channel is measured and compared with the result when all three channels are grounded. The difference is the channel-to-channel crosstalk, stated in LSB. APERTURE DELAY The first ADC code transition should occur at a level 1/2 LSB above the nominal zero scale voltage. The offset error is the deviation of the actual first code transition level from the ideal level. GAIN ERROR The last code transition should occur for an analog value 1 1/2 LSB below the nominal full scale voltage. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. The aperture delay is the time delay that occurs from when a sampling edge is applied to the AD9826 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low, so the aperture delay is measured from each clock’s falling edge to the instant the actual internal sample is taken. POWER SUPPLY REJECTION Power supply rejection specifies the maximum full-scale change that occurs from the initial value when the supplies are varied over the specified limits. –6– REV. A Typical Performance Characteristics–AD9826 20 1.0 10 0.5 0 0 –10 –0.5 –20 0 12000 –1.0 24000 36000 48000 64000 0 200 400 600 800 1000 TPC 1. Typical INL Performance at 15 MSPS TPC 4. Typical INL Performance at 30 MSPS 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 0 12000 24000 36000 48000 –1.0 64000 0 200 400 600 800 1000 TPC 2. Typical DNL Performance at 15 MSPS TPC 5. Typical DNL Performance at 30 MSPS 10 10 NOISE – LSB RMS 5 NOISE – LSB RMS 5 0 0 15 30 GAIN SETTING 45 63 0 0 15 30 GAIN SETTING 45 63 TPC 3. Output Noise vs. Gain TPC 6. Input Referred Noise vs. Gain REV. A –7– AD9826 TIMING DIAGRAMS ANALOG INPUTS tAD PIXEL n (R,G,B) tAD PIXEL (n+1) PIXEL (n+2) tC1 tC2C1 tPRA CDSCLK1 tC1C2 CDSCLK2 tC2 tC2ADF tADCLK ADCCLK tADC2 tC2ADR tADCLK OUTPUT DATA D R(n–2) G(n–2) HIGH BYTE G(n–2) LOW BYTE B(n–2) HB B(n–2) LB R(n–1) HB R(n–1) LB tOD G(n–1) HB G(n–1) LB B(n–1) HB B(n–1) LB R(n) HB R(n) LB G(n) HB G(n) LB Figure 1. 3-Channel CDS Mode Timing It is recommended that CDSCLK falling edges do not occur within the first 10 ns following an ADCCLK edge. ANALOG INPUTS tAD PIXEL n PIXEL (n+1) tAD PIXEL (n+2) tC1 tC2C1 tPRB CDSCLK1 tC1C2 tC2 CDSCLK2 tC2ADR tC2ADF ADCCLK tADCLK OUTPUT DATA D PIXEL (n–4) HIGH BYTE PIXEL (n–4) LOW BYTE PIXEL (n–3) HIGH BYTE tADCLK tOD PIXEL (n–3) LOW BYTE PIXEL (n–2) HIGH BYTE PIXEL (n–2) LOW BYTE NOTE IN 1-CHANNEL CDS MODE, THE CDSCLK1 FALLING EDGE AND THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.” Figure 2. 1-Channel CDS Mode Timing –8– REV. A AD9826 ANALOG INPUTS tAD PIXEL n tAD tC1 tC2C1 PIXEL (n+1) PIXEL (n+2) tPRA CDSCLK1 tC1C2 tC2 CDSCLK2 tC2ADR tADC2 ADCCLK tADCLK OUTPUT DATA D CH1(n–2) HIGH BYTE LOW BYTE tADCLK CH2(n–2) HIGH BYTE LOW BYTE CH1(n–1) HIGH BYTE LOW BYTE CH2(n–1) HIGH BYTE LOW BYTE CH1(n) HIGH BYTE LOW BYTE tC2ADF Figure 3. 2-Channel CDS Mode Timing PIXEL (n+1) tAD tC2 PIXEL n ANALOG INPUTS CDSCLK2 tC2ADR tADC2 ADCCLK tC2ADF tADCLK OUTPUT DATA D CH1(n–2) HIGH BYTE LOW BYTE tADCLK CH2(n–2) HIGH BYTE LOW BYTE CH1(n–1) HIGH BYTE LOW BYTE CH2(n–1) HIGH BYTE LOW BYTE CH1(n) HIGH BYTE LOW BYTE Figure 4. 2-Channel SHA Mode Timing REV. A –9– AD9826 PIXEL n (R,G,B) tAD PIXEL (n+1) ANALOG INPUTS tPRA tC2 CDSCLK2 tC2AD tADCLK ADCCLK tADC2 tC2ADR tADCLK OUTPUT DATA D R (n–2) G (n–2) HIGH BYTE G (n–2) LOW BYTE B (n–2) HB B (n–2) LB R (n–1) HB R (n–1) LB tOD G (n–1) HB G (n–1) LB B (n–1) HB B (n–1) LB R (n) HB R (n) LB G (n) HB G (n) LB Figure 5. 3-Channel SHA Mode Timing PIXEL n tAD ANALOG INPUTS tPRB tC2 CDSCLK2 tC2ADR tC2ADF ADCCLK ttADCLK ADCLK OUTPUT DATA D PIXEL (n–4) HIGH BYTE PIXEL (n–4) LOW BYTE PIXEL (n–3) HIGH BYTE tADCLK tOD PIXEL (n–3) LOW BYTE PIXEL (n–2) HIGH BYTE PIXEL (n–2) LOW BYTE NOTE IN 1-CHANNEL SHA MODE, THE CDSCLK2 RISING EDGE MUST OCCUR WHILE ADCCLK IS “LOW.” Figure 6. 1-Channel SHA Mode Timing –10– REV. A AD9826 ADCCLK tOD OUTPUT DATA HIGH BYTE DB15–DB8 PIXEL n LOW BYTE DB7–DB0 PIXEL n tOD HB n+1 LB n+1 LB n+2 tDV HB n+3 tHZ OEB Figure 7. Digital Output Data Timing ADCCLK tOD OUTPUT DATA HIGH BYTE DB15–DB8 PIXEL n HIGH BYTE DB15–DB8 PIXEL n+1 HB n+2 HB n+3 tHZ tDV OEB Figure 8. Single Byte Mode Digital Output Data Timing R/Wb SDATA A2 A1 A0 tDS D8 D7 D6 D5 D4 D3 D2 D1 D0 tDH SCLK tLS SLOAD tLH Figure 9. Serial Write Operation Timing SDATA A2 A1 A0 D8 tRDV SCLK tLS SLOAD tLH D7 D6 D5 D4 D3 D2 D1 D0 R/Wb Figure 10. Serial Read Operation Timing REV. A –11– AD9826 ANALOG INPUTS PIXEL n (R,G,B) PIXEL (n+1) CDSCLK1 CDSCLK2 ADCCLK RED PGA OUT RED (n–1) RED (n) RED (n+1) GREEN PGA OUT BLUE PGA OUT GREEN (n–1) GREEN (n) GREEN (n+1) BLUE (n–1) BLUE (n) BLUE (n+1) MUX OUT GREEN (n–1) BLUE (n–1) RED (n) GREEN (n) BLUE (n) RED (n+1) GREEN (n+1) OUTPUT DATA D R(n–2) G(n–2) HIGH BYTE G(n–2) LOW BYTE B(n–2) HB B(n–2) LB R(n–1) HB R(n–1) LB G(n–1) HB G(n–1) LB B(n–1) HB B(n–1) LB R(n) HB R(n) LB G(n) HB G(n) LB NOTES 1. THE MUX STATE MACHINE IS INTERNALLY RESET AT THE CDSCLK2 RISING EDGE. 2. EACH PIXEL IS SAMPLED AND AMPLIFIED BY THE PGAs AT CDSCLK2 FALLING EDGE. 3. AFTER CDSCLK2 RISING EDGE, THE NEXT ADCCLK RISING EDGE WILL ALWAYS SELECT RED PGA OUTPUT. 4. THE ADC SAMPLES THE MUX OUTPUT ON ADCCLK FALLING EDGES. 5. THE MUX SWITCHES TO THE NEXT PGA OUTPUT AT ADCCLK RISING EDGES. Figure 11. Internal Timing Diagram for 3-Channel CDS Mode –12– REV. A AD9826 FUNCTIONAL DESCRIPTION 2-Channel CDS Mode The AD9826 can be operated in six different modes: 3-Channel CDS Mode, 3-Channel SHA Mode, 2-Channel CDS Mode, 2-Channel SHA Mode, 1-Channel CDS Mode, and 1-Channel SHA Mode. Each mode is selected by programming the Configuration Registers through the serial interface. For more detail on CDS or SHA mode operation, see the Circuit Operation section. 3-Channel CDS Mode In 3-Channel CDS Mode, the AD9826 simultaneously samples the Red, Green, and Blue input voltages from the CCD outputs. The sampling points for each Correlated Double Sampler (CDS) are controlled by CDSCLK1 and CDSCLK2 (see Figures 11 and 13). CDSCLK1’s falling edge samples the reference level of the CCD waveform. CDSCLK2’s falling edge samples the data level of the CCD waveform. Each CDS amplifier outputs the difference between the CCD’s reference and data levels. Next, the output voltage of each CDS amplifier is level-shifted by an Offset DAC. The voltages are then scaled by the three Programmable Gain Amplifiers before being multiplexed through the 16-Bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The offset and gain values for the Red, Green, and Blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX Configuration register. Timing for this mode is shown in Figure 1. It is recommended that the falling edge of CDSCLK2 occur before the rising edge of ADCCLK, although this is not required to satisfy the minimum timing constraints. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three clock cycles. 3-Channel SHA Mode The 2-Channel Mode is selected by writing a “1” into two of the channel select bits of the MUX register (D4–D6). Bit D5 of the configuration register also needs to be set low to take the part out of 3-Channel Mode. The channels that will be used is determined by the contents of Bits D4–D6 of the MUX Configuration Register (see Table III). The combination of inputs that can be selected are; RG, RB, or GB by writing a “1” into the appropriate bit. The sample order is selected by Bit D7. If D7 is high, the MUX will sample in the following order: RG or RB or GB depending on which channels are turned on. If Bit D7 is set low the mux will sample in the following order: GR or BR or BG depending on which channels are turned on. The AD9826 simultaneously samples the selected channels’ input voltages from the CCD outputs. The sampling points for each Correlated Double Sampler (CDS) are controlled by CDSCLK1 and CDSCLK2 (see Figure 11). CDSCLK1’s falling edge samples the reference level of the CCD waveform. CDSCLK2’s falling edge samples the data level of the CCD waveform. Each CDS amplifier outputs the difference between the CCD’s reference and data levels. Next, the output voltage of each CDS amplifier is level-shifted by an Offset DAC. The voltages are then scaled by the two Programmable Gain Amplifiers before being multiplexed through the 16-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The offset and gain values for the Red, Green, and Blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX Configuration Register. Timing for this mode is shown in Figure 3. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three clock cycles. 2-Channel SHA Mode In 3-Channel SHA Mode, the AD9826 simultaneously samples the Red, Green, and Blue input voltages. The sampling point is controlled by CDSCLK2. CDSCLK2’s falling edge samples the input waveforms on each channel. The output voltages from the three SHAs are modified by the offset DACs and then scaled by the three PGAs. The outputs of the PGAs are then multiplexed through the 16-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The input signal is sampled with respect to the voltage applied to the OFFSET pin (see Figure 14). With the OFFSET pin grounded, a zero volt input corresponds to the ADC’s zero scale output. The OFFSET pin may also be used as a coarse offset adjust pin. A voltage applied to this pin will be subtracted from the voltages applied to the Red, Green, and Blue inputs in the first amplifier stage of the AD9826. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 5. CDSCLK1 should be grounded in this mode. Although it is not required, it is recommended that the falling edge of CDSCLK2 occur before the rising edge of ADCCLK. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three ADCCLK cycles. The offset and gain values for the Red, Green, and Blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX Configuration register. The 2-Channel Mode is selected by writing a “1” into two of the channel select bits of the MUX Register (D4–D6). Bit D5 of the configuration register also needs to be set low to take the part out of 3-Channel Mode. The channels that will be used is determined by the contents of Bits D4–D6 of the MUX Configuration Register (see Table III ). The combination of inputs that can be selected are; RG, RB, or GB by writing a “1” into the appropriate bit. The sample order is selected by Bit D7. If D7 is high, the mux will sample in the following order: RG or RB or GB, depending on which channels are turned on. If Bit D7 is set low, the mux will sample in the following order: GR or BR or BG, depending on which channels are turned on. In 2-Channel SHA Mode, the AD9826 simultaneously samples the selected channels’ input voltages. The sampling point is controlled by CDSCLK2. CDSCLK2’s falling edge samples the input waveforms on each channel. The output voltages from the two SHAs are modified by the offset DACs and then scaled by the two PGAs. The outputs of the PGAs are then multiplexed through the 16-bit ADC. The ADC sequentially samples the PGA outputs on the falling edges of ADCCLK. The input signal is sampled with respect to the voltage applied to the OFFSET pin (see Figure 14). With the OFFSET pin grounded, a zero volt input corresponds to the ADC’s zero scale output. The OFFSET pin may also be used as a coarse offset –13– REV. A AD9826 adjust pin. A voltage applied to this pin will be subtracted from the voltages applied to the Red, Green, and Blue inputs in the first amplifier stage of the AD9826. The input clamp is disabled in this mode. For more information, see the Circuit Operation section. Timing for this mode is shown in Figure 4. CDSCLK1 should be grounded in this mode. The rising edge of CDSCLK2 should not occur before the previous falling edge of ADCCLK, as shown by tADC2. The output data latency is three ADCCLK cycles. The offset and gain values for the Red, Green, and Blue channels are programmed using the serial interface. The order in which the channels are switched through the multiplexer is selected by programming the MUX Configuration Register. 1-Channel CDS Mode This mode operates the same way as the 3-Channel CDS mode. The difference is that the multiplexer remains fixed in this mode, so only the channel specified in the MUX Configuration Register is processed. Timing for this mode is shown in Figure 2. 1-Channel SHA Mode Bit D7 controls the input range of the AD9826. Setting D7 high sets the input range to 4 V while setting Bit D7 low sets the input range to 2 V. Bit D6 controls the internal voltage reference. If the AD9826’s internal voltage reference is used, then this bit is set high. Setting Bit D6 low will disable the internal voltage reference, allowing an external voltage reference to be used. Setting Bit D5 high will configure the AD9826 for 3channel operation. If D5 is set low, the part will be in either 2CH or 1CH mode based on the settings in the MUX Configuration Register (See Table III and the MUX Configuration Register description). Setting Bit D4 high will enable the CDS mode of operation, and setting this bit low will enable the SHA mode of operation. Bit D3 sets the dc bias level of the AD9826’s input clamp. This bit should always be set high for the 4 V clamp bias, unless a CCD with a reset feedthrough transient exceeding 2 V is used. If the 3 V clamp bias level is used, then the peak-to-peak input signal range to the AD9826 is reduced to 3 V maximum. Bit D2 controls the power-down mode. Setting Bit D2 high will place the AD9826 into a very low-power “sleep” mode. All register contents are retained while the AD9826 is in the powered-down state. Bit D0 controls the output mode of the AD9826. Setting Bit D0 high will enable a single byte output mode where only the 8 MSBs of the 16 b ADC will be output on each rising edge of ADCCLK (see Figure 8). If Bit D0 is set low, then the 16 b ADC output is multiplexed into two bytes. The MSByte is output on ADCCLK rising edge and the LSByte is output on ADCCLK falling edge. This mode operates the same way as 3-Channel SHA mode, except that the multiplexer remains stationary. Only the channel specified in the MUX Configuration Register is processed. Timing for this mode is shown in Figure 6. CDSCLK1 should be grounded in this mode of operation. Configuration Register The Configuration Register controls the AD9826’s operating mode and bias levels. Bits D8 and D1 should always be set low. Table I. Internal Register Map Register Name Configuration MUX Config Red PGA Green PGA Blue PGA Red Offset Green Offset Blue Offset Address A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D8 0 0 0 0 0 MSB MSB MSB D7 Input Rng RGB/BGR 0 0 0 D6 VREF Red 0 0 0 D5 Data Bits D4 CDS On Blue D3 Clamp 0 D2 Pwr Dn 0 D1 0 0 D0 1 Byte Out 0 LSB LSB LSB LSB LSB LSB 3CH Mode Green MSB MSB MSB Table II. Configuration Register Settings D8 Set to 0 D7 D6 D5 D4 CDS Operation 1 = CDS Mode* 0 = SHA Mode D3 Input Clamp Bias 1 = 4 V* 0=3V D2 Power-Down 1 = On 0 = Off (Normal)* D1 Set to 0 D0 Output Mode 0 = 2 Byte* 1 = 1 Byte Input Range Internal VREF 3CH Mode 1 = 4 V* 0=2V 1 = Enabled* 0 = Disabled 1 = On* 0 = Off *Power-on default value. –14– REV. A AD9826 MUX Configuration Register PGA Gain Registers The MUX Configuration Register controls the sampling channel order and the 2-Channel Mode configuration in the AD9826. Bits D8 and D3–D0 should always be set low. Bit D7 is used when operating in 3-Channel or 2-Channel Mode. Setting Bit D7 high will sequence the MUX to sample the Red channel first, then the Green channel, and then the Blue channel. When in 3-channel mode, the CDSCLK2 pulse always resets the MUX to sample the Red channel first (see Figure 11). When Bit D7 is set low, the channel order is reversed to Blue first, Green second, and Red third. The CDSCLK2 pulse will always reset the MUX to sample the Blue channel first. Bits D6, D5, and D4 are used when operating in 1 or 2-Channel Mode. Bit D6 is set high to sample the Red channel. Bit D5 is set high to sample the Green channel. Bit D4 is set high to sample the Blue channel. The MUX will remain stationary during 1-channel mode. TwoChannel Mode is selected by setting two of the channel select Bits (D4–D6) high. The MUX samples the channels in the order selected by Bit D7. There are three PGA registers for individually programming the gain in the Red, Green, and Blue channels. Bits D8, D7, and D6 in each register must be set low, and Bits D5 through D0 control the gain range from 1× to 6× in 64 increments. See Figure 17 for a graph of the PGA gain versus PGA register code. The coding for the PGA registers is straight binary, with an all “zeros” word corresponding to the minimum gain setting (1×) and an all “ones” word corresponding to the maximum gain setting (6×). Offset Registers There are three Offset Registers for individually programming the offset in the Red, Green, and Blue channels. Bits D8 through D0 control the offset range from –300 mV to +300 mV in 512 increments. The coding for the Offset Registers is Sign Magnitude, with D8 as the sign bit. Table V shows the offset range as a function of the Bits D8 through D0. Table III. MUX Configuration Register Settings D8 Set to 0 D7 MUX Order 1 = R-G-B* 0 = B-G-R D6 Channel Select 1 = RED* 0 = Off D5 Channel Select 1 = GREEN 0 = Off* D4 Channel Select 1 = BLUE 0 = Off* D3 Set to 0 D2 Set to 0 D1 Set to 0 D0 Set to 0 *Power-on default value. Table IV. PGA Gain Register Settings D8 Set to 0 0 0 D7 Set to 0 0 0 D6 Set to 0 0 0 D5 MSB 0 0 D4 0 0 • • • D3 0 0 D2 0 0 D1 0 0 D0 LSB 0* 1 Gain (V/V) 1.0 1.013 • • • 5.56 6.0 Gain (dB) 0.0 0.12 • • • 14.9 15.56 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 *Power-on default value. Table V. Offset Register Settings D8 MSB 0 0 D7 0 0 D6 0 0 D5 0 0 D4 0 0 • • • D3 0 0 D2 0 0 D1 0 0 D0 LSB 0* 1 Offset (mV) 0 +1.2 • • • +300 0 –1.2 • • • –300 0 1 1 1 0 0 1 0 0 1 0 0 1 0 0 • • • 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 *Power-on default value. REV. A –15– AD9826 CIRCUIT OPERATION Analog Inputs—CDS Mode Operation External Input Coupling Capacitors Figure 12 shows the analog input configuration for the CDS mode of operation. Figure 13 shows the internal timing for the sampling switches. The CCD reference level is sampled when CDSCLK1 transitions from high to low, opening S1. The CCD data level is sampled when CDSCLK2 transitions from high to low, opening S2. S3 is then closed, generating a differential output voltage representing the difference between the two sampled levels. The input clamp is controlled by CDSCLK1. When CDSCLK1 is high, S4 closes and the internal bias voltage is connected to the analog input. The bias voltage charges the external 0.1 µF input capacitor, level-shifting the CCD signal into the AD9826’s input common-mode range. The time constant of the input clamp is determined by the internal 5 kΩ resistance and the external 0.1 µF input capacitance. AD9826 S1 CCD SIGNAL 0.1 F S3 5K S2 S4 1.7k OFFSET + 1F 0.1 F 3V 6.9k 4V 2.2k INPUT CLAMP LEVEL IS SELECTED IN THE CONFIGURATION REGISTER CML 4pF VINR 4pF CML The recommended value for the input coupling capacitors is 0.1 µF. While it is possible to use a smaller capacitor, this larger value is chosen for several reasons: Crosstalk The input coupling capacitor creates a capacitive divider with any parasitic capacitance between PCB traces and on chip traces. CIN should be large relative to these parasitic capacitances in order to minimize this effect. For example, with a 100 pF input capacitance and just a few hundred f F of parasitic capacitance on the PCB and/or the IC the imaging system could expect to have hundreds of LSBs of crosstalk at the 16 b level. Using a large capacitor value = 0.1 µF will minimize any errors due to crosstalk. Signal Attenuation The input coupling capacitor creates a capacitive divider with a CMOS integrated circuit’s input capacitance, attenuating the CCD signal level. CIN should be large relative to the IC’s 10 pF input capacitance in order to minimize this effect. Linearity Some of the input capacitance of a CMOS IC is junction capacitance, which varies nonlinearly with applied voltage. If the input coupling capacitor is too small, then the attenuation of the CCD signal will vary nonlinearly with signal level. This will degrade the system linearity performance. Sampling Errors The internal 4 pF sample capacitors have a “memory” of the previously sampled pixel. There is a charge redistribution error between CIN and the internal sample capacitors for larger pixelto-pixel voltage swings. As the value of CIN is reduced, the resulting error in the sampled voltage will increase. With a CIN value of 0.1 µF, the charge redistribution error will be less than 1 LSB for a full-scale pixel-to-pixel voltage swing. Figure 12. CDS-Mode Input Configuration (All Three Channels Are Identical) S1, S4 CLOSED CDSCLK1 S1, S4 OPEN S1, S4 CLOSED S2 CLOSED CDSCLK2 S2 OPEN S2 CLOSED S3 CLOSED Q3 (INTERNAL) S3 OPEN S3 CLOSED Figure 13. CDS-Mode Internal Switch Timing –16– REV. A AD9826 Analog Inputs—SHA Mode Operation Figure 14 shows the analog input configuration for the SHA mode of operation. Figure 15 shows the internal timing for the sampling switches. The input signal is sampled when CDSCLK2 transitions from high to low, opening S1. The voltage on the OFFSET pin is also sampled on the falling edge of CDSCLK2, when S2 opens. S3 is then closed, generating a differential output voltage representing the difference between the sampled input voltage and the OFFSET voltage. The input clamp is disabled during SHA mode operation. AD9826 S1 INPUT SIGNAL VINR CML 4pF Figure 16 shows how the OFFSET pin may be used in a CIS application for coarse offset adjustment. Many CIS signals have dc offsets ranging from several hundred millivolts to more than 1 V. By connecting the appropriate dc voltage to the OFFSET pin, the CIS signal will be restored to “zero.” After the large dc offset is removed, the signal can be scaled using the PGA to maximize the ADC’s dynamic range. AD9826 RED VINR SHA REDOFFSET GREEN VING SHA GREENOFFSET S3 S2 OPTIONAL DC OFFSET (OR CONNECT TO GND) OFFSET 4pF CML BLUE VINB SHA VING BLUEOFFSET VRED FROM CIS MODULE AVDD R1 DC OFFSET OFFSET 0.1 F VINB R2 Figure 16. SHA-Mode Used with External DC Offset Figure 14. SHA-Mode Input Configuration (All Three Channels Are Identical) S1, S2 CLOSED CDSCLK2 S1, S2 OPEN S1, S2 CLOSED S3 CLOSED Q3 (INTERNAL) S3 OPEN S3 CLOSED Figure 15. SHA-Mode Internal Switch Timing REV. A –17– AD9826 Programmable Gain Amplifiers APPLICATIONS INFORMATION The AD9826 uses one Programmable Gain Amplifier (PGA) for each channel. Each PGA has a gain range from 1× (0 dB) to 6.0× (15.56 dB), adjustable in 64 steps. Figure 17 shows the PGA gain as a function of the PGA register code. Although the gain curve is approximately “linear in dB,” the gain in V/V varies nonlinearly with register code, following the equation: 6.0  63 – G  1 + 5.0    63  where G is the decimal value of the gain register contents, and varies from 0 to 63. Gain = 16 6.00 12 4.75 Circuit and Layout Recommendations The recommended circuit configuration for 3-Channel CDS Mode operation is shown in Figure 18. The recommended input coupling capacitor value is 0.1 µF (see Circuit Operation section for more details). A single ground plane is recommended for the AD9826. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as the rest of the AD9826. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by using external digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of CDSCLK2 should occur coincident with or before the rising edge of ADCCLK (see Figures 1 through 6 for timing). All 0.1 µF decoupling capacitors should be located as close as possible to the AD9826 pins. When operating in 1CH or 2CH Mode, the unused analog inputs should be grounded. For 3-Channel SHA Mode, all of the above considerations also apply, except that the analog input signals are directly connected to the AD9826 without the use of coupling capacitors. The analog input signals must already be dc-biased between 0 V and 4 V. Also, the OFFSET pin should be grounded if the inputs to the AD9826 are to be referenced to ground, or a dc offset voltage should be applied to the OFFSET pin in the case where a coarse offset needs to be removed from the inputs. (See Figure 16 and the Circuit Operation section for more details.) 8 GAIN – dB 3.50 4 GAIN – V/V 2.25 0 0 12 48 24 36 PGA REGISTER VALUE – Decimal 1.00 60 63 Figure 17. PGA Gain Transfer Function 5V CLOCK INPUTS CDSCLK1 CDSCLK2 2 27 1 28 GAIN – V/V GAIN – dB 0.1 F RED INPUT 0.1 F AVDD AVSS 0.1 F GREEN INPUT ADCCLK 3 26 25 24 VINR OFFSET VING CML 0.1 F 23 0.1 F BLUE INPUT 0.1 F 0.1 F 0.1 F 10 F 0.1 F 0.1 F 1.0 F 5V/3V OEB DRVDD 4 5 0.1 F DRVSS 6 (MSB) D7 D6 D5 D4 D3 D2 D1 (LSB)D0 DATA INPUTS AD9826 VINB 22 TOP VIEW CAPT 8 (Not to Scale) 21 CAPB 7 9 20 19 18 17 16 15 10 11 12 13 14 AVSS AVDD SLOAD SCLK SDATA 5V SERIAL INTERFACE Figure 18. Recommended Circuit Configuration, 3-Channel CDS Mode –18– REV. A AD9826 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead 5.3 mm SSOP (RS-28) 0.407 (10.34) 0.397 (10.08) 28 15 0.311 (7.9) 0.301 (7.64) 1 14 0.078 (1.98) PIN 1 0.068 (1.73) 0.07 (1.79) 0.066 (1.67) 0.212 (5.38) 0.205 (5.21) 0.008 (0.203) 0.0256 (0.65) 0.002 (0.050) BSC 8° 0.015 (0.38) 0° SEATING 0.009 (0.229) 0.010 (0.25) PLANE 0.005 (0.127) 0.03 (0.762) 0.022 (0.558) Revision History Location Data Sheet changed from REV. 0 to REV. A. Page Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Edits to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 REV. A –19– – 20– C02367–0–10/01(A) PRINTED IN U.S.A.