20 mW Power, 2.3 V to 5.5 V,
75 MHz Complete DDS
AD9834
Capability for phase modulation and frequency modulation is
provided. The frequency registers are 28 bits; with a 75 MHz
clock rate, resolution of 0.28 Hz can be achieved. Similarly, with
a 1 MHz clock rate, the AD9834 can be tuned to 0.004 Hz
resolution. Frequency and phase modulation are affected by
loading registers through the serial interface and toggling the
registers using software or the FSELECT pin and PSELECT pin,
respectively.
FEATURES
Narrow-band SFDR >72 dB
2.3 V to 5.5 V power supply
Output frequency up to 37.5 MHz
Sine output/triangular output
On-board comparator
3-wire SPI® interface
Extended temperature range: −40°C to +105°C
Power-down option
20 mW power consumption at 3 V
20-lead TSSOP
The AD9834 is written to using a 3-wire serial interface. This
serial interface operates at clock rates up to 40 MHz and is
compatible with DSP and microcontroller standards.
APPLICATIONS
The device operates with a power supply from 2.3 V to 5.5 V.
The analog and digital sections are independent and can be run
from different power supplies, for example, AVDD can equal
5 V with DVDD equal to 3 V.
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect
detection
Test and medical equipment
The AD9834 has a power-down pin (SLEEP) that allows
external control of the power-down mode. Sections of the
device that are not being used can be powered down to
minimize the current consumption. For example, the DAC can
be powered down when a clock output is being generated.
GENERAL DESCRIPTION
The AD9834 is a 75 MHz low power DDS device capable of
producing high performance sine and triangular outputs. It also
has an on-board comparator that allows a square wave to be
produced for clock generation. Consuming only 20 mW of
power at 3 V makes the AD9834 an ideal candidate for powersensitive applications.
The part is available in a 20-lead TSSOP.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DGND
DVDD
CAP/2.5V
REFOUT
ON-BOARD
REFERENCE
REGULATOR
MCLK
VCC
2.5V
FULL-SCALE
CONTROL
FSELECT
28-BIT FREQ0
REG
PHASE
ACCUMULATOR
(28-BIT)
MUX
28-BIT FREQ1
REG
FS ADJUST
Σ
12
SIN
ROM
10-BIT
DAC
MUX
COMP
IOUT
IOUTB
MSB
12-BIT PHASE0 REG
12-BIT PHASE1 REG
MUX
MUX
DIVIDED
BY 2
16-BIT CONTROL
REGISTER
MUX
SIGN BIT OUT
SERIAL INTERFACE
AND
CONTROL LOGIC
COMPARATOR
VIN
FSYNC
SCLK
SDATA
PSELECT
SLEEP RESET
02705-001
AD9834
Figure 1.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.
AD9834
TABLE OF CONTENTS
Features .............................................................................................. 1
Control Register ......................................................................... 17
Applications ....................................................................................... 1
Frequency and Phase Registers ................................................ 19
General Description ......................................................................... 1
Writing to a Frequency Register ............................................... 20
Functional Block Diagram .............................................................. 1
Writing to a Phase Register ....................................................... 20
Revision History ............................................................................... 2
RESET Function ......................................................................... 20
Specifications..................................................................................... 3
SLEEP Function .......................................................................... 20
Timing Characteristics ................................................................ 5
Sign Bit Out Pin .......................................................................... 21
Absolute Maximum Ratings............................................................ 6
The IOUT and IOUTB Pins...................................................... 21
ESD Caution .................................................................................. 6
Applications..................................................................................... 22
Pin Configuration and Function Descriptions ............................. 7
Grounding and Layout .................................................................. 25
Typical Performance Characteristics ............................................. 9
Interfacing to Microprocessors ..................................................... 26
Terminology .................................................................................... 13
AD9834 to ADSP-21xx Interface ............................................. 26
Theory of Operation ...................................................................... 14
AD9834 to 68HC11/68L11 Interface ....................................... 26
Circuit Description ......................................................................... 15
AD9834 to 80C51/80L51 Interface .......................................... 27
Numerically Controlled Oscillator Plus Phase Modulator ... 15
AD9834 to DSP56002 Interface ............................................... 27
SIN ROM ..................................................................................... 15
Evaluation Board ............................................................................ 28
Digital-to-Analog Converter .................................................... 15
Using the AD9834 Evaluation Board....................................... 28
Comparator ................................................................................. 15
Prototyping Area ........................................................................ 28
Regulator...................................................................................... 16
XO vs. External Clock................................................................ 28
Functional Description .................................................................. 17
Power Supply............................................................................... 28
Serial Interface ............................................................................ 17
Bill of Materials ........................................................................... 30
Powering Up the AD9834 ......................................................... 17
Outline Dimensions ....................................................................... 31
Latency ......................................................................................... 17
Ordering Guide .......................................................................... 31
REVISION HISTORY
4/10—Rev. A to Rev. B
Changes to Comparator Section ................................................... 15
Added Figure 28.............................................................................. 16
Changes to Serial Interface Section .............................................. 17
8/06—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changed to 75 MHz Complete DDS................................ Universal
Changes to Features Section............................................................ 1
Changes to Table 1 ............................................................................ 4
Changes to Table 2 ............................................................................ 6
Changes to Table 3 ............................................................................ 8
Added Figure 10, Figures Renumbered Sequentially ...................9
Added Figure 16 and Figure 17, Figures Renumbered
Sequentially ..................................................................................... 10
Changes to Table 6.......................................................................... 19
Changes to Writing a Frequency Register Section ..................... 20
Changes to Figure 29...................................................................... 21
Changes to Table 19 ....................................................................... 30
Changes to Figure 38...................................................................... 28
2/03—Revision 0: Initial Version
Rev. B | Page 2 of 32
AD9834
SPECIFICATIONS
VDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ, RLOAD = 200 Ω for IOUT and IOUTB, unless otherwise noted.
Table 1.
2
Parameter
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate
IOUT Full Scale 3
VOUT Max
VOUT Min
Output Compliance 4
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
Narrow Band (±200 kHz)
B Grade
C Grade
Clock Feedthrough
Wake-Up Time
COMPARATOR
Input Voltage Range
Input Capacitance
Input High-Pass Cutoff Frequency
Input DC Resistance
Input Leakage Current
OUTPUT BUFFER
Output Rise/Fall Time
Output Jitter
VOLTAGE REFERENCE
Internal Reference
REFOUT Output Impedance 5
Reference TC
LOGIC INPUTS
VINH, Input High Voltage
Min
Grade B, Grade C 1
Typ
Max
10
75
3.0
0.6
30
0.8
±1
±0.5
55
Bits
MSPS
mA
V
mV
V
60
−66
−56
dB
dBc
fMCLK = 75 MHz, fOUT = fMCLK/4096
fMCLK = 75 MHz, fOUT = fMCLK/4096
−60
−56
dBc
fMCLK = 75 MHz, fOUT = fMCLK/75
−78
−74
−50
1
−67
−65
dBc
dBc
dBc
ms
fMCLK = 50 MHz, fOUT = fMCLK/50
fMCLK = 75 MHz, fOUT = fMCLK/75
1
V p-p
pF
MHz
MΩ
μA
AC-coupled internally
ns
ps rms
Using a 15 pF load
3 MHz sine wave 0.6 V p-p
10
12
120
1.18
1
100
1.24
1.7
2.0
2.8
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN, Input Capacitance
POWER SUPPLIES
AVDD
DVDD
IAA 6
Test Conditions/Comments
LSB
LSB
10
4
5
1.12
Unit
0.6
0.7
0.8
10
3
2.3
2.3
3.8
5.5
5.5
5
Rev. B | Page 3 of 32
V
kΩ
ppm/°C
V
V
V
V
V
V
μA
pF
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
V
V
mA
fMCLK = 75 MHz, fOUT = fMCLK/4096
AD9834
2
Parameter
IDD6
B Grade
C Grade
IAA + IDD6
B Grade
C Grade
Low Power Sleep Mode
B Grade
C Grade
Grade B, Grade C 1
Typ
Max
Min
Unit
Test Conditions/Comments
IDD code dependent (see Figure 9)
IDD code dependent (see Figure 9)
2.0
2.7
3
3.7
mA
mA
5.8
6.5
8
8.7
mA
mA
0.5
0.6
mA
mA
DAC powered down, MCLK running
DAC powered down, MCLK running
1
B grade: MCLK = 50 MHz; C grade: MCLK = 75 MHz. For specifications that do not specify a grade, the value applies to both grades.
Operating temperature range is as follows: B, C versions: −40°C to +105°C, typical specifications are at 25°C.
3
For compliance, with specified load of 200 Ω, IOUT full scale should not exceed 4 mA.
4
Guaranteed by design.
5
Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
6
Measured with the digital inputs static and equal to 0 V or DVDD.
2
RSET
6.8kΩ
10nF
REFOUT
CAP/2.5V
REGULATOR
ON-BOARD
REFERENCE
12
AD9834
SIN
ROM
FS ADJUST
FULL-SCALE
CONTROL
10-BIT DAC
AVDD
10nF
COMP
IOUT
RLOAD
200Ω
Figure 2. Test Circuit Used to Test the Specifications
Rev. B | Page 4 of 32
20pF
02705-002
100nF
AD9834
TIMING CHARACTERISTICS
DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter 1
t1
t2
t3
t4
t5
t6
t7
t8 MIN
t8 MAX
t9
t10
t11
t11A
t12
1
Limit at TMIN to TMAX
20/13.33
8/6
8/6
25
10
10
5
10
t4 − 5
5
3
8
8
5
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
MCLK period: 50 MHz/75 MHz
MCLK high duration: 50 MHz/75 MHz
MCLK low duration: 50 MHz/75 MHz
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
FSYNC to SCLK hold time
Data setup time
Data hold time
FSELECT, PSELECT setup time before MCLK rising edge
FSELECT, PSELECT setup time after MCLK rising edge
SCLK high to FSYNC falling edge setup time
Guaranteed by design, not production tested.
Timing Diagrams
t1
02705-003
MCLK
t2
t3
Figure 3. Master Clock
MCLK
FSELECT,
PSELECT
VALID DATA
VALID DATA
VALID DATA
02705-004
t11A
t11
Figure 4. Control Timing
t5
t12
t4
SCLK
t7
t6
t8
FSYNC
t10
SDATA
D15
D14
D2
D1
Figure 5. Serial Timing
Rev. B | Page 5 of 32
D0
D15
D14
02705-005
t9
AD9834
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to AGND
DVDD to DGND
AVDD to DVDD
AGND to DGND
CAP/2.5V
Digital I/O Voltage to DGND
Analog I/O Voltage to AGND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature
Reflow Soldering (Pb-Free)
Peak Temperature
Time at Peak Temperature
Ratings
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
+2.75 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
−40°C to +105°C
−65°C to +150°C
150°C
143°C/W
45°C/W
300°C
220°C
260°C (+0/–5)
10 sec to 40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 6 of 32
AD9834
FS ADJUST
1
20
IOUTB
REFOUT 2
19
IOUT
COMP 3
18
AGND
17
VIN
16
SIGN BIT OUT
CAP/2.5V 6
15
FSYNC
DGND 7
14
SCLK
MCLK 8
13
SDATA
FSELECT 9
12
SLEEP
PSELECT 10
11
RESET
AVDD 4
DVDD 5
AD9834
TOP VIEW
(Not to Scale)
02705-006
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 6. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
ANALOG SIGNAL AND REFERENCE
1
FS ADJUST Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the magnitude
of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows:
IOUT FULL SCALE = 18 × VREFOUT/RSET
VREFOUT = 1.20 V nominal, RSET = 6.8 kΩ typical.
2
REFOUT
Voltage Reference Output. The AD9834 has an internal 1.20 V reference that is made available at this pin.
3
COMP
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
17
VIN
Input to Comparator. The comparator can be used to generate a square wave from the sinusoidal DAC output. The
DAC output should be filtered appropriately before being applied to the comparator to improve jitter. When Bit
OPBITEN and Bit SIGNPIB in the control register are set to 1, the comparator input is connected to VIN.
19, 20
IOUT,
Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω should be connected
IOUTB
between IOUT and AGND. IOUTB should preferably be tied through an external load resistor of 200 Ω to AGND, but
it can be tied directly to AGND. A 20 pF capacitor to AGND is also recommended to prevent clock feedthrough.
POWER SUPPLY
4
AVDD
Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling
capacitor should be connected between AVDD and AGND.
5
DVDD
Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling
capacitor should be connected between DVDD and DGND.
6
CAP/2.5V
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board
regulator (when DVDD exceeds 2.7 V). The regulator requires a decoupling capacitor of typically 100 nF that is
connected from CAP/2.5 V to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5 V should be shorted to DVDD.
7
DGND
Digital Ground.
18
AGND
Analog Ground.
DIGITAL INTERFACE AND CONTROL
8
MCLK
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
9
FSELECT
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. The frequency register to be used can be selected using Pin FSELECT or Bit FSEL. When Bit FSEL is
used to select the frequency register, the FSELECT pin should be tied to CMOS high or low.
10
PSELECT
Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator
output. The phase register to be used can be selected using Pin PSELECT or Bit PSEL. When the phase registers are being
controlled by Bit PSEL, the PSELECT pin should be tied to CMOS high or low.
11
RESET
Active High Digital Input. RESET resets appropriate internal registers to zero; this corresponds to an analog output
of midscale. RESET does not affect any of the addressable registers.
12
SLEEP
Active High Digital Input. When this pin is high, the DAC is powered down. This pin has the same function as
Control Bit SLEEP12.
Rev. B | Page 7 of 32
AD9834
Pin No.
13
14
15
Mnemonic
SDATA
SCLK
FSYNC
16
SIGN BIT
OUT
Function
Serial Data Input. The 16-bit serial data-word is applied to this input.
Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge.
Active Low Control Input. This is the frame synchronization signal for the input data. When FSYNC is taken low, the
internal logic is informed that a new word is being loaded into the device.
Logic Output. The comparator output is available on this pin or, alternatively, the MSB from the NCO can be output
on this pin. Setting Bit OPBITEN in the control register to 1 enables this output pin. Bit SIGNPIB determines whether
the comparator output or the MSB from the NCO is output on the pin.
Rev. B | Page 8 of 32
AD9834
TYPICAL PERFORMANCE CHARACTERISTICS
4.0
0
AVDD = DVDD = 3V
TA = 25°C
TA = 25°C
3.5
–10
3.0
–20
SFDR (dBc)
5V
2.0
3V
1.5
–30
–40
–50
1.0
–60
0.5
–70
15
0
30
45
MCLK FREQUENCY (MHz)
60
75
fOUT = 1MHz
–80
02705-007
0
SFDR dB MCLK/7
0
10
20
30
40
50
MCLK FREQUENCY (MHz)
60
02705-010
IDD (mA)
2.5
70
Figure 10. Wideband SFDR vs. MCLK Frequency
Figure 7. Typical Current Consumption (IDD) vs. MCLK Frequency
4.0
0
TA = 25°C
5V
3.5
–10
3.0
AVDD = DVDD = 3V
TA = 25°C
–20
3V
SFDR (dBc)
IDD (mA)
2.5
2.0
1.5
–30
50MHz CLOCK
–40
–50
–60
0.5
–70
1k
10k
100k
fOUT (Hz)
1M
10M
100M
–80
0.001
02705-008
0
100
0.1
1.0
fOUT/fMCLK
10
100
Figure 11. Wideband SFDR vs. fOUT/fMCLK for Various MCLK Frequencies
Figure 8. Typical IDD vs. fOUT for fMCLK = 50 MHz
–60
–40
AVDD = DVDD = 3V
TA = 25°C
–45
–70
–50
SNR (dB)
–65
–75
SFDR dB MCLK/50
–80
TA = 25°C
AVDD = DVDD = 3V
fOUT = MCLK/4096
–55
–60
–85
–65
–90
0
15
30
45
MCLK FREQUENCY (MHz)
60
75
–70
1.0
5.0
10.0
12.5
MCLK FREQUENCY (MHz)
Figure 12. SNR vs. MCLK Frequency
Figure 9. Narrow-Band SFDR vs. MCLK Frequency
Rev. B | Page 9 of 32
25.0
50.0
02705-012
SFDR dB MCLK/7
02705-009
SFDR (dBc)
0.01
02705-011
30MHz CLOCK
1.0
AD9834
1000
0.20
950
0.18
900
0.16
DVDD = 3.3V
DVDD = 2.3V
DVDD = 5.5V
800
0.12
700
0.10
0.08
650
0.06
600
0.04
550
0.02
500
–40
25
TEMPERATURE (°C)
105
0
–40
Figure 13. Wake-Up Time vs. Temperature
–20
0
20
40
60
TEMPERATURE (°C)
80
100
02705-037
5.5V
100
02705-038
750
DVDD (V)
0.14
02705-013
WAKE-UP TIME (µs)
2.3V
850
Figure 16. SIGN BIT OUT Low Level, ISINK = 1 mA
5.5
1.250
DVDD = 5.5V
5.0
1.225
4.5
DVDD = 4.5V
UPPER RANGE
4.0
DVDD (V)
V(REFOUT) (V)
1.200
1.175
LOWER RANGE
3.5
DVDD = 3.3V
3.0
1.150
DVDD = 2.7V
2.5
1.125
2.0
25
TEMPERATURE (°C)
105
1.5
–40
02705-014
1.100
–40
DVDD = 2.3V
–20
0
20
40
60
TEMPERATURE (°C)
80
Figure 17. SIGN BIT OUT High Level, ISINK = 1 mA
Figure 14. VREFOUT vs. Temperature
0
–100
AVDD = DVDD = 5V
TA = 25°C
–10
–110
–20
–30
(dB)
–40
–130
–50
–60
–70
–140
–80
–150
1k
10k
FREQUENCY (Hz)
100k 200k
Figure 15. Output Phase Noise, fOUT = 2 MHz, MCLK = 50 MHz
0
RWB 100
VWB 30
FREQUENCY (Hz)
100k
ST 100 SEC
02705-016
–160
100
–90
–100
02705-015
(dBc/Hz)
–120
Figure 18. fMCLK = 10 MHz; fOUT = 2.4 kHz, Frequency Word = 000FBA9
Rev. B | Page 10 of 32
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
5M
ST 50 SEC
–10
–20
–20
–30
–30
–40
–40
(dB)
–10
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
–100
5M
ST 50 SEC
Figure 20. fMCLK = 10 MHz; fOUT = 3.33 MHz = fMCLK/3,
Frequency Word = 5555555
–10
–10
–20
–20
–30
–30
–40
–40
(dB)
0
–50
–60
–70
–70
–80
–80
–90
–90
160k
ST 200 SEC
Figure 21. fMCLK = 50 MHz; fOUT = 12 kHz, Frequency Word = 000FBA9
–100
02705-019
VWB 30
FREQUENCY (Hz)
VWB 300
FREQUENCY (Hz)
25M
ST 200 SEC
–50
–60
0
RWB 100
0
RWB 1k
Figure 23. fMCLK = 50 MHz; fOUT = 1.2 MHz, Frequency Word = 0624DD3
0
–100
1.6M
ST 200 SEC
–50
02705-018
(dB)
0
VWB 300
FREQUENCY (Hz)
VWB 300
FREQUENCY (Hz)
Figure 22. fMCLK = 50 MHz; fOUT = 120 kHz, Frequency Word = 009D496
0
0
RWB 1k
0
RWB 100
02705-021
VWB 300
FREQUENCY (Hz)
0
RWB 1k
VWB 300
FREQUENCY (Hz)
25M
ST 200 SEC
02705-022
0
RWB 1k
Figure 19. fMCLK = 10 MHz; fOUT = 1.43 MHz = fMCLK/7,
Frequency Word = 2492492
(dB)
–50
02705-020
(dB)
0
02705-017
(dB)
AD9834
Figure 24. fMCLK = 50 MHz; fOUT = 4.8 MHz, Frequency Word = 189374C
Rev. B | Page 11 of 32
0
–10
–10
–20
–20
–30
–30
–40
–40
–50
–50
–60
–60
–70
–70
–80
–80
–90
–90
–100
0
RWB 1k
VWB 300
FREQUENCY (Hz)
25M
ST 200 SEC
–100
Figure 25. fMCLK = 50 MHz; fOUT = 7.143 MHz = fMCLK/7,
Frequency Word = 2492492
0
RWB 1k
VWB 300
FREQUENCY (Hz)
25M
ST 200 SEC
Figure 26. fMCLK = 50 MHz; fOUT = 16.667 MHz = fMCLK/3,
Frequency Word = 5555555
Rev. B | Page 12 of 32
02705-024
(dB)
0
02705-023
(dB)
AD9834
AD9834
TERMINOLOGY
Integral Nonlinearity (INL)
Integral nonlinearity is the maximum deviation of any code
from a straight line passing through the endpoints of the
transfer function. The endpoints of the transfer function are zero
scale, a point 0.5 LSB below the first code transition (000 . . . 00 to
000 . . . 01), and full scale, a point 0.5 LSB above the last code
transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
and ideal 1 LSB change between two adjacent codes in the DAC.
A specified DNL of ±1 LSB maximum ensures monotonicity.
Output Compliance
The output compliance refers to the maximum voltage that can
be generated at the output of the DAC to meet the specifications.
When voltages greater than that specified for the output compliance are generated, the AD9834 may not meet the
specifications listed in the data sheet.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the
fundamental frequency and images of these frequencies are
present at the output of a DDS device. The SFDR refers to the
largest spur or harmonic present in the band of interest. The
wideband SFDR gives the magnitude of the largest harmonic or
spur relative to the magnitude of the fundamental frequency in
the 0 to Nyquist bandwidth. The narrow-band SFDR gives the
attenuation of the largest spur or harmonic in a bandwidth of
±200 kHz about the fundamental frequency.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of
harmonics to the rms value of the fundamental. For the
AD9834, THD is defined as
THD = 20log
V2 2 + V32 + V4 2 + V5 2 + V6 2
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second harmonic
through the sixth harmonic.
Signal-to-Noise Ratio (SNR)
Signal-to-noise ratio is the ratio of the rms value of the
measured output signal to the rms sum of all other spectral
components below the Nyquist frequency. The value for SNR is
expressed in decibels.
Clock Feedthrough
There is feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
output spectrum of the AD9834.
Rev. B | Page 13 of 32
AD9834
THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude
form a(t) = sin (ωt). However, these are nonlinear and not easy
to generate except through piecewise construction. On the
other hand, the angular information is linear in nature, that is,
the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal
by the traditional rate of ω = 2πf.
Knowing that the phase of a sine wave is linear and given a
reference interval (clock period), the phase rotation for that
period can be determined.
ΔPhase = ωΔt
Solving for ω
ω = ΔPhase/Δt = 2πf
MAGNITUDE
+1
Solving for f and substituting the reference clock frequency for
the reference period (1/fMCLK = Δt)
6π
0
4π
2π
f = ΔPhase × fMCLK/2π
–1
2π
PHASE
4π
6π
02705-025
2p
0
Figure 27. Sine Wave
The AD9834 builds the output based on this simple equation. A
simple DDS chip can implement this equation with three major
subcircuits: numerically controlled oscillator + phase modulator,
SIN ROM, and digital-to-analog converter. Each of these
subcircuits is discussed in the Circuit Description section.
Rev. B | Page 14 of 32
AD9834
CIRCUIT DESCRIPTION
The AD9834 is a fully integrated direct digital synthesis (DDS)
chip. The chip requires one reference clock, one low precision
resistor, and eight decoupling capacitors to provide digitally created
sine waves up to 37.5 MHz. In addition to the generation of this RF
signal, the chip is fully capable of a broad range of simple and
complex modulation schemes. These modulation schemes are
fully implemented in the digital domain, allowing accurate and
simple realization of complex modulation algorithms using DSP
techniques.
The internal circuitry of the AD9834 consists of the following
main sections: a numerically controlled oscillator (NCO),
frequency and phase modulators, SIN ROM, a digital-to-analog
converter, a comparator, and a regulator.
NUMERICALLY CONTROLLED OSCILLATOR PLUS
PHASE MODULATOR
This consists of two frequency select registers, a phase
accumulator, two phase offset registers, and a phase offset
adder. The main component of the NCO is a 28-bit phase
accumulator. Continuous time signals have a phase range of 0
to 2π. Outside this range of numbers, the sinusoid functions repeat
themselves in a periodic manner. The digital implementation is no
different. The accumulator simply scales the range of phase
numbers into a multibit digital word. The phase accumulator in
the AD9834 is implemented with 28 bits. Therefore, in the
AD9834, 2π = 228. Likewise, the ΔPhase term is scaled into this
range of numbers:
0 < ΔPhase < 228 − 1.
Making these substitutions into the equation above
f = ΔPhase × fMCLK/228
SIN ROM
To make the output from the NCO useful, it must be converted
from phase information into a sinusoidal value. Phase information maps directly into amplitude; therefore, the SIN ROM uses
the digital phase information as an address to a look-up table
and converts the phase information into amplitude.
Although the NCO contains a 28-bit phase accumulator, the
output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary
because it requires a look-up table of 228 entries. It is necessary
only to have sufficient phase resolution such that the errors due
to truncation are smaller than the resolution of the 10-bit DAC.
This requires the SIN ROM to have two bits of phase resolution
more than the 10-bit DAC.
The SIN ROM is enabled using the OPBITEN and MODE bits
in the control register. This is explained further in Table 18.
DIGITAL-TO-ANALOG CONVERTER
The AD9834 includes a high impedance current source 10-bit
DAC capable of driving a wide range of loads. The full-scale
output current can be adjusted for optimum power and external
load requirements using a single external resistor (RSET).
The DAC can be configured for either single-ended or differential
operation. IOUT and IOUTB can be connected through equal
external resistors to AGND to develop complementary output
voltages. The load resistors can be any value required, as long as
the full-scale voltage developed across it does not exceed the
voltage compliance range. Since full-scale current is controlled
by RSET, adjustments to RSET can balance changes made to the
load resistors.
COMPARATOR
where 0 < ΔPhase < 228 − 1.
The input to the phase accumulator can be selected either from
the FREQ0 register or FREQ1 register, and is controlled by the
FSELECT pin or the FSEL bit. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity
when switching between frequencies.
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit phase registers. The contents
of one of these phase registers is added to the MSBs of the NCO.
The AD9834 has two phase registers, the resolution of these
registers being 2π/4096.
The AD9834 can be used to generate synthesized digital clock
signals. This is accomplished by using the on-board self-biasing
comparator that converts the sinusoidal signal of the DAC to a
square wave. The output from the DAC can be filtered externally
before being applied to the comparator input. The comparator
reference voltage is the time average of the signal applied to VIN.
The comparator can accept signals in the range of approximately
100 mV p-p to 1 V p-p. As the comparator input is ac-coupled, to
operate correctly as a zero crossing detector, it requires a minimum
input frequency of typically 3 MHz. The comparator output is a
square wave with an amplitude from 0 V to DVDD.
Rev. B | Page 15 of 32
AD9834
REGULATOR
The AD9834 is a sampled signal with its output following
Nyquist sampling theorem. Specifically, its output spectrum
contains the fundamental plus aliased signals (images) that
occur at multiples of the reference clock frequency and the
selected output frequency. A graphical representation of the
sampled spectrum, with aliased images, is shown in Figure 28.
The AD9834 has separate power supplies for the analog and
digital sections. AVDD provides the power supply required for
the analog section, and DVDD provides the power supply for
the digital section. Both of these supplies can have a value of
2.3 V to 5.5 V and are independent of each other. For example,
the analog section can be operated at 5 V, and the digital section
can be operated at 3 V, or vice versa.
The prominence of the aliased images is dependent on the ratio
of fOUT to MCLK. If ratio is small the aliased images are very
prominent and of a relatively high energy level as determined by
the sin(x)/x roll-off of the quantized DAC output. In fact,
depending on the fOUT/reference clock relationship, the first
aliased image can be on the order of −3 dB below the
fundamental.
The internal digital section of the AD9834 is operated at 2.5 V.
An on-board regulator steps down the voltage applied at DVDD
to 2.5 V. The digital interface (serial port) of the AD9834 also
operates from DVDD. These digital signals are level shifted
within the AD9834 to make them 2.5 V compatible.
A low-pass filter is generally placed between the output of the
DAC and the input of the comparator to further suppress the
effects of aliased images. Obviously, consideration must be
given to the relationship of the selected output frequency and
the reference clock frequency to avoid unwanted (and
unexpected) output anomalies. To apply the AD9834 as a clock
generator, limit the selected output frequency to
