11 mW Power, 2.3 V to 5.5 V,
Complete DDS
AD9838
FEATURES
Capability for phase modulation and frequency modulation is
provided. The frequency registers are 28 bits wide: with a 16 MHz
clock rate, resolution of 0.06 Hz can be achieved; with a 5 MHz
clock rate, the AD9838 can be tuned to 0.02 Hz resolution.
Frequency and phase modulation are configured by loading
registers through the serial interface and by toggling the registers
using software or the FSELECT and PSELECT pins, respectively.
2.3 V to 5.5 V power supply
MCLK speed: 16 MHz (B grade), 5 MHz (A grade)
Output frequency up to 8 MHz
Sinusoidal and triangular outputs
On-board comparator
3-wire SPI interface
Extended temperature range: −40°C to +125°C
Power-down option
11 mW power consumption at 2.3 V
20-lead LFCSP
The AD9838 is written to via a 3-wire serial interface. This serial
interface operates at clock rates up to 40 MHz and is compatible
with DSP and microcontroller standards.
The device operates with a power supply from 2.3 V to 5.5 V. The
analog and digital sections are independent and can be run from
different power supplies; for example, AVDD can equal 5 V with
DVDD equal to 3 V.
APPLICATIONS
Frequency stimulus/waveform generation
Frequency phase tuning and modulation
Low power RF/communications systems
Liquid and gas flow measurement
Sensory applications: proximity, motion, and defect detection
Test and medical equipment
The AD9838 has a power-down pin (SLEEP) that allows external
control of the power-down mode. Sections of the device that are
not being used can be powered down to minimize current consumption. For example, the DAC can be powered down when
a clock output is being generated.
GENERAL DESCRIPTION
The AD9838 is available in a 20-lead LFCSP_WQ package.
The AD9838 is a low power DDS device capable of producing high
performance sine and triangular outputs. It also has an on-board
comparator that allows a square wave to be produced for clock
generation. Consuming only 11 mW of power at 2.3 V, the
AD9838 is an ideal candidate for power-sensitive applications.
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DGND
DVDD
REFOUT
CAP/2.5V
ON-BOARD
REFERENCE
REGULATOR
MCLK
VCC
2.5V
FULL-SCALE
CONTROL
FSELECT
28-BIT FREQ0
REG
PHASE
ACCUMULATOR
(28-BIT)
MUX
28-BIT FREQ1
REG
FSADJUST
Ȉ
12
SIN
ROM
10-BIT
DAC
MUX
COMP
IOUT
IOUTB
MSB
12-BIT PHASE0 REG
12-BIT PHASE1 REG
MUX
MUX
DIVIDE
BY 2
16-BIT CONTROL
REGISTER
MUX
SIGN BIT OUT
SERIAL INTERFACE
AND
CONTROL LOGIC
COMPARATOR
VIN
FSYNC
SCLK
SDATA
PSELECT
SLEEP RESET
09077-001
AD9838
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
AD9838
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Description.................................................................. 17
Applications....................................................................................... 1
Serial Interface ............................................................................ 17
General Description ......................................................................... 1
Latency Period ............................................................................ 17
Functional Block Diagram .............................................................. 1
Control Register ......................................................................... 17
Revision History ............................................................................... 2
Frequency and Phase Registers ................................................ 19
Specifications..................................................................................... 3
Reset Function ............................................................................ 20
Timing Characteristics ................................................................ 5
Sleep Function ............................................................................ 20
Absolute Maximum Ratings............................................................ 6
SIGN BIT OUT Pin.................................................................... 21
Thermal Resistance ...................................................................... 6
IOUT and IOUTB Pins ............................................................. 21
ESD Caution.................................................................................. 6
Powering Up the AD9838 ......................................................... 21
Pin Configuration and Function Descriptions............................. 7
Applications Information .............................................................. 24
Typical Performance Characteristics ............................................. 9
Grounding and Layout .............................................................. 24
Test Circuit ...................................................................................... 12
Interfacing to Microprocessors................................................. 24
Terminology .................................................................................... 13
Evaluation Board ............................................................................ 26
Theory of Operation ...................................................................... 14
System Demonstration Platform.............................................. 26
Circuit Description......................................................................... 15
AD9838 to SPORT Interface..................................................... 26
Numerically Controlled Oscillator Plus Phase Modulator ... 15
Evaluation Kit ............................................................................. 26
SIN ROM ..................................................................................... 15
Crystal Oscillator vs. External Clock....................................... 26
Digital-to-Analog Converter (DAC) ....................................... 15
Power Supply............................................................................... 26
Comparator ................................................................................. 15
Evaluation Board Schematics ................................................... 27
Regulator...................................................................................... 16
Evaluation Board Layout........................................................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
REVISION HISTORY
4/11—Rev. 0 to Rev. A
Change to Title.................................................................................. 1
Change to Figure 3 ........................................................................... 5
Change to Figure 8 ........................................................................... 9
4/11—Revision 0: Initial Version
Rev. A | Page 2 of 32
AD9838
SPECIFICATIONS
AVDD = DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, TA = TMIN to TMAX, RSET = 6.8 kΩ, RLOAD = 200 Ω for IOUT and IOUTB, unless
otherwise noted.
Table 1.
Parameter 1
SIGNAL DAC SPECIFICATIONS
Resolution
Update Rate
A Grade
B Grade
IOUT Full Scale 2
VOUT Maximum
VOUT Minimum
Output Compliance 3
DC Accuracy
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
DDS SPECIFICATIONS
Dynamic Specifications
Signal-to-Noise Ratio (SNR)
A Grade
B Grade
Total Harmonic Distortion (THD)
A Grade
B Grade
Spurious-Free Dynamic Range (SFDR)
Wideband (0 to Nyquist)
A Grade
B Grade
Narrow-Band (±200 kHz)
A Grade
B Grade
Clock Feedthrough
A Grade
B Grade
Wake-Up Time
COMPARATOR
Input Voltage Range
Input Capacitance
Input High-Pass Cutoff Frequency
Input DC Resistance
Input Leakage Current
OUTPUT BUFFER
Output Rise/Fall Time
Output Jitter
VOLTAGE REFERENCE
Internal Reference
REFOUT Output Impedance 4
Reference TC
FSADJUST Voltage
Min
Typ
Max
10
Test Conditions/Comments
Bits
5
16
3.0
0.6
30
0.8
MSPS
MSPS
mA
V
mV
V
±1
±0.5
LSB
LSB
−63
−64
dB
dB
fMCLK = 5 MHz, fOUT = fMCLK/4096
fMCLK = 16 MHz, fOUT = fMCLK/4096
−64
−64
dBc
dBc
fMCLK = 5 MHz, fOUT = fMCLK/4096
fMCLK = 16 MHz, fOUT = fMCLK/4096
−68
−66
dBc
dBc
fMCLK = 5 MHz, fOUT = fMCLK/50
fMCLK = 16 MHz, fOUT = fMCLK/50
−97
−92
dBc
dBc
fMCLK = 5 MHz, fOUT = fMCLK/50
fMCLK = 16 MHz, fOUT = fMCLK/50
−68
−65
1
dBc
dBc
ms
fMCLK = 5 MHz, fOUT = reset
fMCLK = 16 MHz, fOUT = reset
V p-p
pF
MHz
MΩ
µA
AC-coupled internally
ns
ps rms
Using a 15 pF load
3 MHz sine wave 0.6 V p-p
1
10
3
5
10
12
120
1.11
Unit
1.18
1
100
1.14
1.24
Rev. A | Page 3 of 32
V
kΩ
ppm/°C
V
AD9838
Parameter 1
LOGIC INPUTS
Input High Voltage, VINH
Min
Typ
1.7
2.0
2.8
Input Low Voltage, VINL
Input Current, IINH/IINL
Input Capacitance, CIN
POWER SUPPLIES
AVDD
DVDD
IAA 5
IDD5
A Grade
B Grade
IAA + IDD5
A Grade
B Grade
Low Power Sleep Mode
A Grade
B Grade
Max
0.6
0.7
0.8
10
3
2.3
2.3
3.7
5.5
5.5
5
Unit
Test Conditions/Comments
V
V
V
V
V
V
µA
pF
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
2.3 V to 2.7 V power supply
2.7 V to 3.6 V power supply
4.5 V to 5.5 V power supply
V
V
mA
fMCLK = 16 MHz, fOUT = fMCLK/4096
IDD code dependent; see Figure 7
0.9
1.2
2
2.4
mA
mA
4.6
4.9
7
7.4
mA
mA
See Figure 6
DAC powered down; see Table 17
0.4
0.4
1
Operating temperature range is −40°C to +125°C; typical specifications are at 25°C.
For compliance with the specified load of 200 Ω, IOUT full scale should not exceed 4 mA.
Guaranteed by design.
4
Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
5
Measured with the digital inputs static and equal to 0 V or DVDD.
2
3
Rev. A | Page 4 of 32
mA
mA
AD9838
TIMING CHARACTERISTICS
DVDD = 2.3 V to 5.5 V, AGND = DGND = 0 V, unless otherwise noted.
Table 2.
Parameter 1
t1
t2
t3
t4
t5
t6
t7
t8
Limit at TMIN to TMAX
200/62.5
80/26
80/26
25
10
10
5
10
t4 − 5
5
3
8
8
5
t9
t10
t11
t11A
t12
1
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns min
Description
MCLK period (5 MHz/16 MHz)
MCLK high duration (5 MHz/16 MHz)
MCLK low duration (5 MHz/16 MHz)
SCLK period
SCLK high duration
SCLK low duration
FSYNC to SCLK falling edge setup time
SCLK falling edge to FSYNC rising edge time
Data setup time
Data hold time
FSELECT, PSELECT setup time before MCLK rising edge
FSELECT, PSELECT setup time after MCLK rising edge
SCLK high to FSYNC falling edge setup time
Guaranteed by design; not production tested.
Timing Diagrams
t1
09077-003
MCLK
t2
t3
Figure 2. Master Clock
MCLK
VALID DATA
VALID DATA
VALID DATA
09077-004
t11A
t11
FSELECT,
PSELECT
Figure 3. Control Timing
t5
t12
t4
SCLK
t7
t6
t8
FSYNC
t10
SDATA
D15
D14
D2
D1
Figure 4. Serial Timing
Rev. A | Page 5 of 32
D0
D15
D14
09077-005
t9
AD9838
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
AVDD to AGND
DVDD to DGND
AVDD to DVDD
AGND to DGND
CAP/2.5V
Digital I/O Voltage to DGND
Analog I/O Voltage to AGND
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Maximum Junction Temperature
Lead Temperature, Soldering (10 sec)
IR Reflow, Peak Temperature
Reflow Soldering (Pb Free)
Peak Temperature
Time at Peak Temperature
Rating
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
2.75 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
300°C
220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
20-Lead LFCSP_WQ (CP-20-10)
ESD CAUTION
260°C (+0/−5)
10 sec to 40 sec
Rev. A | Page 6 of 32
θJA
49.5
θJC
5.3
Unit
°C/W
AD9838
20
19
18
17
16
COMP
REFOUT
FSADJUST
IOUTB
IOUT
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
AD9838
TOP
VIEW
(Not to Scale)
15
14
13
12
11
AGND
VIN
SIGN BIT OUT
FSYNC
SCLK
NOTES
1. CONNECT EXPOSED PAD TO GROUND.
09077-006
FSELECT
PSELECT
RESET
SLEEP
SDATA
6
7
8
9
10
AVDD
DVDD
CAP/2.5V
DGND
MCLK
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
AVDD
2
DVDD
3
CAP/2.5V
4
5
DGND
MCLK
6
FSELECT
7
PSELECT
8
RESET
9
SLEEP
10
11
12
SDATA
SCLK
FSYNC
13
SIGN BIT OUT
14
VIN
15
16, 17
AGND
IOUT,
IOUTB
Description
Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V. A 0.1 µF decoupling
capacitor should be connected between AVDD and AGND.
Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V. A 0.1 µF decoupling
capacitor should be connected between DVDD and DGND.
The digital circuitry operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board
regulator when DVDD exceeds 2.7 V. The regulator requires a decoupling capacitor of 100 nF typical, which is
connected from CAP/2.5V to DGND. If DVDD is less than or equal to 2.7 V, CAP/2.5V should be shorted to DVDD.
Digital Ground.
Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The
output frequency accuracy and phase noise are determined by this clock.
Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase
accumulator. The frequency register to be used can be selected using the FSELECT pin or the FSEL bit. When
the FSEL bit is used to select the frequency register, the FSELECT pin should be tied to CMOS high or low.
Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added to the phase accumulator
output. The phase register to be used can be selected using the PSELECT pin or the PSEL bit. When the PSEL bit
is used to select the phase register, the PSELECT pin should be tied to CMOS high or low.
Active High Digital Input. This pin resets the appropriate internal registers to 0 (this corresponds to an analog
output of midscale). RESET does not affect any of the addressable registers.
Active High Digital Input. When this pin is high, the DAC is powered down. This pin has the same function as
the SLEEP12 control bit.
Serial Data Input. The 16-bit serial data-word is applied to this input.
Serial Clock Input. Data is clocked into the AD9838 on each falling edge of SCLK.
Active Low Control Input. FSYNC is the frame synchronization signal for the input data. When FSYNC is taken
low, the internal logic is informed that a new word is being loaded into the device.
Logic Output. The comparator output is available on this pin or, alternatively, the MSB from the NCO can be
output on this pin. Setting the OPBITEN bit in the control register to 1 enables this output pin. The SIGN/PIB bit
determines whether the comparator output or the MSB from the NCO is output on this pin.
Input to Comparator. The comparator can be used to generate a square wave from the sinusoidal DAC output.
The DAC output should be filtered appropriately before it is applied to the comparator to reduce jitter. When
the OPBITEN and SIGN/PIB bits in the control register are set to 1, the comparator input is connected to VIN.
Analog Ground.
Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω should be connected
between IOUT and AGND. IOUTB should be tied to AGND through an external load resistor of 200 Ω, but it can
be tied directly to AGND. A 20 pF capacitor to AGND is also recommended to prevent clock feedthrough.
Rev. A | Page 7 of 32
AD9838
Pin No.
18
Mnemonic
FSADJUST
19
20
REFOUT
COMP
EP
Description
Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND to determine the magnitude
of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows:
IOUT FULL SCALE = 18 × FSADJUST/RSET
FSADJUST = 1.14 V nominal, RSET = 6.8 kΩ typical
Voltage Reference Output. The AD9838 has an internal 1.20 V reference that is available at this pin.
DAC Bias Pin. This pin is used for decoupling the DAC bias voltage.
Exposed Pad. Connect the exposed pad to ground.
Rev. A | Page 8 of 32
AD9838
TYPICAL PERFORMANCE CHARACTERISTICS
–40
6.0
VDD = 5V
–50
5.0
–55
VDD = 3V
SFDR (dB)
IDD + IAA (mA)
AVDD = DVDD = 3V
TA = 25°C
0Hz TO NYQUIST
–45
5.5
4.5
–60
MCLK/7
–65
4.0
–70
MCLK/50
3.5
0
2
4
6
8
10
12
MCLK FREQUENCY (MHz)
14
16
18
–80
09077-020
3.0
1
Figure 6. Typical Current Consumption (IDD + IAA) vs. MCLK Frequency
for fOUT = MCLK/10
Figure 9. Wideband SFDR vs. MCLK Frequency
–40
2.5
–45
2.0
VDD = 5V
–50
1.5
SNR (dB)
IDD (mA)
16
6
11
MCLK FREQUENCY (MHz)
09077-023
–75
VDD = 3V
1.0
–55
–60
0.5
0
2
4
6
8
10
12
MCLK FREQUENCY (MHz)
14
16
18
–70
09077-021
0
0
2
Figure 7. Typical Current Consumption (IDD) vs. MCLK Frequency
for fOUT = MCLK/10
4
6
8
10
12
MCLK FREQUENCY (MHz)
16
18
120
140
Figure 10. SNR vs. MCLK Frequency
–91
1000
AVDD = DVDD = 3V
TA = 25°C
±200kHz
–92
900
–93
WAKE-UP TIME (µs)
VDD = 2.3V
–94
MCLK/50
–95
MCLK/7
–96
800
VDD = 5.5V
700
600
–97
500
–99
0
2
4
6
8
10
12
MCLK FREQUENCY (MHz)
14
16
400
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
100
Figure 11. Wake-Up Time vs. Temperature
Figure 8. Narrow-Band SFDR vs. MCLK Frequency
Rev. A | Page 9 of 32
09077-037
–98
09077-022
SFDR (dB)
14
09077-024
–65
AD9838
1.180
0
–10
1.178
VDD = 2.7V
–20
1.176
–30
VDD = 5.0V
POWER (dB)
VREF (V)
1.174
1.172
1.170
–40
–50
–60
–70
1.168
–80
1.166
0
20
40
60
80
TEMPERATURE (°C)
100
120
140
09077-038
–20
–100
0
Figure 12. VREF vs. Temperature
20
30
40
50
60
70
FREQUENCY (kHz)
80
90
100
Figure 15. Power vs. Frequency, fMCLK = 16 MHz, fOUT = 3.8 kHz,
Frequency Word = 0x000FBA9
0.20
0
0.18
–10
DVDD = 3.3V
0.16
DVDD = 2.3V
–20
DVDD = 5.5V
0.14
–30
POWER (dB)
0.12
0.10
0.08
–40
–50
–60
0.06
–70
0.04
–80
0.02
–90
–20
0
20
40
60
TEMPERATURE (°C)
80
100
–100
09077-045
0
–40
0
10
20
30
40
50
60
70
FREQUENCY (kHz)
80
90
100
09077-048
DVDD (V)
10
09077-047
–90
1.164
–40
Figure 16. Power vs. Frequency, fMCLK = 5 MHz, fOUT = 1.2 kHz,
Frequency Word = 0x000FBA9
Figure 13. SIGN BIT OUT Pin, Low Level, ISINK = 1 mA
0
5.5
DVDD = 5.5V
–10
5.0
–20
4.5
DVDD = 4.5V
–30
POWER (dB)
3.5
DVDD = 3.3V
3.0
–40
–50
–60
–70
DVDD = 2.7V
2.5
–80
DVDD = 2.3V
1.5
–40
–20
0
20
40
60
TEMPERATURE (°C)
–90
80
Figure 14. SIGN BIT OUT Pin, High Level, ISINK = 1 mA
100
–100
0
0.5
1.0
1.5
FREQUENCY (MHz)
2.0
2.5
09077-049
2.0
09077-046
DVDD (V)
4.0
Figure 17. Power vs. Frequency, fMCLK = 5 MHz, fOUT = 0.714 MHz = fMCLK/7,
Frequency Word = 0x2492492
Rev. A | Page 10 of 32
AD9838
0
–10
–20
POWER (dB)
–30
–40
–50
–60
–70
–90
0
1
2
3
4
5
FREQUENCY (MHz)
6
7
8
09077-050
–80
Figure 18. Power vs. Frequency, fMCLK = 16 MHz, fOUT = 2.28 MHz,
Frequency Word = 0x2492492
Rev. A | Page 11 of 32
AD9838
TEST CIRCUIT
RSET
6.8k
10nF
CAP/2.5V
REGULATOR
REFOUT
ON-BOARD
REFERENCE
12
AD9838
SIN
ROM
FSADJUST
FULL-SCALE
CONTROL
10-BIT DAC
AVDD
COMP
IOUT
Figure 19. Test Circuit Used to Test Specifications
Rev. A | Page 12 of 32
10nF
RLOAD
200
20pF
09077-002
100nF
AD9838
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation of any code from a straight line
passing through the endpoints of the transfer function. The
endpoints of the transfer function are zero scale, a point 0.5 LSB
below the first code transition (000 … 00 to 000 … 01), and full
scale, a point 0.5 LSB above the last code transition (111 … 10
to 111 … 11). The error is expressed in LSBs.
Total Harmonic Distortion (THD)
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the rms value of the fundamental. For the AD9838,
THD is defined as
Differential Nonlinearity (DNL)
DNL is the difference between the measured and ideal 1 LSB
change between two adjacent codes in the DAC. A specified
DNL of ±1 LSB maximum ensures monotonicity.
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through sixth harmonics.
Output Compliance
Output compliance refers to the maximum voltage that can be
generated at the output of the DAC to meet the specifications.
When voltages greater than that specified for the output compliance are generated, the AD9838 may not meet the specifications
listed in the data sheet.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency. The value for SNR is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at
the output of a DDS device. The spurious-free dynamic range
(SFDR) refers to the largest spur or harmonic present in the
band of interest. The wideband SFDR gives the magnitude of
the largest spur or harmonic relative to the magnitude of the
fundamental frequency in the 0 to Nyquist bandwidth. The
narrow-band SFDR gives the attenuation of the largest spur or
harmonic in a bandwidth of ±200 kHz about the fundamental
frequency.
THD 20 log
V2 2 V3 2 V4 2 V5 2 V6 2
V1
Clock Feedthrough
There is feedthrough from the MCLK input to the analog
output. Clock feedthrough refers to the magnitude of the
MCLK signal relative to the fundamental frequency in the
output spectrum of the AD9838.
Rev. A | Page 13 of 32
AD9838
THEORY OF OPERATION
Sine waves are typically thought of in terms of their magnitude
form: a(t) = sin(ωt). However, sine waves are nonlinear and not
easy to generate except through piecewise construction. On the
other hand, the angular information is linear in nature; that is,
the phase angle rotates through a fixed angle for each unit of
time. The angular rate depends on the frequency of the signal
by the traditional rate of ω = 2πf.
MAGNITUDE
Knowing that the phase of a sine wave is linear and given a
reference interval (clock period), the phase rotation for that
period can be determined as follows:
ΔPhase = ωΔt
Solving for ω,
ω = ΔPhase/Δt = 2πf
6ʌ
f = ΔPhase × fMCLK∕2π
4ʌ
2ʌ
–1
2ʌ
PHASE
4ʌ
6ʌ
09077-025
228
(2)
Solving for f and substituting the reference clock frequency for
the reference period (1/fMCLK = Δt),
+1
0
(1)
0
(3)
The AD9838 builds the output based on this simple equation. A
simple DDS chip can implement this equation with three major
subcircuits: numerically controlled oscillator (NCO) plus phase
modulator, SIN ROM, and digital-to-analog converter (DAC).
Each subcircuit is described in the Circuit Description section.
Figure 20. Sine Wave
Rev. A | Page 14 of 32
AD9838
CIRCUIT DESCRIPTION
The AD9838 is a fully integrated direct digital synthesis (DDS)
chip. The chip requires one reference clock, one low precision
resistor, and eight decoupling capacitors to provide digitally
created sine waves up to 8 MHz. In addition to the generation
of this RF signal, the chip is fully capable of a broad range of
simple and complex modulation schemes. These modulation
schemes are fully implemented in the digital domain, allowing
accurate and simple realization of complex modulation algorithms using DSP techniques.
The internal circuitry of the AD9838 consists of the following
main sections: a numerically controlled oscillator (NCO),
frequency and phase modulators, SIN ROM, a digital-to-analog
converter, a comparator, and a regulator.
NUMERICALLY CONTROLLED OSCILLATOR PLUS
PHASE MODULATOR
The AD9838 consists of two frequency select registers, a phase
accumulator, two phase offset registers, and a phase offset adder.
The main component of the NCO is a 28-bit phase accumulator.
Continuous time signals have a phase range of 0 to 2π. Outside
this range of numbers, the sinusoid functions repeat themselves
in a periodic manner. The digital implementation is no different.
The accumulator simply scales the range of phase numbers into
a multibit digital word. The phase accumulator in the AD9838
is implemented with 28 bits. Therefore, in the AD9838, 2π = 228.
Likewise, the ΔPhase term is scaled into this range of numbers:
0 < ΔPhase < 228 − 1
With these substitutions, Equation 3 becomes
f = ΔPhase × fMCLK∕228
(4)
28
where 0 < ΔPhase < 2 − 1.
The input to the phase accumulator can be selected from either
the FREQ0 register or the FREQ1 register and is controlled by
the FSELECT pin or the FSEL bit in the control register. NCOs
inherently generate continuous phase signals, thus avoiding any
output discontinuity when switching between frequencies.
Following the NCO, a phase offset can be added to perform
phase modulation using the 12-bit phase registers. The contents
of one of these phase registers is added to the MSBs of the NCO.
The AD9838 has two phase registers; their resolution is 2π/4096.
SIN ROM
To make the output from the NCO useful, it must be converted
from phase information into a sinusoidal value. Because phase
information maps directly to amplitude, the SIN ROM uses the
digital phase information as an address to a lookup table and
converts the phase information into amplitude.
Although the NCO contains a 28-bit phase accumulator, the
output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary
because a lookup table of 228 entries would be required. It is only
necessary to have sufficient phase resolution such that the errors
due to truncation are smaller than the resolution of the 10-bit
DAC. Therefore, the SIN ROM must have two bits of phase
resolution more than the 10-bit DAC.
The SIN ROM is enabled using the OPBITEN and MODE bits
(Bit D5 and Bit D1) in the control register (see Table 19).
DIGITAL-TO-ANALOG CONVERTER (DAC)
The AD9838 includes a high impedance, current source, 10-bit
DAC capable of driving a wide range of loads. The full-scale
output current can be adjusted for optimum power and external
load requirements using a single external resistor (RSET).
The DAC can be configured for single-ended or differential
operation. The IOUT and IOUTB pins can be connected through
equal external resistors to AGND to develop complementary
output voltages. The load resistors can be of any value required,
as long as the full-scale voltage developed across them does not
exceed the output compliance range. Because full-scale current
is controlled by RSET, adjustments to RSET can balance changes
made to the load resistors.
COMPARATOR
The AD9838 can be used to generate synthesized digital clock
signals. This is accomplished by using the on-board self-biasing
comparator that converts the sinusoidal signal of the DAC to a
square wave. The output from the DAC can be filtered externally
before being applied to the comparator input. The comparator
reference voltage is the time average of the signal applied to VIN.
The comparator can accept signals in the range of approximately
100 mV p-p to 1 V p-p. The comparator input is ac-coupled;
therefore, to operate correctly as a zero-crossing detector, the
comparator requires a minimum input frequency of 3 MHz typical. The comparator output is a square wave with an amplitude
from 0 V to DVDD.
The AD9838 provides a sampled signal with its output following Nyquist sampling theorem. Specifically, its output spectrum
contains the fundamental plus aliased signals (images) that occur
at multiples of the reference clock frequency and the selected
output frequency. A graphical representation of the sampled
spectrum, with aliased images, is shown in Figure 21.
Rev. A | Page 15 of 32
AD9838
REGULATOR
The prominence of the aliased images depends on the ratio of
fOUT to MCLK. If the ratio is small, the aliased images are very
prominent and of a relatively high energy level as determined by
the sin(x)/x roll-off of the quantized DAC output. In fact, depending on the fOUT/reference clock ratio, the first aliased image can
be on the order of −3 dB below the fundamental.
The AD9838 has separate power supplies for the analog and
digital sections. AVDD provides the power supply required for
the analog section, and DVDD provides the power supply for
the digital section. Both supplies can have a value of 2.3 V to
5.5 V and are independent of each other. For example, the
analog section can be operated at 5 V, and the digital section
can be operated at 3 V, or vice versa.
A low-pass filter is generally placed between the output of the
DAC and the input of the comparator to further suppress the
effects of aliased images. To avoid unwanted (and unexpected)
output anomalies, it is necessary to consider the relationship of
the selected output frequency and the reference clock frequency.
The internal digital section of the AD9838 is operated at 2.5 V.
An on-board regulator steps down the voltage applied at DVDD
to 2.5 V. The digital interface (serial port) of the AD9838 also
operates from DVDD. These digital signals are level shifted
within the AD9838 to make them 2.5 V compatible.
To apply the AD9838 as a clock generator, limit the selected
output frequency to
