a
10-Bit 40 MSPS CCD Signal Processor
with Integrated Timing Driver
AD9847
FEATURES
Correlated Double Sampler (CDS)
–2 dB to +10 dB Pixel Gain Amplifier (PxGA®)
2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA)
10-Bit 40 MHz A/D Converter
Black Level Clamp with Variable Level Control
Complete On-Chip Timing Driver
Precision Timing™ Core with 500 ps
Resolution at 40 MSPS
On-Chip 5 V Horizontal and RG Drivers
48-Lead LQFP Package
GENERAL DESCRIPTION
The AD9847 is a highly integrated CCD signal processor for
digital still camera applications. The AD9847 includes a complete analog front end with A/D conversion, combined with
a programmable timing driver. The Precision Timing core allows
adjustment of high speed clocks with approximately 500 ps
resolution at clock speeds of 40 MHz.
The AD9847 is specified at pixel rates of 40 MHz. The analog
front end includes black level clamping, CDS, PxGA, VGA, and a
10-bit A/D converter. The timing driver provides the high speed
CCD clock drivers for RG and H1–H4. Operation is programmed
using a 3-wire serial interface.
APPLICATIONS
Digital Still Cameras
Packaged in a space-saving 48-lead LQFP, the AD9847 is specified over an operating temperature range of –20°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
VRT
4 6dB
2dB TO 36dB
VRB
VREF
10
CDS
CCDIN
CLAMP
DOUT
ADC
VGA
PxGA
CLAMP
INTERNAL
CLOCKS
CLPOB
CLPDM
RG
H1–H4
4
HORIZONTAL
DRIVERS
AD9847
PBLK
PRECISION
TIMING
CORE
CLI
SYNC
GENERATOR
HD
VD
INTERNAL
REGISTERS
SL
SCK
SDATA
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2003 Analog Devices, Inc.
AD9847–SPECIFICATIONS
GENERAL SPECIFICATIONS
Parameter
Min
TEMPERATURE RANGE
Operating
Storage
–20
–65
MAXIMUM CLOCK RATE
40
POWER SUPPLY VOLTAGE
Analog (AVDD1, 2, 3)
Digital1 (DVDD1) H1–H4
Digital2 (DVDD2) RG
Digital3 (DVDD3) D0–D11
Digital4 (DVDD4) All Other Digital
Typ
Unit
+85
+150
°C
°C
MHz
2.7
3.0
3.0
POWER DISSIPATION
DVDD1 (@ 5 V, 100 pF H Loading, 40 MSPS)
DVDD2 (@ 5 V, 20 pF RG Loading, 40 MSPS)
DVDD1 (@ 3 V, 100 pF H Loading, 40 MSPS)
DVDD2 (@ 3 V, 20 pF H Loading, 40 MSPS)
AVDD1, 2, 3, DVDD3, 4 (@ 3 V, 40 MSPS)
Total Shutdown Mode
Max
3.6
5.5
5.5
3.0
3.0
V
V
V
V
V
450
45
180
15
200
1
mW
mW
mW
mW
mW
mW
Specifications subject to change without notice.
DIGITAL SPECIFICATIONS
(TMIN to TMAX, AVDD1 = DVDD3, DVDD4 = 2.7 V, DVDD1, DVDD2 = 5.25 V, CL = 20 pF, unless
otherwise noted.)
Parameter
Symbol
Min
LOGIC INPUTS
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
VIH
VIL
IIH
IIL
CIN
2.1
LOGIC OUTPUTS
High Level Output Voltage, IOH = 2 mA
Low Level Output Voltage, IOL = 2 mA
VOH
VOL
2.2
CLI INPUT
High Level Input Voltage
(AVDD1, 2 + 0.5 V)
Low Level Input Voltage
VIH–CLI
VIL–CLI
1.85
VOH
VOL
4.75
RG AND H-DRIVER OUTPUTS
High Level Output Voltage
(DVDD1, 2 – 0.5 V)
Low Level Output Voltage
Maximum Output Current (Programmable)
Maximum Load Capacitance
Typ
Max
0.6
10
10
10
V
V
µA
µA
pF
0.5
V
V
0.85
V
V
0.5
24
100
Unit
V
V
mA
pF
Specifications subject to change without notice.
–2–
REV. A
AD9847
ANALOG SPECIFICATIONS (T
MIN
Parameter
to TMAX, AVDD = DVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted.)
Min
CDS
Gain
Allowable CCD Reset Transient*
Max Input Range before Saturation*
Max CCD Black Pixel Amplitude*
PIXEL GAIN AMPLIFIER (PxGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Min Gain (32)
Med Gain (0)
Max Gain (31)
VARIABLE GAIN AMPLIFIER (VGA)
Max Input Range
Max Output Range
Gain Control Resolution
Gain Monotonicity
Gain Range
Low Gain (91)
Max Gain (1023)
Max
0
500
Unit
150
1.0
1.6
V p-p
V p-p
Steps
64
Guaranteed
–2
4
10
dB
dB
dB
1.6
2.0
2
36
dB
dB
256
Steps
0
63.75
LSB
LSB
Measured at ADC Output
10
± 0.4
Guaranteed
2.0
± 1.0
Bits
LSB
V
2.0
1.0
V
V
SYSTEM PERFORMANCE
Specifications Include Entire
Signal Chain
Gain Includes 4 dB Default PxGA
5
6
38
0.2
0.25
40
7
*Input signal characteristics defined as follows:
500mV TYP
RESET
TRANSIENT
150mV MAX
OPTICAL
BLACK PIXEL
1V MAX
INPUT
SIGNAL RANGE
Specifications subject to change without notice.
REV. A
Med Gain (4 dB) Is Default Setting
V p-p
V p-p
Steps
1024
Guaranteed
VOLTAGE REFERENCE
Reference Top Voltage (VRT)
Reference Bottom Voltage (VRB)
Gain Accuracy
Low Gain (91)
Max Gain (1023)
Peak Nonlinearity, 500 mV Input Signal
Total Output Noise
Power Supply Rejection (PSR)
Notes
dB
mV
V p-p
mV
1.0
BLACK LEVEL CLAMP
Clamp Level Resolution
Clamp Level
Min Clamp Level (0)
Max Clamp Level (255)
A/D CONVERTER
Resolution
Differential Nonlinearity (DNL)
No Missing Codes
Full-Scale Input Voltage
Typ
–3–
dB
dB
%
LSB rms
dB
12 dB Gain Applied
AC Grounded Input, 6 dB Gain Applied
Measured with Step Change on Supply
AD9847
TIMING SPECIFICATIONS (C to 29 pF, f
L
Parameter
MASTER CLOCK (CLI)
CLI Clock Period
CLI High/Low Pulsewidth
Delay from CLI to Internal Pixel
Period Position
CLI =
40 MHz, Serial Timing in Figures 3a and 3b, unless otherwise noted.)
Symbol
Min
tCLI
tADC
25
12.5
tCLIDLY
EXTERNAL MODE CLAMPING
CLPDM Pulsewidth
CLPOB Pulsewidth*
tCDM
tCOB
4
2
SAMPLE CLOCKS
SHP Rising Edge to SHD Rising Edge
tS1
10
DATA OUTPUTS
Output Delay from Programmed Edge
Pipeline Delay
SERIAL INTERFACE
Maximum SCK Frequency
SL to SCK Setup Time
SCK to SL Hold Time
SDATA Valid to SCK Rising Edge Setup
SCK Falling Edge to SDATA Valid Hold
SCK Falling Edge to SDATA Valid Read
Typ
Max
ns
ns
6
ns
10
20
Pixels
Pixels
ns
6
9
tOD
10
10
10
10
10
10
fSCLK
tLS
tLH
tDS
tDH
tDV
Unit
ns
Cycles
MHz
ns
ns
ns
ns
ns
*Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.
Specifications subject to change without notice.
–4–
REV. A
AD9847
ABSOLUTE MAXIMUM RATINGS
AVDD1, 2, 3 to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V
DVDD1, 2 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +5.5 V
DVDD3, 4 to DVSS . . . . . . . . . . . . . . . . . . . . –0.3 to +3.9 V
Digital Outputs to DVSS3 . . . . . . . . –0.3 to DVDD3 + 0.3 V
CLPOB, CLPDM, BLK to DVSS4 . –0.3 to DVDD4 + 0.3 V
CLI to AVSS . . . . . . . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
SCK, SL, SDATA to DVSS4 . . . . . –0.3 to DVDD4 + 0.3 V
VRT, VRB to AVSS . . . . . . . . . . . . . –0.3 to AVDD + 0.3 V
BYP1–3, CCDIN to AVSS . . . . . . . . –0.3 to AVDD + 0.3 V
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Lead Temperature (10 sec) . . . . . . . . . . . . . . . . . . . . . . 300°C
THERMAL CHARACTERISTICS
Thermal Resistance
48-Lead LQFP Package . . . . . . . . . . . . . . . . . . . JA = 92°C/W
ORDERING GUIDE
Model
Temperature
Range
Package
Description
Package
Option
AD9847AKST
–20°C to +85°C
Thin Plastic Quad Flatpack (LQFP)
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9847 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. A
–5–
AD9847
SDI
SCK
CLPOB
CLPDM
HBLK
PBLK
VD
HD
DVSS4
DVDD4
NC
NC
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
(LSB) D0
1
PIN 1
IDENTIFIER
D1 2
D2 3
D3 4
D4 5
DVSS3 6
AD9847
TOP VIEW
(Not to Scale)
DVDD3 7
D5 8
36
SL
35
REFT
34
REFB
33
CMLEVEL
32
AVSS3
31
AVDD3
30
BYP3
29 CCDIN
D6 9
D7 10
28
BYP2
BYP1
26 AVDD2
27
D8 11
(MSB) D9 12
25
AVSS2
AVDD1
CLI
AVSS1
DVDD2
RG
DVSS2
H4
H3
DVDD1
DVSS1
NC = NO CONNECT
H2
H1
13 14 15 16 17 18 19 20 21 22 23 24
PIN FUNCTION DESCRIPTIONS
Pin No.
Mnemonic
Type*
Description
1–5
6
7
8–12
13, 14
15
16
17, 18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47, 48
D0–D4
DVSS3
DVDD3
D5–D9
H1, H2
DVSS1
DVDD1
H3, H4
DVSS2
RG
DVDD2
AVSS1
CLI
AVDD1
AVSS2
AVDD2
BYP1
BYP2
CCDIN
BYP3
AVDD3
AVSS3
CMLEVEL
REFB
REFT
SL
SDI
SCK
CLPOB
CLPDM
HBLK
PBLK
VD
HD
DVSS4
DVDD4
NC
DO
P
P
DO
DO
P
P
DO
P
DO
P
P
DI
P
P
P
AO
AO
AI
AO
P
P
AO
AO
AO
DI
DI
DI
DI
DI
DI
DI
DI
DI
P
P
NC
Data Outputs
Digital Ground 3—Data Outputs
Digital Supply 3—Data Outputs
Data Outputs (D9 IS MSB)
Horizontal Clocks (to CCD)
Digital Ground 1—H Drivers
Digital Supply 1—H Drivers
Horizontal Clocks (to CCD)
Digital Ground 1—RG Driver
Reset Gate Clock (to CCD)
Digital Supply 2—RG Driver
Analog Ground 1
Master Clock Input
Analog Supply 1
Analog Ground 2
Analog Supply 2
Bypass Pin (0.1 µF to AVSS)
Bypass Pin (0.1 µF to AVSS)
Analog Input for CCD Signal
Bypass Pin (0.1 µF to AVSS)
Analog Supply 3
Analog Ground 3
Internal Bias Level Decoupling (0.1 µF to AVSS)
Reference Bottom Decoupling (1.0 µF to AVSS)
Reference Top Decoupling (1.0 µF to AVSS)
3-Wire Serial Load (from µP)
3-Wire Serial Data Input (from µP)
3-Wire Serial Clock (from µP)
Optical Black Clamp Pulse
Dummy Black Clamp Pulse
HCLK Blanking Pulse
Preblanking Pulse
Vertical Sync Pulse
Horizontal Sync Pulse
Digital Ground 4—VD, HD, CLPOB, CLPDM, HBLK, PBLK, SCK, SL, SDATA
Digital Supply 4—VD, HD, CLPOB, CLPDM, HBLK, PBLK, CK, SL
Internally Not Connected
*Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power
–6–
REV. A
AD9847
Equivalent Input/Output Circuits
AVDD2
DVDD4
R
330
AVSS2
AVSS2
DVSS4
Circuit 1. CCDIN (Pin 29)
Circuit 4. Digital Inputs (Pins 36–44)
AVDD1
DVDD1
DATA
330
25k
CLI
1.4V
ENABLE
OUTPUT
AVSS1
Circuit 2. CLI (Pin 23)
DVDD4
DVSS1
DVDD3
Circuit 5. H1–H4 and RG (Pins 13, 14, 17, 18, 20)
DATA
THREESTATE
DOUT
DVSS4
DVSS3
Circuit 3. Data Outputs D0–D9 (Pins 1–5, 8–12)
Typical Performance Characteristics
4
0.25
3
OUTPUT NOISE – LSB
0.50
0
–0.25
2
1
–0.50
0
200
400
0
600
800
1000
0
200
400
600
VGA GAIN CODE – LSB
800
1000
TPC 1. Typical DNL
TPC 2. Output Noise vs. VGA Gain Setting
REV. A
–7–
AD9847
SYSTEM OVERVIEW
V-DRIVER
Figures 1a and 1b show the typical system application diagrams
for the AD9847. The CCD output is processed by the AD9847’s
AFE circuitry, which consists of a CDS, PxGA, VGA, black
level clamp, and A/D converter. The digitized pixel information is
sent to the digital image processor chip, where all post-processing
and compression occurs. To operate the CCD, CCD timing parameters are programmed into the AD9847 from the image processor
through the 3-wire serial interface. From the system master clock,
CLI, provided by the image processor, the AD9847 generates
the high speed CCD clocks and all internal AFE clocks. All
AD9847 clocks are synchronized with VD and HD.
V1–V4, VSG1–VSG8, SUBCK
H1–H4, RG
DOUT
CLPOB
CCD
HD, VD
DIGITAL IMAGE
PROCESSING
ASIC
HBLK
SERIAL
INTERFACE
Figure 1b. Typical Application (External Mode)
Figure 2 shows the horizontal and vertical counter dimensions for
the AD9847. All internal horizontal clocking is programmed using
these dimensions to specify line and pixel locations.
DOUT
AD9847
PBLK
CLI
H1–H4, RG
INTEGRATED
AFE + TD
CLPDM
HD, VD
V1–V4, VSG1–VSG8, SUBCK
CCDIN
AD9847
INTEGRATED
AFE + TD
V-DRIVER
CCD
CCDIN
MAXIMUM FIELD DIMENSIONS
DIGITAL IMAGE
PROCESSING
ASIC
CLI
12-BIT HORIZONTAL = 4096 PIXELS MAX
SERIAL
INTERFACE
Figure 1a. Typical Application (Internal Mode)
12-BIT VERTICAL = 4096 LINES MAX
Figure 1a shows the AD9847 used in internal mode, in which all
the horizontal pulses (CLPOB, CLPDM, PBLK, and HBLK)
are programmed and generated internally. Figure 1b shows the
AD9847 operating in external mode, in which the horizontal
pulses are supplied externally by the image processor.
The H-drivers for H1–H4 and RG are included in the AD9847,
allowing these clocks to be directly connected to the CCD. The
AD9847 supports H-drive voltage of 5 V.
Figure 2. Vertical and Horizontal Counters
–8–
REV. A
AD9847
SERIAL INTERFACE TIMING
SDATA
A0
A1
A2
A3
t DS
A4
A5
A6
A7
D0
D1
D2
D3
D4
D5
XX
XX
t DH
SCK
t LS
t LH
SL
SL UPDATED
VD/HD UPDATED
VD
HD
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES.
2. 14 SCK EDGES ARE NEEDED TO WRITE ADDRESS AND DATA BITS.
3. FOR 16-BIT SYSTEMS, TWO EXTRA DUMMY BITS MAY BE WRITTEN. DUMMY BITS ARE IGNORED.
4. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.
Figure 3a. Serial Write Operation
DATA FOR STARTING
REGISTER ADDRESS
SDATA
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
D4
DATA FOR NEXT
REGISTER ADDRESS
D5
D0
D1
D2
D3
D4
D5
D0
D1
...
...
SCK
...
SL
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 6-BIT DATA-WORDS.
3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA-WORD (ALL SIX BITS MUST BE WRITTEN).
4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. NEW DATA IS UPDATED EITHER AT THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.
Figure 3b. Continuous Serial Write Operation
COMPLETE REGISTER LISTING
Table I. SL Updated Registers
Register
Description
Register
Description
oprmode
ctlmode
preventpdate
readback
vdhdpol
fieldval
hblkretime
tgcore_rstb
h12pol
h1posloc
h1negloc
AFE Operation Modes
AFE Control Modes
Prevents Loading of VD-Updated Registers
Enables Serial Register Readback Mode
VD/HD Active Polarity
Internal Field Pulse Value
Retimes the H1 hblk to Internal Clock
Reset Bar Signal for Internal TG Core
H1/H2 Polarity Control
H1 Positive Edge Location
H1 Negative Edge Location
h1drv
h2drv
h3drv
h4drv
rgpol
rgposloc
rgnegloc
rgdrv
shpposloc
shdposloc
H1 Drive Current
H2 Drive Current
H3 Drive Current
H4 Drive Current
RG Polarity
RG Positive Edge Location
RG Negative Edge Location
RG Drive Current
SHP Sample Location
SHD Sample Location
NOTES
All addresses and default values are expressed in hexadecimal.
All registers are VD/HD updated as shown in Figure 3a, except for those that are SL updated.
REV. A
D2
–9–
AD9847
clpdmscp3 register, the contents of Address 0x81 must be
written first, followed by the contents of Address 0x82. The
register will be updated after the completion of the write to
Register 0x82, either at the next SL rising edge or the next
VD/HD falling edge.
Accessing a Double-Wide Register
There are many double-wide registers in the AD9847, e.g.,
oprmode, clpdmtog1_0, and clpdmscp3, and so on. These registers are configured into two consecutive 6-bit registers with the
least significant six bits located in the lower of the two addresses
and the remaining most significant bits located in the higher of
the two addresses. For example, the six LSBs of the clpdmscp3
register, clpdmscp3[5:0], are located at address 0x81. The most
significant six bits of the clpdmscp3 register, clpdmscp3[11:6],
are located at Address 0x82. The following rules must be followed when accessing double-wide registers:
1. When accessing a double-wide register, BOTH addresses
must be written to.
2. The lower of the two consecutive addresses for the doublewide register must be written to first. In the example of the
Address
Bit
Content
3. A single write to the lower of the two consecutive addresses
of a double-wide register that is not followed by a write to the
higher address of the registers is not permitted. This will not
update the register.
4. A single write to the higher of the two consecutive addresses of a
double-wide register that is not preceded by a write to the lower
of the two addresses is not permitted. Although the write to the
higher address will update the full double-wide register, the
lower six bits of the register will be written with an indeterminate value if the lower address was not written to first.
Width
Default
Value
Register Name
Register Description
6
2
6
4
6
2
6
6
6
6
6
00
00
16
02
00
02
00
00
00
00
00
oprmode[5:0]
oprmode[7:6]
ccdgain[5:0]
ccdgain[9:6]
refblack[5:0]
refblack[7:6]
ctlmode
pxga gain0
pxga gain1
pxga gain2
pxga gain3
AFE Operation Mode (See AFE Register Breakdown)
AFE Registers # Bits 56
00
01
02
03
04
05
06
07
08
09
0A
[5:0]
[1:0]
[5:0]
[3:0]
[5:0]
[1:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
VGA Gain
Black Clamp Level
Control Mode (See AFE Register Breakdown)
PxGA Color 0 Gain
PxGA Color 1 Gain
PxGA Color 2 Gain
PxGA Color 3 Gain
Miscellaneous/Extra # Bits 26
0F
[5:0]
6
00
INITIAL2
16
17
18
19
1B
1C
[0]
[5:0]
[5:0]
[0]
[5:0]
[0]
1
6
6
1
6
1
00
00
00
00
00
00
out_cont
update[5:0]
update[11:6]
preventupdate
doutphase
disablerestore
1D
1E
[0]
[0]
1
1
00
01
vdhdpol
fieldval
1F
20
[0]
[5:0]
1
6
00
00
hblkretime
INITIAL1
26
[0]
1
00
tgcore_rstb
–10–
See Recommended Power Up Sequence Section. Should be
set to “4” decimal (000100).
Output Control (0 = Make All Outputs DC Inactive)
Serial Data Update Control (Sets the line within the field
for serial data update to occur)
Prevent the Update of the VD/HD Updated Registers
DOUT Phase Control
Disable CCDIN DC Restore Circuit During PBLK
(1 = Disable)
VD/HD Active Polarity (0 = Low Active, 1 = High Active)
Internal Field Pulse Value (0 = Next Field Odd,
1 = Next Field Even)
Re-Sync hblk to h1 Clock
See Recommended Power Up Sequence. Should be set to
“53” decimal (110101).
TG Core Reset_Bar (0 = Hold TG Core in Reset,
1 = Resume Normal Operation)
REV. A
AD9847
Address
Bit
Content
Width
Default
Value
Register Name
Register Description
1
1
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
0
2
6
6
2
6
6
2
6
6
2
01
00
01
2C
00
35
00
01
3E
02
16
03
00
3F
3F
3F
3F
01
3F
3F
3F
3F
00
00
3F
3F
00
3F
3F
00
3F
3F
00
clpdmdir
clpdmpol
clpdmspol0
clpdmtog1_0[5:0]
clpdmtog1_0[11:6]
clpdmtog2_0[5:0]
clpdmtog2_0[11:6]
clpdmspol1
clpdmtog1_1[5:0]
clpdmtog1_1[11:6]
clpdmtog2_1[5:0]
clpdmtog2_1[11:6]
clpdmspol2
clpdmtog1_2[5:0]
clpdmtog1_2[11:6]
clpdmtog2_2[5:0]
clpdmtog2_2[11:6]
clpdmspol3
clpdmtog1_3[5:0]
clpdmtog1_3[11:6]
clpdmtog2_3[5:0]
clpdmtog2_3[11:6]
clpdmscp0
clpdmsptr0
clpdmscp1[5:0]
clpdmscp1[11:6]
clpdmsptr1
clpdmscp2[5:0]
clpdmscp2[11:6]
clpdmsptr2
clpdmscp3[5:0]
clpdmscp3[11:6]
clpdmsptr3
CLPDM Internal/External (0 = Internal, 1 = External)
CLPDM External Active Polarity (0 = Low Active, 1 = High Active)
Sequence #0: Start Polarity for CLPDM
Sequence #0: Toggle Position 1 for CLPDM
CLPDM # Bits 146
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
[0]
[0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
7A
7B
7C
7D
7E
7F
80
81
82
83
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
REV. A
Sequence #0: Toggle Position 2 for CLPDM
Sequence #1: Start Polarity for CLPDM
Sequence #1: Toggle Position 1 for CLPDM
Sequence #1: Toggle Position 2 for CLPDM
Sequence #2: Start Polarity for CLPDM
Sequence #2: Toggle Position 1 for CLPDM
Sequence #2: Toggle Position 2 for CLPDM
Sequence #3: Start Polarity for CLPDM
Sequence #3: Toggle Position 1 for CLPDM
Sequence #3: Toggle Position 2 for CLPDM
CLPDM Sequence-Change-Position #0 (Hardcoded to 0)
CLPDM Sequence Pointer for SCP #0
CLPDM Sequence-Change-Position #1
CLPDM Sequence Pointer for SCP #1
CLPDM Sequence-Change-Position #2
CLPDM Sequence Pointer for SCP #2
CLPDM Sequence-Change-Position #3
CLPDM Sequence Pointer for SCP #3
–11–
AD9847
Address
Bit
Content
Width
Default
Value
Register Name
Register Description
1
1
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
0
2
6
6
2
6
6
2
6
6
2
01
00
01
0E
00
2B
00
01
2B
06
3F
3F
00
3F
3F
3F
3F
01
3F
3F
3F
3F
00
03
01
00
01
02
00
00
37
03
03
clpobdir
clpobpol
clpobpol0
clpobtog1_0[5:0]
clpobtog1_0[11:6]
clpobtog2_0[5:0]
clpobtog2_0[11:6]
clpobpol1
clpobtog1_1[5:0]
clpobtog1_1[11:6]
clpobtog2_1[5:0]
clpobtog2_1[11:6]
clpobspol2
clpobtog1_2[5:0]
clpobtog1_2[11:6]
clpobtog2_2[5:0]
clpobtog2_2[11:6]
clpobspol3
clpobtog1_3[5:0]
clpobtog1_3[11:6]
clpobtog2_3[5:0]
clpobtog2_3[11:6]
clpobscp0
clpobsptr0
clpobscp1[5:0]
clpobscp1[11:6]
clpobsptr1
clpobscp2[5:0]
clpobscp2[11:6]
clpobsptr2
clpobscp3[5:0]
clpobscp3[11:6]
clpobsptr3
CLPOB Internal/External (0 = Internal, 1 = External)
CLPOB External Active Polarity (0 = Low Active, 1 = High Active)
Sequence #0: Start Polarity for CLPOB
Sequence #0: Toggle Position 1 for CLPOB
CLPOB # Bits 146
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
[0]
[0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
–12–
Sequence #0: Toggle Position 2 for CLPOB
Sequence #1: Start Polarity for CLPOB
Sequence #1: Toggle Position 1 for CLPOB
Sequence #1: Toggle Position 2 for CLPOB
Sequence #2: Start Polarity for CLPOB
Sequence #2: Toggle Position 1 for CLPOB
Sequence #2: Toggle Position 2 for CLPOB
Sequence #3: Start Polarity for CLPOB
Sequence #3: Toggle Position 1 for CLPOB
Sequence #3: Toggle Position 2 for CLPOB
CLPOB Sequence-Change-Position #0 (Hardcoded to 0)
CLPOB Sequence Pointer for SCP #0
CLPOB Sequence-Change-Position #1
CLPOB Sequence Pointer for SCP #1
CLPOB Sequence-Change-Position #2
CLPOB Sequence Pointer for SCP #2
CLPOB Sequence-Change-Position #3
CLPOB Sequence Pointer for SCP #3
REV. A
AD9847
Address
Bit
Content
Width
Default
Value
Register Name
Register Description
HBLK # Bits 147
A4
A5
A6
[0]
[0]
[0]
1
1
1
01
00
01
hblkdir
hblkpol
hblkextmask
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
BB
BC
BD
BE
BF
C0
C1
C2
C3
C4
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
0
2
6
6
2
6
6
2
6
6
2
01
3E
00
0D
06
01
38
00
3C
02
00
3F
3F
3F
3F
01
3F
3F
3F
3F
00
00
3F
3F
00
3F
3F
00
3F
3F
00
hblkmask0
hblktog1_0[5:0]
hblktog1_0[11:6]
hblkbtog2_0[5:0]
hblkbtog2_0[11:6]
hblkmask1
hblktog1_1[5:0]
hblktog1_1[11:6]
hblktog2_1[5:0]
hblktog2_1[11:6]
hblkmask2
hblktog1_2[5:0]
hblktog1_2[11:6]
hblktog2_2[5:0]
hblktog2_2[11:6]
hblkmask3
hblktog1_3[5:0]
hblktog1_3[11:6]
hblktog2_3[5:0]
hblktog2_3[11:6]
hblkscp0
hblksptr0
hblkscp1[5:0]
hblkscp1[11:6]
hblksptr1
hblkscp2[5:0]
hblkscp2[11:6]
hblksptr2
hblkscp3[5:0]
hblkscp3[11:6]
hblksptr3
REV. A
HBLK Internal/External (0 = Internal, 1 = External)
HBLK External Active Polarity (0 = Low Active, 1 = High Active)
HBLK External Masking Polarity (0 = Mask H1 and H3 Low,
1 = Mask H1 and H3 High)
Sequence #0: Masking Polarity for HBLK
Sequence #0: Toggle Low Position for HBLK
Sequence #0: Toggle High Position for HBLK
Sequence #1: Masking Polarity for HBLK
Sequence #1: Toggle Low Position for HBLK
Sequence #1: Toggle High Position for HBLK
Sequence #2: Masking Polarity for HBLK
Sequence #2: Toggle Low Position for HBLK
Sequence #2: Toggle High Position for HBLK
Sequence #3: Masking Polarity for HBLK
Sequence #3: Toggle Low Position for HBLK
Sequence #3: Toggle High Position for HBLK
HBLK Sequence-Change-Position #0 (Hardcoded to 0)
HBLK Sequence Pointer for SCP #0
HBLK Sequence-Change-Position #1
HBLK Sequence Pointer for SCP #1
HBLK Sequence-Change-Position #2
HBLK Sequence Pointer for SCP #2
HBLK Sequence-Change-Position #3
HBLK Sequence Pointer for SCP #3
–13–
AD9847
Address
Bit
Content
Width
Default
Value
Register Name
Register Description
1
1
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
1
6
6
6
6
0
2
6
6
2
6
6
2
6
6
2
01
00
01
3D
00
2A
06
00
2A
06
3F
3F
00
3F
3F
3F
3F
01
3F
3F
3F
3F
00
02
01
00
01
02
00
00
37
03
02
pblkdir
pblkpol
pblkspol0
pblktog1_0[5:0]
pblktog1_0[11:6]
pblkbtog2_0[5:0]
pblkbtog2_0[11:6]
pblkspol1
pblktog1_1[5:0]
pblktog1_1[11:6]
pblktog2_1[5:0]
pblktog2_1[11:6]
pblkspol2
pblktog1_2[5:0]
pblktog1_2[11:6]
pblktog2_2[5:0]
pblktog2_2[11:6]
pblkspol3
pblktog1_3[5:0]
pblktog1_3[11:6]
pblktog2_3[5:0]
pblktog2_3[11:6]
pblkscp0
pblksptr0
pblkscp1[5:0]
pblkscp1[11:6]
pblksptr1
pblkscp2[5:0]
pblkscp2[11:6]
pblksptr2
pblkscp3[5:0]
pblkscp3[11:6]
pblksptr3
PBLK Internal/External (0 = Internal, 1 = External)
PBLK External Active Polarity (0 = Low Active, 1 = High Active)
Sequence #0: Start Polarity for PBLK
Sequence #0: Toggle Position 1 for PBLK
H1/H2 Polarity Control (0 = No Inversion, 1 = Inversion)
H1 Positive Edge Location
H1 Negative Edge Location
H1 Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA,
3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
H2 Drive Strength
H3 Drive Strength
H4 Drive Strength
RG Polarity Control (0 = No Inversion, 1 = Inversion)
RG Positive Edge Location
RG Negative Edge Location
RG Drive Strength (0 = OFF, 1 = 3.5 mA, 2 = 7 mA,
3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA)
SHP (Positive) Edge Sampling Location
SHD (Positive) Edge Sampling Location
PBLK # Bits 146
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
[0]
[0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
[0]
[5:0]
[5:0]
[5:0]
[5:0]
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
[5:0]
[5:0]
[1:0]
Sequence #0: Toggle Position 2 for PBLK
Sequence #1: Start Polarity for PBLK
Sequence #1: Toggle Position 1 for PBLK
Sequence #1: Toggle Position 2 for PBLK
Sequence #2: Start Polarity for PBLK
Sequence #2: Toggle Position 1 for PBLK
Sequence #2: Toggle Position 2 for PBLK
Sequence #3: Start Polarity for PBLK
Sequence #3: Toggle Position 1 for PBLK
Sequence #3: Toggle Position 2 for PBLK
PBLK Sequence-Change-Position #0 (Hardcoded to 0)
PBLK Sequence Pointer for SCP #0
PBLK Sequence-Change-Position #1
PBLK Sequence Pointer for SCP #1
PBLK Sequence-Change-Position #2
PBLK Sequence Pointer for SCP #2
PBLK Sequence-Change-Position #3
PBLK Sequence Pointer for SCP #3
H1–H4, RG, SHP, SHD # Bits 53
E5
E6
E7
E8
[0]
[5:0]
[5:0]
[2:0]
1
6
6
3
00
00
20
03
h1pol
h1posloc
h1negloc
h1drv
E9
EA
EB
EC
ED
EE
EF
[2:0]
[2:0]
[2:0]
[0]
[5:0]
[5:0]
[2:0]
3
3
3
1
6
6
3
03
03
03
00
00
10
02
h2drv
h3drv
h4drv
rgpol
rgposloc
rgnegloc
rgdrv
F0
F1
[5:0]
[5:0]
6
6
24
00
shpposloc
shdposloc
–14–
REV. A
AD9847
Address
Bit
Content
Width
Default
Value
Register Name
Register Description
AFE Register Breakdown
oprmode
[7:0]
Serial Address:
8'h00 {oprmode[5:0]}, 8'h01 {oprmode[7:6]}
8'h0
[1:0]
2'h0
2'h1
2'h2
2'h3
powerdown[1:0]
[2]
[3]
[4]
[5]
[6]
[7]
ctlmode
disblack
test mode
test mode
test mode
test mode
test mode
[5:0]
6'h0
[2:0]
Serial Address: 8'h06 {cltmode[5:0]}
3'h0
3'h1
3'h2
3'h3
3'h4
3'h5
3'h6
3'h7
[3]
[4]
ctlmode[2:0]
tristateout
PRECISION TIMING HIGH SPEED TIMING
GENERATION
Timing Resolution
The AD9847 generates flexible high speed timing signals using
the Precision Timing core. This core is the foundation for generating
the timing used for both the CCD and the AFE, the reset gate RG,
horizontal drivers H1–H4, and the SHP/SHD sample clocks.
A unique architecture makes it routine for the system designer to
optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling.
POSITION
Off
Mosaic Separate
VD Selected/Mosaic Interlaced
Mosaic Repeat
Three-Color
Three-Color II
Four-Color
Four-Color II
Enable PxGA (High Active)
Latch Output Data on Selected DOUT Edge
Leave Output Latch Transparent
ADC Outputs Are Driven
ADC Outputs Are Three-Stated
enablepxga
outputlat
1'h0
1'h1
1'h0
1'h1
[5]
Full Power
Fast Recovery
Reference Standby
Total Shutdown
Disable Black Loop Clamping (High Active)
Test Mode—Should Be Set Low
Test Mode—Should Be Set High
Test Mode—Should Be Set Low
Test Mode—Should Be Set Low
Test Mode—Should Be Set Low
The Precision Timing core uses a 1⫻ master clock input (CLI) as
a reference. This clock should be the same as the CCD pixel clock
frequency. Figure 4 illustrates how the internal timing core
divides the master clock period into 48 steps or edge positions.
Therefore, the edge resolution of the Precision Timing core is
(tCLI /48). For more information on using the CLI input, see the
Applications Information section.
P[12]
P[0]
P[24]
P[36]
P[48]=P[0]
CLI
tCLIDLY
...
...
1 PIXEL
PERIOD
NOTES
1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS ( tCLIDLY = 6 ns TYP).
Figure 4. High Speed Clock Resolution from CLI Master Clock Input
REV. A
–15–
AD9847
High Speed Clock Programmability
Figure 5 shows how the high speed clocks RG, H1–H4, SHP,
and SHD are generated. The RG pulse has programmable rising
and falling edges and may be inverted using the polarity control.
The horizontal clocks H1 and H3 have programmable rising and
falling edges and polarity control. The H2 and H4 clocks are
always inverses of H1 and H3, respectively. Table II summarizes
the high speed timing registers and their parameters.
The edge location registers are 6 bits wide, but there are only 48
valid edge locations available. Therefore, the register values are
mapped into four quadrants, with each quadrant containing 12 edge
locations. Table III shows the correct register values for the
corresponding edge locations. Figure 6 shows the range and
default locations of the high speed clock signals.
(3)
(4)
CCD SIGNAL
(1)
(2)
RG
(5)
(6)
H1/H3
H2/H4
NOTES
PROGRAMMABLE CLOCK POSITIONS:
(1) RG RISING EDGE AND (2) FALLING EDGE
(3) SHP AND (4) SHD SAMPLE LOCATION
(5) H1/H3 RISING EDGE POSITION AND (6) FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3)
Figure 5. High Speed Clock Programmable Locations
Table II. H1–H4, RG, SHP, SHD Timing Parameters
Register Name
Length
Range
Description
POL
POSLOC
1b
6b
High/Low
0–47 Edge Location
NEGLOC
DRV
6b
3b
0–47 Edge Location
0–7 Current Steps
Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion)
Positive Edge Location for H1, H3, and RG
Sample Location for SHP, SHD
Negative Edge Location for H1, H3, and RG
Drive Current for H1–H4 and RG Outputs (3.5 mA per Step)
Table III. Precision Timing Edge Locations
Quadrant
Edge Location (Decimal)
Register Value (Decimal)
Register Value (Binary)
I
II
III
IV
0 to 11
12 to 23
24 to 35
36 to 47
0 to 11
16 to 27
32 to 43
48 to 59
000000 to 001011
010000 to 011011
100000 to 101011
110000 to 111011
–16–
REV. A
AD9847
POSITION
P[0]
P[24]
P[12]
P[48] = P[0]
P[36]
PIXEL
PERIOD
RGf[12]
RGr[0]
RG
Hf[24]
Hr[0]
H1/H3
SHP[28]
SHD[48]
tS1
CCD SIGNAL
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD.
2. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN ABOVE.
Figure 6. High Speed Clock Default and Programmable Locations
H-Driver and RG Outputs
In addition to the programmable timing positions, the AD9847
features on-chip output drivers for the RG and H1–H4 outputs.
These drivers are powerful enough to directly drive the CCD
inputs. The H-driver current can be adjusted for optimum rise/fall
time into a particular load by using the DRV registers. The RG
drive current is adjustable using the RGDRV register. Each 3-bit
DRV register is adjustable in 3.5 mA increments, with the minimum setting of 0 equal to OFF or three-state and the maximum
setting of 7 equal to 24.5 mA.
As shown in Figure 7, the H2/H4 outputs are inverses of H1/H3.
The internal propagation delay resulting from the signal inversion
is less than 1 ns, which is significantly less than the typical rise
time driving the CCD load. This results in a H1/H2 crossover
voltage at approximately 50% of the output swing. The crossover
voltage is not programmable.
P[12]
P[0]
H1/H3
tRISE
H2/H4
tPD
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