a
FEATURES
125 MHz Clock Rate
On-Chip High Performance DAC and High Speed
Comparator
DAC SFDR > 50 dB @ 40 MHz A OUT
32-Bit Frequency Tuning Word
Simplified Control Interface: Parallel Byte or Serial
Loading Format
Phase Modulation Capability
3.3 V or 5 V Single-Supply Operation
Low Power: 380 mW @ 125 MHz (5 V)
Low Power: 155 mW @ 110 MHz (3.3 V)
Power-Down Function
Ultrasmall 28-Lead SSOP Packaging
APPLICATIONS
Frequency/Phase—Agile Sine Wave Synthesis
Clock Recovery and Locking Circuitry for Digital
Communications
Digitally Controlled ADC Encode Generator
Agile Local Oscillator Applications
GENERAL DESCRIPTION
The AD9850 is a highly integrated device that uses advanced
DDS technology coupled with an internal high speed, high
performance D/A converter and comparator to form a complete, digitally programmable frequency synthesizer and
clock generator function. When referenced to an accurate
clock source, the AD9850 generates a spectrally pure, frequency/phase programmable, analog output sine wave. This
sine wave can be used directly as a frequency source, or it can
be converted to a square wave for agile-clock generator applications. The AD9850’s innovative high speed DDS core provides
a 32-bit frequency tuning word, which results in an output
tuning resolution of 0.0291 Hz for a 125 MHz reference clock
input. The AD9850’s circuit architecture allows the generation
of output frequencies of up to one-half the reference clock
frequency (or 62.5 MHz), and the output frequency can be digitally changed (asynchronously) at a rate of up to 23 million new
frequencies per second. The device also provides five bits of
digitally controlled phase modulation, which enables phase
shifting of its output in increments of 180°, 90°, 45°, 22.5°,
CMOS, 125 MHz
Complete DDS Synthesizer
AD9850
FUNCTIONAL BLOCK DIAGRAM
+VS
DAC RSET
REF
CLOCK IN
HIGH SPEED
DDS
MASTER
RESET
32-BIT
TUNING
WORD
FREQUENCY
UPDATE/
DATA REGISTER
RESET
WORD LOAD
CLOCK
GND
10-BIT
DAC
PHASE
AND
CONTROL
WORDS
ANALOG
OUT
ANALOG
IN
FREQUENCY/PHASE
DATA REGISTER
CLOCK OUT
CLOCK OUT
DATA INPUT REGISTER
SERIAL
LOAD
COMPARATOR
PARALLEL
LOAD
AD9850
1-BIT
40 LOADS
8-BITS
5 LOADS
FREQUENCY, PHASE, AND CONTROL
DATA INPUT
11.25°, and any combination thereof. The AD9850 also contains
a high speed comparator that can be configured to accept the
(externally) filtered output of the DAC to generate a low jitter
square wave output. This facilitates the device’s use as an
agile clock generator function.
The frequency tuning, control, and phase modulation words are
loaded into the AD9850 via a parallel byte or serial loading
format. The parallel load format consists of five iterative loads
of an 8-bit control word (byte). The first byte controls phase
modulation, power-down enable, and loading format; Bytes 2 to
5 comprise the 32-bit frequency tuning word. Serial loading is
accomplished via a 40-bit serial data stream on a single pin. The
AD9850 Complete DDS uses advanced CMOS technology to
provide this breakthrough level of functionality and performance
on just 155 mW of power dissipation (3.3 V supply).
The AD9850 is available in a space-saving 28-lead SSOP,
surface-mount package. It is specified to operate over the
extended industrial temperature range of –40°C to +85°C.
REV. H
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© 2004 Analog Devices, Inc. All rights reserved.
AD9850–SPECIFICATIONS (V = 5 V ⴞ 5% except as noted, R
S
Parameter
SET
= 3.9 k⍀)
Temp
Test Level
Min
Full
Full
IV
IV
1
1
25°C
25°C
IV
IV
3.2
4.1
25°C
25°C
25°C
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
V
V
I
V
I
V
I
I
V
IV
IV
I
25°C
25°C
25°C
IV
IV
IV
25°C
25°C
25°C
25°C
IV
IV
IV
IV
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Current
Input Voltage Range
Comparator Offset*
25°C
25°C
25°C
25°C
Full
V
IV
I
IV
VI
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage 5 V Supply
Logic 1 Voltage 3.3 V Supply
Logic 0 Voltage
Propagation Delay, 5 V Supply (15 pF Load)
Propagation Delay, 3.3 V Supply (15 pF Load)
Rise/Fall Time, 5 V Supply (15 pF Load)
Rise/Fall Time, 3.3 V Supply (15 pF Load)
Output Jitter (p-p)
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
VI
VI
VI
V
V
V
V
V
CLOCK OUTPUT CHARACTERISTICS
Clock Output Duty Cycle (Clk Gen. Config.)
25°C
IV
CLOCK INPUT CHARACTERISTICS
Frequency Range
5 V Supply
3.3 V Supply
Pulse Width High/Low
5 V Supply
3.3 V Supply
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
RSET = 3.9 kΩ
RSET = 1.95 kΩ
Gain Error
Gain Temperature Coefficient
Output Offset
Output Offset Temperature Coefficient
Differential Nonlinearity
Integral Nonlinearity
Output Slew Rate (50 Ω, 2 pF Load)
Output Impedance
Output Capacitance
Voltage Compliance
Spurious-Free Dynamic Range (SFDR)
Wideband (Nyquist Bandwidth)
1 MHz Analog Out
20 MHz Analog Out
40 MHz Analog Out
Narrowband
40.13579 MHz ± 50 kHz
40.13579 MHz ± 200 kHz
4.513579 MHz ± 50 kHz/20.5 MHz CLK
4.513579 MHz ± 200 kHz/20.5 MHz CLK
–2–
AD9850BRS
Typ
Max
125
110
–10
+10
150
10
50
0.5
0.5
400
120
0.75
1
8
1.5
63
50
46
MHz
MHz
ns
ns
10.24
20.48
50
Unit
mA
mA
% FS
ppm/°C
µA
nA/°C
LSB
LSB
V/µs
kΩ
pF
V
72
58
54
dBc
dBc
dBc
80
77
84
84
dBc
dBc
dBc
dBc
3
pF
kΩ
µA
V
mV
500
–12
0
30
+12
VDD
30
4.8
3.1
5.5
7
3
3.5
80
V
V
V
ns
ns
ns
ns
ps
50 ± 10
%
0.4
REV. H
AD9850
AD9850BRS
Min
Typ
Max
Parameter
Temp
Test Level
CMOS LOGIC INPUTS (Including CLKIN)
Logic 1 Voltage, 5 V Supply
Logic 1 Voltage, 3.3 V Supply
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
25°C
25°C
25°C
25°C
25°C
25°C
I
IV
IV
I
I
V
Full
Full
Full
Full
VI
VI
VI
VI
30
47
44
76
48
60
64
96
mA
mA
mA
mA
Full
Full
Full
Full
VI
VI
VI
VI
100
155
220
380
160
200
320
480
mW
mW
mW
mW
Full
Full
V
V
30
10
POWER SUPPLY (AOUT = 1/3 CLKIN)
+VS Current @
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
PDISS @
62.5 MHz Clock, 3.3 V Supply
110 MHz Clock, 3.3 V Supply
62.5 MHz Clock, 5 V Supply
125 MHz Clock, 5 V Supply
PDISS Power-Down Mode
5 V Supply
3.3 V Supply
3.5
2.4
0.8
12
12
3
Unit
V
V
V
µA
µA
pF
mW
mW
*Tested by measuring output duty cycle variation.
Specifications subject to change without notice.
TIMING CHARACTERISTICS*(V = 5 V ⴞ 5% except as noted, R
S
Parameter
tDS
tDH
tWH
tWL
tWD
tCD
tFH
tFL
tCF
tFD
tRH
tRL
tRS
tOL
tRR
(Data Setup Time)
(Data Hold Time)
(W_CLK Minimum Pulse Width High)
(W_CLK Minimum Pulse Width Low)
(W_CLK Delay after FQ_UD)
(CLKIN Delay after FQ_UD)
(FQ_UD High)
(FQ_UD Low)
(Output Latency from FQ_UD)
Frequency Change
Phase Change
(FQ_UD Minimum Delay after W_CLK)
(CLKIN Delay after RESET Rising Edge)
(RESET Falling Edge after CLKIN)
(Minimum RESET Width)
(RESET Output Latency)
(Recovery from RESET)
Wake-Up Time from Power-Down Mode
SET
Temp
Test Level
AD9850BRS
Min
Typ Max
Unit
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
3.5
3.5
3.5
3.5
7.0
3.5
7.0
7.0
ns
ns
ns
ns
ns
ns
ns
ns
Full
Full
Full
Full
Full
Full
Full
Full
25°C
IV
IV
IV
IV
IV
IV
IV
IV
V
18
13
7.0
3.5
3.5
5
13
2
CLKIN Cycles
CLKIN Cycles
ns
ns
ns
CLKIN Cycles
CLKIN Cycles
CLKIN Cycles
µs
*Control functions are asynchronous with CLKIN.
Specifications subject to change without notice.
REV. H
= 3.9 k⍀)
–3–
5
AD9850
ABSOLUTE MAXIMUM RATINGS*
EXPLANATION OF TEST LEVELS
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS
Digital Output Continuous Current . . . . . . . . . . . . . . . 5 mA
DAC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . 300°C
SSOP θJA Thermal Impedance . . . . . . . . . . . . . . . . . . 82°C/W
Test Level
I
100% Production Tested.
III Sample Tested Only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI All devices are 100% production tested at 25°C. 100%
production tested at temperature extremes for military
temperature devices; guaranteed by design and
characterization testing for industrial devices.
*Absolute maximum ratings are limiting values, to be applied individually, and
beyond which the serviceability of the circuit may be impaired. Functional
operability under any of these conditions is not necessarily implied. Exposure of
absolute maximum rating conditions for extended periods of time may affect
device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9850 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Application Note: Users are cautioned not to apply digital input signals prior to power-up of this
device. Doing so may result in a latch-up condition.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9850BRS
AD9850BRS-REEL
AD9850BRSZ*
AD9850BRSZ-REEL*
AD9850/CGPCB
AD9850/FSPCB
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Shrink Small Outline Package (SSOP)
Shrink Small Outline Package (SSOP)
Shrink Small Outline Package (SSOP)
Shrink Small Outline Package (SSOP)
Evaluation Board Clock Generator
Evaluation Board Frequency Synthesizer
RS-28
RS-28
RS-28
RS-28
*Z = Pb-free part.
–4–
REV. H
AD9850
PIN CONFIGURATION
D3
1
28 D4
D2
2
27 D5
D1
3
26 D6
LSB D0
4
25 D7 MSB/SERIAL LOAD
DGND
5
24 DGND
DVDD
6
W CLK
7
FQ UD
8 (Not to Scale) 21 IOUT
23 DVDD
AD9850
TOP VIEW
22 RESET
9
20 IOUTB
AGND 10
19 AGND
AVDD 11
18 AVDD
CLKIN
RSET 12
17 DACBL (NC)
QOUTB 13
16 VINP
QOUT 14
15 VINN
NC = NO CONNECT
Table I. PIN FUNCTION DESCRIPTIONS
Pin
No.
Mnemonic
Function
4 to 1,
28 to 25
D0 to D7
8-Bit Data Input. This is the 8-bit data port for iteratively loading the 32-bit frequency and the 8-bit phase/
control word. D7 = MSB; D0 = LSB. D7 (Pin 25) also serves as the input pin for the 40-bit serial data-word.
5, 24
DGND
Digital Ground. These are the ground return leads for the digital circuitry.
6, 23
DVDD
Supply Voltage Leads for Digital Circuitry.
7
W_CLK
Word Load Clock. This clock is used to load the parallel or serial frequency/phase/control words.
8
FQ_UD
Frequency Update. On the rising edge of this clock, the DDS updates to the frequency (or phase)
loaded in the data input register; it then resets the pointer to Word 0.
9
CLKIN
Reference Clock Input. This may be a continuous CMOS-level pulse train or sine input biased at
1/2 V supply. The rising edge of this clock initiates operation.
10, 19
AGND
Analog Ground. These leads are the ground return for the analog circuitry (DAC and comparator).
11, 18
AVDD
Supply Voltage for the Analog Circuitry (DAC and Comparator).
12
RSET
DAC’s External RSET Connection. This resistor value sets the DAC full-scale output current. For
normal applications (FS IOUT = 10 mA), the value for RSET is 3.9 kΩ connected to ground. The RSET/IOUT
relationship is IOUT = 32 (1.248 V/RSET).
13
QOUTB
Output Complement. This is the comparator’s complement output.
14
QOUT
Output True. This is the comparator’s true output.
15
VINN
Inverting Voltage Input. This is the comparator’s negative input.
16
VINP
Noninverting Voltage Input. This is the comparator’s positive input.
17
DACBL (NC) DAC Baseline. This is the DAC baseline voltage reference; this lead is internally bypassed and should
normally be considered a no connect for optimum performance.
20
IOUTB
Complementary Analog Output of the DAC.
21
IOUT
Analog Current Output of the DAC.
22
RESET
Reset. This is the master reset function; when set high, it clears all registers (except the input register), and
the DAC output goes to cosine 0 after additional clock cycles—see Figure 7.
REV. H
–5–
AD9850–Typical Performance Characteristics
Spectrum
CH1 S
AD9850
10dB/REF
–8.6dBm
CH1 S
76.642 dB
CLOCK 125MHz
Fxd
Spectrum
10dB/REF
–10dBm
59.925 dB
CLOCK 125MHz
AD9850
Fxd
0
0
RBW # 100Hz
START 0Hz
VBW 100Hz
RBW # 300Hz
START 0Hz
ATN # 30dB SWP 762 sec
STOP 62.5MHz
VBW 300Hz
ATN # 30dB SWP 182.6 sec
STOP 62.5MHz
TPC 1. SFDR, CLKIN = 125 MHz/fOUT = 1 MHz
TPC 4. SFDR, CLKIN = 125 MHz/fOUT = 20 MHz
CH1 S
CH1 S
Spectrum
AD9850
10dB/REF
–10dBm
54.818 dB
Fxd
CLOCK 125MHz
Spectrum
12dB/REF
0dBm
–85.401 dB
–23 kHz
AD9850
Mkr
0
0
RBW # 300Hz
START 0Hz
VBW 300Hz
ATN # 30dB
RBW # 3Hz
VBW 3Hz
CENTER 4.513579MHz
SWP 182.6 sec
STOP 62.5MHz
ATN # 20dB
SWP 399.5 sec
SPAN 400kHz
TPC 5. SFDR, CLKIN = 20.5 MHz/fOUT = 4.5 MHz
TPC 2. SFDR, CLKIN = 125 MHz/fOUT = 41 MHz
Tek Run: 100GS/s ET Sample
–105
PN.3RD
–110
: 300ps
@: 25.26ns
–115
–120
dBc
–125
–130
–135
–140
–145
–150
1
Ch 1
500mV⍀
M 20.0ns
D 500ps
–155
100
Ch 1
1.58V
Runs After
TPC 3. Typical Comparator Output Jitter,
AD9850 Configured as Clock Generator with
42 MHz LP Filter (40 MHz AOUT/125 MHz CLKIN)
10k
1k
OFFSET FROM 5MHz CARRIER – Hz
100k
TPC 6. Output Residual Phase Noise (5 MHz
AOUT/125 MHz CLKIN)
–6–
REV. H
AD9850
Tek Run: 50.0GS/s ET Average
Tek Run: 50.0GS/s ET Average
Ch 1 Rise
2.870ns
Ch 1 Fall
3.202ns
1
1
Ch1 1.00V⍀
M 1.00ns Ch 1
1.74V
Ch1 1.00V⍀
TPC 7. Comparator Output Rise Time
(5 V Supply/15 pF Load)
M 1.00ns Ch 1
1.74V
TPC 10. Comparator Output Fall Time
(5 V Supply/15 pF Load)
68
90
fOUT = 1/3 OF CLKIN
80
64
70
SUPPLY CURRENT – mA
66
SFDR – dB
62
60
58
VCC = 5V
56
VCC = 3.3V
54
52
0
20
40
60
80
CLKIN – MHz
100
120
50
40
VCC = 3.3V
30
10
140
0
20
40
60
80
100
CLOCK FREQUENCY – MHz
120
140
TPC 11. Supply Current vs. CLKIN Frequency
(AOUT = 1/3 of CLKIN)
75
90
fOUT = 1MHz
70
80
VCC = 5V
65
70
SFDR – dB
SUPPLY CURRENT – mA
VCC = 5V
20
TPC 8. SFDR vs. CLKIN Frequency
(AOUT = 1/3 of CLKIN)
60
50
30
60
fOUT = 20MHz
55
VCC = 3.3V
fOUT = 40MHz
50
40
45
0
10
20
30
FREQUENCY OUT – MHz
40
TPC 9. Supply Current vs. AOUT Frequency
(CLKIN = 125/110 MHz for 5 V/3.3 V Plot)
REV. H
60
5
10
15
DAC IOUT – mA
20
TPC 12. SFDR vs. DAC IOUT (AOUT = 1/3 of CLKIN)
–7–
AD9850
+VS
IF
FREQUENCY
IN
5-POLE ELLIPTICAL
42MHz LOW-PASS
200⍀ IMPEDANCE
GND
LOW-PASS
FILTER
IOUT
200⍀
100k⍀
8-b ⴛ 5 PARALLEL DATA,
DATA OR 1-b ⴛ 40 SERIAL DATA,
470pF
PROCESSOR BUS RESET, AND 2
CLOCK LINES
100k⍀
100⍀
AD9850 IOUTB
VINN
XTAL
CLK
VINP
OSC
QOUT
CMOS
QOUTB
CLOCK
OUTPUTS
RSET
COMP
FILTER
125MHz
AD9850
COMPLETE DDS
Rx
IF IN
3a. Frequency/Phase–Agile Local Oscillator
200⍀
125MHz
REFERENCE
CLOCK
TRUE
VCA
ADC CLOCK
FREQUENCY
LOCKED TO Tx CHIP/
SYMBOL PN RATE
125MHz
REFERENCE
CLOCK
AD9850
COMPLETE
DDS
FILTER
PHASE
COMPARATOR
LOOP
FILTER
RF
FREQUENCY
OUT
VCO
DIVIDE-BY-N
TUNING
WORD
3b. Frequency/Phase–Agile Reference for PLL
REF
FREQUENCY
Rx
BASEBAND
DIGITAL
DATA
OUT
DIGITAL
DEMODULATOR
TUNING
WORD
REFERENCE
Figure 1. Basic AD9850 Clock Generator Application
with Low-Pass Filter
I
8
I/Q MIXER
AD9059
AND
LOW-PASS Q DUAL 8-BIT 8
ADC
FILTER
RF
FREQUENCY
OUT
FILTER
PHASE
COMPARATOR
VCO
PROGRAMMABLE
DIVIDE-BY-N
FUNCTION
FILTER
AGC
LOOP
FILTER
RF
FREQUENCY
OUT
AD9850
ADC ENCODE
COMPLETE
DDS
AD9850
32
CLOCK
GENERATOR CHIP/SYMBOL/PN
RATE DATA
TUNING WORD
3c. Digitally-Programmable Divide-by-N Function in PLL
Figure 2. AD9850 Clock Generator Application in a
Spread-Spectrum Receiver
Figure 3. AD9850 Complete DDS Synthesizer in
Frequency Up-Conversion Applications
The frequency tuning word sets the modulus of the counter,
which effectively determines the size of the increment (∆ Phase)
that is added to the value in the phase accumulator on the next
clock pulse. The larger the added increment, the faster the
accumulator overflows, which results in a higher output frequency. The AD9850 uses an innovative and proprietary
algorithm that mathematically converts the 14-bit truncated
value of the phase accumulator to the appropriate COS value.
This unique algorithm uses a much reduced ROM look-up table
and DSP techniques to perform this function, which contributes
to the small size and low power dissipation of the AD9850. The
relationship of the output frequency, reference clock, and tuning
word of the AD9850 is determined by the formula
THEORY OF OPERATION AND APPLICATION
The AD9850 uses direct digital synthesis (DDS) technology, in the
form of a numerically controlled oscillator, to generate a frequency/
phase-agile sine wave. The digital sine wave is converted to analog
form via an internal 10-bit high speed D/A converter, and an
on-board high speed comparator is provided to translate the analog
sine wave into a low jitter TTL/CMOS compatible output square
wave. DDS technology is an innovative circuit architecture that
allows fast and precise manipulation of its output frequency under
full digital control. DDS also enables very high resolution in the
incremental selection of output frequency; the AD9850 allows an
output frequency resolution of 0.0291 Hz with a 125 MHz reference clock applied. The AD9850’s output waveform is phase continuous when changed.
fOUT = (∆ Phase × CLKIN)/232
The basic functional block diagram and signal flow of the
AD9850 configured as a clock generator is shown in Figure 4.
where:
∆ Phase is the value of the 32-bit tuning word.
CLKIN is the input reference clock frequency in MHz.
fOUT is the frequency of the output signal in MHz.
The DDS circuitry is basically a digital frequency divider function
whose incremental resolution is determined by the frequency of
the reference clock divided by the 2N number of bits in the
tuning word. The phase accumulator is a variable-modulus
counter that increments the number stored in it each time it
receives a clock pulse. When the counter overflows, it wraps
around, making the phase accumulator’s output contiguous.
The digital sine wave output of the DDS block drives the internal high speed 10-bit D/A converter that reconstructs the sine
wave in analog form. This DAC has been optimized for dynamic
performance and low glitch energy as manifested in the low
jitter performance of the AD9850. Because the output of the
–8–
REV. H
AD9850
REF
CLOCK
DDS CIRCUITRY
N
PHASE
ACCUMULATOR
AMPLITUDE/COS
CONV.
ALGORITHM
D/A
CONVERTER
LP
COMPARATOR
CLK
OUT
TUNING WORD SPECIFIES
OUTPUT FREQUENCY
AS A FRACTION OF REF
CLOCK FREQUENCY
COS (x)
IN DIGITAL DOMAIN
Figure 4. Basic DDS Block Diagram and Signal Flow of AD9850
AD9850 is a sampled signal, its output spectrum follows the
Nyquist sampling theorem. Specifically, its output spectrum
contains the fundamental plus aliased signals (images) that
occur at multiples of the reference clock frequency ± the
selected output frequency. A graphical representation of the
sampled spectrum, with aliased images, is shown in Figure 5.
SIGNAL AMPLITUDE
fOUT
sin(x)/x ENVELOPE
x=()fo/fc
fc – fo
fc + fo
2fc – fo
fc
2fc + fo
3fc – fo
and automatically places itself in the power-down mode. When
in this state, if the clock frequency again exceeds the threshold,
the device resumes normal operation. This shutdown mode
prevents excessive current leakage in the dynamic registers of
the device.
The D/A converter output and comparator inputs are available
as differential signals that can be flexibly configured in any
manner desired to achieve the objectives of the end system. The
typical application of the AD9850 is with single-ended output/
input analog signals, a single low-pass filter, and the generation
of the comparator reference midpoint from the differential DAC
output as shown in Figure 1.
Programming the AD9850
120MHz
20MHz
80MHz
2ND IMAGE
FUNDAMENTAL 1ST IMAGE
100MHz
REFERENCE CLOCK
FREQUENCY
180MHz
3RD IMAGE
220MHz
4TH IMAGE
280MHz
5TH IMAGE
Figure 5. Output Spectrum of a Sampled Signal
In this example, the reference clock is 100 MHz and the output
frequency is set to 20 MHz. As can be seen, the aliased images
are very prominent and of a relatively high energy level as determined by the sin(x)/x roll-off of the quantized D/A converter
output. In fact, depending on the fo/reference clock relationship, the first aliased image can be on the order of –3 dB below
the fundamental. A low-pass filter is generally placed between
the output of the D/A converter and the input of the comparator to further suppress the effects of aliased images. Obviously, consideration must be given to the relationship of the
selected output frequency and the reference clock frequency
to avoid unwanted (and unexpected) output anomalies.
To apply the AD9850 as a clock generator, limit the selected
output frequency to
