AD9853-45PCB

a FEATURES Universal Low Cost Solution for HFC Network Return-Channel TX Function: 5 MHz–42 MHz/ 5 MHz–65 MHz 165 MHz Internal Reference Clock Capability Includes Programmable Pulse-Shaping FIR Filters and Programmable Interpolating Filters FSK/QPSK/DQPSK/16-QAM/D16-QAM Modulation Formats 6 Internal Reference Clock Multiplier Integrated Reed-Solomon FEC Function Programmable Randomizer/Preamble Function Supports Interoperable Cable Modem Standards Internal SINx/x Compensation >50 dB SFDR @ 42 MHz Output Frequency (Single Tone) Controlled Burst Mode Operation +3.3 V to +5 V Single Supply Operation Low Power: 750 mW @ Full Clock Speed (3.3 V Supply) Space Saving Surface Mount Packaging APPLICATIONS HFC Data, Telephony and Video Modems Wireless LAN Programmable Digital QPSK/16-QAM Modulator AD9853 GENERAL DESCRIPTION The AD9853 integrates a high speed direct-digital synthesizer (DDS), a high performance, high speed digital-to-analog converter (DAC), digital filters and other DSP functions onto a single chip, to form a complete and flexible digital modulator device. The AD9853 is intended to function as a modulator in network applications such as interactive HFC, WLAN and MMDS, where cost, size, power dissipation, functional integration and dynamic performance are critical attributes. The AD9853 is fabricated on an advanced CMOS process and it sets a new standard for CMOS digital modulator performance. The device is loaded with programmable functionality and provides a direct interface port to the AD8320, digitallyprogrammable cable driver amplifier. The AD9853/AD8320 chipset forms a highly integrated, low power, small footprint and cost-effective solution for the HFC return-path requirement and other more general purpose modulator applications. The AD9853 is available in a space saving surface mount package and is specified to operate over the extended industrial temperature range of –40°C to +85°C. FUNCTIONAL BLOCK DIAGRAM FIR FILTER INTERPOLATION FILTER AD9853 INV SYNC FILTER 10-BIT DAC AOUT TO LP FILTER AND AD8320 CABLE DRIVER AMPLIFER SERIAL DATA IN R-S FEC XOR DATA DELAY & MUX ENCODER: FSK QPSK DQPSK 16-QAM D16-QAM 10 FIR FILTER INTERPOLATION FILTER SINE DDS COSINE 10 RANDOMIZER PREAMBLE INSERTION GAIN CONTROL TO DRIVER AMP CLOCK 6 CONTROL FUNCTIONS REF CLOCK IN FEC TXENABLE RESET ENABLE/ DISABLE SERIAL CONTROL BUS: 32-BIT OUTPUT FREQUENCY TUNING WORD INPUT DATA RATE/MODULATION FORMAT FEC/RANDOMIZER/PREAMBLE ENABLE/CONFIGURATION FIR FILTER COEFFICIENTS REF CLOCK MULTIPLIER ENABLE I/Q PHASE INVERT SLEEP MODE R EV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9853–SPECIFICATIONS 6 Parameter REF CLOCK INPUT CHARACTERISTICS Frequency Range 6× REFCLK Disabled (+3.3 V Supply) 6× REFCLK Enabled (+3.3 V Supply) 6× REFCLK Disabled (+5 V Supply) 6× REFCLK Enabled (+5 V Supply) Duty Cycle Input Capacitance Input Impedance DAC OUTPUT CHARACTERISTICS Resolution Full-Scale Output Current Gain Error Output Offset Output Offset Temperature Coefficient Differential Nonlinearity Integral Nonlinearity Output Capacitance Phase Noise @ 1 kHz Offset, 40 MHz AOUT 6× REFCLK Enabled 6× REFCLK Disabled Voltage Compliance Range Wideband SFDR (Single Tone): 1 MHz AOUT 20 MHz AOUT 42 MHz AOUT 65 MHz AOUT1 MODULATOR CHARACTERISTICS I/Q Offset Adjacent Channel Power Error Vector Magnitude In-Band Spurious Emission 5 MHz–42 MHz AOUT 5 MHz–65 MHz AOUT1 Passband Amplitude Ripple (VS = +3.3 V 5%, RSET = 3.9 k , Reference Clock Frequency = 20.48 MHz with REFCLK Enabled, Symbol Rate = 2.56 MS/s, = 0.25, unless otherwise noted) Temp Test Level Min Typ Max Units Full Full Full Full +25°C +25°C +25°C IV IV IV IV IV V V 42 7 108 18 40 3 100 10 10 126 21 168 28 60 MHz MHz MHz MHz % pF MΩ Bits mA % FS µA nA/°C LSB LSB pF dBc dBc V dBc dBc dBc dBc dB dBm % dBc dBc dB +25°C +25°C +25°C Full +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C IV I I V I I V V V I IV IV IV IV IV IV IV IV IV V 5 –10 20 +10 10 0.75 1.5 50 0.5 0.5 5 –100 –110 –0.5 62 52 48 42 48 44 1 42 40 ± 0.3 68 54 50 44 +1.5 2 TIMING CHARACTERISTICS Serial Control Bus Maximum Frequency Minimum Clock Pulsewidth Low (tPWL) Minimum Clock Pulsewidth High (tPWH) Maximum Clock Rise/Fall Time Minimum Data Setup Time (tDS) Minimum Data Hold Time (tDH) Minimum Clock Setup—Stop Condition (tCS) Minimum Clock Hold—Start Condition (tCH) RESET Minimum TXENABLE Low to RESET Low (tTR) Minimum RESET High to Start Condition (tRH) FEC ENABLE Minimum FEC ENABLE/DISABLE to TXENABLE High (tFH) Minimum FEC ENABLE/DISABLE to TXENABLE Low (tFL) Full Full Full Full Full Full Full Full Full Full Full Full IV IV IV IV IV IV IV IV IV IV IV IV 25 10 10 100 10 10 10 10 10 10 0 0 MHz ns ns ns ns ns ns ns ns ns ns ns – 2– REV. C AD9853 Parameter TIMING CHARACTERISTICS (Continued) Wake-Up Time–PLL Power-Down Wake-Up Time–DAC Power-Down Wake-Up Time–Digital Power-Down Data Latency (tDL) Minimum RESET Pulsewidth Low (tRL) CMOS LOGIC INPUTS Logic “1” Voltage, +5 V Supply Logic “1” Voltage, +3.3 V Supply Logic “0” Voltage Logic “1” Current Logic “0” Current Input Capacitance POWER SUPPLY +VS Current (+3.3 V + 5%) Full Operating Conditions With PLL Power-Down Enabled With DAC Power-Down Enabled With Digital Power-Down Enabled With All Power-Down Enabled +VS Current (+5 V + 5%) 2 Temp +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C +25°C Test Level IV IV IV IV IV I I I I I V Min Typ 1 200 5 6 10 Max Units ms µs µs Symbols ns V V V µA µA pF +3.5 +3.0 +0.4 12 12 3 +25°C +25°C +25°C +25°C +25°C +25°C I I I I I I 184 178 170 36 16 400 230 224 216 54 20 595 mA mA mA mA mA mA NOTES 1 Reference clock = 28 MHz with clock multiplier enabled; supply voltage = +5 V. 2 Maximum values are obtained under worst case operating modes. Typical values are valid for most applications. Specifications subject to change without notice. EXPLANATION OF TEST LEVELS Test Level I – 100% Production Tested. III – Sample Tested Only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – Devices are 100% production tested at +25°C and guaranteed by design and characterization testing for industrial operating temperature range. Maximum Junction Temperature . . . . . . . . . . . . . . . +150°C VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +VS Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (10 sec Soldering) . . . . . . . . . . . . +300°C MQFP θJA Thermal Impedance . . . . . . . . . . . . . . . . . 36°C/W *Absolute maximum ratings are limiting values, to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. Exposure of absolute maximum rating conditions for extended periods of time may affect device reliability. ABSOLUTE MAXIMUM RATINGS* ORDERING GUIDE Model Temperature Range Package Description Package Option AD9853AS –40°C to +85°C Metric Quad Flatpack S-44A (MQFP) CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9853 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. C – 3– AD9853 PIN FUNCTION DESCRIPTIONS PIN CONFIGURATION 44-Lead Metric Quad Flatpack (S-44A) TX ENABLE REF CLK IN CA CLOCK 33 CA ENABLE PIN 1 IDENTIFIER Pin # Pin Name Pin Function Digital Ground Digital Supply Voltage Bit Clock for Control Bus Data 4 Control Bus Data In Control Bus Data In 5 FEC Enable Enables/Disables FEC 6 Address Bit Address Bit for Control Bus 11, 26, 31 Test Data Out Factory Use—Serial Test Data Out 12, 13 PLL GND PLL Ground 14 PLL VCC Supply Voltage for PLL 15 PLL Filter PLL Loop Filter Connection 16, 19, 23 AGND Analog Ground 17 NC No Connect 18 DAC Rset Rset Resistor Connection 20, 22 AVDD Analog Supply Voltage 21 DAC Baseline DAC Baseline Voltage 24 IOUT Analog Current Output of the DAC 25 IOUTB Complementary Analog Current Output of the DAC 27 Test CLK Factory Use—Scan Clock 28 Test Latch Factory Use—Scan Latch 29 Test Data In Factory Use—Serial Test Data In 30 Test Data Enable Factory Use—Serial Test Data Enable, Grounded for Normal Operation 32 RESET Master Device Reset Function 33 CA Enable Cable Amplifier Enable 34 CA Clock Cable Amplifier Serial Control Clock 35 CA Data Cable Amplifier Serial Control Data 38 REF CLK IN Reference Clock Input 41 Data In Input Serial Data Stream 42 TXENABLE Pulse that Frames the Valid Input Data Stream 1, 7, 9, 10, 36, 39, 44 DGND 2, 8, 37, 40, 43 DVDD 3 Control Bus Clock DATA IN 44 43 42 41 40 39 38 37 36 35 34 DGND 1 DVDD CONTROL BUS CLOCK CONTROL BUS DATA IN FEC ENABLE 2 3 4 5 CA DATA DGND DGND DVDD DGND DVDD DVDD 32 RESET 31 TEST DATA OUT 30 TEST DATA ENABLE 29 TEST DATA IN 28 TEST LATCH 27 TEST CLK 26 TEST DATA OUT 25 IOUTB 24 IOUT 23 AGND AD9853 TOP VIEW (Not to Scale) ADDRESS BIT 6 DGND 7 DVDD 8 DGND 9 DGND 10 TEST DATA 11 OUT 12 13 14 15 16 17 18 19 20 21 22 DAC BASELINE AGND PLL GND AGND PLL GND PLL VCC PLL FILTER DAC RSET AVDD NC NC = NO CONNECT AVDD –4– REV. C AD9853 Table I. Modulator Function Description Modulation Encoding Format Output Carrier Frequency Range Serial Input Data Rate Pulse-Shaping FIR Filter Interpolation Range FSK*, QPSK, DQPSK, 16-QAM, D16-QAM, Selectable via Control Bus DC – 63 MHz with +3.3 V Supply Voltage DC – 84 MHz with +5 V Supply Voltage Evenly Divisible Fraction of Reference Clock 41 Tap, Linear Phase, 10-Bit Coefficients Fully Programmable via Control Bus Interpolation Rate = (4/M) × (ICIC1) × (ICIC2) where: M = 2 for QPSK, M = 4 for 16-QAM Minimum and Maximum Rates Minimum Interpolation Rate—QPSK = 2 × 3 × 2 = 12 16-QAM = 1 × 4 × 3 = 12 Maximum Interpolation Rate—QPSK = 2 × 31 × 63 = 3906 16-QAM = 1 × 31 × 63 = 1953 These are the minimum and maximum interpolation ratios from the input data rate to the system clock. The interpolation range is a function of the fixed interpolation factor of four in the FIR filters, the programmed CIC filter interpolation rates (ICIC1, ICIC2), as well as system timing constraints. Maximum Reference Clock Frequency 6× REFCLK R-S FEC +3.3 V Supply: 21 MHz with 6× REFCLK enabled, 126 MHz with 6× REFCLK disabled +5 V Supply: 28 MHz with 6× REFCLK enabled, 168 MHz with 6× REFCLK disabled Fixed 6× reference clock multiplier, enable/disable control via control bus Enable/disable via control bus and dedicated control pin. Control pin enable/disable function: Logic “1” = Enable Logic “0” = Disable Primitive Polynomial: p(x) = x8 + x4 + x3 + x2 + 1 Code Generator Polynomial: g(x) = (x + α0)(x + α1)(x + α2) . . . (x + α2t –1) Selectable via Control Bus t = 0–10 (Programmable) Codeword Length (N) = 255 max (Programmable) N = K + 2 t (K Range = 16 ≤ K ≤ 255 – 2 t) FEC/Randomizer can be transposed in signal chain via control bus. I/Q Channel Spectrum Preamble Insertion Randomizer I × COS + Q × SIN (default) or I × COS – Q × SIN, selectable via control bus. 0–96 Bits, Programmable Length and Content Enable/Disable Control via Control Bus Generating Polynomial: x6 + x5 + 1, Programmable Seed (Davic/DVB-Compliant) or x15 + x14 + 1, Programmable Seed (DOCSIS-Compliant) Randomizer and FEC blocks can be transposed in signal chain, via control bus. *In FSK mode, F0:F1 are direct DDS Cosine output. The two interpolator stages of the AD9853 are not used in the FSK mode and should be programmed for maximum interpolation rates to reduce unnecessary current consumption. This means that Interpolator #1 should be set to a decimal value of 31, and Interpolator #2 should be set to decimal value of 63. This is easily accomplished by programming Registers 12 and 13 (hex) with the values of FF (hex). REV. C –5– AD9853 Table II. Control Register Functional Assignment Register Address (Note 1) 00h 01h DATA D7 MSB MSB D6 D5 D4 LSB D3 Randomizer Insertion 0 = After RS 1 = Before RS D2 D1 D0 LSB (Note 3) Value of K (Message Length in Bytes) for Reed-Solomon Encoder, where 1610 ≤ K ≤ 25510 (Note 2) The Number of Correctable Byte Errors (t) for the Reed-Solomon Encoder, where 0 ≤ t ≤ 1010. For t = 0, the RS encoder is effectively disabled. Randomizer Length 002 = 6 Bit 012 = 15 Bit 102 = Randomizer OFF 112 = Randomizer OFF LSB 02h 03h MSB MSB Lower Eight Bits of Seed Value for 15-Bit Randomizer (Not Used for 6-Bit Randomizer) Upper Seven Bits of Seed Value for 15-Bit Randomizer – OR – Seed Value for 6-Bit Randomizer (D1 not used in this case). Preamble Length (L) where 0 ≤ L ≤ 96 Bits (Note 4) LSB 04h 05h MSB LSB Modulation Mode 0002 = QPSK , 0012 = DQPSK, 0102 = 16-QAM 0112 = D16-QAM , 1002 = FSK The MSB of the preamble always resides in D7 of Address 11h and is the first preamble bit to be clocked out of the device during transmission of a packet. Up to 96 bits of preamble are available as specified in Register 04h. Unused bits are don’t care for L < 96. MSB MSB MSB MSB Preamble Data. (Note 5) Interpolator #1: RATE Rate Change Factor (R) where 310 ≤ R ≤ 3110 Interpolator #2: RATE Rate Change Factor (R) where 210 ≤ R ≤ 6310 LSB 2× Multiplier 0 = OFF 1 = ON LSB LSB LSB LSB 06h : 11h 12h 13h 14h Interpolator #1: SCALE 15h6 16h : 19h 1Ah : 1Dh 1Eh5 1Fh : : : 46h 47h 48h (Note 7) 49h (Note 8) MSB Interpolator #2: SCALE Frequency Tuning Word #1 FSK Mode: Specifies the “space” frequency (F0). All Other Modes: Specifies the carrier frequency. Frequency Tuning Word #2 FSK Mode: Specifies the “mark” frequency (F1). (Addresses 1Ah–1Dh are only valid for FSK mode.) MSB-3 MSB-1 MSB LSB MSB MSB-2 MSB0 10-Bit FIR End Tap Coefficient, a0 LSB0 FIR Intermediate Tap Coefficients, a1 – a19 MSB-2 MSB20 Spectrum 0 = I × Cos + Q × Sin 1 = I × Cos – Q × Sin MSB MSB-3 MSB-1 Digital Power 0 = Normal 1 = Shutdown 10-Bit FIR Center Tap Coefficient, a20 LSB20 6× RefClk 0 = Off 1 = On PLL Mode 0 = Awake 1 = Sleep DAC Mode 0 = Awake 1 = Sleep LSB AD8320 Cable Driver Gain Control Byte (GCB) The absolute gain, AV, of the AD8320 is given by: AV = 0.316 + 0.077 × GCB (where 0 ≤ GCB ≤ 25510) 6 NOTES 1 The 8-bit Register Address is preceded by an 8-bit Device Address, which is given by 000001XY, where the value of Bits X and Y are determined as follows: X 0 1 2 Voltage Applied to Pin 6 GND +VS Y 0 1 Desired Register Function WRITE READ Readback of register 15h results in a value that is 2 × the actual programmed value. This is a design error in the readback function. Assertion of RESET (Pin 32) sets the contents of this register to 0. 8 Registers 0h–48h may be written to using a single register address followed by a contiguous data sequence (see Figure 27). Register 49h, however, must be written to individually; i.e., a separately addressed 8-bit data sequence. 7 This register must be loaded with a nonzero value even if the RS encoder has been disabled by setting T = 0 in register 01h. Unused regions are don’t care bit locations. 4 If a preamble is not used this register must be initialized to a value of 0 by the user. 5 Addresses 06h–011h and 1Eh–47h are write only. 3 –6– REV. C Typical Performance Characteristics–AD9853 Modulated Output Spectrum with 3.3 V Supply, α = 0.25, 20.48 MHz REFCLK 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 6MHz/ STOP 60MHz RBW = 3kHz VBW = 3kHz SWT = 17s RF ATT = 10dB REF LVL = –20dBm 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 6MHz/ STOP 60MHz RBW = 3kHz VBW = 3kHz SWT = 17s RF ATT = 10dB REF LVL = –20dBm Figure 1. QPSK, 320 kb/s, AOUT = 10 MHz Figure 4. QPSK, 1.28 Mb/s, AOUT = 10 MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 6MHz/ STOP 60MHz RBW = 3kHz VBW = 3kHz SWT = 17s RF ATT = 10dB REF LVL = –20dBm 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 6MHz/ STOP 60MHz RBW = 3kHz VBW = 3kHz SWT = 17s RF ATT = 10dB REF LVL = –20dBm Figure 2. QPSK, 640 kb/s, AOUT = 20 MHz Figure 5. QPSK, 2.56 Mb/s, AOUT = 20 MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 6MHz/ STOP60 MHz RBW = 3kHz VBW = 3kHz SWT = 17s RF ATT = 10dB REF LVL = –20dBm 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0Hz 6MHz/ STOP60 MHz RBW = 3kHz VBW = 3kHz SWT = 17s RF ATT = 10dB REF LVL = –20dBm Figure 3. QPSK, 1.28 Mb/s, AOUT = 42 MHz Figure 6. QPSK, 5.12 Mb/s, AOUT = 42 MHz REV. C –7– AD9853 Modulated Output Spectrum with 5 V Supply, 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –10 0 START 0Hz 8MHz/ STOP 80MHz RBW = 3kHz VBW = 3kHz SWT = 22.5s RF ATT = 10dB REF LVL = –20dBm = 0.25, 27.5 MHz REFCLK 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 START 0 Hz 8 MHz/ STOP 80 MHz RBW = 3kHz VBW = 3kHz SWT = 22.5s RF ATT = 10dB REF LVL = –20dBm Figure 7. QPSK, 1.375 Mb/s, AOUT = 65 MHz Figure 10. QPSK, 5.5 Mb/s, AOUT = 65 MHz Single Tone Output Spectrum with +3.3 V Supply, 20.48 MHz REFCLK 0 –10 0 0 –20 0 –30 0 –40 0 –50 0 –60 0 –70 0 –80 0 –90 –100 START 0Hz 6MHz/ STOP 60MHz RBW = 3kHz VBW = 3kHz SWT = 17s RF ATT = 30dB REF LVL = 0dBm 0 –10 0 0 –20 0 –30 –40 0 0 –50 0 –60 –70 0 0 –80 0 –90 –100 START 0Hz 6MHz/ STOP 60MHz RBW = 3kHz VBW = 3kHz SWT = 17s RF ATT = 30dB REF LVL = 0dBm Figure 8. AOUT = 1 MHz Figure 11. AOUT = 20 MHz 0 –10 0 –20 0 –30 0 0 –40 –50 0 –60 0 –70 0 –80 0 –90 0 –100 START 0Hz 6MHz/ STOP 60MHz RBW = 3kHz VBW = 3kHz SWT = 17s RF ATT = 30dB REF LVL = 0dBm 0 –10 0 –20 0 –30 0 0 –40 –50 0 –60 0 –70 0 –80 0 –90 0 –100 CENTER 40Hz 8MHz/ SPAN 80MHz RBW = 5kHz VBW = 5kHz SWT = 8s RF ATT = 30dB REF LVL = 0dBm Figure 9. AOUT = 42 MHz Figure 12. AOUT = 65 MHz (+5 V Supply, 27.5 MHz REFCLK) –8– REV. C AD9853 Output Phase Noise Plots, AOUT = 40 MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 40Hz 1kHz/ SPAN 10MHz RBW = 30Hz VBW = 30Hz SWT = 56s RF ATT = 20dB REF LVL = –1dBm 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 CENTER 40Hz 1kHz/ SPAN 10kHz RBW = 30Hz VBW = 30Hz SWT = 56s RF ATT = 20dB REF LVL = –1dBm Figure 13. 6 REFCLK Enabled Figure 14. 6 REFCLK Disabled CH PWR = –6.98dBm ACP UP = –44.95dBm ACP LOW = –44.66dBm ALT1 UP = –65.96dBm ALT1 LOW = –65.99dBm Figure 15. Adjacent Channel Power, AOUT = 30 MHz, 2.56 MS/s, Channel BW = 3.2 MHz (α = 0.25) REV. C –9– AD9853 Typical Plots of Eye Diagrams and Constellations REF LVL –7dBm 1.2 CF 42MHz MEAS SIGNAL SR 1.28MHz EYE [1] DEMOD QPSK REF LVL –8dBm 1.2 CF 42MHz MEAS SIGNAL SR 1.28MHz EYE [1] DEMOD 16QAM T1 –1.2 0 SYMBOLS 3 T1 –1.2 0 SYMBOLS 3 Figure 16. QPSK Modulation Figure 18. 16-QAM Modulation REF LVL –7dBm 1.2 CF 42MHz MEAS SIGNAL SR 1.28MHz CONSTELLATION DEMOD QPSK 1.2 REF LVL –8dBm CF 42MHz MEAS SIGNAL SR 1.28MHz CONSTELLATION DEMOD 16QAM T1 –1.2 –1.5 REAL 1.5 –1.2 –1.5 T1 REAL 1.5 Figure 17. QPSK Modulation Figure 19. 16-QAM Modulation –10– REV. C AD9853 95 0.80 85 AMBIENT TEMP – C BIT RATE >2Mb/s VCC = +5V CONTINUOUS MODE 0.75 CLK = 122.88 MHz VCC = +3.3V CONTINUOUS MODE 75 POWER – Watts 0.70 65 0.65 55 0.60 45 110 115 120 125 130 135 140 145 150 155 160 165 170 MAX CLOCK RATE – MHz 0.55 0 1 2 3 4 BIT RATE – Mb/s 5 6 Figure 20. Max CLK Rate vs. Ambient Temperature (To Ensure Max Junction Temp is Not Exceeded) Figure 23. PWR Consumption vs. Bit Rate 2.6 2.5 CLK = 165MHz VCC = +5.0V BIT RATE = 3.4Mb/s 2.4 VCC = +5.0V 2.2 POWER – Watts 2.4 2.0 CLK = 165MHz CONTINUOUS MODE POWER – Watts 1.5 2.0 2.5 3.0 3.5 2.3 2.2 1.8 1.6 1.4 1.2 0 2.1 VCC = +4.0V 2.0 0.5 1.0 1.9 0 20 40 60 80 BURST MODE DUTY CYCLE – % 100 BIT RATE – Mb/s Figure 21. Power Consumption vs. Bit Rate Figure 24. Power Consumption vs. Burst Duty Cycle –40 AOUT = 42MHz –40 AOUT = 65MHz –42 SPURIOUS IN-BAND EMISSION – dBc AOUT = 32MHz –45 SPURIOUS IN-BAND EMISSION – dBc –44 AOUT = 40MHz –46 –50 AOUT = 22MHz –48 AOUT = 20MHz –50 CLK = 165MHz VCC = +4.0V TO +5.0V –55 AOUT = 12MHz CLK = 122.88 MHz VCC = +3.3V –60 5.12 2.56 1.28 BIT RATE – Mb/s 0.64 –52 3.5 1.75 0.88 BIT RATE – Mb/s 0.44 Figure 22. Spurious Emission vs. Bit Rate vs. AOUT Figure 25. Spurious Emission vs. Bit Rate vs. AOUT REV. C –11– AD9853 FRAME STRUCTURE: MIN TXENABLE LOW TIME = PREAMBLE + 8 SYMBOLS. (EQUATES TO 8 SYMBOLS MINIMUM SPACING BETWEEN BURSTS WITH NO CHANGE IN PROFILE) TXENABLE NOTE: DATA RATE MUST BE PRECISELY SYNCHRONIZED WITH RISING EDGE OF TXENABLE D1 D2 D3 D4 D5 D6 D7 DN DON'T CARE D1 D2 D3 D4 D5 D6 D7 DN DON'T CARE DATA IN INTERNAL CODEWORD STRUCTURE AT R-S OUTPUT DATA PACKET = K BYTES ONE CODEWORD FEC PARITY (2T BYTES) DATA PACKET = K BYTES ONE CODEWORD FEC PARITY (2T BYTES) TXENABLE TO AOUT LATENCY FRAME STRUCTURE FOR MULTIPLE CODE WORDS OR CONTINOUS TRANSMISSION: TXENABLE DATA IN D1 D2 D3 D4 D5 D6 D7 DN DON'T CARE D1 D2 D3 D4 D5 D6 D7 DN DON'T CARE DATA PACKET = K BYTES FEC PARITY (2T BYTES) DATA PACKET = K BYTES FEC PARITY (2T BYTES) INPUT DATA PROCESSING: TXENABLE INTERNAL BIT CLOCK DATA IN D1 D2 D3 D4 D5 D59 D60 D61 D62 D63 D64 D65 DN ENCODER INPUT PREAMBLE INSERTION PREAMBLE LENGTH = 96 BITS MAXIMUM DURING THIS INTERVAL THE DATA IS R-S ENCODED, RANDOMIZED, AND DELAYED TO SYNCHRONIZE WITH THE END OF THE PREAMBLE DATA. D1 D2 DATA PACKET AND FEC PARITY COMPLETE FRAME AS PRESENTED TO MODULATOR ENCODER: PREAMBLE CODEWORD(S) NOTES ON BURST TRANSMISSION OPERATION: 1. PACKET LENGTH = NUMBER OF INFORMATION BYTES, K 2. IN FEC MODE TXENABLE MUST BE KEPT HIGH FOR N (K+2T) BYTES WHERE N IS THE NUMBER OF CODEWORDS 3. IF NECESSARY, ZERO FILL THE LAST CODEWORD TO REACH ASSIGNED K DATA BYTES PER CODEWORD 1 4. THE INPUT DATA IS SAMPLED AT THE BIT RATE FREQUENCY (fB) WITH THE FIRST SAMPLE TAKEN AT RISING EDGE OF TXENABLE (# OF PREAMBLE BITS) 5. PREAMBLE DELAY = (BIT RATE FREQUENCY) 2 (fB) SECONDS AFTER THE 6. DATA RATE MUST BE EXACT SUB-MULTIPLE OF REFERENCE CLOCK. Figure 26. Data Framing and Processing –12– REV. C AD9853 WRITE S DEVICE ADDRESS A(S) REGISTER ADDRESS A(S) DATA A(S) DATA A(S) P LSB = 0 LSB = 1 READ S DEVICE ADDRESS A(S) REGISTER ADDRESS A(S) S DEVICE ADDRESS A(S) DATA A(M) DATA A(M) P S = START CONDITION P = STOP CONDITION A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(M) = NO ACKNOWLEDGE BY MASTER Figure 27. Serial Control Bus—Read and Write Sequences MSB 0 0 0 0 0 1 A R/W LSB 0 = WRITE / 1 = READ ADDRESS CONTROL (SET VIA DEVICE PIN 6) Figure 28. Serial Control Bus—8-Bit Device Address Detail FEC DISABLE/ ENABLE CONTROL TX ENABLE t FH t FL tFH = FEC TO TXENABLE SETUP TIME = 0ns tFL = FEC TO TXENABLE HOLD TIME = 0ns Figure 29. FEC Enable/Disable Timing Diagram TX ENABLE t TR t RL RESET t MP t PWH t PWL CONTROL CLOCK t RH t CH t DS t DH t CS CONTROL DATA tTR = MINIMUM TXENABLE LOW TO RESET LOW = 10ns tRL = MINIMUM RESET PULSEWIDTH = 10ns tRH = MINIMUM RESET TO START CONDITION = 10ns tCH = MINIMUM CLOCK HOLD TIME START CONDITION = 10ns tCS = MINIMUM CLOCK SETUP TIME STOP CONDITION = 10ns tDS = MINIMUM DATA SETUP TIME = 10ns tDH = MINIMUM DATA HOLD TIME = 10ns tPWH = tPWL = MINIMUM CLOCK PULSEWIDTH HIGH/LOW = 10ns tMP = MINIMUM CLOCK PERIOD = 40ns = 25MHz Figure 30. Serial Control Interface Timing Diagram REV. C –13– AD9853 t RL RESET CONTROL BUS NOTE 1 NOTE 2 NOTE 2 START UP SEQUENCE TXENABLE DAC OUT t DL tRL: MINIMUM RESET LOW TIME = 10ns tDL: DATA LATENCY = 6 SYMBOLS NOTE 1. DURING THIS INTERVAL ALL CONTROL BUS REGISTERS MUST BE PROGRAMMED. NOTE 2. DURING THIS INTERVAL THE CONTROL REGISTER (48h) MAY NEED TO BE REPROGRAMMED DUE TO BEING CLEARED BY THE PRECEDING RESET PULSE. NOTE 3. THREE RESETS ARE REQUIRED TO ENSURE THAT THE DATA PATH IS ZERO'D. Figure 31. Recommended Start-Up Sequence NOTES ON THE RESET FUNCTION: 1. RESET IS ACTIVE LOW 2. RESET ZEROS THE CONTROL REGISTER AT ADDRESS 48 HEX WHICH CAUSES THE FOLLOWING DEFAULT CONDITION TO EXIST: A. 6 REFCLK IS DISABLED B. OUTPUT SPECTRUM IS SET TO I COS+Q SIN C. DIGITAL PLL POWER-DOWN IS DISABLED D. PLL POWER-DOWN IS DISABLED E. DAC PLL POWER-DOWN IS DISABLED 3. SERIAL CONTROL BUS IS RESET AND INITIALIZED. 4. OUTPUTS OF MODULATION ENCODERS ARE SET TO ZERO. THIS ALLOWS THE FIR FILTERS AND SUBSEQUENT INTERPOLATION FILTERS TO BE FLUSHED WITH ZEROS AS LONG AS TXENABLE IS HELD LOW. 5. THE PREAMBLE IS CLEARED UPON EXECUTION OF THE RESET FUNCTION. GAIN CONTROL BUS DATA IN REF CLOCK IN AD9853 DIGITAL QPSK/16–QAM MODULATOR COUPLING CIRCUIT AND LP FILTER AD8320 PROGRAMMABLE CABLE DRIVER AMPLIFIER TO DIPLEXER DIRECT CONTROL LINES SERIAL CONTROL BUS CONTROL CONTROL PROCESSOR PROCESSOR POWER DOWN Figure 32. Basic Implementation of AD9853 Digital Modulator and AD8320 Programmable Cable Driver Amplifier in Return-Path Application –14– REV. C AD9853 THEORY OF OPERATION The AD9853 is a highly integrated modulator function that has been specifically designed to meet the requirements of the HFC upstream function for both interoperable and proprietary system implementations. The AD8320 is a companion cable driver amplifier with a digitally-programmable gain function, that interfaces to the AD9853 modulator and directly drives the cable plant with the modulated carrier. Together, the AD9853 and AD8320 provide an easily implementable transmitter solution for the HFC return-path requirement. CONTROL AND DATA INTERFACE As shown in the device’s block diagram on the front page, the various transmit parameters, which include the input data rate, modulation format, FEC and randomizer configurations, as well as all the other modulator functions, are programmed into the AD9853 via a serial control bus. The AD8320 cable driver amp gain can be programmed directly from the AD9853 via a 3-wire bus by writing to the appropriate AD9853 register. The AD9853 also contains dedicated pins for FEC enable/disable and a RESET function. Note: TXENABLE pin must be held low for the duration of all serial control bus operations. The AD9853’s serial control bus consists of a bidirectional data line and a clock line. Communication is initiated upon a start condition, which is defined as a high-to-low transition of the data line while the clock is held high. Communication terminates upon a stop condition, which is defined as a low-to-high transition in the data line while the clock is held high. Ordinarily, the data line transitions only while the clock line is low to avoid a start or stop condition. Data is always written or read back in 8-bit bytes followed by a single acknowledge bit. The microcontroller or ASIC (i.e., the bus master) transfers eight data bits and the AD9853 (i.e., the slave) issues the acknowledge bit. The acknowledge bit is active low and is clocked out on every ninth clock pulse. The bus master must three-state the data line during the ninth clock pulse and allow the AD9853 to pull it low. A valid write sequence consists of a minimum of three bytes. This means 27 clock pulses (three bytes with nine clock pulses each) must be provided by the bus master. The first byte is a chip address byte that is predefined except for Bit Positions 1 and 0. Bit Positions 7, 6, 5, 4 and 3 must be zero. Bit Position 2 must be a one. Bit 1 is set according to the external address pin on the AD9853 (1 if the pin is connected to +VS; 0 if the pin is grounded). Bit 0 is set to 1 if a read operation is desired, 0 if a write operation is desired. The second byte is a register address with valid addresses between 00h and 49h. An address which is outside of this range will not be acknowledged. The third byte is data for the address register. Multiple data bytes are allowed and loaded sequentially. That is, the first data byte is written to the addressed register and any subsequent data bytes are written to subsequent register addresses. It is permissible to write all registers by issuing a valid chip address byte, then an address byte of 00h and then 72 (48h) data bytes. Address 49h must be written independently, that is, not in conjunction with any other address. A valid read sequence consists of a minimum of four bytes (refer to Figure 27). This means the bus master must provide 36 clock pulses (four bytes with nine clock pulses each). Like the write sequence, the first two bytes are the Chip Address Byte, with the REV. C read/write bit set to 0, and the readback register address. After the slave provides an acknowledge at the end of the register address, the master must present a START condition on the bus, followed by the Chip Address Byte with the read/write bit set to a 1. The slave proceeds to provide an acknowledge. During the next eight clocks the slave will write to the bus from the register address. The master must provide an acknowledge on the ninth clock of this byte. Any subsequent clocks from the master will force the slave to read back from subsequent registers. At the end of the read-back cycle, the MASTER must force a “no-acknowledge” and then a STOP condition. This will take the SLAVE out of read-back mode. Not all of the serial control bus registers can be read back. Registers (06h–11h) and (1Eh– 47h) are write only. Also, like the writing procedure, register 49h must be read from independently. INPUT DATA SYNCHRONIZATION The serial input data interface consists of two pins, the serial data input pin and a TXENABLE pin. The input data arrives at the bit rate and is framed by the TXENABLE signal as shown in Figure 26. A high frequency sampling clock continuously samples the TXENABLE signal to detect the rising edge. Once the rising edge of TXENABLE is detected, an internal sampler strobes the serial data at the correct point in time relative to the positive TXENABLE transition and then continues to sample at the correct interval based on the programmed Input Data rate. For proper synchronization of the AD9853, 1) the input burst data must be accurately framed by TXENABLE and 2) the input data rate must be an exact even submultiple of the system clock. Typically this will require that the input data rate clock be synchronized with reference clock. REED-SOLOMON ENCODER The AD9853 contains a programmable Reed-Solomon (R-S) encoder capable of generating an (N, K) code where N is the code word length and K is the message length. Error correction becomes vital to reliable communications when the transmission channel conditions are less than ideal. The original message can be precisely reconstructed from a corrupted transmission as long as the number of message errors is within the encoder’s limits. When forward error correction (FEC) is engaged, either through the serial control interface bus or hardware (logic high at Pin 5), it is implemented using the following MCNS-compatible field generator and primitive polynomials: Primitive Polynomial: p(x) = x8 + x4 + x3 + x2 + 1 Code Generator Polynomial: g(x) = (x + a0)(x + a1)(x + a2) . . . (x + a2t – 1) The code-word structure is defined as follows: N = K + 2t (bytes) where: N = code-word length K = message length (in bytes), programmable from 16–255 t= number of byte errors that can be corrected programmable from 0–10. A Code Word is the sum of the Message Length (in bytes) and number of Check Bytes required to correct byte errors at the –15– AD9853 receive end. The values actually programmed on the serial control bus are “K” and “t,” which will define N as shown in the above code-word structure equation. As can be seen from the code-word structure equation, two check bytes are required to correct each byte error. Setting t = 0 and K > 0 will bypass the Reed-Solomon encoding process. Since Reed-Solomon works on bytes of information and not bits, a single byte error can be as small as one inverted bit out of a byte, or as large as eight inverted bits of one byte; in either instance the result is one byte error. For example, if the value “t” is specified as 5, the R-S FEC could be correcting as many as 40, or as few as 05, erroneous bits, but those errors must be contained in 5 message bytes. If the errors are spread among more than five bytes, the message will not be fully error corrected. When using the R-S encoder, the message data needs to be partitioned or “gapped” with “don’t care” data for the time duration of the check bytes as shown in the timing diagram of Figure 26. During the intervals between message data, the device ignores data at the input. The position of the R-S encoder in the coding data path can be switched with the randomizer by exercising Register 1, Bit D3, via the serial control bus. RANDOMIZER FUNCTION PREAMBLE INSERTION BLOCK As shown in the block diagram of the AD9853, the circuit includes a programmable preamble insertion register. This register is 96 bits long and is transmitted upon receiving the TXENABLE signal. It is transmitted without being Reed-Solomon encoded or scrambled. Ramp-up data, to allow for receiver synchronization, is included as the first bits in the preamble, followed by user burst profile or channel equalization information. The first bit of R-S encoded and scrambled information data is timed to immediately follow the last bit of preamble data. For most modulation modes, a minimum preamble is required. This minimum is one symbol, two bits for DQPSK or four bits for either 16-QAM or D16-QAM. No preamble is required for either FSK or QPSK. In conformance with DAVIC/DVB standards, the preamble is not differentially coded in DQPSK mode. However the preamble data can be differentially precoded when loaded into the preamble register. The last symbol of the preamble is used as the reference point for the first internal differentially coded symbol so the preamble and data will effectively be coded differentially. In the D16-QAM mode, the preamble is always differentially coded internally. MODULATION ENCODER The next stage in the modulation chain is the randomizing or “scrambling” stage. Randomizing is necessary due to the fact that impairments in digital transmission can be a function of the statistics of the digital source. Receiver symbol synchronization is more easily maintained if the input sequence appears random or equiprobable. Long strings of 0s or 1s can cause a bit or symbol synchronizer to lose synchronization. If there are repetitive patterns in the data, discrete spurs can be produced, causing interchannel interference. In modulation schemes relying on suppressed carrier transmission, nonrandom data can increase the carrier feedthrough. Using a randomizer effectively “whitens” the data. The technique used in the AD9853 to randomize the data is to perform a modulo 2 logic addition of the data with a pseudorandom sequence. The pseudorandom sequence is generated by a shift register of length m with an exclusive OR combination of the nth bit and the last (mth) bit of the shift register that is fed back to the shift register input. By choosing the appropriate feedback point, a maximal length sequence is generated. The maximal length sequence will repeat after every 2m clock cycles, but appears effectively “random” at the output. The criterion for maximal length is that the polynomial 1 + xn + xm be irreducible and prime over the Galois field. The AD9853 contains the following two polynomial configurations in hardware: x15 + x14 +1 :MCNS (DOCSIS) compatible. x6 + x5 +1 :DAVIC/DVB compatible. The seed value is fully programmable for both configurations. The seed value is reset prior to each burst and is used to calculate the randomizer bit, which is combined in an exclusive XOR with the first bit of data from each burst. The first bit of data in a burst is the MSB of the first symbol following the last symbol of the internally generated preamble. The preamble, followed by the encoded and scrambled data is then modulation encoded according to the selected modulation format. The available modulation formats are FSK, QPSK, DQPSK, 16-QAM and D16-QAM. The corresponding symbol constellations support the interactive HFC cable specifications called out by MCNS (DOCSIS), 802.14 and DAVIC/DVB. The data arrives at the modulation encoder at the input bit rate and is demultiplexed as modulation encoded symbols into separate I and Q paths. For QPSK and DQPSK, the symbol rate is one-half of the bit rate and each symbol is comprised of two bits. For 16-QAM and D16-QAM, the symbol rate is onefourth the bit rate and each symbol is comprised of four bits. In the FSK mode, although the 1 and 0 data is entered into the serial data input, it effectively bypasses the encoding, scrambling and modulation paths. The FSK data is directly routed to the direct digital synthesizer (DDS) where it is used to switch the DDS between two stored tuning words (F0:F1) to achieve FSK modulation in a phase-continuous manner. By holding the input at either 1 or 0, a single frequency continuous wave can be output for system test or CW transmission purposes. Differential encoding of data is frequently used to overcome phase ambiguity error or a “false lock” condition that can be introduced in carrier-recovery circuits used to demodulate the signal. In straight QPSK and 16-QAM, the phase of the received signal is compared to that of a “recovered carrier” of known phase to demodulate the signal in a coherent manner. If the phase of the recovered carrier is in error, then demodulation will be in error. Differential encoding of data at the transmit end eliminates the need for absolute phase coherency of the recovered carrier at the receive end. If a coherent reference generated by a phase lock loop experiences a phase inversion while demodulating in a differentially coded format, the errors would be limited to the symbol during which the inversion occurred and the following symbol. Differential coding uses the phase of the “previously transmitted symbol” as a reference point to compare to the current symbol. The change in phase from one symbol to REV. C –16– AD9853 the next contains the message information and is used to demodulate the signal instead of the absolute phase of the signal. The transmitter and receiver must use the same symbol derivation scheme. Differential encoding in the AD9853 occurs while data still exists as a serial data stream. When in straight QPSK or 16-QAM, the serial data stream passes to the symbol mapper/format encoder stage without modification. When differential encoding is engaged, the serial data stream is modified prior to the symbol mapper/format stage according to Table VI. Only I1 and Q1 are modified, even in the D16-QAM mode whose symbols are composed of Q1, I1, Q0, I0. In D16-QAM, only the two MSBs of the 4-bit symbol are modified; furthermore, the “previously transmitted symbol” referred to in Table VI are the two MSBs of the previous 4-bit symbol. Symbol mapping for QPSK and DQPSK are identical. Symbol mapping for 16-QAM and D16-QAM are slightly different (see Figure 37) in accordance with MCNS (DOCSIS) specifications. Special Note: For most modulation modes, a minimum preamble is required. For DQPSK the minimum preamble is one symbol (2 bits) and for either 16-QAM or D16-QAM the minimum preamble is one symbol (4 bits). For FSK or QPSK, no preamble is required. User should be additionally aware that in the DQPSK mode, the preamble is not differentially encoded in accordance with MCNS (DOCSIS) specifications. If the preamble must be differentially encoded, it can “pre-encoded” using the derivation in Table VI. In D16-QAM, the preamble is always differentially encoded as is the “payload” data. When initiating a new differentially encoded transmission, the “previously transmitted symbol” is always the last symbol of the preamble. PROGRAMMABLE PULSE-SHAPING FIR FILTERS 0 and 1 yield a tradeoff between excess bandwidth in the frequency domain and tail suppression in the time domain. The FIR filter coefficients for the SRRC response may be calculated using a variety of methods. One such method uses the Inverse Fourier Transform Integral to calculate the impulse response (time domain) from the SRRC frequency response (frequency domain). An example of this method is shown in Figure 33. Of course, this method requires that the SRRC frequency response be known beforehand. The FIR filters in the AD9853 are implemented in hardware using a fixed point architecture of 10-bit, twos complement integers. Thus, each of the filter coefficients, ai, is an integer such that: –512 ≤ ai ≤ 511 [i = 0, 1, … , 40] PROGRAMMABLE INTERPOLATION FILTERS The AD9853 employs two stages of interpolation filters in each of the I and Q channels of the modulator. These filters are implemented as Cascaded Integrator-Comb (CIC) filters. CIC filters are unique in that they not only provide a low-pass frequency response characteristic, but also provide the ability to have one sampling rate at the input and another sampling rate at the output. In general, a CIC filter may either be used as an interpolator (low-to-high sample rate conversion) or as a decimator (high-to-low sample rate conversion). In the case of the AD9853, the CIC filters are configured as interpolators, only. Furthermore, the interpolation is done in two separate stages with each stage designed so that the rate change is programmable. The first interpolator stage offers rate change ratios of 3 to 31, while the second stage offers rate change ratios of 2 to 63. As stated in the previous section, the data coming out of the FIR filters is oversampled by four. Spectral images appear at their output (a direct result of the sampling process). These images are replicas of the baseband spectrum which are repeated at intervals of four times the symbol rate (the rate at which the FIR filters sample the data). The images are an unwanted byproduct of the sampling process and effectively represent a source of noise. Normally, the output of the FIR filters would be fed directly to the input of the I and Q modulator. This means that the spectral images produced by the FIRs would become part of the modulated signal—definitely not a desirable consequence. This is where the CIC filters play their role. Since they have a low-pass characteristic, they can be used to eliminate the spectral images produced by the FIRs. Frequency Response of the CIC Filters The I and Q data paths of the modulator each contain a pulse shaping filter. Each is a 41-tap, linear phase FIR. They are used to provide bandwidth containment and pulse shaping of the data in order to minimize intersymbol interference. The filter coefficients are programmable, so any realizable linear phase response characteristic may be implemented. The linear phase restriction is due to the fact that the user may only define the center coefficient and the lower 20 coefficients. The hardware fills in the upper 20 coefficients as a mirror image of the lower 20. This forces a linear phase response. It should also be noted that the pulse shaping filter upsamples the symbol rate by a factor of four. Normally, a square-root raised cosine (SRRC) response is desired. In fact, the AD9853 Evaluation Board software driver implements an SRRC response. When using the SRRC response, an excess bandwidth factor (α) is defined that affects the low pass roll-off characteristic of the filter (where 0 ≤ α ≤ 1). When α = 0, the SRRC is an ideal low-pass filter with a “brick wall” at one-half of the symbol rate (the Nyquist bandwidth of the data). Although this provides maximum bandwidth containment, it has the adverse affect of causing the tails of the time domain response to be large, which increases intersymbol interference (ISI). On the other hand, when α = 1, the SRRC yields a smooth roll-off characteristic that significantly reduces the time domain tails, which improves ISI. Unfortunately, the cost of this benefit is a doubling of the bandwidth of the data signal. Values of α between REV. C The frequency response of a CIC filter is predictable. It can be shown that the system function of a CIC filter is:  R M −1  H (z ) =  ∑ z − k   k=0  N Where N is the number of cascaded integrator (or comb) sections, R is the rate change ratio, and M is the number of unit delays in each integrator/comb stage. For the AD9853, two of these variables are fixed as a result of the hardware implementation; specifically, N = 4 and M = 1. As mentioned earlier, R (the rate change ratio) is programmable. –17– AD9853 SQUARE-ROOT RAISED COSINE (SRRC) FIR FILTER COMPUTE AND PLOT SRRC FILTER COEFFICIENTS: tap := 0..TAPS – 1 ttap := 1 . tap – TAPS – 1 2 FreqScale ...MAP THE FILTER TAP INDEX TO TIME DOMAIN (CENTERED AT T=0) BW h(t) := 0 h . SCALEPROC GAIN max(h) SRRC(f) . cos(2 . . f . t)df ...INVERSE FOURIER INTEGRAL COMPUTE SRRC IMPULSE RESPONSE (TIME DOMAIN) FROM THE SRRC FREQUENCY RESPONSE (FREQUENCY DOMAIN). THE COS() FUNCTION REPLACES THE NORMAL COMPLEX EXPONENTIAL BECAUSE WE ARE RESTRICTED TO REAL FILTER COEFFICIENTS. htap := h(ttap) h := INT ...SRRC FILTER COEFFICIENTS INTEGERIZED AND SCALED SRRC IMPULSE RESPONSE 500 htap 0 0 5 10 15 20 TAP 0 hT = 0 0 1 3 2 2 3 –2 4 –5 5 –2 6 5 7 7 8 1 9 –7 10 –7 11 7 12 19 13 7 14 15 16 17 71 18 19 20 ...FIR FILTER COEFFICIENTS 25 30 35 40 –34 –71 –48 260 438 511 COMPUTE AND PLOT SRRC FREQUENCY RESPONSE: freq_pts := 250 n := 0..freq_pts – 1 0.5 f := freq_pts – 1 fn := f . n ...DEFINE NUMBER OF FREQUENCY POINTS AND FREQUENCY STEP SIZE (FOR PLOTTING PURPOSES) ...CREATE VECTOR OF UNIFORMLY SPACED FREQUENCY POINTS {fmax = 0.5; A REQUIREMENT OF THE GAIN() FUNCTION}, ...NORMALIZED FREQUENCY RESPONSE K := (| gain(h,0) |)–1 Hn := K . | gain (h,fn) | SRRC NORMALIZED FREQUENCY RESPONSE 0 FREQUENCY SCALED TO SYMBOL RATE Hn – dB –20 –40 –60 0 0.2 0.4 0.6 0.8 1.0 1.2 FREQUENCY SCALE – fn 1.4 1.6 1.8 2.0 GLOBAL DECLARATIONS CONSTANTS: 0.5 . BW 0.5 (1 + ) 1 PROC_GAIN 511 SCALE TAPS 41 FreqScale 4 ...EXCESS BANDWIDTH FACTOR FOR SRRC FREQUENCY RESPONSE ...BANDWIDTH OF SRRC FILTER (RELATIVE TO SYMBOL RATE) ...PROCESSING GAIN OF CIC FILTERS (USED TO CORRELATE RESULTS WITH AD9853 EVAL. BD.) ...SETS MAX VALUE OF SRRC FILTER BASED ON FINITE WORD SIZE ...NUMBER OF FIR PULSE SHAPING FILTER TAPS ...UPSAMPLING RATIO OF FIR PULSE SHAPING FILTER (RELATIVE TO THE SYMBOL RATE) FUNCTIONS: InRange (x,a,b) (x a) . (x b) INT(x) floor (x + 0.5) dB(x) if (| x | = 0, 200, 20. log (| x |)) SRRC(f) passband 0.5 . (1 – ) stopband 0.5 (1 + ) if InRange (f, 0, stopband) 1 if InRange (f, 0, passband) cos 4. . (2 . f + ...RETURNS 1 IF a