AD9861-80EB

Mixed-Signal Front-End (MxFE™) Baseband Transceiver for Broadband Applications AD9861 FEATURES Receive path includes dual 10-bit analog-to-digital converters with internal or external reference, 50 MSPS and 80 MSPS versions Transmit path includes dual 10-bit, 200 MSPS digital-toanalog converters with 1×, 2×, or 4× interpolation and programmable gain control Internal clock distribution block includes a programmable phase-locked loop and timing generation circuitry, allowing single-reference clock operation 20-pin flexible I/O data interface allows various interleaved or noninterleaved data transfers in half-duplex mode and interleaved data transfers in full-duplex mode Configurable through register programmability or optionally limited programmability through mode pins Independent Rx and Tx power-down control pins 64-lead LFCSP package (9 mm × 9 mm footprint) 3 configurable auxiliary converter pins VIN+A ADC VIN–A VIN+B ADC VIN–B I/O INTERFACE CONFIGURATION BLOCK DATA MUX AND LATCH Rx DATA FUNCTIONAL BLOCK DIAGRAM I/O INTERFACE CONTROL FLEXIBLE I/O BUS [0:19] LOW-PASS INTERPOLATION FILTER IOUT+A DAC IOUT–A IOUT+B DAC IOUT–B DATA LATCH AND DEMUX Tx DATA AUX ADC AUX DAC ADC CLOCK AUX DAC DAC CLOCK AUX ADC PLL CLKIN APPLICATIONS Broadband access Broadband LAN Communications (modems) AD9861 AUX DAC 03606-0-001 Figure 1. GENERAL DESCRIPTION The AD9861 is a member of the MxFE family—a group of integrated converters for the communications market. The AD9861 integrates dual 10-bit analog-to-digital converters (ADC) and dual 10-bit digital-to-analog converters (TxDAC®). Two speed grades are available, -50 and -80. The -50 is optimized for ADC sampling of 50 MSPS and less, while the -80 is optimized for ADC sample rates between 50 MSPS and 80 MSPS. The dual TxDACs operate at speeds up to 200 MHz and include a bypassable 2× or 4× interpolation filter. Three auxiliary converters are also available to provide required system level control voltages or to monitor system signals. The AD9861 is optimized for high performance, low power, small form factor, and to provide a cost-effective solution for the broadband communication market. The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADC and TxDAC clocks are generated within a timing generation block that provides user programmable options such as divide circuits, PLL multipliers, and switches. A flexible, bidirectional 20-bit I/O bus accommodates a variety Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. of custom digital back ends or open market DSPs. In half-duplex systems, the interface supports 20-bit parallel transfers or 10-bit interleaved transfers. In full-duplex systems, the interface supports an interleaved 10-bit ADC bus and an interleaved 10-bit TxDAC bus. The flexible I/O bus reduces pin count and, therefore, reduces the required package size on the AD9861 and the device to which it connects. The AD9861 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC interpolation rate, and control ADC and TxDAC power-down. The SPI provides more programmable options for both the TxDAC path (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal duty cycle stabilizer, and twos complement data format). The AD9861 is packaged in a 64-lead LFCSP (low profile, fine pitched, chip scale package). The 64-lead LFCSP footprint is only 9 mm × 9 mm, and is less than 0.9 mm high, fitting into tightly spaced applications such as PCMCIA cards One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. AD9861 TABLE OF CONTENTS Tx Path Specifications ...................................................................... 3 Rx Path Specifications ...................................................................... 4 Power Specifications......................................................................... 5 Digital Specifications........................................................................ 5 Timing Specifications....................................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Pin Function Descriptions ...................... 8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 21 Theory of Operation ...................................................................... 22 System Block ............................................................................... 22 Rx Path Block .............................................................................. 22 Tx Path Block .............................................................................. 24 Auxiliary Converters.................................................................. 27 Digital Block................................................................................ 30 Programmable Registers............................................................ 42 Clock Distribution Block .......................................................... 45 Outline Dimensions ....................................................................... 49 Ordering Guide .......................................................................... 50 REVISION HISTORY Revision 0: Initial Version Rev. 0 | Page 2 of 52 AD9861 Tx PATH SPECIFICATIONS Table 1. AD9861-50 and AD9861-80 FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 kΩ; differential load resistance of 100 Ω1; TxPGA = 20 dB, AVDD = DVDD = 3.3 V, unless otherwise noted Parameter Tx PATH GENERAL Resolution Maximum DAC Update Rate Maximum Full-Scale Output Current Full-Scale Error Gain Mismatch Error Offset Mismatch Error Reference Voltage Output Capacitance Phase Noise (1 kHz Offset, 6 MHz Tone) Output Voltage Compliance Range TxPGA Gain Range TxPGA Step Size Tx PATH DYNAMIC PERFORMANCE (IOUTFS = 20 mA; FOUT = 1 MHz) SNR SINAD THD SFDR, Wideband (DC to Nyquist) SFDR, Narrowband (1 MHz Window) 1 Temp Full Full Full Full 25°C Full Full Full 25°C Full Full Full Test Level IV IV IV V IV IV V V V IV V V Min Typ 10 Max Unit Bits MHz mA 200 20 1% –3.5 –0.1 1.23 5 –115 –1.0 20 0.10 +1.0 +3.5 +0.1 % FS % FS V pF dBc/Hz V dB dB Full Full Full Full Full IV IV IV IV IV 60.2 59.7 64.6 72.5 60.8 60.7 −77.5 76.0 81.0 −65.8 dB dB dBc dBc dBc See Figure 2 for description of the TxDAC termination scheme. TxDAC 50Ω 50Ω 03606-0-030 Figure 2. Diagram Showing Termination of 100 Ω Differential Load for Some TxDAC Measurements Rev. 0 | Page 3 of 52 AD9861 Rx PATH SPECIFICATIONS Table 2. AD9861-50 and AD9861-80 FADC = 50 MSPS for the AD9861-50, 80 MSPS for the AD9861-80; internal reference; differential analog inputs, ADC_AVDD = DVDD = 3.3V, unless otherwise noted Parameter Rx PATH GENERAL Resolution Maximum ADC Sample Rate Gain Mismatch Error Offset Mismatch Error Reference Voltage Reference Voltage (REFT–REFB) Error Input Resistance (Differential) Input Capacitance Input Bandwidth Differential Analog Input Voltage Range Rx PATH DC ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Aperature Delay Aperature Uncertainty (Jitter) Input Referred Noise AD9861-50 Rx PATH DYNAMIC PERFORMANCE (VIN = –0.5 dBFS; FIN = 10 MHz) SNR SINAD SINAD THD (Second to Ninth Harmonics) SFDR, Wideband (DC to Nyquist) Crosstalk between ADC Inputs AD9861-80 Rx PATH DYNAMIC PERFORMANCE (VIN = –0.5 dBFS; FIN = 10 MHz) SNR SINAD THD (Second to Ninth Harmonics) SFDR, Wideband (DC to Nyquist) Crosstalk between ADC Inputs Temp Full Full Full Full Full Full Full Full Full Full 25°C 25°C 25°C 25°C 25°C Test Level V IV V V V IV V V V V V V V V V Min Typ 10 50/80 ±0.2 ±0.1 1.0 ±6 2 5 30 2 ±0.75 ±0.75 2.0 1.2 450 Max Unit Bits MSPS % FS % FS V mV kΩ pF MHz V p-p differential LSB LSB ns ps rms uV –30 +30 Full Full 25°C Full Full Full IV IV IV IV IV V 55.5 55.6 58.5 65.7 60 60 60 −71.5 73.5 80 −64.6 dBc dBc dBc dBc dBc dB Full Full Full Full Full IV IV IV IV V 55.4 52.7 59.5 59.0 −67 67 80 dBc dBc dBc dBc dB Rev. 0 | Page 4 of 52 AD9861 POWER SPECIFICATIONS Table 3. AD9861-50 and AD9861-80 Analog and digital supplies = 3.3 V; FCLKIN = 50 MHz; PLL 4× setting; normal timing mode Parameter POWER SUPPLY RANGE Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Driver Supply Voltage (DRVDD) ANALOG SUPPLY CURRENTS TxPath (20 mA Full-Scale Outputs) TxPath (2 mA Full-Scale Outputs) Rx Path (-80, at 80 MSPS) RxPath (-80, at 40 MSPS, Low Power Mode) RxPath (-80, at 20 MSPS, Ultralow Power Mode) Rx Path (-50, at 50 MSPS) RxPath (-50, at 50 MSPS, Low Power Mode) RxPath (-50, at 16 MSPS, Ultralow Power Mode) TxPath, Power-Down Mode RxPath, Power-Down Mode PLL DIGITAL SUPPLY CURRENTS TxPath, 1× Interpolation, 50 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode TxPath, 2× Interpolation, 100 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode TxPath, 4× Interpolation, 200 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode RxPath Digital, Half-Duplex 24 Mode Temp Full Full Full Test Level IV IV IV Min 2.7 2.7 2.7 Typ Max 3.6 3.6 3.6 Unit V V V Full Full Full Full Full Full Full Full Full Full Full Full V V V V V V V V V V V V 70 20 165 82 35 103 69 28 2 5 12 20 mA mA mA mA mA mA mA mA mA mA mA mA Full V 50 mA Full V 80 mA Full V 15 mA DIGITAL SPECIFICATIONS Table 4. AD9861-50 and AD9861-80 Parameter LOGIC LEVELS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Output Logic High Voltage, VOH (1 mA Load) Output Logic Low Voltage, VOL (1 mA Load) DIGITAL PIN Input Leakage Current Input Capacitance Minimum RESET Low Pulse Width Digital Output Rise/Fall Time Temp Full Full Full Full Full Full Full Full Test Level IV IV IV IV IV IV IV IV Min DRVDD – 0.7 0.4 DRVDD – 0.6 0.4 12 3 5 2.8 4 Typ Max Unit V V V V µA pF Input Clock Cycles ns Rev. 0 | Page 5 of 52 AD9861 TIMING SPECIFICATIONS Table 5. AD9861-50 and AD9861-80 Parameter INPUT CLOCK CLKIN Clock Rate (PLL Bypassed) PLL Input Frequency PLL Ouput Frequency TxPATH DATA Setup Time (HD20 Mode, Time Required Before Data Latching Edge) Hold Time (HD20 Mode, Time Required After Data Latching Edge) Latency 1× Interpolation (data in until peak output response) Latency 2× Interpolation (data in until peak output response) Latency 4× Interpolation (data in until peak output response) RxPATH DATA Output Delay (HD20 Mode, tOD) Temp Full Full Full Full Test Level IV IV IV V Min 1 16 32 5 Typ Max 200 200 350 Unit MHz MHz MHz ns (see Clock Distribution Block section) ns (see Clock Distribution Block section) DAC Clock Cycles DAC Clock Cycles DAC Clock Cycles ns (see Clock Distribution Block section) ADC Clock Cycles Full V –1.5 Full Full Full Full V V V V 7 35 83 –1.5 Latency Full V 5 Table 6. Explanation of Test Levels Level I II III IV V VI Description 100% production tested. 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. Rev. 0 | Page 6 of 52 AD9861 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Electrical AVDD Voltage DRVDD Voltage Analog Input Voltage Digital Input Voltage Digital Output Current Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating 3.9 V max 3.9 V max –0.3 V to AVDD + 0.3 V –0.3 V to DVDD – 0.3 V 5 mA max –40°C to +85°C 150°C 300°C –65°C to +150°C Thermal Resistance 64-lead LFCSP (4-layer board): θJA = 24.2 (paddle soldered to ground plan, 0 LPM Air) θJA = 30.8 (paddle not soldered to ground plan, 0 LPM Air) Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 7 of 52 AD9861 PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS SPI_CS TxPWRDWN RxPWRDWN ADC_AVDD REFT ADC_AVSS VIN+A VIN–A VREF VIN–B VIN+B ADC_AVSS REFB ADC_AVDD PLL_AVDD PLL_AVSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SPI_DIO SPI_CLK SPI_SDO/AUX_SPI_SDO ADC_LO_PWR/AUX_SPI_CS DVDD DVSS AVDD IOUT–A IOUT+A AGND REFIO FSADJ AGND IOUT+B IOUT–B AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 CLKIN 47 AUXADC_REF 46 RESET 45 AUX_DACC/AUX_ADCB 44 L0 43 L1 AD9861 TOP VIEW (Not to Scale) 42 L2 41 L3 40 L4 39 L5 38 L6 37 L7 36 L8 35 L9 34 AUX_SPI_CLK 33 IFACE1 IFACE2 IFACE3 U9 U8 U7 U6 U5 U4 U3 U2 U1 U0 AUX_DACA/AUX_ADCA2 AUX_DACB/AUX_ADCA1 DRVDD DRVSS 03606-0-019 Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5, 31 6, 32 7, 16, 50, 51, 61 8, 9 10, 13, 49, 53, 59 11 12 14, 15 17 18 19–28 29 30 33 Name1 SPI_DIO (Interp1) SPI_CLK (Interp0) SPI_SDO/AUXSPI_SDO (FD/HD) ADC_LO_PWR/AUX_SPI_CS DVDD DVSS AVDD IOUT–A, IOUT+A AGND, AVSS REFIO FSADJ IOUT+B, IOUT−B IFACE2 (10/20) IFACE3 U9–U0 AUX1 AUX2 IFACE1 Description2, 3 SPI: Serial Port Data Input. No SPI: Tx Interpolation Pin, MSB. SPI: Serial Port Shift Clock. No SPI: Tx Interpolation Pin, LSB. SPI: 4-Wire Serial Port Data Output/Data Output Pin for AuxSPI. No SPI: Configures Full-Duplex or Half-Duplex Mode. ADC Low Power Mode Enable. Defined at power-up. CS for AuxSPI. Digital Supply. Digital Ground. Analog Supply. DAC A Differential Output. Analog Ground. Tx DAC Band Gap Reference Decoupling Pin. Tx DAC Full-Scale Adjust Pin. DAC B Differential Output. SPI: Buffered CLKIN. Can be configured as system clock output. No SPI: For FD: Buffered CLKIN; For HD20 or HD10 : 10/20 Configuration Pin. Clock Output. Upper Data Bit 9 to Upper Data Bit 0. Configurable as either AuxADC_A2 or AuxDAC_A. Configurable as either AuxADC_A1 or AuxDAC_B. SPI: For FD: TxSYNC; For HD20, HD10, or Clone: Tx/Rx. No SPI: FD >> TxSYNC; HD20 or HD10: Tx/Rx. Rev. 0 | Page 8 of 52 AD9861 Pin No. 34 35–44 45 46 47 48 52 54, 55 56 57, 58 60 62 63 64 1 2 Name1 AUX_SPI_CLK L9–L0 AUX3 RESET AUX_ADC_REF CLKIN REFB VIN+B, VIN−B VREF VIN−A, VIN+A REFT RxPwrDwn TxPwrDwn SPI_CS Description2, 3 CLK for AuxSPI. Lower Data Bit 9 to Lower Data Bit 0. Configurable as either AuxADC_B or AuxDAC_C. Chip Reset When Low. Decoupling for AuxADC On-Chip Reference. Clock Input. ADC Bottom Reference. ADC B Differential Input. ADC Band Gap Reference. ADC A Differential Input. ADC Top Reference. Rx Analog Power-Down Control. Tx Analog Power-Down Control. SPI: Serial Port Chip Select. At power-up or reset, this must be high. No SPI: Tie low to disable SPI and use mode pins. This pin must be tied low. Underlined pin names and descriptions apply when the device is configured without a serial port interface, referred to as no SPI mode. Pin function depends if the serial port is used to configure the AD9861 (called SPI mode) or if mode pins are used to configure the AD9861 (called No SPI mode). The differences are indicated by the SPI and No SPI labels in the description column. 3 Some pin descriptions depend on the interface configuration, full-duplex (FD), half-duplex interleaved data (HD10), half-duplex parallel data (HD20), and a half-duplex interface similar to the AD9860 and AD9862 data interface called clone mode (Clone). Clone mode requires a serial port interface. Rev. 0 | Page 9 of 52 AD9861 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 03606-0-031 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-032 –100 –110 0 5 15 10 FREQUENCY (MHz) 20 25 Figure 4. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 2 MHz Tone 0 –10 –20 –30 Figure 7. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 1 MHz and 2 MHz Tones 0 –10 –20 –30 AMPLITUDE (dBFS) 03606-0-033 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-034 Figure 5. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 5 MHz Tone Figure 8. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 5 MHz and 8 MHz Tones 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 03606-0-035 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-036 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 6. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 24 MHz Tone Figure 9. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 20 MHz and 25 MHz Tones Rev. 0 | Page 10 of 52 AD9861 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 03606-0-037 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-038 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 10. AD9861-50 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 76 MHz Tone Figure 13. AD9861-50 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 70 MHz and 72 MHz Tones 62 NORMAL POWER @ 50MSPS 62 NORMAL POWER @ 50MSPS 10.0 9.8 LOW POWER ADC @ 25MSPS 59 59 LOW POWER ADC @ 25MSPS 9.6 9.4 SINAD (dBc) SNR (dBc) 9.2 56 9.0 8.8 ULTRALOW POWER ADC @ 16MSPS 8.6 8.4 8.2 50 0 5 15 10 INPUT FREQUENCY (MHz) 20 8.0 25 56 53 ULTRALOW POWER ADC @ 16MSPS 53 03606-0-039 50 0 5 15 10 INPUT FREQUENCY (MHz) 20 25 Figure 11. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Frequency Figure 14. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SINAD Performance vs. Input Frequency 80 LOW POWER ADC @ 25MSPS –50 75 NORMAL POWER @ 50MSPS –55 70 –60 SFDR (dBc) THD (dBc) ULTRALOW POWER ADC @ 16MSPS –65 NORMAL POWER @ 50MSPS 65 60 ULTRALOW POWER ADC @ 16MSPS 03606-0-041 –70 LOW POWER ADC @ 25MSPS –80 0 5 10 15 INPUT FREQUENCY (MHz) 20 25 50 0 5 10 15 INPUT FREQUENCY (MHz) 20 25 Figure 12. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SFDR Performance vs. Input Frequency Figure 15. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone THD Performance vs. Input Frequency Rev. 0 | Page 11 of 52 03606-0-042 55 –75 03606-0-040 ENOB (Bits) AD9861 70 60 50 90 SFDR 80 70 –80 –70 –60 –50 –40 –90 SFDR (dBFS) 40 IDEAL SNR 30 SNR 20 10 0 0 –5 –10 –15 –20 –25 –30 INPUT AMPLITUDE (dBFS) –35 –40 60 50 40 30 20 0 –5 –10 –15 –20 –25 –30 INPUT AMPLITUDE (dBFS) –35 –45 –20 –40 Figure 16. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Amplitude Figure 19. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone THD and SFDR Performance vs. Input Amplitude 62 AVE (–40°C) 61 AVE (+25°C) 62 10.0 9.9 61 AVE (–40°C) AVE (+25°C) 9.8 9.7 SINAD (dBc) SNR (dBc) 59 AVE (+85°C) 59 AVE (+85°C) 9.5 9.4 58 58 9.3 9.2 9.1 03606-0-046 03606-0-045 57 57 56 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V) 3.6 56 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V) 9.0 3.6 Figure 17. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. ADC_AVDD and Temperature –70.0 –70.5 –71.0 –71.5 AVE (+85°C) Figure 20. AD9861-50 Rx Path at 50 MSPS, 10 MHz Input Tone SINAD Performance vs. ADC_AVDD and Temperature 70 71 72 AVE (+85°C) 73 74 AVE (+25°C) 75 AVE (–40°C) 76 03606-0-047 THD (dBc) –72.0 AVE (+25°C) –72.5 –73.0 –73.5 AVE (–40°C) –74.0 –74.5 –75.0 3.6 3.3 3.0 INPUT AMPLITUDE (dBFS) SFDR (dBc) 77 78 3.6 2.7 3.3 3.0 INPUT AMPLITUDE (dBFS) 2.7 Figure 18. AD9861-50 Rx Path Single-Tone THD Performance vs. ADC_AVDD and Temperature Figure 21. AD9861-50 Rx Path Single-Tone SFDR Performance vs. ADC_AVDD and Temperature Rev. 0 | Page 12 of 52 03606-0-048 ENOB (Bits) 60 60 9.6 03606-0-044 03606-0-043 –30 THD (dBFS) THD SNR (dBc) AD9861 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 03606-0-049 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-050 –100 –110 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 Figure 22. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 2 MHz Tone Figure 25. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 1 MHz and 2 MHz Tones 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 03606-0-051 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-052 –100 –110 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 Figure 23. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 5 MHz Tone Figure 26. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 5 MHz and 8 MHz Tones 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 03606-0-053 AMPLITUDE (dBFS) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-054 –100 –110 0 5 10 15 20 25 FREQUENCY (MHz) 30 35 40 Figure 24. AD9861-80 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 24 MHz Tone Figure 27. AD9861-80 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 20 MHz and 25 MHz Tones Rev. 0 | Page 13 of 52 AD9861 62 LOW POWER ADC @ 40MSPS ULTRALOW POWER ADC @ 16MSPS 62 LOW POWER ADC @ 40MSPS 9.8 ULTRALOW POWER ADC @ 16MSPS 9.6 59 NORMAL POWER @ 80MSPS SINAD (dBc) 10.0 59 9.4 ENOB (Bits) 03606-0-058 SNR (dBc) NORMAL POWER @ 80MSPS 56 9.2 9.0 8.8 8.6 56 53 03606-0-055 53 8.4 8.2 50 0 5 10 15 20 INPUT FREQUENCY (MHz) 25 8.0 30 03606-0-056 50 0 5 10 15 20 INPUT FREQUENCY (MHz) 25 30 Figure 28. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. Input Frequency and Power Setting Figure 31. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SINAD Performance vs. Input Frequency and Power Setting 85 LOW POWER ADC @ 40MSPS 80 ULTRALOW POWER ADC @ 16MSPS SFDR (dBc) THD (dBc) 75 –50 –55 –60 –65 LOW POWER ADC @ 40MSPS –70 70 NORMAL POWER @ 80MSPS 65 03606-0-057 –75 NORMAL POWER @ 80MSPS –80 0 5 ULTRALOW POWER ADC @ 16MSPS 20 25 60 0 5 10 15 INPUT FREQUENCY (MHz) 20 25 10 15 INPUT FREQUENCY (MHz) Figure 29. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SFDR Performance vs. Input Frequency and Power Setting Figure 32. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone THD Performance vs. Input Frequency and Power Setting 70 60 50 –80 80 –70 70 –60 SFDR 60 40 IDEAL SNR 30 20 10 0 0 –5 –10 –15 –20 –25 –30 INPUT AMPLITUDE (dBFS) –35 –40 –50 THD 50 –40 40 SNR 03606-0-059 03606-0-060 –30 30 –20 0 –5 –10 –15 –20 –25 –30 INPUT AMPLITUDE (dBFS) –35 –45 20 –40 Figure 30. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. Input Amplitude Figure 33. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone THD Performance vs. Input Amplitude Rev. 0 | Page 14 of 52 SFDR (dBFS) THD (dBFS) SNR (dBc) AD9861 62 62 10.0 9.9 61 AVE (+85°C) 60 SINAD (dBc) SNR (dBc) 61 AVE (–40°C) 60 AVE (+85°C) 59 AVE (+25°C) 9.8 9.7 9.6 9.5 9.4 ENOB (Bits) 03606-0-066 59 AVE (+25°C) 58 58 AVE (–40°C) 03606-0-065 9.3 9.2 9.1 57 57 56 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V) 3.6 56 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V) 9.0 3.6 Figure 34. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SNR Performance vs. AVDD and Temperature Figure 37. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SINAD Performance vs. AVDD and Temperature 70 69 68 67 AVE (+25°C) AVE (–40°C) 65 AVE (+85°C) 66 67 68 AVE (–40°C) 65 AVE (+85°C) 64 63 62 61 60 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V) 03606-0-061 SFDR (dBc) THD (dBc) 66 69 70 71 72 73 74 75 2.7 3.0 3.3 ADC_AVDD VOLTAGE (V) AVE (+25°C) 3.6 3.6 Figure 35. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone THD Performance vs. AVDD and Temperature Figure 38. AD9861-80 Rx Path at 80 MSPS, 10 MHz Input Tone SFDR Performance vs. AVDD and Temperature 120 NORM 100 180 160 NORM ADC AVDD CURRENT (mA) ADC AVDD CURRENT (mA) 140 120 100 LP 80 60 40 20 0 0 10 20 30 40 50 FCLK (MHz) 60 70 80 ULP 03606-0-064 80 LP 60 40 ULP 03606-0-063 20 0 0 10 20 30 FCLK (MHz) 40 50 Figure 36. AD9861-50 ADC_AVDD Current vs. Sampling Rate for Different ADC Power Levels Figure 39. AD9861-80 ADC_AVDD Current vs. ADC Sampling Rate for Different ADC Power Levels Rev. 0 | Page 15 of 52 03606-0-062 AD9861 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 03606-0-068 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-069 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 40. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 33 Ω Differential Load Figure 43. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 33 Ω Differential Load 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 03606-0-070 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-071 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 41. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 60 Ω Differential Load Figure 44. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 60 Ω Differential Load 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 03606-0-072 AMPLITUDE (dBc) –40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-073 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 42. AD9861 Tx Path 1 MHz Single-Tone Output FFT of Tx Path with 2 mA Full-Scale Output into 600 Ω Differential Load Figure 45. AD9861 Tx Path 5 MHz Single-Tone Output FFT of Tx Path with 2 mA Full-Scale Output into 600 Ω Differential Load Rev. 0 | Page 16 of 52 AD9861 –50 –50 –60 –60 THD (dBc) –80 THD (dBc) 03606-0-074 –70 –70 –80 –90 –90 03606-0-075 –100 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25 –100 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25 Figure 46. AD9861 Tx Path THD vs. Output Frequency of Tx Path with 20 mA Full-Scale Output into 60 Ω Differential Load Figure 49. AD9861 Tx Path THD vs. Output Frequency of Tx Path with 2 mA Full-Scale Output into 600 Ω Differential Load 62 62 61 61 60 60 SINAD (dBc) 59 SINAD (dBc) 03606-0-076 59 58 58 56 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25 56 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25 Figure 47. AD9861 Tx Path SINAD vs. Output Frequency of Tx Path, with 20 mA Full-Scale Output into 60 Ω Differential Load Figure 50. AD9861 Tx Path SINAD vs. Output Frequency of Tx Path, with 2 mA Full-Scale Output into 600 Ω Differential Load –70 –70 –75 –75 IMD (dBc) –85 IMD (dBc) –80 –80 –85 –90 03606-0-078 –90 03606-0-079 –95 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25 –95 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25 Figure 48. AD9861 Tx Path Dual-Tone (0.5 MHz Spacing) IMD vs. Output Frequency of Tx Path, with 20 mA Full-Scale Output into 60 Ω Differential Load Figure 51. AD9861 Tx Path Dual-Tone (0.5 MHz Spacing) IMD vs. Output Frequency of Tx Path, with 2 mA Full-Scale Output into 600 Ω Differential Load Rev. 0 | Page 17 of 52 03606-0-077 57 57 AD9861 Figure 52 to Figure 57 use the same input data to the Tx path, a 64-carrier OFDM signal over a 20 MHz bandwidth, centered at 20 MHz. The center two carriers are removed from the signal to obser ve the in-band intermodulation distortion (IMD) from the DAC output. –30 –40 –50 –30 –40 –50 AMPLITUDE (dBc) –70 –80 –90 –100 –110 03606-0-080 AMPLITUDE (dBc) –60 –60 –70 –80 –90 –100 –110 –120 –130 18.75 19.25 19.75 20.25 FREQUENCY (MHz) 20.75 03606-0-081 –120 –130 7.5 12.5 17.5 22.5 FREQUENCY (MHz) 27.5 32.5 21.25 Figure 52. AD9861 Tx Path FFT, 64-Carrier (Center Two Carriers Removed) OFDM Signal over 20 MHz Bandwidth, Centered at 20 MHz, with 20 mA Full-Scale Output into 60 Ω Differential Load –30 –40 –50 Figure 55. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 52 –30 –40 –50 AMPLITUDE (dBc) –70 –80 –90 –100 –110 03606-0-082 AMPLITUDE (dBc) –60 –60 –70 –80 –90 –100 –110 –120 –130 27.5 28.0 28.5 29.0 29.5 30.0 30.5 31.0 FREQUENCY (MHz) 31.5 32.0 03606-0-083 –120 –130 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 FREQUENCY (MHz) 11.5 12.0 12.5 32.5 Figure 53. AD9861 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 52 Figure 56. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 52 –30 –40 –50 –30 –40 –50 AMPLITUDE (dBc) –70 –80 –90 –100 –110 03606-0-084 AMPLITUDE (dBc) –60 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 03606-0-085 –120 –130 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 Figure 54. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 1× Interpolation Figure 57. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 4× Interpolation Rev. 0 | Page 18 of 52 AD9861 Figure 58 to Figure 63 use the same input data to the Tx path, a 256-carrier OFDM signal over a 1.75 MHz bandwidth, centered at 7 MHz. The center four carriers are removed from the signal to obser ve the in-band intermodulation distortion (IMD) from the DAC output. –40 –50 –60 –40 –50 –60 AMPLITUDE (dBc) –80 –90 –100 –110 –120 –130 –140 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 FREQUENCY (MHz) 7.6 7.8 03606-0-086 AMPLITUDE (dBc) –70 –70 –80 –90 –100 –110 –120 –130 –140 6.97 6.98 6.99 7.00 7.01 FREQUENCY (MHz) 7.02 03606-0-087 8.0 7.03 Figure 58. AD9861 Tx Path FFT, 256-Carrier (Center Four Carriers Removed) OFDM Signal over 1.75 MHz Bandwidth, Centered at 7 MHz, with 20 mA Full-Scale Output into 60 Ω Differential Load –40 –50 –60 Figure 61. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 58 –40 –50 –60 AMPLITUDE (dBc) –80 –90 –100 –110 –120 –130 –140 6.06 6.08 6.10 6.12 6.14 FREQUENCY (MHz) 6.16 6.18 03606-0-088 AMPLITUDE (dBc) –70 –70 –80 –90 –100 –110 –120 –130 –140 7.81 7.83 7.85 7.87 7.89 FREQUENCY (MHz) 7.91 7.93 03606-0-089 Figure 59. AD9861 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 58 –30 –40 –50 –60 AMPLITUDE (dBc) Figure 62. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 52 –30 –40 –50 –60 AMPLITUDE (dBc) 03606-0-090 –70 –80 –90 –100 –110 –120 –130 0 5 10 15 FREQUENCY (MHz) 20 25 –70 –80 –90 –100 –110 –120 –130 0 5 10 15 FREQUENCY (MHz) 20 25 03606-0-091 Figure 60. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 1× Interpolation Figure 63. AD9861 Tx Path FFT of OFDM Signal in Figure 52, with 4× Interpolation Rev. 0 | Page 19 of 52 AD9861 Figure 64 to Figure 69 use the same input data to the Tx path, a 256-carrier OFDM signal over a 23 MHz bandwidth, centered at 23 MHz. The center four carriers are removed from the signal to obser ve the in-band intermodulation distortion (IMD) from the DAC output. –40 –50 –60 –40 –50 –60 AMPLITUDE (dBc) 03606-0-092 AMPLITUDE (dBc) –70 –80 –90 –100 –110 –120 –130 –140 9 14 19 24 FREQUENCY (MHz) 29 34 –70 –80 –90 –100 –110 –120 –130 –140 22.6 22.7 22.8 22.9 23.0 23.1 FREQUENCY (MHz) 23.2 23.3 03606-0-093 23.4 Figure 64. AD9861 Tx Path FFT, 256-Carrier (Center Four Carriers Removed) OFDM Signal over 23 MHz Bandwidth, Centered at 7 MHz, with 20 mA Full-Scale Output into 60 Ω Differential Load –40 –50 –60 Figure 67. AD9861 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 64 –40 –50 –60 –70 AMPLITUDE (dBc) 03606-0-094 AMPLITUDE (dBc) –70 –80 –90 –100 –110 –120 –130 –140 10.5 10.7 10.9 11.1 11.3 11.5 11.7 11.9 FREQUENCY (MHz) 12.1 12.3 –80 –90 –100 –110 –120 –130 –140 33.5 33.7 33.9 34.1 34.3 34.5 34.7 34.9 FREQUENCY (MHz) 35.1 35.3 03606-0-095 12.5 35.5 Figure 65. AD9861 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 64 –30 –40 –50 Figure 68. AD9861 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 64 –30 –40 –50 AMPLITUDE (dBc) –70 –80 –90 –100 –110 03606-0-096 AMPLITUDE (dBc) –60 –60 –70 –80 –90 –100 –110 –120 –130 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 90 03606-0-097 –120 –130 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 90 Figure 66. AD9861 Tx Path FFT of OFDM Signal in Figure 52 with 1× Interpolation Figure 69. AD9861 Tx Path FFT of OFDM Signal in Figure 52 with 4× Interpolation Rev. 0 | Page 20 of 52 AD9861 TERMINOLOGY Input Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the CLKIN signal and the instant at which the analog input is actually sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk Coupling onto one channel being driven by a –0.5 dBFS signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by obser ving the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the input phase 180° and taking the peak measurement again. Then the difference is computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) The effective number of bits is calculated from the measured SNR based on the following equation: ENOB = SNRMEASURED − 1.76 dB 6.02 Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of an LSB using a “best straight line” determined by a least square cur ve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK− and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full-scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (i.e., degrades as signal level is lowered) or dBFS (i.e., always related back to converter full scale). SFDR does not include harmonic distortion components. Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dBc. Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that a signal should be left in the logic high state to achieve rated performance; pulse width low is the minimum time a signal should be left in the low state, logic low. Full-Scale Input Power Expressed in dBm, full-scale input power is computed using the following equation: ⎛V 2 Z Power FULLSCALE = 10 log ⎜ FULLSCALE − RMS INPUT ⎜ 0.001 ⎝ ⎞ ⎟ ⎟ ⎠ Gain Error Gain error is the difference between the measured and ideal full-scale input voltage range of the ADC. Rev. 0 | Page 21 of 52 AD9861 THEORY OF OPERATION SYSTEM BLOCK The AD9861 is targeted to cover the mixed-signal front end needs of multiple wireless communication systems. It features a receive path that consists of dual 10-bit receive ADCs, and a transmit path that consists of dual 10-bit transmit DACs (TxDAC). The AD9861 integrates additional functionality typically required in most systems, such as power scalability, additional auxiliary converters, Tx gain control, and clock multiplication circuitry. The AD9861 minimizes both size and power consumption to address the needs of a range of applications from the low power portable market to the high performance base station market. The part is provided in a 64-lead lead frame chip scale package (LFCSP) that has a footprint of only 9 mm × 9 mm. Power consumption can be optimized to suit the particular application beyond just a speed grade option by incorporating power-down controls, low power ADC modes, TxDAC power scaling, and a half-duplex mode, which automatically disables the unused digital path. The AD9861 uses two 10-bit buses to transfer Rx path data and Tx path data. These two buses support 20-bit parallel data transfers or 10-bit interleaved data transfers. The bus is configurable through either external mode pins or through internal registers settings. The registers allow many more options for configuring the entire device. The following sections discuss the various blocks of the AD9861: Rx block, Tx block, the auxiliary converters, the digital block, programmable registers and the clock distribution block. The differential input stage is dc self-biased and allows differential or single-ended inputs. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The latency of the Rx path is about 5 clock cycles. Rx Path Analog Input Equivalent Circuit The Rx path analog inputs of the AD9861 incorporate a novel structure that merges the function of the input sample-andhold amplifiers (SHAs) and the first pipeline residue amplifiers into a single, compact switched capacitor circuit. This structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers by eliminating one amplifier in the pipeline. Figure 70 illustrates the equivalent analog inputs of the AD9861 (a switched capacitor input). Bringing CLK to logic high opens switch S3 and closes switches S1 and S2; this is the sample mode of the input circuit. The input source connected to VIN+ and VIN− must charge capacitor CH during this time. Bringing CLK to a logic low opens S2, and then switch S1 opens followed by closing S3. This puts the input circuit into hold mode. S1 VIN+ RIN VCM RIN VIN– CIN 03606-0-002 CH + CIN S3 CH – S2 Rx PATH BLOCK Rx Path General Description The AD9861 Rx path consists of two 10-bit, 50 MSPS (for the AD9861-50) or 80 MSPS (for the AD9861-80) analog-to-digital converters (ADCs). The dual ADC paths share the same clocking and reference circuitr y to provide optimal matching characteristics. Each of the ADCs consists of a 9-stage differential pipelined switched capacitor architecture with output error correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the falling edge of the input clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage’s input signal, and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each one of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. Figure 70. Differential Input Architecture The structure of the input SHA places certain requirements on the input drive source. The differential input resistors are typically 2 kΩ each. The combination of the pin capacitance, CIN, and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to 10-bit accuracy in one-half of a clock cycle. When the SHA goes into sample mode, the input source must charge or discharge capacitor CH from the voltage already stored on it to the new voltage. In the worst case, a full-scale voltage step on the input source must provide the charging current through the RON of switch S1 (typically 100 Ω) to a settled voltage within one-half of the ADC sample period. This situation corresponds to driving a low input impedance. On the other hand, when the source voltage equals the value previously stored on CH, the hold capacitor requires no input current and the equivalent input impedance is extremely high. Rev. 0 | Page 22 of 52 AD9861 Rx Path Application Section Adding series resistance between the output of the signal source and the VIN pins reduces the drive requirements placed on the signal source. Figure 71 shows this configuration. AD9861 RSERIES VIN+ CSHUNT VIN– RSERIES 03606-0-003 default 1 V VREF reference accepts a 2 V p-p differential input swing and the offset voltage should be REFT = AVDD/2 + 0.5 V REFB = AVDD/2 – 0.5 V AD9861 REFT 0.1µF TO ADCs REFB 0.1µF VREF 10µF 0.1µF 0.1µF 10µF Figure 71. Typical Input The bandwidth of the particular application limits the size of this resistor. For applications with signal bandwidths less than 10 MHz, the user may insert series input resistors and a shunt capacitor to produce a low-pass filter for the input signal. Additionally, adding a shunt capacitance between the VIN pins can lower the ac load impedance. The value of this capacitance depends on the source resistance and the required signal bandwidth. The Rx input pins are self-biased to provide this midsupply, common-mode bias voltage, so it is recommended to ac couple the signal to the inputs using dc blocking capacitors. In systems that must use dc coupling, use an op amp to comply with the input requirements of the AD9861. The inputs accept a signal with a 2 V p-p differential input swing centered about one-half of the supply voltage (AVDD/2). If the dc bias is supplied externally, the internal input bias circuit should be powered down by writing to registers Rx_A dc bias [Register 0x3, Bit 6] and Rx_B dc bias [Register 0x4, Bit 7]. The ADCs in the AD9861 are designed to sample differential input signals. The differential input provides improved noise immunity and better THD and SFDR performance for the Rx path. In systems that use single-ended signals, these inputs can be digitized, but it is recommended that a single-ended-todifferential conversion be performed. A single-ended-todifferential conversion can be performed by using a transformer coupling circuit (typically for signals above 10 MHz) or by using an operational amplifier, such as the AD8138 (typically for signals below 10 MHz). 0.5V 03606-0-020 Figure 72. Typical Rx Path Decoupling An external reference may be used for systems that require a different input voltage range, high accuracy gain matching between multiple devices, or improvements in temperature drift and noise characteristics. When an external reference is desired, the internal Rx band gap reference must be powered down using the VREF2 register [Register 0x5, Bit 4] and the external reference driving the voltage level on the VREF pin. The external voltage level should be one-half of the desired peak-topeak differential voltage swing. The result is that the differential voltage references are driven to new voltages: REFT = AVDD/2 +VREF/2 V REFB = AVDD/2 – VREF/2 V If an external reference is used, it is recommended not to exceed a differential offset voltage for the reference greater than 1 V. Clock Input and Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9861 contains clock duty cycle stabilizer circuitr y (DCS). The DCS retimes the internal ADC clock (nonsampling edge) and provides the ADC with a nominal 50% duty cycle. Input clock rates of over 40 MHz can use the DCS so that a wide range of input clock duty cycles can be accommodated. Conversely, DCS should not be used for Rx sampling below 40 MSPS. Maintaining a 50% duty cycle clock is particularly important in high speed applications when proper sample-and-hold times for the converter are required to maintain high performance. The DCS can be enabled by writing highs to the Rx_A/Rx_B CLK duty register bits [Register 0x06/0x07, Bit 4]. The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 2 µs to 3 µs to allow the DLL to adjust to the new rate and settle. High speed, high resolution ADCs are sensitive to the quality of the clock input. The ADC Voltage References The AD9861 10-bit ADCs use internal references that are designed to provide for a 2 V p-p differential input range. The internal band gap reference generates a stable 1 V reference level and is decoupled through the VREF pin. REFT and REFB are the differential references generated based on the voltage level of VREF. Figure 72 shows the proper decoupling of the reference pins VREF, REFT, and REFB when using the internal reference. Decoupling capacitors should be placed as close to the reference pins as possible. External references REFT and REFB are centered at AVDD/2 with a differential voltage equal to the voltage at VREF (by default 1 V when using the internal reference), allowing a peakto-peak differential voltage swing of 2× VREF. For example, the Rev. 0 | Page 23 of 52 AD9861 degradation in SNR at a given full-scale input frequency (fINPUT), due only to aperture jitter (tA), can be calculated with the following equation: SNR degradation = 20 log [(½)πFINtA)] In the equation, the rms aperture jitter, tA, represents the rootsum-square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input is a digital signal that should be treated as an analog signal with logic level threshold voltages, especially in cases where aperture jitter may affect the dynamic range of the AD9861. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. 3, 4, and 5. Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a power-down, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and the duration of the power-down. Typically, it takes approximately 5 ms to restore full operation with fully discharged 0.1 µF and 10 µF decoupling capacitors on REFT and REFB. Tx PATH BLOCK The AD9861 transmit (Tx) path includes dual interpolating 10-bit current output DACs that can be operated independently or can be coupled to form a complex spectrum in an image reject transmit architecture. Each channel includes two FIR filters, making the AD9861 capable of 1×, 2×, or 4× interpolation. High speed input and output data rates can be achieved within the limitations of Table 9. Table 9. AD9861 Tx Path Maximum Data Rate Input Data Rate per Channel (MSPS) 80 160 80 80 50 50 DAC Sampling Rate (MSPS) 80 160 160 160 200 200 Power Dissipation and Standby Mode The power dissipation of the AD9861 Rx path is proportional to its sampling rate. The Rx path portion of the digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by IDRVDD = VDRVDD × CLOAD × fCLOCK × N Interpolation Rate 1× 2× 4× 20-Bit Interface Mode FD, HD10, Clone HD20 FD, HD10, Clone HD20 FD, HD10, Clone HD20 where N is the number of bits changing and CLOAD is the average load on the digital pins that changed. The analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates, which increases with clock frequency. The baseline power dissipation for either speed grade can be reduced by asserting the ADC_LO_PWR pin, which reduces internal ADC bias currents by half, in some case resulting in degraded performance. To further reduce power consumption of the ADC, the ADC_LO_PWR pin can be combined with a serial programmable register setting to configure an ultralow power mode. The ultralow power mode reduces the power consumption by a fourth of the normal power consumption. The ultralow power mode can be used at slower sampling frequencies or if reduced performance is acceptable. To configure the ultralow power mode, assert the ADC_LO_PWR pin and write the following register settings: Register 0x08 Register 0x09 Register 0x0A (MSB) ‘0000 1100’ (MSB) ‘0111 0000’ (MSB) ‘0111 0000’ By using the dual DAC outputs to form a complex signal, an external analog quadrature modulator, such as the Analog Devices AD8349, can enable an image rejection architecture. (Note: the AD9861 evaluation board includes a quadrature modulator in the Tx path that accommodates the AD8345, AD8346 and the AD8345 footprints.) To optimize the image rejection capability, as well as LO feedthrough suppression in this architecture, the AD9861 offers programmable (via the SPI port) fine (trim) gain and offset adjustment for each DAC. Also included in the AD9861 are a phase-locked loop (PLL) clock multiplier and a 1.2 V band gap voltage reference. With the PLL enabled, a clock applied to the CLKIN input is multiplied internally and generates all necessary internal synchronization clocks. Each 10-bit DAC provides two complementary current outputs whose full-scale currents can be determined from a single external resistor. An external pin, TxPWRDWN, can be used to power down the Tx path, when not used, to optimize system power consumption. Using the TxPWRDWN pin disables clocks and some analog circuitry, saving both digital and analog power. The power-down mode leaves the biases enabled to facilitate a quick recovery time, typically