AD9863-50EB

Mixed-Signal Front-End (MxFE™) Baseband Transceiver for Broadband Applications AD9863 FEATURES Receive path includes dual 12-bit, 50 MSPS analog-to-digital converters with internal or external reference Transmit path includes dual 12-bit, 200 MSPS digital-toanalog converters with 1×, 2×, or 4× interpolation and programmable gain control Internal clock distribution block includes a programmable phase-locked loop and timing generation circuitry, allowing single-reference clock operation 24-pin flexible I/O data interface allows various interleaved or noninterleaved data transfers in half-duplex mode and interleaved data transfers in full-duplex mode Configurable through register programmability or optionally limited programmability through mode pins Independent Rx and Tx power-down control pins 64-lead LFCSP package (9 mm × 9 mm footprint) VIN+A ADC VIN–A VIN+B ADC VIN–B I/O INTERFACE CONFIGURATION BLOCK DATA MUX AND LATCH Rx DATA FUNCTIONAL BLOCK DIAGRAM I/O INTERFACE CONTROL FLEXIBLE I/O BUS [0:23] LOW-PASS INTERPOLATION FILTER IOUT+A DAC IOUT–A IOUT+B DAC IOUT–B ADC CLOCK DATA LATCH AND DEMUX Tx DATA CLKIN1 CLOCK GENERATION BLOCK DAC CLOCK PLL CLKIN2 03604-0-070 AD9863 APPLICATIONS Broadband access Broadband LAN Communications (modems) Figure 1. GENERAL DESCRIPTION The AD9863 is a member of the MxFE family—a group of integrated converters for the communications market. The AD9863 integrates dual 12-bit analog-to-digital converters (ADC) and dual 12-bit digital-to-analog converters (TxDAC®). The AD9863 ADCs are optimized for ADC sampling of 50 MSPS and less. The dual TxDACs operate at speeds up to 200 MHz and include a bypassable 2× or 4× interpolation filter. The AD9863 is optimized for high performance, low power, and small form factor to provide a cost-effective solution for the broadband communications market. The AD9863 uses a single input clock pin (CLKIN) or two independent clocks for the Tx path and the Rx path. The ADC and TxDAC clocks are generated within a timing generation block that provides user programmable options such as divide circuits, PLL multipliers, and switches. A flexible, bidirectional 24-bit I/O bus accommodates a variety of custom digital back ends or open market DSPs. In half-duplex systems, the interface supports 24-bit parallel transfers or 12-bit interleaved transfers. In full-duplex systems, the interface supports a 12-bit interleaved ADC bus and a 12-bit interleaved TxDAC bus. The flexible I/O bus reduces pin count, also reducing the required package size on the AD9863 and the device to which it connects. The AD9863 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC interpolation rate, and control ADC and TxDAC power-down. The SPI provides more programmable options for both the TxDAC path (for example, coarse and fine gain control and offset control for channel matching) and the ADC path (for example, the internal duty cycle stabilizer and twos complement data format). The AD9863 is packaged in a 64-lead LFCSP (low profile, fine pitched, chip scale package). The 64-lead LFCSP footprint is only 9 mm × 9 mm and is less than 0.9 mm high, fitting into such tightly spaced applications as PCMCIA cards. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD9863 TABLE OF CONTENTS Tx Path Specifications...................................................................... 3 Rx Path Specifications...................................................................... 4 Power Specifications......................................................................... 5 Digital Specifications........................................................................ 5 Timing Specifications....................................................................... 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 Terminology .................................................................................... 17 Theory of Operation ...................................................................... 18 System Block ............................................................................... 18 Rx Path Block.............................................................................. 18 Tx Path Block.............................................................................. 20 Digital Block................................................................................ 23 Programmable Registers............................................................ 33 Clock Distribution Block .......................................................... 36 Outline Dimensions ....................................................................... 40 Ordering Guide .......................................................................... 40 REVISION HISTORY 4/05—Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 40 11/03— Revision 0: Initial Version Rev. A| Page 2 of 40 AD9863 Tx PATH SPECIFICATIONS FDAC = 200 MSPS; 4× interpolation; RSET = 4.02 kΩ; differential load resistance of 100 Ω1; TxPGA = 20 dB; AVDD = DVDD = 3.3 V, unless other wise noted. Table 1. Parameter Tx PATH GENERAL Resolution Maximum DAC Update Rate Maximum Full-Scale Output Current Full-Scale Error Gain Mismatch Error Offset Mismatch Error Reference Voltage Output Capacitance Phase Noise (1 kHz Offset, 6 MHz Tone) Output Voltage Compliance Range TxPGA Gain Range TxPGA Step Size Tx PATH DYNAMIC PERFORMANCE (IOUTFS = 20 mA; FOUT = 1 MHz) SNR SINAD T HD SFDR, Wide Band (DC to Nyquist) SFDR, Narrow Band (1 MHz Window) 1 Temp Full Full Full Full 25°C Full Full Full 25°C Full Full Full Test Level IV IV IV V IV IV V V V IV V V Min Typ 12 Max Unit Bits MHz mA 200 20 1% −3.5 −0.1 1.23 5 −115 −1.0 20 0.10 +1.0 +3.5 +0.1 % FS % FS V pF dBc/Hz V dB dB Full Full Full Full Full IV IV IV IV IV 70.8 64.3 68.5 72.8 71.6 71 −79 77 81 −66.3 dB dB dBc dBc dBc See Figure 2 for description of the TxDAC termination scheme. TxDAC 03604-0-071 50Ω 50Ω Figure 2. Diagram Showing Termination of 100 Ω Differential Load for Some TxDAC Measurements Rev. A | Page 3 of 40 AD9863 RX PATH SPECIFICATIONS FADC = 50 MSPS; internal reference; differential analog inputs, ADC_AVDD = DVDD = 3.3 V, unless otherwise noted. Table 2. Parameter Rx PATH GENERAL Resolution Maximum ADC Sample Rate Gain Mismatch Error Offset Mismatch Error Reference Voltage Reference Voltage (REFT–REFB) Error Input Resistance (Differential) Input Capacitance Input Bandwidth Differential Analog Input Voltage Range Rx PATH DC ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Aperture Delay Aperture Uncertainty (Jitter) Input Referred Noise AD9863 Rx PATH DYNAMIC PERFORMANCE (VIN = –0.5 dBFS; FIN = 10 MHz) SNR SINAD THD (Second to Ninth Harmonics) SFDR, Wide Band (DC to Nyquist) Crosstalk Between ADC Inputs Temp Full Full Full Full Full Full Full Full Full Full 25°C 25°C 25°C 25°C 25°C Test Level V IV V V V IV V V V V V V V V V Min Typ 12 50 ±0.2 ±0.1 1.0 ±6 2 5 30 2 ±0.75 ±0.75 2.0 1.2 250 Max Unit Bits MSPS % FS % FS V mV kΩ pF MHz V p-p differential LSB LSB ns ps rms µV −30 +30 Full Full Full Full Full V V IV IV V 68.3 67 65.5 −73 74 80 −66.6 dBc dBc dBc dBc dB Rev. A| Page 4 of 40 AD9863 POWER SPECIFICATIONS Analog and digital supplies = 3.3 V; FCLKIN1 = FCLKIN2 = 50 MHz; PLL 4× setting; normal timing mode. Table 3. Parameter POWER SUPPLY RANGE Analog Supply Voltage (AVDD) Digital Supply Voltage (DVDD) Driver Supply Voltage (DRVDD) ANALOG SUPPLY CURRENTS Tx Path (20 mA Full-Scale Outputs) Tx Path (2 mA Full-Scale Outputs) Rx Path (50 MSPS) Rx Path (50 MSPS, Low Power Mode) Rx Path (20 MSPS, Low Power Mode) Tx Path, Power-Down Mode Rx Path, Power-Down Mode PLL DIGITAL SUPPLY CURRENTS Tx Path, 1× Interpolation, 50 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode Tx Path, 2× Interpolation, 100 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode Tx Path, 4× Interpolation, 200 MSPS DAC Update for Both DACs, Half-Duplex 24 Mode Rx Path Digital, Half-Duplex 24 Mode Temp Full Full Full Test Level IV IV IV Min 2.7 2.7 2.7 Typ Max 3.6 3.6 3.6 Unit V V V Full Full Full Full Full Full Full Full Full V V V V V V V V V 70 20 103 69 55 2 5 12 20 mA mA mA mA mA mA mA mA mA Full V 50 mA Full V 80 mA Full V 15 mA DIGITAL SPECIFICATIONS Table 4. Parameter LOGIC LEVELS Input Logic High Voltage, VIH Input Logic Low Voltage, VIL Output Logic High Voltage, VOH (1 mA Load) Output Logic Low Voltage, VOL (1 mA Load) DIGITAL PIN Input Leakage Current Input Capacitance Minimum RESET Low Pulse Width Digital Output Rise/Fall Time Temp Full Full Full Full Full Full Full Full Test Level IV IV IV IV IV IV IV IV Min DRVDD − 0.7 0.4 DRVDD − 0.6 0.4 12 3 5 2.8 4 Typ Max Unit V V V V µA pF Input clock cycles ns Rev. A | Page 5 of 40 AD9863 TIMING SPECIFICATIONS Table 5. Parameter INPUT CLOCK CLKIN2 Clock Rate (PLL Bypassed) PLL Input Frequency PLL Ouput Frequency TxPATH DATA Setup Time (HD24 Mode, Time Required Before Data Latching Edge) Hold Time (HD24 Mode, Time Required After Data Latching Edge) Latency 1× Interpolation (Data In Until Peak Output Response) Latency 2× Interpolation (Data In Until Peak Output Response) Latency 4× Interpolation (Data In Until Peak Output Response) RxPATH DATA Output Delay (HD24 Mode, tOD) Temp Full Full Full Full Test Level IV IV IV V Min 1 16 32 5 Typ Max 200 200 350 Unit MHz MHz MHz ns (see Clock Distribution Block section) ns (see Clock Distribution Block section) DAC clock cycles DAC clock cycles DAC clock cycles ns ( see Clock Distribution Block section) ADC clock cycles Full V −1.5 Full Full Full Full V V V V 7 35 83 −1.5 Latency Full V 5 Table 6. Explanation of Test Levels Level I II III IV V VI Description 100% production tested. 100% production tested at 25°C and guaranteed by design and characterization at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25°C and guaranteed by design and characterization for industrial temperature range. Rev. A| Page 6 of 40 AD9863 ABSOLUTE MAXIMUM RATINGS Table 7. Parameter Electrical AVDD Voltage DRVDD Voltage Analog Input Voltage Digital Input Voltage Digital Output Current Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating 3.9 V max 3.9 V max −0.3 V to AVDD + 0.3 V −0.3 V to DVDD − 0.3 V 5 mA max −40°C to +85°C 150°C 300°C −65°C to +150°C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE 64-lead LFCSP (4-layer board): θJA = 24.2 (paddle soldered to ground plan, 0 LPM air) θJA = 30.8 (paddle not soldered to ground plan, 0 LPM air) ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 40 AD9863 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SPI_CS TxPWRDWN RxPWRDWN ADC_AVDD REFT ADC_AVSS VIN+A VIN–A VREF VIN–B VIN+B ADC_AVSS REFB ADC_AVDD PLL_AVDD PLL_AVSS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 SPI_DIO SPI_CLK SPI_SDO ADC_LO_PWR DVDD DVSS AVDD IOUT–A IOUT+A AGND REFIO FSADJ AGND IOUT+B IOUT–B AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 AD9863 TOP VIEW (Not to Scale) 42 41 40 39 38 37 36 35 34 33 CLKIN1 CLKIN2 RESET L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 IFACE1 Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 3 4 5, 31 6, 32 7, 16, 50, 51, 61 8, 9 10, 13, 49, 53, 59 11 12 14, 15 17 18 19 to 30 33 Name1 SPI_DIO (Interp1) SPI_CLK (Interp0) SPI_SDO (FD/HD) ADC_LO_PWR DVDD, DRVDD DVSS, DRVDD AVDD IOUT−A, IOUT+A AGND, AVSS REFIO FSADJ IOUT+B, IOUT−B IFACE2 (12/24) IFACE3 U11 to U0 IFACE1 Description2, 3 SPI: Serial Port Data Input. No SPI: Tx Interpolation Pin, MSB. SPI: Serial Port Shift Clock. No SPI: Tx Interpolation Pin, LSB. SPI: 4-Wire Serial Port Data Output. No SPI: Configures Full-Duplex or Half-Duplex Mode. ADC Low Power Mode Enable. Defined at power-up. Digital Supply. Digital Ground. Analog Supply. DAC A Differential Output. Analog Ground. Tx DAC Band Gap Reference Decoupling Pin. Tx DAC Full-Scale Adjust Pin. DAC B Differential Output. SPI: Buffered CLKIN. Can be configured as system clock output. No SPI: Buffered CLKIN for FD; 12/24 configuration pin for HD24 or HD12. Clock Output. Upper Data Bit 11 to Upper Data Bit 0. SPI: TxSYNC for FD; Tx/Rx for HD24, HD12, or clone. No SPI: FD >> TxSYNC; HD24 or HD12: Tx/Rx. Clone mode requires a serial port interface. Lower Data Bit 11 to Lower Data Bit 0. Chip Reset When Low. Clock Input 2. Clock Input 1. Rev. A| Page 8 of 40 34 to 45 46 47 48 L11 to L0 RESET CLKIN2 CLKIN1 03604-0-072 IFACE2 IFACE3 U11 U10 U9 U8 U7 U6 U5 U4 U3 U2 U1 U0 DRVDD DRVSS AD9863 Pin No. 52 54, 55 56 57, 58 60 62 63 64 Name1 REFB VIN+B, VIN−B VREF VIN−A, VIN+A REFT RxPWRDWN TxPWRDWN SPI_CS Description2, 3 ADC Bottom Reference. ADC B Differential Input. ADC Band Gap Reference. ADC A Differential Input. ADC Top Reference. Rx Analog Power-Down Control. Tx Analog Power-Down Control. SPI: Serial Port Chip Select. At power-up or reset, this must be high. No SPI: Tie low to disable SPI and use mode pins. This pin must be tied low. 1 2 3 Underlined pin names and descriptions apply when the device is configured without a serial port interface, referred to as No SPI mode. Some pin descriptions depend on whether a serial port is used (SPI mode) or not (No SPI mode), indicated by the labels SPI and No SPI. Some pin descriptions depend on the interface configuration: full-duplex (FD), half-duplex interleaved data (HD12), half-duplex parallel data (HD24), and a half-duplex interface similar to the AD9860 and AD9862 data interface called clone mode (Clone). Clone mode requires a serial port interface. Rev. A | Page 9 of 40 AD9863 TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 03604-0-001 0 –10 –20 –30 40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03604-0-004 40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 4. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 2 MHz Tone 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 03604-0-002 Figure 7. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 1 MHz and 2 MHz Tones 0 –10 –20 –30 40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03604-0-005 40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 5. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 5 MHz Tone 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 03604-0-003 Figure 8. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 5 MHz and 8 MHz Tones 0 –10 –20 –30 40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03604-0-006 40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 6. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 24 MHz Tone Figure 9. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 20 MHz and 25 MHz Tones Rev. A| Page 10 of 40 AD9863 0 –10 –20 –30 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 03604-0-007 0 –10 –20 –30 40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03604-0-010 40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 10. AD9863 Rx Path Single-Tone FFT of Rx Channel B Path Digitizing 76 MHz Tone 74 Figure 13. AD9863 Rx Path Dual-Tone FFT of Rx Channel A Path Digitizing 70 MHz and 72 MHz Tones 74 12.0 11.8 11.6 71 71 11.4 SINAD (dBc) SNR (dBc) LOW POWER @ 25MSPS 68 LOW POWER @ 25MSPS 68 11.2 11.0 10.8 10.6 NORMAL POWER @ 50MSPS 65 03604-0-008 65 10.4 10.2 ULTRALOW POWER @ 16MSPS 62 0 5 10 15 INPUT FREQUENCY (MHz) 20 10.0 25 03604-0-011 NORMAL POWER @ 50MSPS ULTRALOW POWER @ 16MSPS 62 0 5 10 15 INPUT FREQUENCY (MHz) 20 25 Figure 11. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Frequency 80 Figure 14. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone SINAD Performance vs. Input Frequency –50 75 NORMAL POWER @ 50MSPS –55 70 SFDR (dBc) –60 LOW POWER @ 25MSPS THD (dBc) ULTRALOW POWER @ 16MSPS 65 –65 NORMAL POWER @ 50MSPS –70 60 03604-0-009 ULTRALOW POWER @ 16MSPS –80 0 5 LOW POWER @ 25MSPS 20 25 50 0 5 10 15 INPUT FREQUENCY (MHz) 20 25 10 15 INPUT FREQUENCY (MHz) Figure 12. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone SFDR Performance vs. Input Frequency Figure 15. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone THD Performance vs. Input Frequency Rev. A | Page 11 of 40 03604-0-012 55 –75 ENOB (Bits) AD9863 80 70 60 90 80 70 SFDR –90 –80 –70 –60 –50 THD 40 30 20 0 –5 –10 –15 –20 –25 –30 INPUT AMPLITUDE (dBFS) –35 –40 –30 –20 –40 SFDR (dBFS) SNR 40 30 20 03604-0-013 60 50 10 0 0 –5 –10 –15 –20 –25 –30 –35 INPUT AMPLITUDE (dBFS) –40 –45 –50 Figure 16. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. Input Amplitude 74 74 Figure 19. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone THD and SFDR Performance vs. Input Amplitude 12.0 11.8 72 71 70 11.6 11.4 SINAD (dBc) SNR (dBc) 11.2 68 AVE +85°C 65 10.4 11.0 10.8 10.6 68 66 AVE –40°C 03604-0-014 AVE +85°C 62 3.6 3.3 3.0 INPUT AMPLITUDE (dBFS) 2.7 AVE +25°C AVE –40°C 62 2.7 3.0 3.3 INPUT FREQUENCY (MHz) 10.2 10.0 3.6 Figure 17. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone SNR Performance vs. ADC_AVDD and Temperature –70.0 –70.5 –71.0 –71.5 AVE –40°C AVE +25°C Figure 20. AD9863 Rx Path at 50 MSPS, 10 MHz Input Tone SINAD Performance vs. ADC_AVDD and Temperature 78 77 76 AVE +85°C 75 AVE +25°C 74 73 72 –72.5 –73.0 AVE +85°C –73.5 –74.0 03604-0-015 SFDR (dBc) THD (dBc) –72.0 AVE –40°C –74.5 –75.0 2.7 71 70 2.7 3.0 3.3 INPUT AMPLITUDE (dBFS) 3.6 3.0 3.3 INPUT AMPLITUDE (dBFS) 3.6 Figure 18. AD9863 Rx Path Single-Tone THD Performance vs. ADC_AVDD and Temperature Figure 21. AD9863 Rx Path Single-Tone SFDR Performance vs. ADC_AVDD and Temperature Rev. A| Page 12 of 40 03604-0-018 03604-0-017 64 AVE +25°C ENOB (Bits) 03604-0-016 THD (dBFS) 50 SNR (dBc) AD9863 0 –10 –20 –30 0 –10 –20 –30 AMPLITUDE (dBc) 40 –50 –60 –70 –80 –90 03604-0-019 AMPLITUDE (dBc) 40 –50 –60 –70 –80 –90 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 03604-0-022 –100 –110 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 22. AD9863 Tx Path 1 MHz Single-Tone Output FFT of Tx Path with 20 mA Full-Scale Output into 33 Ω Differential Load –50 50 Figure 25. AD9863 Tx Path 5 MHz Single-Tone Output FFT of Tx Channel A with 20 mA Full-Scale Output into 33 Ω Differential Load 74 –60 60 72 SNR SFDR (dBc) THD (dBc) –70 THD –80 SFDR –90 70 SNR/SINAD (dBc) 70 SINAD 68 80 66 90 03604-0-020 –100 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 100 25 62 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25 Figure 23. AD9863 Tx Path THD/SFDR vs. Output Frequency of Tx Channel A, with 20 mA Full-Scale Output into 60 Ω Differential Load –50 Figure 26. AD9863 Tx Path SINAD/SNR vs. Output Frequency of Tx Path with 20 mA Full-Scale Output into 60 Ω Differential Load –50 –55 –60 2mA, 600Ω –70 20mA, 60Ω –60 –65 THD (dBc) IMD (dBc) –70 –75 –80 –85 20mA, 33Ω 2mA, 600Ω –80 20mA, 33Ω –90 03604-0-021 –90 –95 20mA, 60Ω –100 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25 03604-0-024 –100 0 5 10 15 OUTPUT FREQUENCY (MHz) 20 25 Figure 24. AD9863 Tx Path THD vs. Output Frequency of Tx Channel A Figure 27. AD9863 Tx Path Dual-Tone (0.5 MHz Spacing) IMD vs. Output Frequency Rev. A | Page 13 of 40 03604-0-023 64 AD9863 Figure 28 to Figure 33 use the same input data to the Tx path, a 64-carrier OFDM signal over a 20 MHz bandwidth, centered at 20 MHz. The two center carriers are removed from the signal to obser ve the in-band intermodulation distortion (IMD) from the DAC output. –20 –30 –40 –20 –30 –40 AMPLITUDE (dBc) –60 –70 –80 –90 –100 03604-0-025 AMPLITUDE (dBc) –50 –50 –60 –70 –80 –90 –100 –110 –120 18.75 03604-0-028 –110 –120 7.5 12.5 17.5 22.5 FREQUENCY (MHz) 27.5 32.5 19.25 19.75 20.25 FREQUENCY (MHz) 20.75 21.25 Figure 28. AD9863 Tx Path FFT, 64-Carrier ( Two Center Carriers Removed) OFDM Signal over 20 MHz Bandwidth, Centered at 20 MHz, with 20 mA Full-Scale Output into 60 Ω Differential Load –20 –30 –40 Figure 31. AD9863 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 28 –20 –30 –40 AMPLITUDE (dBc) –50 –60 –70 –80 –90 –100 –110 –120 7.5 03604-0-026 AMPLITUDE (dBc) –50 –60 –70 –80 –90 –100 –110 –120 27.5 03604-0-029 28.0 28.5 29.0 8.0 8.5 9.0 9.5 10.0 10.5 11.0 FREQUENCY (MHz) 11.5 12.0 12.5 29.5 30.0 30.5 31.0 FREQUENCY (MHz) 31.5 32.0 32.5 Figure 29. AD9863 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 28 –20 –30 –40 Figure 32. AD9863 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 28 –20 –30 –40 AMPLITUDE (dBc) –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 03604-0-027 AMPLITUDE (dBc) –50 –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 80 03604-0-030 Figure 30. AD9863 Tx Path FFT of OFDM Signal in Figure 28 with 1x Interpolation Rev. A| Page 14 of 40 Figure 33. AD9863 Tx Path FFT of OFDM Signal in Figure 28 with 2x Interpolation AD9863 Figure 34 to Figure 39 use the same input data to the Tx path, a 256-carrier OFDM signal over a 1.75 MHz bandwidth, centered at 7 MHz. The four center carriers are removed from the signal to obser ve the in-band intermodulation distortion (IMD) from the DAC output. –30 –40 –50 –30 –40 –50 AMPLITUDE (dBc) –70 –80 –90 –100 –110 03604-0-031 AMPLITUDE (dBc) –60 –60 –70 –80 –90 –100 –110 –120 –130 6.97 03604-0-034 –120 –130 6.0 6.2 6.4 6.6 6.8 7.0 7.2 7.4 FREQUENCY (MHz) 7.6 7.8 8.0 6.98 6.99 7.00 7.01 FREQUENCY (MHz) 7.02 7.03 Figure 34. AD9863 Tx Path FFT, 256-Carrier (Four Center Carriers Removed) OFDM Signal over 1.75 MHz Bandwidth, Centered at 7 MHz, with 20 mA Full-Scale Output into 60 Ω Differential Load –30 –40 –50 Figure 37. AD9863 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 34 –30 –40 –50 AMPLITUDE (dBc) –60 –70 –80 –90 –100 –110 –120 –130 6.06 03604-0-032 AMPLITUDE (dBc) –60 –70 –80 –90 –100 –110 –120 –130 7.81 03604-0-035 7.83 7.85 6.08 6.10 6.12 6.14 FREQUENCY (MHz) 6.16 6.18 7.87 7.89 FREQUENCY (MHz) 7.91 7.93 Figure 35. AD9863 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 34 –30 –40 –50 Figure 38. AD9863 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 34 –30 –40 –50 AMPLITUDE (dBc) AMPLITUDE (dBc) –60 –70 –80 –90 –100 –110 03604-0-033 –60 –70 –80 –90 –100 –110 –120 –130 0 5 10 15 FREQUENCY (MHz) 20 25 03604-0-036 –120 –130 0 5 10 15 FREQUENCY (MHz) 20 25 Figure 36. AD9863 Tx Path FFT of OFDM Signal in Figure 34, with 1× Interpolation Figure 39. AD9863 Tx Path FFT of OFDM Signal in Figure 34, with 2× Interpolation Rev. A | Page 15 of 40 AD9863 Figure 40 to Figure 45 use the same input data to the Tx path, a 256-carrier OFDM signal over a 23 MHz bandwidth, centered at 23 MHz. The four center carriers are removed from the signal to obser ve the in-band intermodulation distortion (IMD) from the DAC output. –30 –40 –50 –30 –40 –50 AMPLITUDE (dBc) –70 –80 –90 –100 03604-0-037 AMPLITUDE (dBc) –60 –60 –70 –80 –90 –100 –110 –120 6.97 03604-0-040 –110 –120 9 14 19 24 FREQUENCY (MHz) 29 34 6.98 6.99 7.00 7.01 FREQUENCY (MHz) 7.02 7.03 Figure 40. AD9863 Tx Path FFT, 256-Carrier (Four Center Carriers Removed) OFDM Signal over 23 MHz Bandwidth, Centered at 7 MHz, with 20 mA Full-Scale Output into 60 Ω Differential Load –30 –40 –50 Figure 43. AD9863 Tx Path FFT, In-Band IMD Products of OFDM Signal in Figure 40 –30 –40 –50 AMPLITUDE (dBc) –60 –70 –80 –90 –100 03604-0-038 AMPLITUDE (dBc) –60 –70 –80 –90 –100 –110 –120 33.5 03604-0-041 –110 –120 10.5 10.7 10.9 11.1 11.3 11.5 11.7 11.9 FREQUENCY (MHz) 12.1 12.3 12.5 33.7 33.9 34.1 34.3 34.5 34.7 34.9 FREQUENCY (MHz) 35.1 35.3 35.5 Figure 41. AD9863 Tx Path FFT, Lower-Band IMD Products of OFDM Signal in Figure 40 –30 –40 –50 Figure 44. AD9863 Tx Path FFT, Upper-Band IMD Products of OFDM Signal in Figure 40 –30 –40 –50 AMPLITUDE (dBc) –60 –70 –80 –90 –100 03604-0-039 AMPLITUDE (dBc) –60 –70 –80 –90 –100 –110 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 90 03604-0-042 –110 –120 0 10 20 30 40 50 60 FREQUENCY (MHz) 70 80 90 Figure 42. AD9863 Tx Path FFT of OFDM Signal in Figure 40, with 1× Interpolation Figure 45. AD9863 Tx Path FFT of OFDM Signal in Figure 40, with 2× Interpolation Rev. A| Page 16 of 40 AD9863 TERMINOLOGY Input Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the CLKIN1 signal and the instant at which the analog input is actually sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Crosstalk C oupling onto one channel being driven by a −0.5 dBFS signal when the adjacent interfering channel is driven by a full-scale signal. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. Peak differential voltage is computed by obser ving the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. Peak-to-peak differential is computed by rotating the input phase 180° and taking the peak measurement again. Then the difference is computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) The effective number of bits is calculated from the measured SNR based on the following equation: ENOB = SNR MEASURED − 1 .76 dB 6 .02 Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of an LSB using a “best straight line” determined by a least square cur ve fit. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Output Propagation Delay The delay between a differential crossing of CLK+ and CLK− and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio The ratio of a change in input offset voltage to a change in power supply voltage. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. It also may be reported in dBc (for example, degrades as signal level is lowered) or dBFS (for example, always related back to converter full scale). SFDR does not include harmonic distortion components. Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics) reported in dBc. Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that a signal should be left in the logic high state to achieve rated performance; pulse width low is the minimum time a signal should be left in the low state, logic low. Full-Scale Input Power Expressed in dBm, full-scale input power is computed using the following equation: ⎛V 2 Z Power FULLSCALE = 10 log ⎜ FULLSCALE −RMS INPUT ⎜ 0.001 ⎝ ⎞ ⎟ ⎟ ⎠ Gain Error Gain error is the difference between the measured and ideal full-scale input voltage range of the ADC. Rev. A | Page 17 of 40 AD9863 THEORY OF OPERATION SYSTEM BLOCK The AD9863 is targeted to cover the mixed-signal front end needs of multiple wireless communications systems. It features a receive path that consists of dual 12-bit receive ADCs and a transmit path that consists of dual 12-bit transmit DACs (TxDAC). The AD9863 integrates additional functionality typically required in most systems, such as power scalability, Tx gain control, and clock multiplication circuitry. The AD9863 minimizes both size and power consumption to address the needs of a range of applications from the low power portable market to the high performance base station market. The part is provided in a 64-lead lead frame chip scale package (LFCSP) that has a footprint of only 9 mm × 9 mm. Power consumption can be optimized to suit the particular application beyond just a speed grade option by incorporating power-down controls, low power ADC modes, TxDAC power scaling, and a half-duplex mode, which automatically disables the unused digital path. The AD9863 uses two 12-bit buses to transfer Rx path data and Tx path data. These two buses support 24-bit parallel data transfers or 12-bit interleaved data transfers. The bus is configurable through either external mode pins or internal registers settings. The registers allow many more options for configuring the entire device. The following sections discuss the various blocks of the AD9863: Rx Path Block, Tx Path Block, Digital Block, Programmable Registers, and Clock Distribution Block. The differential input stage is dc self-biased and allows differential or single-ended inputs. The output-staging block aligns the data, carries out the error correction, and passes the data to the output buffers. The latency of the Rx path is about 5 clock cycles. Rx Path Analog Input Equivalent Circuit The Rx path analog inputs of the AD9863 incorporate a novel structure that merges the function of the input sample-and-hold amplifiers (SHAs) and the first pipeline residue amplifiers into a single, compact switched capacitor circuit. By eliminating one amplifier in the pipeline, this structure achieves considerable noise and power savings over a conventional implementation that uses separate amplifiers. Figure 46 illustrates the equivalent analog inputs of the AD9863 (a switched capacitor input). Bringing CLK to logic high opens Switch S3 and closes Switch S1 and Switch S2; this is the sample mode of the input circuit. The input source connected to VIN+ and VIN− must charge capacitor CH during this time. Bringing CLK to a logic low opens Switch S2, and then Switch S1 opens, followed by the closing of Switch S3. This puts the input circuit into hold mode. S1 VIN+ RIN VCM RIN VIN– CIN CIN S3 CH 03604-0-073 CH + S2 – Rx PATH BLOCK Rx Path General Description The AD9863 Rx path consists of two 12-bit, 50 MSPS analogto-digital converters (ADCs). The dual ADC paths share the same clocking and reference circuitr y to provide optimal matching characteristics. Each of the ADCs consists of a 9-stage differential pipelined switched capacitor architecture with output error correction logic. The pipelined architecture permits the first stage to operate on a new input sample, while the remaining stages operate on preceding samples. Sampling occurs on the falling edge of the input clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC and a residual multiplier to drive the next stage of the pipeline. The residual multiplier uses the flash ADC output to control a switched capacitor digital-to-analog converter (DAC) of the same resolution. The DAC output is subtracted from the stage’s input signal, and the residual is amplified (multiplied) to drive the next pipeline stage. The residual multiplier stage is also called a multiplying DAC (MDAC). One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. Figure 46. Differential Input Architecture The structure of the input SHA places certain requirements on the input drive source. The differential input resistors are typically 2 kΩ each. The combination of the pin capacitance, CIN, and the hold capacitance, CH, is typically less than 5 pF. The input source must be able to charge or discharge this capacitance to 12-bit accuracy in one-half of a clock cycle. When the SHA goes into sample mode, the input source must charge or discharge capacitor CH from the voltage already stored on it to the new voltage. In the worst case, a full-scale voltage step on the input source must provide the charging current through the RON of Switch S1 (typically 100 Ω) to a settled voltage within one-half of the ADC sample period. This situation corresponds to driving a low input impedance. On the other hand, when the source voltage equals the value previously stored on CH, the hold capacitor requires no input current and the equivalent input impedance is extremely high. Rev. A| Page 18 of 40 AD9863 Rx Path Application Section Adding series resistance between the output of the signal source and the VIN pins reduces the drive requirements placed on the signal source. Figure 47 shows this configuration. AD9863 RSERIES VIN+ CSHUNT 03604-0-074 default 1 V VREF reference accepts a 2 V p-p differential input swing, and the offset voltage should be REFT = AVDD/2 + 0.5 V REFB = AVDD/2 − 0.5 V AD9863 REFT 0.1µF TO ADCs 0.1µF REFB 0.1µF VREF 10µF 0.1µF VIN– RSERIES 10µF Figure 47. Typical Input The bandwidth of the particular application limits the size of this resistor. For applications with signal bandwidths less than 10 MHz, the user may insert series input resistors and a shunt capacitor to produce a low-pass filter for the input signal. In addition, adding a shunt capacitance between the VIN pins can lower the ac load impedance. The value of this capaci tance depends on the source resistance and the required signal bandwidth. The Rx input pins are self-biased to provide this midsupply, common-mode bias voltage, so it is recommended to ac couple the signal to the inputs using dc blocking capacitors. In systems that must use dc coupling, use an op amp to comply with the input requirements of the AD9863. The inputs accept a signal with a 2 V p-p differential input swing centered about one-half of the supply voltage (AVDD/2). If the dc bias is supplied externally, the internal input bias circuit should be powered down by writing to registers Rx_A dc bias [Register 0x03, Bit 6] and Rx_B dc bias [Register 0x04, Bit 7]. The ADCs in the AD9863 are designed to sample differential input signals. The differential input provides improved noise immunity and better THD and SFDR performance for the Rx path. In systems that use single-ended signals, these inputs can be digitized, but it is recommended that a single-ended-todifferential conversion be performed. A single-ended-todifferential conversion can be performed by using a transformer coupling circuit (typically for signals above 10 MHz) or by using an operational amplifier, such as the AD8138 (typically for signals below 10 MHz). 0.5V Figure 48. Typical Rx Path Decoupling An external reference may be used for systems that require a different input voltage range, high accuracy gain matching between multiple devices, or improvements in temperature drift and noise characteristics. When an external reference is desired, the internal Rx band gap reference must be powered down using the VREF register [Register 0x05, Bit 4], with the external reference driving the voltage level on the VREF pin. The external voltage level should be one-half of the desired peak-to-peak differential voltage swing. The result is that the differential voltage references are driven to new voltages: REFT = AVDD/2 +VREF/2 V REFB = AVDD/2 − VREF/2 V If an external reference is used, it is recommended not to exceed a differential offset voltage greater than 1 V for the reference. Clock Input and Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9863 contains clock duty cycle stabilizer circuitr y (DCS). The DCS retimes the internal ADC clock (nonsampling edge) and provides the ADC with a nominal 50% duty cycle. Input clock rates of over 40 MHz can use the DCS so that a wide range of input clock duty cycles can be accommodated. Conversely, DCS should not be used for Rx sampling below 40 MSPS. Maintaining a 50% duty cycle clock is particularly important in high speed applications when proper sample-and-hold times for the converter are required to maintain high performance. The DCS can be enabled by writing highs to the Rx_A/Rx_B CLK duty register bits [Register 0x06/Register 0x07, Bit 4]. The duty cycle stabilizer uses a delay-locked loop to create the nonsampling edge. As a result, any changes to the sampling frequency require approximately 2 µs to 3 µs to allow the DLL to adjust to the new rate and settle. High speed, high resolution ADCs are sensitive to the quality of the clock input. The ADC Voltage References The AD9863 12-bit ADCs use internal references that are designed to provide for a 2 V p-p differential input range. The internal band gap reference generates a stable 1 V reference level and is decoupled through the VREF pin. REFT and REFB are the differential references generated based on the voltage level of VREF. Figure 48 shows the proper decoupling of the reference pins VREF, REFT, and REFB when using the internal reference. Decoupling capacitors should be placed as close to the reference pins as possible. External references REFT and REFB are centered at AVDD/2 with a differential voltage equal to the voltage at VREF (by default 1 V when using the internal reference), allowing a peakto-peak differential voltage swing of 2× VREF. For example, the Rev. A | Page 19 of 40 03604-0-075 AD9863 degradation in SNR at a given full-scale input frequency (fINPUT), due to aperture jitter (tA), can be calculated with the following equation: SNR degradation = 20 log [(½)πFINtA)] In the equation, the rms aperture jitter, tA, represents the rootsum-square of all jitter sources, which includes the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. The clock input is a digital signal that should be treated as an analog signal with logic level threshold voltages, especially in cases where aperture jitter may affect the dynamic range of the AD9863. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter cr ystal-controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. Either of the ADCs in the AD9863 Rx path can be placed in standby mode independently by writing to the appropriate SPI register bits in Register 3, Register 4, and Register 5. The minimum standby power is achieved when both channels are placed in full power-down mode using the appropriate SPI register bits in Register 3, Register 4, and Register 5. Under this condition, the internal references are powered down. When either or both of the channel paths are enabled after a powerdown, the wake-up time is directly related to the recharging of the REFT and REFB decoupling capacitors and the duration of the power-down. Typically, it takes approximately 5 ms to restore full operation with fully discharged 0.1 µF and 10 µF decoupling capacitors on REFT and REFB. 120 NORMAL 100 AVDD CURRENT (mA) 80 LOW POWER 60 Power Dissipation and Standby Mode The power dissipation of the AD9863 Rx path is proportional to its sampling rate. The Rx path portion of the digital (DRVDD) power dissipation is determined primarily by the strength of the digital drivers and the load on each output bit. The digital drive current can be calculated by IDRVDD = VDRVDD × CLOAD × fCLOCK × N where N is the number of bits changing and CLOAD is the average load on the digital pins that changed. The analog circuitr y is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. Each speed grade dissipates a baseline power at low sample rates, which increases with clock frequency. The baseline power dissipation for either speed grade can be reduced by asserting the ADC_LO_PWR pin, which reduces internal ADC bias currents by half, in some cases resulting in degraded performance. To further reduce power consumption of the ADC, the ADC_LO_PWR pin can be combined with a serial programmable register setting to configure an ultralow power mode. The ultralow power mode reduces power consumption by a fourth of the normal power consumption. The ultralow power mode can be used at slower sampling frequencies or if reduced performance is acceptable. To configure the ultralow power mode, assert the ADC_LO_PWR pin during power-up and write the following register settings: Register 0x08 Register 0x09 Register 0x0A (MSB) 0000 1100 (MSB) 0111 0000 (MSB) 0111 0000 40 ULTRALOW POWER 03604-0-043 20 0 0 5 10 15 20 25 30 35 40 Rx PATH SAMPLING RATE (MHz) 45 50 Figure 49. Typical Rx Path Analog Supply Current vs. Sample Rate, VDD = 3.3 V for Normal, Low, and Ultralow Power Modes Tx PATH BLOCK The AD9863 transmit (Tx) path includes dual interpolating 12-bit current output DACs that can be operated independently or can be coupled to form a complex spectrum in an image reject transmit architecture. Each channel includes two FIR filters, making the AD9863 capable of 1×, 2×, or 4× interpolation. High speed input and output data rates can be achieved within the limitations listed in Table 9. Table 9. AD9863 Tx Path Maximum Data Rate Input Data Rate per Channel (MSPS) 80 160 80 80 50 50 DAC Sampling Rate (MSPS) 80 160 160 160 200 200 Interpolation Rate 1× 2× 4× 24-Bit Interface Mode FD, HD12, Clone HD24 FD, HD12, Clone HD24 FD, HD12, Clone HD24 Figure 49 shows the typical analog power dissipation (ADC_AVDD = 3.3 V) for the ADC vs. sampling rate for the normal power, low power, and ultralow power modes. By using the dual DAC outputs to form a complex signal, an external analog quadrature modulator, such as the Analog Devices AD8349, can enable an image rejection architecture. (Note: the AD9863 evaluation board includes a quadrature modulator in the Tx path that accommodates the AD8345, AD8346, and AD8349 footprints.) To optimize the image rejection capability as well as LO feedthrough suppression in Rev. A| Page 20 of 40 AD9863 this architecture, the AD9863 offers programmable (via the SPI port), fine (trim) gain and offset adjustment for each DAC. Also included in the AD9863 are a phase-locked loop (PLL) clock multiplier and a 1.2 V band gap voltage reference. With the PLL enabled, a clock applied to the CLKIN2 input is multiplied internally and generates all necessar y internal synchronization clocks. Each 12-bit DAC provides two complementar y current outputs whose full-scale currents can be determined from a single external resistor. An external pin, TxPWRDWN, can be used to power down the Tx path when not in use, optimizing system power consumption. Using the TxPWRDWN pin disables clocks and some analog circuitr y, saving both digital and analog power. The powerdown mode leaves the biases enabled to facilitate a quick recover y time, typically