AD9879

Mixed-Signal Front End Set-Top Box, Cable Modem AD9879 FEATURES Low cost 3.3 V MxFE™ for DOCSIS-, EURO-DOCSIS-, DVB-, DAVIC-compliant set-top box and cable modem applications 232 MHz quadrature digital upconverter 12-bit direct IF DAC (TxDAC+™) Up to 65 MHz carrier frequency DDS Programmable sampling clock rates 16× upsampling interpolation LPF Single-tone frequency synthesis Analog Tx output level adjust Direct cable amp interface 12-bit, 33 MSPS direct IF ADC with optional video clamping input 10-bit, 33 MSPS direct IF ADC Dual 7-bit, 16.5 MSPS sampling I/Q ADC 12-bit Σ-∆ auxiliary DAC FUNCTIONAL BLOCK DIAGRAM I TX DATA TX Q ⇑16 SINC–1 12 DAC TX DDS Σ -∆ Σ-∆_OUT CA_PORT 4 SPORT CONTROL REGISTERS PLL XM/N MCLK 2 RXIQ[3:0] 8 MUX RXI ADC MUX 2 RXQ 10 ADC RX10 RXIF[11:0] MUX 12 ADC MUX 02773-001 APPLICATIONS Cable modem and satellite systems Set-top boxes Power line modem PC multimedia Digital communications Data and video modems QAM, OFDM, FSK modulation AD9879 RX12 CLAMP VIDEO Figure 1. GENERAL DESCRIPTION The AD9879 is a single-supply set-top box and cable modem mixed-signal front end. The device contains a transmit path interpolation filter, complete quadrature digital upconverter, and transmit DAC. The receive path contains a 12-bit ADC, a 10-bit ADC, and dual 7-bit ADCs. All internally required clocks and an output system clock are generated by the phase-locked loop (PLL) from a single cr ystal or clock input. The transmit path interpolation filter provides an upsampling factor of 16× with an output signal bandwidth as high as 8.3 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0.0 dB to 7.5 dB in 0.5 dB steps is available to preser ve SNR when reduced output levels are required. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. The 12-bit and 10-bit IF ADCs can convert direct IF inputs up to 70 MHz and run at sample rates up to 33 MSPS. A video input with an adjustable signal clamping level, along with the 10-bit ADC, allow the AD9879 to process an NTSC and a QAM channel simultaneously. The programmable Σ-Δ DAC can be used to control external components, such as variable gain amplifiers (VGAs) or voltage controlled tuners. The CA port provides an interface to the AD8321/AD8323 or AD8322/AD8327 programmable gain amplifier (PGA) cable drivers, enabling host processor control via the MxFE SPORT. The AD9879 is available in a 100-lead MQFP. It offers enhanced receive path undersampling performance and lower cost when compared with the pin-compatible AD9873. The AD9879 is specified over the commercial (−40°C to +85°C) temperature range. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. AD9879 TABLE OF CONTENTS Specifications..................................................................................... 4 Absolute Maximum Ratings............................................................ 7 Explanation of Test Levels ........................................................... 7 Thermal Characteristics .............................................................. 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Terminology .................................................................................... 10 Theory of Operation ...................................................................... 11 Transmit Path .............................................................................. 11 Data Assembler ........................................................................... 11 Interpolation Filter ..................................................................... 12 Digital Upconverter.................................................................... 12 DPLL-A Clock Distribution...................................................... 12 Clock and Oscillator Circuitry ................................................. 12 Programmable Clock Output REFCLK ................................... 13 Reset and Transmit Power-Down ............................................ 14 Σ-Δ Outputs ................................................................................ 15 Register Map and Bit Definitions ................................................. 16 Register 0x00—Initialization .................................................... 17 Register 0x01—Clock Configuration....................................... 17 Register 0x02—Power-Down .................................................... 17 Registers 0x03–0x04—Σ-Δ and Flag Control ......................... 17 Register 0x07—Video Input Configuration ............................ 17 Register 0x08—ADC Clock Configuration ............................ 18 Register 0x0C—Die Revision.................................................... 18 Register 0x0D—Tx Frequency Tuning Words LSBs .............. 18 Register 0x0E—DAC Gain Control ......................................... 18 Register 0x0F—Tx Path Configuration ................................... 18 Registers 0x10–0x17—Carrier Frequency Tuning ................. 19 Serial Interface for Register Control ............................................ 20 General Operation of the Serial Interface ............................... 20 Instruction Byte .......................................................................... 20 Serial Interface Port Pin Description ....................................... 20 MSB/LSB Transfers .................................................................... 20 Notes on Serial Port Operation ................................................ 21 Transmit Path (Tx) ......................................................................... 22 Transmit Timing......................................................................... 22 Data Assembler ........................................................................... 22 Half-Band Filters (HBFs) .......................................................... 22 Cascaded Integrator-Comb (CIC) Filter ................................. 22 Combined Filter Response ........................................................ 22 Tx Signal Level Considerations ................................................ 24 Tx Throughput and Latency ..................................................... 24 Digital-to-Analog Converter .................................................... 25 Programming the AD8321/AD8323 or AD8322/AD8327 Cable Driver Amplifier Gain Control ..................................................... 26 Receive Path (Rx) ........................................................................... 27 IF10 and IF12 ADC Operation ................................................ 27 Input Signal Range and Digital Output Codes ....................... 27 Driving the Inputs ...................................................................... 27 PCB Design Considerations.......................................................... 28 Component Placement .............................................................. 28 Power Planes and Decoupling .................................................. 28 Ground Planes ............................................................................ 29 Signal Routing............................................................................. 29 Outline Dimensions ....................................................................... 30 Ordering Guide .......................................................................... 30 Rev. A | Page 2 of 32 AD9879 REVISION HISTORY 6/05—Rev. 0 to Rev. A Updated Format.................................................................. Universal Changed OSCOUT to REFCLK....................................... Universal Changed REF CLK to REFCLK........................................ Universal Changes to Specifications Section................................................... 4 Changes to Figure 13 ...................................................................... 21 Changes to Equation 18.................................................................. 24 Changes to Equation 21.................................................................. 24 Changes to Outline Dimensions ................................................... 30 Changes to Ordering Guide........................................................... 30 8/02—Revision 0: Initial Version Rev. A | Page 3 of 32 AD9879 SPECIFICATIONS VAS = 3.3 V ± 5%, VDS = 3.3 V ± 10%, fOSCIN = 27 MHz, fSYSCLK = 216 MHz, fMCLK = 54 MHz (M = 8), ADC clock from OSCIN, RSET = 4.02 kΩ, 75 Ω DAC load, unless otherwise noted. Table 1. Parameter OSCIN AND XTAL CHARACTERISTICS Frequency Range Duty Cycle Input Impedance MCLK Cycle to Cycle Jitter Tx DAC CHARACTERISTICS Resolution Maximum Sample Rate Full-Scale Output Current Gain Error (Using Internal Reference) Offset Error Reference Voltage (REFIO Level) Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Output Capacitance Phase Noise @ 1 kHz Offset, 42 MHz Crystal and OSCIN Multiplier Enabled at 16× Output Voltage Compliance Range Wideband SFDR 5 MHz Analog Out, IOUT = 10 mA 65 MHz Analog Out, IOUT = 10 mA Narrow-band SFDR (±1 MHz Window) 5 MHz Analog Out, IOUT = 10 mA Tx MODULATOR CHARACTERISTICS I/Q Offset Pass-Band Amplitude Ripple (f < fIQCLK/8) Pass-Band Amplitude Ripple (f < fIQCLK/4) Stop-Band Response (f > fIQCLK × 3/4) Tx GAIN CONTROL Gain Step Size Gain Step Error Settling Time to 1% (Full-Scale Step) IQ ADC CHARACTERISTICS Resolution1 Maximum Conversion Rate Pipeline Delay Offset Matching Between I and Q ADCs Gain Matching Between I and Q ADCs Analog Input Input Voltage Range1 Input Capacitance Differential Input Resistance AC Performance (AIN = 0.5 dBFS, fIN = 5 MHz) Effective Number of Bits (ENOB) Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) Temp Full Full 25°C 25°C N/A Full Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full Full Full Full Full Full Full Full 25°C 25°C 25°C N/A Full N/A Full Full Full 25°C 25°C 25°C 25°C 25°C 25°C Test Level II II III III N/A II II I I I III III III III II III III III II II II II III III III N/A II N/A III III III III III I I I I 5.00 34.7 41.3 Min 3 35 Typ Max 29 65 Unit MHz % MΩ||pF ps rms Bits MHz mA % FS % FS V LSB LSB pF dBc/Hz V dBc dBc dBc dB dB dB dB dB dB µs Bits MHz ADC cycles LSBs LSBs Vppd pF kΩ Bits dB dB dB 50 100||3 6 12 232 4 −2.0 1.18 10 −1.0 ±1.0 1.23 ±2.5 ±8 5 −110 20 +2.0 1.28 −0.5 60.8 44.0 65.4 50 66.9 46.2 72.3 55 +1.5 ±0.1 ±0.5 −63 0.5 60 >80 >80 >85 >50 dB dB dB dB dB tMCLK cycles ns MHz ns ns ns ns ns MHz ns ns ms ns ns ns V V µA µA pF V V mA mA mA mA mA mA mA 4 66 3 3 0 TOSC/4 – 2.0 −1.0 1.0 TOSC/4 + 3.0 +1.0 15 30 30 1 25 0 30 VDRVDD – 0.7 0.4 12 12 3 VDRVDD – 0.6 0.4 163 95 68 119 16 113 110 184 126 IQ ADC in default mode. ADC Clock Select Register 8, Bit 3 set to 0. Rev. A | Page 6 of 32 AD9879 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Power Supply (VAVDD,VDVDD,VDRVDD) Digital Output Current Digital Inputs Analog Inputs Operating Temperature Maximum Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 sec) Rating 3.9 V 5 mA −0.3 V to VDRVDD + 0.3 V −0.3 V to VAVDD + 0.3 V −40°C to +85°C 150°C −65°C to +150°C 300°C EXPLANATION OF TEST LEVELS I Devices are 100% production tested at +25°C and guaranteed by design and characterization testing for commercial operating temperature range (−40ºC to +85°C). Parameter is guaranteed by design and/or characterization testing. Parameter is a typical value only. Test level definition is not applicable. II III N/A Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 100-Lead MQFP θJA = 40.5°C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 7 of 32 AD9879 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIDEO IN REFB12 REFT12 REFT10 AGND REFB10 AGND AGND AGND AVDD AVDD AVDD IF10+ AVDD IF12+ IF12– IF10– AGND 83 Q+ 82 100 95 92 90 96 94 89 88 87 86 85 99 98 84 97 93 DNC DRGND DRVDD IF(11) IF(10) IF(9) IF(8) IF(7) IF(6) IF(5) IF(4) IF(3) IF(2) IF(1) IF(0) RXIQ(3) RXIQ(2) RXIQ(1) RXIQ(0) RXSYNC DRGND DRVDD MCLK DVDD DGND TXSYNC TXIQ(5) TXIQ(4) TXIQ(3) TXIQ(2) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PIN 1 91 81 Q– 80 79 78 77 76 75 74 73 72 71 DNC I+ I– DNC DNC DNC AGNDIQ AVDDIQ DRVDD REFCLK DRGND DGND Σ-∆ Σ-∆_OUT FLAG1 DVDD Σ-∆ CA_EN CA_DATA CA_CLK DVDDOSC OSCIN XTAL DGNDOSC AGNDPLL PLLFILT AVDDPLL DVDDPLL DGNDPLL AVDDTX TX+ TX– AD9879 TOP VIEW (Pins Down) 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 41 43 44 35 38 31 32 36 39 45 47 34 37 40 46 48 49 33 TXIQ(1) 42 DVDDTX DNC RESET REFIO DGNDTX FSADJ DVDD DGND DVDD DGND DGND CS PROFILE AGNDTX TXIQ(0) SDIO SCLK SDO PWRDN 50 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 35, 75 to 77, 80 2, 21, 70 3, 22, 72 4 to 15 16 to 19 20 23 24, 33, 38 25, 34, 39, 40 26 27 to 32 36 37 Mnemonic DNC DRGND DRVDD IF[11:0] RXIQ[3:0] RXSYNC MCLK DVDD DGND TXSYNC TXIQ[5:0] PROFILE RESET Description Do Not Connect. Pins are not bonded to die. Pin Driver Digital Ground. Pin Driver Digital 3.3 V Supply. 12-Bit ADC Digital Output. Muxed I and Q ADCs Output. Sync Output, IF, I and Q ADCs. Master Clock Output. Digital 3.3 V Supply. Digital Ground. Sync Input for Transmit Port. Digital Input for Transmit Port. Profile Selection Inputs. Chip Reset Input (Active Low). Rev. A | Page 8 of 32 02773-002 AD9879 Pin No. 41 42 43 44 45 46 47 48 49 50 51, 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 71 73 74 78, 79 81, 82 83, 88, 91, 96, 99 84, 87, 92, 95 85 86 89, 90 93 94 97, 98 100 Mnemonic SCLK CS SDIO SDO DGNDTX DVDDTX PWRDN REFIO FSADJ AGNDTX TX−, TX+ AVDDTX DGNDPLL DVDDPLL AVDDPLL PLLFILT AGNDPLL DGNDOSC XTAL OSCIN DVDDOSC CA_CLK CA_DATA CA_EN DVDD Σ-∆ FLAG1 Σ-∆_OUT DGND Σ-∆ REFCLK AVDDIQ AGNDIQ I−, I+ Q−, Q+ AGND AVDD REFB10 REFT10 IF10−, IF10+ REFB12 REFT12 IF12−, IF12+ VIDEO IN Description SPORT Clock. SPORT Chip Select. SPORT Data I/O. SPORT Data Output. Tx Path Digital Ground. Tx Path Digital 3.3 V Supply. Power-Down Transmit Path. TxDAC Decoupling (to AGND). DAC Output Adjust (External Resistor). Tx Path Analog Ground. Tx Path Complementary Outputs. Tx Path Analog 3.3 V Supply. PLL Digital Ground. PLL Digital 3.3 V Supply. PLL Analog 3.3 V Supply. PLL Loop Filter Connection. PLL Analog Ground. Oscillator Digital Ground. Crystal Oscillator Inverted Output. Oscillator Clock Input. Oscillator Digital 3.3 V Supply. Serial Clock to Cable Driver. Serial Data to Cable Driver. Serial Enable to Cable Drive. Σ-∆ Digital 3.3 V Supply. Digital Output Flag 1. Σ-∆ DAC Output. Σ-∆ Digital Ground. Programmable Reference Clock Output. 7-Bit ADCs Analog 3.3 V Supply. 7-Bit ADCs Analog Ground. Differential Input to I ADC. Differential Input to Q ADC. 12-Bit ADC Analog Ground. 12-Bit ADC Analog 3.3 V Supply. 10-Bit ADC Decoupling Node. 10-Bit ADC Decoupling Node. Differential Input to 10-Bit ADC. 12-Bit ADC Decoupling Node. 12-Bit ADC Decoupling Node. Differential Input to IF ADC. Video Clamp Input, 12-Bit ADC. Rev. A | Page 9 of 32 AD9879 TERMINOLOGY Aperture Delay The aperture delay is a measure of the sample-and-hold amplifier (SHA) performance. It specifies the time delay between the rising edge of the sampling clock input and when the input signal is held for conversion. Aperture Uncertainty (Jitter) Aperture jitter is the variation in aperture delay for successive samples. It is manifested as noise on the input to the ADC. Channel-to-Channel Isolation (Crosstalk) In an ideal multichannel system, the signal in one channel does not influence the signal level of another channel. The channelto-channel isolation specification is a measure of the change that occurs to a grounded channel as a full-scale signal is applied to another channel. Differential Nonlinearity Error (DNL, No Missing Codes) An ideal converter exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 10-bit resolution indicates that all 1,024 codes, respectively, must be present over all operating ranges. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the formula N = (SINAD − 1.76 dB∕6.02) it is possible to determine a measure of performance expressed as N, the effective number of bits. Thus, the effective number of bits for a device’s sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Gain Error The first code transition should occur at an analog value 1/2 LSB above full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between the first and last code transitions and the ideal difference between the first and last code transitions. Input Referred Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output code is calculated in LSB and converted to an equivalent voltage. This results in a noise figure that can be directly referred to the input of the MxFE. Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through the positive full scale. The point used as the negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line. Offset Error First transition should occur for an analog value 1/2 LSB above −FS. Offset error is defined as the deviation of the actual transition from that point. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or break down, resulting in nonlinear performance. Phase Noise Single-sideband phase noise power is specified relative to the carrier (dBc/Hz) at a given frequency offset (1 kHz) from the carrier. Phase noise can be measured directly in single-tone transmit mode with a spectrum analyzer that supports noise marker measurements. It detects the relative power between the carrier and the offset (1 kHz) sideband noise and takes the resolution bandwidth (RBW) into account by subtracting 10 log(RBW). It also adds a correction factor that compensates for the implementation of the resolution bandwidth, log display, and detector characteristic. Pipeline Delay (Latency) Pipeline delay is the number of clock cycles between conversion initiation and the availability of the associated output data. Power Supply Rejection Power supply rejection specifies the converter’s maximum fullscale change when the supplies are varied from nominal to minimum and maximum specified voltages. Signal-to-Noise and Distortion (SINAD) Ratio SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in decibels. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in dB, between the rms amplitude of the DAC output signal (or the ADC input signal) and the peak spurious signal over the specified bandwidth (Nyquist bandwidth, unless otherwise noted). Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal, and is expressed as a percentage or in decibels. Rev. A | Page 10 of 32 AD9879 THEORY OF OPERATION To gain a general understanding of the AD9879, refer to the block diagram of the device architecture in Figure 3. The device consists of a transmit path, receive path, and auxiliar y functions, such as a DPLL, a Σ-Δ DAC, a serial control port, and a cable amplifier interface. The transmit DAC resolution is 12 bits and can run at sampling rates as high as 232 MSPS. Analog output scaling from 0.0 dB to 7.5 dB in 0.5 dB steps is available to preser ve SNR when reduced output levels are required. DATA ASSEMBLER The AD9879 data path operates on two 12-bit words, the I and Q components, which compose a complex symbol. The data assembler builds the 24-bit complex symbols from four consecutive 6-bit nibbles read over the TxIQ[5:0] bus. The nibbles are strobed synchronous to the master clock, MCLK, into the data assembler. A high level on TxSYNC signals the start of a transmit symbol. The first two nibbles of the symbol form the I component, and the second two nibbles form the Q component. Symbol components are assumed to be in twos complement format. The timing of the interface is fully described in the Transmit Timing section of this data sheet. TRANSMIT PATH The transmit path contains an interpolation filter, a complete quadrature digital upconverter, an inverse sinc filter, and a 12-bit current output DAC. The maximum output current of the DAC is set by an external resistor. The Tx output PGA provides additional transmit signal level control. The transmit path interpolation filter provides an upsampling factor of 16 with an output signal bandwidth as high as 5.8 MHz. Carrier frequencies up to 65 MHz with 26 bits of frequency tuning resolution can be generated by the direct digital synthesizer (DDS). AD9879 DATA ASSEMBLER TXIQ 6 I 12 FIR LPF 4 12 CIC LPF COS 4 — TXSYNC Q 12 4 12 4 SIN (fIQCLK) ÷4 MCLK REFCLK ÷R (fMCLK) ÷4 DDS QUADRATURE MODULATOR DAC GAIN CONTROL SINC–1 BYPASS MUX SINC–1 12 DAC FSADJ TX (fSYSCLK) (fOSCIN) PLL OSCIN × M XTAL OSCIN Σ-∆ INPUT REGISTER 12 Σ-∆ Σ-∆_OUT CA_PORT PROFILE SPORT 3 CA INTERFACE PROFILE SELECT ÷8 FLAG1 ÷2 (fOSCIN) ÷2 7 4 SERIAL INTERFACE ADC I INPUT RXIQ[3:0] 4 IQ MUX 7 ADC Q INPUT RXPORT RXSYNC ÷2 (fOSCIN) 12 10 ADC IF10 INPUT IF[11:0] IF MUX 12 ADC MUX IF12 INPUT VIDEO INPUT CLAMP LEVEL DAC Figure 3. Block Diagram Rev. A | Page 11 of 32 02773-003 – — + AD9879 INTERPOLATION FILTER Once through the data assembler, the IQ data streams are fed through a 4× FIR low-pass filter and a 4× cascaded integratorcomb (CIC) low-pass filter. The combination of these two filters results in the sample rate increasing by a factor of 16. In addition to the sample rate increase, the half-band filters provide the low-pass filtering characteristic necessary to suppress the spectral images between the original sampling frequency and the new (16× higher) sampling frequency. External loop filter components consisting of a series resistor (1.3 kΩ) and capacitor (0.01 µF) provide the compensation zero for the OSCIN multiplier PLL loop. The overall loop performance has been optimized for these component values. DPLL-A CLOCK DISTRIBUTION Figure 3 shows the clock signals used in the transmit path. The DAC sampling clock, fDAC, is generated by DPLL-A. FDAC has a frequency equal to L × fOSCIN, where fOSCIN is the internal signal generated by either the crystal oscillator when a crystal is connected between the OSCIN and XTAL pins or the clock that is fed into the OSCIN pin, and L is the multiplier programmed through the serial port. L can have the values of 1, 2, 3, or 8. The transmit path expects a new half word of data at the rate of fCLK-A. When the Tx multiplexer is enabled, the frequency of Tx Port is fCLK−A = 2 × fDA/K = 2 × L × fOSCIN/K where K is the interpolation factor. The interpolation factor can be programmed to be 1, 2, or 4. When the Tx multiplexer is disabled, the frequency of the Tx Port is fCLK−A = fDAC/K = L × fOSCIN/K (2) (1) DIGITAL UPCONVERTER The digital quadrature modulator stage following the CIC filters is used to frequency shift (upconvert) the baseband spectrum of the incoming data stream up to the desired carrier frequency. The carrier frequency is controlled numerically by a direct digital synthesizer (DDS). The DDS uses the internal system clock (fSYSCLK) to generate the desired carrier frequency with a high degree of precision. The carrier is applied to the I and Q multipliers in quadrature fashion (90° phase offset) and summed to yield a data stream that is the modulated carrier. The modulated carrier becomes the 12-bit sample sent to the DAC. The receive path contains a 12-bit ADC, a 10-bit ADC, and a dual 7-bit ADC. All internally required clocks and an output system clock are generated by the PLL from a single crystal or clock input. The 12-bit and 10-bit IF ADCs can convert direct IF inputs up to 70 MHz and run at sample rates up to 33 MSPS. A video input with an adjustable signal clamping level along with the 10-bit ADC allow the AD9879 to process an NTSC and a QAM channel simultaneously. The programmable Σ-Δ DAC can be used to control external components, such as variable gain amplifiers (VGAs) or voltage controlled tuners. The CA_PORT provides an interface to the AD8321/AD8323 or AD8322/AD8327 programmable gain amplifier (PGA) cable drivers, enabling host processor control via the MxFE SPORT. Receive Section The AD9879 includes two high speed, high performance ADCs. The 10-bit and 12-bit direct IF ADCs deliver excellent undersampling performance with input frequencies as high as 70 MHz. The sampling rate can be as high as 33 MSPS. The ADC sampling frequency can be derived directly from the OSCIN signal or from the on-chip OSCIN multiplier. For highest dynamic performance, it is advisable to choose an OSCIN frequency that can be directly used as the ADC sampling clock. Digital IQ ADC outputs are multiplexed to one 4-bit bus, clocked by a frequency (fMCLK) of four times the sampling rate. The IF ADCs use a multiplexed 12-bit interface with an output word rate of fMCLK. OSCIN Clock Multiplier The AD9879 can accept either an input clock into the OSCIN pin or a fundamental mode XTAL across the OSCIN pin and XTAL pins as the device’s main clock source. The internal PLL then generates the fSYSCLK signal from which all other internal signals are derived. The DAC uses fSYSCLK as its sampling clock. For DDS applications, the carrier is typically limited to about 30% of fSYSCLK. For a 65 MHz carrier, the system clock required is above 216 MHz. The OSCIN multiplier function maintains clock integrity, as evidenced by the excellent phase noise characteristics and low clock-related spur in the output spectrum of the AD9879’s systems. CLOCK AND OSCILLATOR CIRCUITRY The internal oscillator of the AD9879 generates all sampling clocks from a simple, low cost, parallel resonance, fundamental frequency quartz crystal. Figure 4 shows how the quartz crystal is connected between OSCIN (Pin 61) and XTAL (Pin 60) with parallel resonant load capacitors as specified by the crystal manufacturer. The internal oscillator circuitry can also be overdriven by a TTL-level clock applied to OSCIN with XTAL left unconnected. fOSCIN = fMCLK × M (3) Rev. A | Page 12 of 32 AD9879 An internal PLL generates the DAC sampling frequency, fSYSCLK, by multiplying OSCIN frequency M times. The MCLK signal (Pin 23), fMCLK, is derived by dividing fSYSCLK by 4. fSYSCLK = fOSCIN × M fMCLK = fOSCIN × M/4 (4) (5) Figure 3 shows that ADCs are either sampled directly by a low jitter clock at OSCIN or by a clock that is derived from the PLL output. Operating modes can be selected in Register 0x08. Sampling the ADCs directly with the OSCIN clock requires MCLK to be programmed to be twice the OSCIN frequency. PROGRAMMABLE CLOCK OUTPUT REFCLK The AD9879 provides an auxiliar y output clock on Pin 71, REFCLK. The value of the MCLK divider bit field, R, determines its output frequency as shown: fREFCLK = fMCLK/R, for R = 2 − 3 fREFCLK = fOSCIN/R, for R = 0 (6) (7) An external PLL loop filter (Pin 57) consisting of a series resistor and ceramic capacitor (Figure 18, R1 = 1.3 kΩ, C12 = 0.01 µF) is required for stability of the PLL. Also, a shield surrounding these components is recommended to minimize external noise coupling into the PLL’s voltage controlled oscillator input (guard trace connected to AVDDPLL). In its default setting (0x00 in Register 0x01), the REFCLK pin provides a buffered output of fOSCIN. CP1 10µF C1 C2 0.1µF 0.1µF CP2 10µF C3 0.1µF C4 C5 0.1µF 0.1µF C6 0.1µF 100 VIDEO IN REFB12 REFT12 REFT10 AGND REFB10 AGND AGND AGND AVDD AVDD AVDD IF10+ AGND 83 AVDD IF12+ IF12– IF10– Q+ 82 95 92 96 94 90 89 88 87 86 85 99 98 93 84 97 DNC 1 91 81 Q– 80 PIN 1 DNC DRGND DRVDD (MSB) IF(11) IF(10) 2 3 4 5 79 78 77 76 I+ I– DNC DNC IF(9) 6 75 DNC IF(8) IF(7) IF(6) IF(5) IF(4) 7 8 9 10 11 74 73 72 71 AGNDIQ AVDDIQ DRVDD REFCLK DRGND IF(3) IF(2) IF(1) IF(0) (MSB) RXIQ(3) RXIQ(2) RXIQ(1) RXIQ(0) RXSYNC DRGND DRVDD MCLK DVDD DGND TXSYNC (MSB) TXIQ(5) TXIQ(4) TXIQ(3) TXIQ(2) 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 AD9879 TOP VIEW (Pins Down) 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DGND Σ-∆ Σ-∆_OUT FLAG1 DVDD Σ-∆ CA_EN CA_DATA CA_CLK DVDDOSC OSCIN XTAL DGNDOSC AGNDPLL PLLFILT AVDDPLL DVDDPLL DGNDPLL AVDDTX TX+ TX– GUARD TRACE C12 R1 1.3kΩ 0.01µF C10 20pF C11 20pF 41 43 35 38 44 31 32 36 39 34 37 40 42 45 47 33 46 48 49 TXIQ(1) DNC DVDDTX DGND DGND RESET DGND DVDD DVDD CS DGNDTX FSADJ PROFILE AGNDTX TXIQ(0) PWRDN REFIO SCLK SDIO SDO 50 C13 0.1µF RSET 4.02kΩ Figure 4. Basic Connection Diagram Rev. A | Page 13 of 32 02773-004 AD9879 RESET AND TRANSMIT POWER-DOWN Power-Up Sequence On initial power-up, the RESET pin should be held low until the power supply is stable. Once RESET is deasserted, the AD9879 can be programmed over the serial port. The on-chip PLL requires a maximum of 1 millisecond after the rising edge of RESET or a change of the multiplier factor (M) to completely settle. It is recommended that the PWRDN pin be held low during the reset and PLL settling time. Changes to ADC Clock Select (Register 0x08) or SYS Clock Divider N (Register 0x01) should be programmed before the rising edge of PWRDN. Once the PLL is frequency locked and after the PWRDN pin is brought high, transmit data can be sent reliably. If the PWRDN pin cannot be held low throughout the reset and PLL settling time period, the power-down digital Tx bit or the PWRDN pin should be pulsed after the PLL has settled. This will ensure correct transmit filter initialization. A software reset (writing a 1 into Bit 5 of Register 0x00) is functionally equivalent to the hardware reset but does not force Register 0x00 to its default value. VS RESET 02773-005 1msMIN PWRDN 5 MCLKMIN Figure 5. Power-Up Sequence for Tx Data Path Transmit Power-Down A low level on the PWRDN pin stops all clocks linked to the digital transmit data path and resets the CIC filter. Deasserting PWRDN reactivates all clocks. The CIC filter is held in a reset state for 80 MCLK cycles after the rising edge of PWRDN to allow for flushing of the half-band filters with new input data. Transmit data bursts should be padded with at least 20 symbols of null data directly before the PWRDN pin is deasserted. Immediately after the PWRDN pin is deasserted, the transmit burst should start with a minimum of 20 null data symbols. This avoids unintended DAC output samples caused by the transmit path latency and filter settling time. Software Power-Down Digital Tx (Bit 5 in Register 02x00) is functionally equivalent to the hardware PWRDN pin and takes effect immediately after the last register bit has been written over the serial port. RESET To initiate a hardware reset, the RESET pin should be held low for at least 100 nanoseconds. All internally generated clocks stop during reset. The rising edge of RESET resets the PLL clock multiplier and reinitializes the programmable registers to their default values. The same sequence as described in the Power-Up Sequence section should be followed after a reset or change in M. PWRDN 5MCLKMIN 20 NULL SYMBOLS DATA SYMBOLS 0 0 20 NULL SYMBOLS 0 0 0 TXIQ 0 0 0 TXSYNC Figure 6. Timing Sequence to Flush Tx Data Path Rev. A | Page 14 of 32 02773-006 AD9879 Σ-∆ OUTPUTS The AD9879 contains an on-chip Σ-Δ output that provides a digital logic bit stream with an average duty cycle that varies between 0% and (4095/4096)%, depending on the programmed code, as shown in Figure 7. This bit stream can be low-pass filtered to generate a programmable dc voltage of VDC = (Σ-Δ Code/4096)(VH) + VL where: VH = VDRVDD − 0.6 V VL = 0.4 V 8 tMCLK 4096 × 8 tMCLK In set-top box and cable modem applications, the output can be used to control external variable gain amplifiers or RF tuners. A simple single-pole RC low-pass filter provides sufficient filtering (see Figure 8). In more demanding applications where additional gain, level shift, or drive capability is required, a first or second order active filter might be considered for each Σ-Δ output (see Figure 9). (8) 0x000 0x001 0x002 0x800 0xFFF 8 tMCLK 4096 × 8 tMCLK 02773-007 AD9879 CONTROL WORD MCLK ÷8 12 DAC Σ-∆ R C DC (VL TO VH) Figure 7. Σ-∆ Output Signals Figure 8. Σ-∆ RC Filter C AD9879 Σ-∆ SIGMA-DELTA R VSD R1 R VOUT OP250 R VOUT = (VSD + VOFFSET) (1 + R/R1)/2 C VOFFSET 02773-009 TYPICAL: R = 50kΩ C = 0.1µF f–3dB = 1/(2πRC) = 318Hz Figure 9. Σ-∆ Active Filter with Gain and Offset Rev. A | Page 15 of 32 02773-008 TYPICAL: R = 50kΩ C = 0.1µF f–3dB = 1/(2πRC) = 318Hz AD9879 REGISTER MAP AND BIT DEFINITIONS Table 4. Register Map1 Address (hex) 0x00 0x01 0x02 Bit 7 SDIO Bidirectional PLL Lock Detect PowerDown PLL Bit 6 SPI Bytes LSB First Bit 5 RESET Bit 4 Bit 3 Bit 2 Bit 1 OSCIN Multiplier M[4:0] Bit 0 Default (hex) 0x08 0x00 PowerDown Reference IQ and IF10 ADC Flag 1 PowerDown IQ ADC 0x00 Type Read/Write Read/Write Read/Write MCLK/REFCLK Ratio R[5:0] PowerDown DAC Tx PowerDown Digital Tx PowerDown IF12 ADC Power-Down Reference IF12 ADC PowerDown IF10 ADC 0x03 0x04 0x05 0x06 0x07 0x08 Σ-∆ Output Control Word [3:0] Flag 0 0 0 Video Input Enable ADCs Clocked Direct from OSCIN Flag 0 Enable 0 0 0x00 0x00 0x00 0x00 0x00 0x80 Read/Write Read/Write Read/Write Read Only Read/Write Read/Write 0 0 0 0 0 0 Σ-∆ Output Control Word [11:4] 0 0 0 0 0 0 Clamp Level for Video Input [6:0] Enable 7-Bits IQ ADC 0 Send 12-Bit ADC Data Only 0 Rx Port Fast Edge Rate 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 1 Tx Frequency Tuning Word Profile 0 LSBs [1:0] 0 0 0 0 DAC Fine Gain Control [3:0] 0 0 0 Tx Path Tx Path Tx Path Tx Path Tx Path Spectral Transmit Select AD8322/ Bypass Inversion Single Profile 1 AD8327 Gain Sinc-1 Tone Control Mode Filter Tx Path Frequency Tuning Word Profile 0 [9:2] Tx Path Frequency Tuning Word Profile 0 [17:10] Tx Path Frequency Tuning Word Profile 0 [25:18] Cable Driver Amplifier Coarse Gain Control Profile 0 [7:4] Fine Gain Control Profile 0 [3:0] Tx Path Frequency Tuning Word Profile 1 [9:2] Tx Path Frequency Tuning Word Profile 1 [17:10] Tx Path Frequency Tuning Word Profile 1 [25:18] Cable Driver Amplifier Coarse Gain Control Profile 1 [7:4] Fine Gain Control Profile 1 [3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PowerDown RxSYNC and IQ ADC Clocks 0 0 0 0 0 Send 10-Bit ADC Data Only 0 0 0 0 0 0 Version [3:0] Tx Frequency Tuning Word Profile 1 LSBs [1:0] 0 0 0 0 0 0 0x00 0x00 0x00 0x05 0x00 Read/Write Read/Write Read/Write Read/Write Read/Write 0x00 0x00 Read/Write Read/Write 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Register bits denoted with 0 must be programmed with a 0 each time that register is written. Rev. A | Page 16 of 32 AD9879 REGISTER 0x00—INITIALIZATION Bits 0–4: OSCIN Multiplier This register field is used to program the on-chip multiplier (PLL) that generates the chip’s high frequency system clock fSYSCLK. The value of M depends on the ADC clocking mode selected, as shown in Table 5. Table 5. ADC Clock Select 1, fOSCIN 0, fMCLK (PLL Derived) M 8 16 REGISTER 0x02—POWER-DOWN Sections of the chip that are not used can be powered down when the corresponding bits are set high. This register has a default value of 0x00, with all sections active. Bit 0: Power-Down IQ ADC Active high powers down the IQ ADC. Bit 1: Power-Down IQ and IF10 ADC Reference Active high powers down the IQ and IF10 ADC reference. Bit 2: Power-Down IF10 ADC Active high powers down the IF10 ADC. When using the AD9879 in systems where the Tx path and Rx path do not operate simultaneously, the value of M can be programmed from 1 to 31. The maximum fSYSCLK rate of 236 MHz must be observed, whatever value is chosen for M. When M is set to 1, the internal PLL is disabled and all internal clocks are derived directly from OSCIN. Bit 3: Power-Down IF12 ADC Reference Active high powers down the 12-bit ADC reference. Bit 4: Power-Down IF12 ADC Active high powers down the IF12 ADC. Bit 5: RESET Writing a 1 to this bit resets the registers to their default values and restarts the chip. The RESET bit always reads back 0. The bits in Register 0x00 are not affected by this software reset. A low level at the RESET pin, however, would force all registers, including all bits in Register 0x00, to their default state. Bit 5: Power-Down Digital TX Active high powers down the digital transmit section of the chip, similar to the function of the PWRDN pin. Bit 6: Power-Down DAC TX Active high powers down the DAC. Bit 6: SPI Bytes LSB First Active high indicates SPI serial port access of instruction byte and data registers are least significant bit (LSB) first. Default low indicates most significant bit (MSB) first format. Bit 7: Power-Down PLL Active high powers down the OSCIN multiplier. REGISTERS 0x03–0x04—Σ-∆ AND FLAG CONTROL The Σ-Δ control word is 12 bits wide and split into MSB bits [11:4] and LSB bits [3:0]. Changes to the Σ-Δ control words take effect immediately for every MSB or LSB register write. Σ-Δ output control words have a default value of 0. The control words are in straight binary format with 0x000 corresponding to the bottom of the scale and 0xFFF corresponding to the top of the scale. See Figure 8 for details. If the flag enable (Register 0x03, Bit 0) is set high, the Σ-Δ_OUT pin maintains a fixed logic level determined directly by the MSB of the Σ-Δ control word. The FLAG1 pin assumes the logic level programmed into the FLAG1 bit (Register 0x03, Bit 1). Bit 7: SDIO Bidirectional Active high configures the serial port as a three-signal port with the SDIO pin used as a bidirectional input/output pin. Default low indicates the serial port uses four signals with SDIO configured as an input and SDO configured as an output. REGISTER 0x01—CLOCK CONFIGURATION Bits 0–5: MCLK/REFCLK Ratio This bit field defines R, the ratio between the auxiliary clock output, REFCLK and MCLK. R can be any integer number between 2 and 63. At default zero (R = 0), REFCLK provides a buffered version of the OSCIN clock signal. Bit 7: PLL Lock Detect When this bit is set low, the REFCLK pin functions in its default mode and provides an output clock with frequency fMCLK/R, as described above. If this bit is set to 1, the REFCLK pin is configured to indicate whether the PLL is locked to fOSCIN. In this mode, the REFCLK pin should be low-pass filtered with an RC filter of 1.0 kΩ and 0.1 µF. A low output on REFCLK indicates the PLL has achieved lock with fOSCIN. REGISTER 0x07—VIDEO INPUT CONFIGURATION Bits 0–6: Clamp Level Control Value The 7-bit clamp level control value is used to set an offset to the automatic clamp level control loop. The actual ADC output has a clamp level offset equal to 16 times the clamp level control value as shown: Clamp Level Offset = Clamp Level Control Value × 16 (9) Rev. A | Page 17 of 32 AD9879 The default value for the clamp level control value is 0x20. This results in an ADC output clamp level offset of 512 LSBs. The valid programming range for the clamp level control value is from 0x16 to 0x127. REGISTER 0x0E—DAC GAIN CONTROL Bits 0–3: DAC Fine Gain Control This bit field sets the DAC gain if the Tx Path AD8321/AD8323 gain control select bit (Register F, Bit 3) is set to 0. The DAC gain can be set from 0.0 dB to 7.5 dB in increments of 0.5 dB. Table 6 details the programming. Table 6. DAC Gain Control Bits [3:0] 0000 0001 0010 0011 .... 1110 1111 DAC Gain 0.0 dB (default) 0.5 dB 1.0 dB 1.5 dB .... 7.0 dB 7.5 dB REGISTER 0x08—ADC CLOCK CONFIGURATION Bit 0: Send 10-Bit ADC Data Only When this bit is set high, the device enters a nonmultiplexed mode and only the data from the 10-bit ADC is sent to the IF [11:0] digital output port. Bit 1: Send 12-Bit ADC Data Only When this bit is set high, the device enters a nonmultiplexed mode and only data from the 12-bit ADC is sent to the IF [11:0] digital output port. Bit 3: Enable 7-Bits, IQ ADC When this bit is active, the IQ ADC is put into 7-bit mode. In this mode, the full-scale input range is 2 Vppd. When this bit is set inactive, the IQ ADC is put into 6-bit mode and the fullscale input voltage range is 1 Vppd. REGISTER 0x0F—Tx PATH CONFIGURATION Bit 0: Single-Tone Tx Mode Active high configures the AD9879 for single-tone applications such as FSK. The AD9879 supplies a single frequency output as determined by the frequency tuning word selected by the active profile. In this mode, the TXIQ input data pins are ignored but should be tied to a valid logic voltage level. The default value is 0 (inactive). Bit 4: Power-Down RXSYNC and IQ ADC Clocks Setting this bit to 1 powers down the IQ ADC’s sampling clock and stops the RXSYNC output pin. It can be used for additional power saving on top of the power-down selections in Register 0x02. Bit 1: Spectral Inversion Tx When set to 1, inverted modulation is performed. MODULATOR_OUT = [I cos(ωt) + Q sin(ωt)] The default is logic low, noninverted modulation. MODULATOR_OUT = [I cos(ωt) + Q sin(ωt)] (11) (10) Bit 5: Rx Port Fast Edge Rate Setting this bit to 1 increases the output drive strength of all digital output pins, except MCLK, REFCLK, Σ-Δ_OUT, and FLAG1. These pins always have high output drive capability. Bit 7: ADC Clocked Direct from OSCIN When set high, the input clock at OSCIN is used directly as the ADC sampling clock. When set low, the internally generated master clock, MCLK, is divided by two and used as the ADC sampling clock. Best ADC performance is achieved when the ADCs are sampled directly from fOSCIN using an external crystal or low jitter crystal oscillator. Bit 2: Tx Path Bypass Sinc–1 Filter Setting this bit high bypasses the digital inverse sinc filter of the Tx path. Bit 3: Tx Path AD8322/AD8327 Gain Control Mode This bit changes the manner in which transmit gain control is performed. Typically either AD8321/AD8323 (default 0) or AD8222/AD8327 (default 1) variable gain cable drivers are programmed over the chip’s 3-wire CA interface. The Tx gain control select changes the interpretation of the bits in Registers 0x13 and 0x17. See the Cable Driver Gain Control section. REGISTER 0x0C—DIE REVISION Bits 0–3: Version The die version of the chip can be read from this register. REGISTER 0x0D—Tx FREQUENCY TUNING WORDS LSBs This register accommodates two LSBs for both frequency tuning words. For more information, see the description in the Registers 0X10–0X17—Carrier Frequency Tuning section. Rev. A | Page 18 of 32 AD9879 Bit 5: Tx Path Select Profile 1 The AD9879 quadrature digital upconverter is capable of storing two preconfigured modulation modes called profiles. Each profile defines a transmit frequency tuning word and cable driver amplifier gain (DAC gain) setting. The profile select bit or PROFILE pin programs the current register profile to be used. The profile select bit should always be 0 if the PROFILE pin is to be used to switch between profiles. Using the profile select bit as a means of switching between different profiles requires the PROFILE pin to be tied low. Table 7. Cable Driver Gain Control Bits [7:4] 0000 0001 ... 0111 1000 CA Interface Transmit Word 0000 0000 (default) 0000 0001 ... 0100 0000 1000 0000 In this mode, the lower bits determine the fine gain setting of the DAC output. Table 8. DAC Output Fine Gain Setting Bits [3:0] 0000 0001 ... 1110 1111 DAC Fine Gain 0.0 dB (default) 0.5 dB ... 7.0 dB 7.5 dB REGISTERS 0x10–0x17—CARRIER FREQUENCY TUNING Tx Path Frequency Tuning Words The frequency tuning word (FTW) determines the DDSgenerated carrier frequency (fC) and is formed via a concatenation of register addresses. The 26-bit FTW is spread over four register addresses. Bit 25 is the MSB and Bit 0 is the LSB. The carrier frequency equation is given as fc = [FTW × fSYSCLK]/226 where: fSYSCLK = M × fOSCIN. FTW < 0 × 2000000. Changes to FTW bytes take effect immediately. (12) New data is automatically sent over the 3-wire CA interface (and DAC gain adjust) whenever the value of the active gain control register changes or a new profile is selected. The default value is 0x00 (lowest gain). The formula for the combined output level calculation of the AD9879 fine gain and AD8327 or AD8322 coarse gain is V8327 = V9879(0) + (fine)/2 + 6(coarse) − 19 V8322 = V9879(0) + (fine)/2 + 6(coarse) − 14 where: fine is the decimal value of Bits [3:0]. coarse is the decimal value of Bits [7:8]. V9879(0) is level at AD9879 output in dBmV for fine = 0. V8327 is level at output of AD8327 in dBmV. V8322 is level at output of AD8322 in dBmV. (13) (14) Cable Driver Gain Control The AD9879 has a 3-pin interface to the AD832x family of programmable gain cable driver amplifiers. This allows direct control of the cable driver’s gain through the AD9879. In its default mode, the complete 8-bit register value is transmitted over the 3-wire cable amplifier (CA) interface. If Bit 3 of Register 0x0F is set high, Bits [7:4] determine the 8-bit word sent over the CA interface according to Table 7. Rev. A | Page 19 of 32 AD9879 SERIAL INTERFACE FOR REGISTER CONTROL The AD9879 serial port is a flexible, synchronous serial communication port that allows easy interface to many industry-standard microcontrollers and microprocessors. The interface allows read/write access to all registers that configure the AD9879. Single or multiple byte transfers are supported. Also, the interface can be programmed to read words either MSB first or LSB first. The serial interface port of the AD9879 I/O can be configured to have one bidirectional I/O (SDIO) pin or two unidirectional I/O (SDIO/SDO) pins. Table 10. Bit Decodes N1 0 0 1 1 N0 0 1 0 1 Description Transfer 1 byte Transfer 2 bytes Transfer 3 bytes Transfer 4 bytes GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to a communication cycle with the AD9879. Phase 1 is the instruction cycle, which is the writing of an instruction byte into the AD9879 that is coincident with the first eight SCLK rising edges. The instruction byte provides the AD9879 serial port controller with information regarding the data transfer cycle, which is Phase 2 of the communication cycle. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The first eight SCLK rising edges of each communication cycle are used to write the instruction byte into the AD9879. The eight remaining SCLK edges are for Phase 2 of the communication cycle. Phase 2 is the actual data transfer between the AD9879 and the system controller. Phase 2 of the communication cycle is a transfer of 1 to 4 data bytes as determined by the instruction byte. Normally, using one multibyte transfer is the preferred method. However, single byte data transfers are useful to reduce CPU overhead when register access requires one byte only. Registers change immediately upon writing to the last bit of each transfer byte. The Bits A4:A0 determine which register is accessed during the data transfer portion of the communication cycle. For multibyte transfers, this address is the starting byte address. The remaining register addresses are generated by the AD9879. SERIAL INTERFACE PORT PIN DESCRIPTION SCLK—Serial Clock The serial clock pin is used to synchronize data transfers from the AD9879 and to run the serial port state machine. The maximum SCLK frequency is 15 MHz. Input data to the AD9879 is sampled upon the rising edge of SCLK. Output data changes upon the falling edge of SCLK. CS—Chip Select Active low input starts and gates a communication cycle. It allows multiple devices to share a common serial port bus. The SDO and SDIO pins go to a high impedance state when CS is high. Chip select should stay low during the entire communication cycle. SDIO—Serial Data I/O Data is always written into the AD9879 on this pin. However, this pin can be used as a bidirectional data line. The configuration of this pin is controlled by Bit 7 of Register 0x00. The default is Logic 0, which configures the SDIO pin as unidirectional. INSTRUCTION BYTE Table 9 illustrates the information contained in the instruction byte. Table 9. Instruction Byte Information MSB I7 R/W I6 N1 I5 N0 I4 A4 I3 A3 I2 A2 I1 A1 LSB I0 A0 SDO—Serial Data Out Data is read from this pin for protocols that use separate lines for transmitting and receiving data. When the AD9879 operates in a single bidirectional I/O mode, this pin does not output data and is set to a high impedance state. MSB/LSB TRANSFERS The AD9879 serial port can support both MSB first or LSB first data formats. This functionality is controlled by the LSB-first bit in Register 0x00. The default is MSB first. When this bit is set active high, the AD9879 serial port is in LSB-first format. In LSB-first mode, the instruction byte and data bytes must be written from the LSB to the MSB. In LSBfirst mode, the serial port internal byte address generator increments for each byte of the multibyte communication cycle. The R/W bit of the instruction byte determines whether a read or a write data transfer will occur after the instruction byte write. Logic high indicates a read operation. Logic low indicates a write operation. The N1:N0 bits determine the number of bytes to be transferred during the data transfer cycle. The bit decodes are shown in Table 10. Rev. A | Page 20 of 32 AD9879 When this bit is set default low, the AD9879 serial port is in MSB-first format. In MSB-first mode, the instruction byte and data bytes must be written from the MSB to the LSB. In MSBfirst mode, the serial port internal byte address generator decrements for each byte of the multibyte communication cycle. When incrementing from 0x1F, the address generator changes to 0x00. When decrementing from 0x00, the address generator changes to 0x1F. The same considerations apply to setting the reset bit in Register 0x00. All other registers are set to their default values, but the software reset does not affect the bits in Register 0x00. It is recommended to use only single-byte transfers when changing serial port configurations or initiating a software reset. A write to Bits 1, 2, and 3 of Register 0x00 with the same logic levels as Bits 7, 6, and 5 (bit pattern: XY1001YX binar y) allows the user to reprogram a lost serial port configuration and to reset the registers to their default values. A second write to Register 0x00 with the reset bit low and the serial port configuration as specified above (XY) reprograms the OSCIN multiplier setting. A changed fSYSCLK frequency is stable after a maximum of 200 fMCLK cycles (wake-up time). NOTES ON SERIAL PORT OPERATION The AD9879 serial port configuration bits reside in Bits 6 and 7 of Register 0x00. It is important to note that the configuration changes immediately upon writing to the last bit of the register. For multibyte transfers, writing to this register may occur during the middle of the communication cycle. Care must be taken to compensate for this new configuration for the remaining bytes of the current communication cycle. tDS CS SCLK INSTRUCTION CYCLE DATA TRANSFER CYCLE CS tSCLK tPWH tPWL SCLK 02773-010 SDIO SDO R/W N1 N0 A4 A3 A2 A1 D7n D6n D20 D10 D00 SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 10. Serial Register Interface Timing MSB First Figure 12. Timing Diagram for Register Write to AD9879 CS SCLK SDIO SDO A0 INSTRUCTION CYCLE DATA TRANSFER CYCLE CS SCLK 02773-011 02773-013 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D00 D10 D20 D6n D7n D6n D7n tDV SDIO SDO DATA BIT N DATA BIT N – 1 Figure 11. Serial Register Interface Timing LSB First Figure 13. Timing Diagram for Register Read Rev. A | Page 21 of 32 02773-012 A0 D7n D6n D20 D10 D00 tDS tDH AD9879 TRANSMIT PATH (TX) tSU MCLK tHD TXSYNC TXIQ TXI[11:6] TXI[5:0] TXQ[11:6] TXQ[5:0] TXI[11:6] TXI[5:0] TXQ[11:6] TXQ[5:0] TXI[11:6] TXI[5:0] Figure 14. Transmit Path Timing TRANSMIT TIMING The AD9879 provides a master clock, MCLK, and expects 6-bit multiplexed TxIQ data upon each rising edge. Transmit symbols are framed with the TxSYNC input. TxSYNC high indicates the start of a transmit symbol. Four consecutive 6-bit data packages form a symbol (I MSB, I LSB, Q MSB, and Q LSB). CASCADED INTEGRATOR-COMB (CIC) FILTER The CIC filter is configured as a programmable interpolator and provides a sample rate increase by a factor of 4. The frequency response of the CIC filter is given by DATA ASSEMBLER The input data stream is representative complex data. Two 6-bit words form a 12-bit symbol component (in twos complement format). Four input samples are required to produce one I/Q data pair. The I/Q sample rate, fIQCLK, at the input to the first half-band filter is a quarter of the input data rate, fMCLK. The I/Q sample rate, fIQCLK, puts a bandwidth limit on the maximum transmit spectrum. This is the familiar Nyquist limit and is equal to one-half fIQCLK, hereafter referred to as fNYQ. ⎡ 1 1 − e − j (2πf ( 4 ) ) ⎤ ⎡⎛ 1 ⎞ sin(4πf ) ⎤ H(f) = ⎢⎛ ⎞ = ⎢⎜ ⎟ ⎜⎟ ⎥ j( 2πf) ⎥ ⎣⎝ 4 ⎠ 1 − e ⎦ ⎣⎝ 4 ⎠ sin(πf ) ⎦ 3 02773-014 3 (15) The frequency response in this form has f scaled to the output sample rate of the CIC filter. That is, f = 1 corresponds to the frequency of the output sample rate of the CIC filter. H(f/R) yields the frequency response with respect to the input sample of the CIC filter. COMBINED FILTER RESPONSE The combined frequency response of HBF 1, HBF 2, and CIC puts a limit on the input signal bandwidth that can be propagated through the AD9879. The usable bandwidth of the filter chain puts a limit on the maximum data rate that can be propagated through the AD9879. A look at the pass-band detail of the combined filter response (Figure 15 and Figure 16) indicates that to maintain an amplitude error of no more than 1 dB, signals are restricted to a bandwidth of no more than approximately 60% of fNYQ. HALF-BAND FILTERS (HBFs) HBF 1 and HBF 2 are both interpolating filters, each of which doubles the sampling rate. Together, HBF 1 and HBF 2 have 26 taps and provide a factor-of-four increase in the sampling rate (4 × fIQCLK or 8 × fNYQ). In relation to phase response, both HBFs are linear phase filters. As such, virtually no phase distortion is introduced within the pass band of the filters. This is an important feature, because phase distortion is generally intolerable in a data transmission system. Rev. A | Page 22 of 32 AD9879 1 1 0 –1 0 –1 MAGNITUDE (dB) –2 MAGNITUDE (dB) 02773-015 –2 –3 –3 –4 –5 –6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY RELATIVE TO I/Q NYQUIST BW –4 –5 –6 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 FREQUENCY RELATIVE TO I/Q NYQUIST BW 1.0 1.0 Figure 15. Cascaded Filter Pass-Band Detail (N = 4) Figure 16. Cascaded Filter Pass-Band Detail (N = 3) To keep the bandwidth of the data in the flat portion of the filter pass band, the user must oversample the baseband data by at least a factor of two prior to representing it to the AD9879. Without oversampling, the Nyquist bandwidth of the baseband data corresponds to the fNYQ. Consequently, the upper end of the data bandwidth suffers 6 dB or more of attenuation due to the frequency response of the digital filters. There is an additional concern if the baseband data applied to the AD9879 has been pulse shaped. Typically, pulse shaping is applied to the baseband data via a filter having a raised cosine response. In such cases, an α value is used to modify the bandwidth of the data where the value of α is such that 0 < α < 1. A value of 0 causes the data bandwidth to correspond to the Nyquist bandwidth. A value of 1 causes the data bandwidth to be extended to twice the Nyquist bandwidth. Thus, with 2× oversampling of the baseband data and α =1, the Nyquist bandwidth of the data corresponds with the I/Q Nyquist bandwidth. As stated earlier, this results in problems near the upper edge of the data bandwidth due to the frequency response of the filters. The maximum value of α that can be implemented is 0.45. This is because the data bandwidth becomes: 1 (1 + α ) f NYQ = 0.725 f NYQ 2 02773-016 (16) which puts the data bandwidth at the extreme edge of the flat portion of the filter response. If a particular application requires an α value between 0.45 and 1, then the user must oversample the baseband data by at least a factor of four. The combined HBF1, HBF2, and CIC filter introduces a worst-case droop of less than 0.2 dB over the frequency range of the data to be transmitted. Rev. A | Page 23 of 32 AD9879 Tx SIGNAL LEVEL CONSIDERATIONS The quadrature modulator introduces a maximum gain of 3 dB in signal level. To visualize this, assume that both the I data and Q data are fixed at the maximum possible digital value, x. The output of the modulator, z is then: z = [x cos(ωt) – x sin(ωt)] (17) The following example assumes a PK/rms level of 10 dB: Maximum Symbol Component Input Value = ±(2,047 LSBs − 0.2 dB) = ±2,000 LSBs Maximum Complex Input RMS Value = 2,000 LSBs + 6 dB − Pk/rms (dB) = 1,265 LSBs rms (20) (21) O The maximum complex input rms value calculation uses both I and Q symbol components that add a factor of 2 (6 dB) to the formula. Z X I 02773-017 X Table 11 shows typical I-Q input test signals with amplitude levels related to 12-bit full scale (FS). Tx THROUGHPUT AND LATENCY Data inputs impact the output fairly quickly but remain effective due to the filter characteristics of the AD9879. Data transmit latency through the AD9879 is easiest to describe in terms of fSYSCLK clock cycles (4 fMCLK). The numbers quoted are when an effect is first seen after an input value changes. Latency of I/Q data entering the data assembler (AD9879 input) to the DAC output is 119 fSYSCLK clock cycles (29.75 fMCLK cycles). DC values applied to the data assembler input takes up to 176 fSYSCLK clock cycles (44 fMCLK cycles) to propagate and settle at the DAC output. Frequency hopping is accomplished via changing the PROFILE input pin. The time required to switch from one frequency to another is less than 232 fSYSCLK cycles (58.5 fMCLK cycles). Figure 17. 16-Quadrature Modulation It can be shown that |z| assumes a maximum value of z= (x 2 + x 2 ) = x 2 (a gain of + 3 dB) (18) However, if the same number of bits are used to represent the |z| values, as is used to represent the x values, an overflow occurs. To prevent this possibility, an effective −3 dB attenuation is internally implemented on the I and Q data path. (z = (1/ 2 + 1/ 2 ) = x ) (19) AD9879 DAC AD832x LOW-PASS FILTER TX CA 75Ω 3 CA_EN CA_DATA CA_CLK VARIABLE GAIN CABLE DRIVER AMPLIFIER Figure 18. 16-Quadrature Modulation Table 11. I–Q Input Test Signals Analog Output Single Tone (fC – f) Single Tone (fC + f) Dual Tone (fC ± f) Digital Input I = cos(f) Q = cos(f + 90°) = −sin(f) I = cos(f) Q = cos(f + 270°) = +sin(f) I = cos(f) Q = cos(f + 180°) = −cos(f) or Q = +cos(f) Input Level FS – 0.2 dB FS – 0.2 dB FS – 0.2 dB FS – 0.2 dB FS – 0.2 dB FS – 0.2 dB Modulator Output Level FS – 3.0 dB FS – 3.0 dB FS 02773-018 Rev. A | Page 24 of 32 AD9879 DIGITAL-TO-ANALOG CONVERTER A 12-bit digital-to-analog converter (DAC) is used to convert the digitally processed waveform into an analog signal. The worst-case spurious signals due to the DAC are the harmonics of the fundamental signal and their aliases. The conversion process produces aliased components of the fundamental signal at n × fSYSCLK ± fCARRIER (n = 1, 2, 3). These are typically filtered with an external RLC filter at the DAC output. It is important for this analog filter to have a sufficiently flat gain and linear phase response across the bandwidth of interest to avoid modulation impairments. A relatively inexpensive seventhorder elliptical low-pass filter is sufficient to suppress the aliased components for HFC network applications. The AD9879 provides true and complement current outputs. The full-scale output current is set by the RSET resistor at Pin 49 and the DAC gain register. Assuming maximum DAC gain, the value of RSET for a particular full-scale IOUT is determined using the following equation: RSET = 32 VDACRSET/IOUT = 39.4/IOUT (22) The load can be a simple resistor to ground, an op amp currentto-voltage converter, or a transformer-coupled circuit. It is best not to attempt to directly drive highly reactive loads (such as an LC filter). Driving an LC filter without a transformer requires the filter to be doubly terminated for best performance. The filter input and output should both be resistively terminated with the appropriate values. The parallel combination of the two terminations determines the load the AD9879 sees for signals within the filter pass band. For example, a 50 Ω terminated input/output low-pass filter looks like a 25 Ω load to the AD9879. The output compliance voltage of the AD9879 is −0.5 V to +1.5 V. To avoid signal distortion, any signal developed at the DAC output should not exceed +1.5 V. Furthermore, the signal may extend below ground as much as 0.5 V without damage or signal distortion. The AD9879 true and complement outputs can be differentially combined for common-mode rejection using a broadband 1:1 transformer. Using a grounded center tap results in signals at the AD9879 DAC output pins that are symmetrical about ground. As previously mentioned, by differentially combining the two signals, the user can provide some degree of commonmode signal rejection. A differential combiner might consist of a transformer or an operational amplifier. The object is to combine or amplify only the difference between two signals and to reject any common, usually undesirable, characteristic, such as 60 Hz hum or clock feedthrough that is equally present on both individual signals. Connecting the AD9879 true and complement outputs to the differential inputs of the gain programmable cable drivers AD8321/AD8323 or AD8322/AD8327 provides an optimized solution for the standard compliant cable modem upstream channel. The cable driver’s gain can be programmed through a direct 3-wire interface using the profile registers of the AD9879. For example, if a full-scale output current of 20 mA is desired, then RSET = (39.4/0.02) Ω, or approximately 2 kΩ. The following equation calculates the full-scale output current including the programmable DAC gain control. IOUT = [39.4/RSET] × 10(−7.5 + 0.5 NGAIN)/20 where NGAIN is the value of DAC fine gain control [3:0]. The full-scale output current range of the AD9879 is 4 mA to 20 mA. Full-scale output currents outside of this range degrade SFDR performance. SFDR is also slightly affected by output matching; the two outputs should be terminated equally for best SFDR performance. The output load should be located as close as possible to the AD9879 package to minimize stray capacitance and inductance. AD9879 DAC TX CA LOW-PASS FILTER 3 CA_EN CA_DATA CA_CLK (23) AD832x 8 tMCLK 4 tMCLK 8 tMCLK 4 tMCLK 8 tMCLK 75Ω CA_EN 02773-019 CA_CLK CA_DATA MSB LSB 02773-020 VARIABLE GAIN CABLE DRIVER AMPLIFIER Figure 19. Cable Amplifier Connection Figure 20. Cable Amplifier Interface Timing Rev. A | Page 25 of 32 AD9879 PROGRAMMING THE AD8321/AD8323 OR AD8322/AD8327 CABLE DRIVER AMPLIFIER GAIN CONTROL Programming the gain of the AD832x family of cable driver amplifiers can be accomplished via the AD9879 cable amplifier control interface. Four 8-bit registers within the AD9879 (one per profile) store the gain value to be written to the serial 3-wire port. Typically, either the AD8321/AD8323 or AD8322/AD8327 variable gain cable amplifiers are connected to the chip’s 3-wire cable amplifier interface. The Tx gain control select bit in Register 0x0F changes the interpretation of the bits in Registers 0x13, 0x17, 0x1B, and 0x1F. See the Cable Driver Gain Control section register description. Data transfers to the gain programmable cable driver amplifier are initiated by the following four conditions. 1. Power-Up and Hardware Reset—Upon initial power-up and every hardware reset, the AD9879 clears the contents of the gain control registers to 0, which defines the lowest gain setting of the AD832x. Thus, the AD9879 writes all 0s out of the 3-wire cable amplifier control interface. Software Reset—Writing a 1 to Bit 5 of Address 0x00 initiates a software reset. Upon a software reset, the AD9879 clears the contents of the gain control registers to 0 for the lowest gain and sets the profile select to 0. The AD9879 writes all 0s out of the 3-wire cable amplifier control interface if the gain was previously on a different setting (other than 0). 3. Change in Profile Selection—The AD9879 samples the PROFILE input pin together with the two profile select bits and writes to the AD832x gain control registers when a change in profile and gain is determined. The data written to the cable driver amplifier comes from the AD9879 gain control register associated with the current profile. Write to AD9879 Cable Driver Amplifier Control Registers—The AD9879 writes gain control data associated with the current profile to the AD832x whenever the selected AD9879 cable driver amplifier gain setting is changed. 4. Once a new stable gain value is detected (48 MCLK to 64 MCLK cycles after initiation), a data write starts with CA_EN going low. The AD9879 always finishes a write sequence to the cable driver amplifier once it is started. The logic controlling data transfers to the cable driver amplifier uses up to 200 MCLK cycles and is designed to prevent erroneous write cycles from occurring. 2. Rev. A | Page 26 of 32 AD9879 RECEIVE PATH (Rx) IF10 AND IF12 ADC OPERATION The IF10 and IF12 ADCs have a common architecture and share many of the same characteristics from an applications standpoint. Most of the information in this section is applicable to both IF ADCs. Differences, where they exist, are highlighted. signal should be biased to a dc level equal to the midpoint of the ADC reference voltages, REFT12 and REFB12. Nominally, this level is 1.2 V. When ac-coupled, the ADC inputs self bias to this voltage and require no additional input circuitr y. Figure 23 illustrates a recommended circuit that eases the burden on the signal source by isolating its output from the ADC input. The 33 Ω series termination resistors isolate the amplifier outputs from any capacitive load, which typically improves settling time. The series capacitors provide ac signal coupling which ensures the ADC inputs operate at the optimal dc bias voltage. The shunt capacitor sources the dynamic currents required to charge the SHA input capacitors, removing this requirement from the ADC buffer. The values of CC and CS should be calculated to get the correct HPF and LPF corner frequencies. tEE REFCLK M=8 INPUT SIGNAL RANGE AND DIGITAL OUTPUT CODES The IF ADCs have differential analog inputs labeled IF+ and IF−. The signal input, VAIN, is the voltage difference between the two input pins, VAIN = VIF+ – VIF−. The full-scale input voltage range is determined by the internal reference voltages, REFT and REFB, which define the top and bottom of the scale. The peak input voltage to the ADC is the difference between REFT and REFB, which is 1 Vppd. This results in the ADC full-scale input voltage range of 2 Vppd. The digital output code is straight binar y and is illustrated in Table 12. Table 12. Digital Output Codes IF[11:0] 111...111 111...111 111...110 ... 100...001 100...000 011...111 ... 000...001 000...000 000...000 Input Signal Voltage VAIN ≥ +1.0 V VAIN = +1.0 – 1 LSB V VAIN = +1.0 – 2 LSB V VAIN = +1 LSB V VAIN = 0.0 V VAIN = −1 LSB V VAIN = −1.0 + 2 LSB V VAIN = −1.0 V VAIN < −1.0 V tOD tMD MCLK RXIQ DATA I[7:4] I[3:0] Q[7:4] Q[3:0] I[7:4] I[3:0] RXSYNC 02773-021 02773-022 IF DATA IF10 IF12 IF10 IF12 IF10 IF12 Figure 21. Rx Port Timing (Default Mode: Multiplexed IF ADC Data) tEE REFCLK M=8 The IF10 ADC digital output code occupies the 10 MSBs of the Rx digital output port (IF[11:2]). The output codes clamp to the top or the bottom of the scale when the inputs are overdriven. tOD tMD MCLK DRIVING THE INPUTS The IF ADCs have differential switched capacitor sample-andhold amplifier (SHA) inputs. The nominal differential input impedance is 4.0 kΩ||3 pF. This impedance can be used as the effective termination impedance when calculating filter transfer characteristics and voltage signal attenuation from non-zero source impedances. It should be noted, however, that for best performance, additional requirements must be met by the signal source. The SHA has input capacitors that must be recharged each time the input is sampled. This results in a dynamic input current at the device input. This demands that the source has low (