AD9895KBCZRL

a CCD Signal Processors with Precision Timing™ Generator AD9891/AD9895 FEATURES AD9891: 10-Bit 20 MHz Version AD9895: 12-Bit 30 MHz Version Correlated Double Sampler (CDS) 4
6 dB Pixel Gain Amplifier ( PxGA®) 2 dB to 36 dB 10-Bit Variable Gain Amplifier (VGA) 10-Bit 20 MHz A/D Converter (AD9891) 12-Bit 30 MHz A/D Converter (AD9895) Black Level Clamp with Variable Level Control Complete On-Chip Timing Generator Precision Timing Core with 1 ns Resolution On-Chip 5 V Horizontal and RG Drivers 2-Phase and 4-Phase H-Clock Modes 4-Phase Vertical Transfer Clocks Electronic and Mechanical Shutter Modes On-Chip Driver for External Crystal On-Chip Sync Generator with External Sync Option 64-Lead CSPBGA Package PRODUCT DESCRIPTION The AD9891 and AD9895 are highly integrated CCD signal processors for digital still camera applications. Both include a complete analog front end with A/D conversion combined with a full-function programmable timing generator. A Precision Timing core allows adjustment of high speed clocks with 1 ns resolution at 20 MHz operation and 700 ps resolution at 30 MHz operation. The AD9891 is specified at pixel rates of up to 20 MHz, and the AD9895 is specified at 30 MHz. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 10-Bit or 12-Bit A/D converter. The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. Operation is programmed using a 3-wire serial interface. Packaged in a space-saving 64-lead CSPBGA, the AD9891 and AD9895 are specified over an operating temperature range of –20°C to +85°C. APPLICATIONS Digital Still Cameras Digital Video Camcorders Industrial Imaging FUNCTIONAL BLOCK DIAGRAM VRT VRB AD9891/AD9895 4dB
6dB CDS CCDIN PxGA 2dB TO 36dB VREF 10 OR 12 ADC VGA CLAMP DOUT CLAMP DCLK INTERNAL CLOCKS CLPOB/PBLK RG 4 HORIZONTAL DRIVERS FD/LD PRECISION TIMING GENERATOR MSHUT STROBE H1–H4 CLO 4 V1–V4 8 V-H CONTROL SYNC GENERATOR INTERNAL REGISTERS VSG1–VSG8 VSUB SUBCK HD VD SYNC CLI SL SCK DATA PxGA is a registered trademark and Precision Timing is a trademark of Analog Devices, Inc. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD9891/AD9895 TABLE OF CONTENTS SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 DIGITAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . 3 AD9891 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . 4 AD9895 ANALOG SPECIFICATIONS . . . . . . . . . . . . . . 5 TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . 6 PACKAGE THERMAL CHARACTERISTICS . . . . . . . . 6 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6 ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PIN CONFIGURATION-AD9891 . . . . . . . . . . . . . . . . . . . 7 PIN FUNCTION DESCRIPTIONS-AD9891 . . . . . . . . . . . 7 PIN CONFIGURATION-AD9895 . . . . . . . . . . . . . . . . . . . 8 PIN FUNCTION DESCRIPTIONS-AD9895 . . . . . . . . . . . 8 SPECIFICATION DEFINITIONS . . . . . . . . . . . . . . . . . . . 9 EQUIVALENT CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . 9 TYPICAL PERFORMANCE CHARACTERISTICS . . . . 10 SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical System Block Diagram . . . . . . . . . . . . . . . . . . . . 11 PRECISION TIMING HIGH SPEED TIMING GENERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timing Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 High Speed Clock Programmability . . . . . . . . . . . . . . . . . .12 H-Driver and RG Outputs . . . . . . . . . . . . . . . . . . . . . . . . .13 Digital Data Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 HORIZONTAL CLAMPING AND BLANKING . . . . . . . . 15 Individual CLPOB, CLPDM, and PBLK Sequences . . . . . 15 Individual HBLK Sequences . . . . . . . . . . . . . . . . . . . . . . .15 Horizontal Sequence Control . . . . . . . . . . . . . . . . . . . . . . .15 VERTICAL TIMING GENERATION . . . . . . . . . . . . . . . .17 Individual Vertical Sequences . . . . . . . . . . . . . . . . . . . . . .18 Individual Vertical Regions . . . . . . . . . . . . . . . . . . . . . . . .19 Complete Field: Combining the Regions . . . . . . . . . . . . . . 20 Vertical Sequence Alteration . . . . . . . . . . . . . . . . . . . . . . .21 Second Vertical Sequence During VSG Lines . . . . . . . . . . 22 Vertical Sweep Mode Operation . . . . . . . . . . . . . . . . . . . .22 Vertical Multiplier Mode . . . . . . . . . . . . . . . . . . . . . . . . . .24 Frame Transfer CCD Mode . . . . . . . . . . . . . . . . . . . . . . 24 Vertical Sensor Gate (Shift Gate) Timing . . . . . . . . . . . . .25 SHUTTER TIMING CONTROL . . . . . . . . . . . . . . . . . . . .26 Normal Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 High Precision Shutter Mode . . . . . . . . . . . . . . . . . . . . . . .26 Low Speed Shutter Mode . . . . . . . . . . . . . . . . . . . . . . . . .26 SUBCK Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Readout After Exposure . . . . . . . . . . . . . . . . . . . . . . . . . . .27 VSUB Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 MSHUT and STROBE Control . . . . . . . . . . . . . . . . . . . .27 Example of Exposure and Readout of Interlaced Frame . . .29 ANALOG FRONT END DESCRIPTION AND OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC Restore . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Correlated Double Sampler . . . . . . . . . . . . . . . . . . . . . . . 30 Input Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PxGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 PxGA Color Steering Mode Timing . . . . . . . . . . . . . . . . 31 Variable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PxGA and VGA Gain Curves . . . . . . . . . . . . . . . . . . . . . 33 Optical Black Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 POWER-UP AND SYNCHRONIZATION . . . . . . . . . . . . 34 Recommended Power-Up Sequence for Master Mode . . . .34 SYNC During Master Mode Operation . . . . . . . . . . . . . . .35 Synchronization in Slave Mode . . . . . . . . . . . . . . . . . . . . .35 POWER-DOWN MODE OPERATION . . . . . . . . . . . . . . 35 HORIZONTAL TIMING SEQUENCE EXAMPLE . . . . . 37 VERTICAL TIMING EXAMPLE . . . . . . . . . . . . . . . . . . . 39 CIRCUIT LAYOUT INFORMATION . . . . . . . . . . . . . . . .40 SERIAL INTERFACE TIMING . . . . . . . . . . . . . . . . . . . . .41 Notes About Accessing a Double-Wide Register . . . . . . . 41 NOTES ON REGISTER LISTING . . . . . . . . . . . . . . . . . . 42 COMPLETE REGISTER LISTING . . . . . . . . . . . . . . . . . 43 OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 57 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 –2– REV. A AD9891/AD9895–SPECIFICATIONS Parameter Min TEMPERATURE RANGE Operating Storage –20 –65 POWER SUPPLY VOLTAGE AVDD1, AVDD2 (AFE Analog Supply) TCVDD (Timing Core Analog Supply) RGVDD (RG Driver) HVDD (H1–H4 Drivers) DRVDD (Data Output Drivers) DVDD (Digital) 2.7 2.7 3.0 3.0 2.7 2.7 Typ 3.0 3.0 5.0 5.0 3.0 3.0 Max Unit +85 +150 °C °C 3.6 3.6 5.25 5.25 3.6 3.6 V V V V V V POWER DISSIPATION–AD9891 (See TPC 1 for Power Curves) 20 MHz, Typ Supply Levels, 100 pF H1–H4 Loading Power from HVDD Only* Power-Down 1 Mode Power-Down 2 Mode Power-Down 3 Mode 380 220 42 8 2.5 mW mW mW mW mW POWER DISSIPATION–AD9895 (See TPC 4 for Power Curves) 30 MHz, Typ Supply Levels, 100 pF H1–H4 Loading Power from HVDD Only* Power-Down 1 Mode Power-Down 2 Mode Power-Down 3 Mode 600 320 138 22 2.5 mW mW mW mW mW MAXIMUM CLOCK RATE (CLI) AD9891 AD9895 * 20 30 MHz MHz The total power dissipated by the HVDD supply may be approximated using the equation: Total HVDD Power = [CLOAD
HVDD
Pixel Frequency]
HVDD
Number of H-Outputs Used Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation. Actual HVDD power may be slightly higher than the calculated value because of stray capacitance inherent in the PCB layout/routing. Specifications subject to change without notice. DIGITAL SPECIFICATIONS (RGVDD = HVDD = 4.75 V to 5.25 V, DVDD = DRVDD = 2.7 V to 3.5 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted.) Parameter Symbol Min LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance VIH VIL IIH IIL CIN 2.1 LOGIC OUTPUTS (Except H and RG) High Level Output Voltage @ IOH = 2 mA Low Level Output Voltage @ IOL = 2 mA VOH VOL 2.2 VOH VOL VDD – 0.5 RG and H-DRIVER OUTPUTS (H1–H4) High Level Output Voltage @ Max Current Low Level Output Voltage @ Max Current Maximum Output Current (Programmable) Maximum Load Capacitance (for Each Output) REV. A –3– Max 0.6 10 10 10 0.5 0.5 24 100 Specifications subject to change without notice. Typ Unit V V µA µA pF V V V V mA pF AD9891/AD9895 AD9891–ANALOG SPECIFICATIONS Parameter Min CDS Gain Allowable CCD Reset Transient Max Input Range before Saturation Max CCD Black Pixel Amplitude PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (PxGA Code 32) Med Gain (PxGA Code 0) Max Gain (PxGA Code 31) VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (VGA Code 70) Max Gain (VGA Code 1023) * Max Unit dB mV V p-p mV 1.0 ± 200 1.0 1.6 Notes Input signal characteristics* V p-p V p-p Steps 64 Guaranteed –2.5 +3.5 +9.5 dB dB dB 1.6 2.0 Default setting V p-p V p-p Steps 1024 Guaranteed 2 36 dB dB 256 Steps 0 63.75 LSB LSB Measured at ADC output 10 ± 0.4 Guaranteed 2.0 VOLTAGE REFERENCE Reference Top Voltage (VRT) Reference Bottom Voltage (VRB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code 70) Max Gain (VGA Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Typ 0 500 BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level Max Clamp Level A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage (AVDD1, AVDD2 = 3.0 V, fCLI = 20 MHz, TMIN to TMAX, unless otherwise noted.) ± 1.0 V 2.0 1.0 5 38.5 Bits LSB V V 6 39.5 0.2 0.6 40 7 40.5 dB dB % LSB rms dB Includes entire signal chain Includes 4 dB default PxGA gain Gain = (0.035
Code) + 3.55 dB 12 dB gain applied AC grounded input, 6 dB gain applied Measured with step change on supply Input signal characteristics defined as follows: 500mV TYP RESET TRANSIENT 200mV MAX OPTICAL BLACK PIXEL 1V MAX INPUT SIGNAL RANGE Specifications subject to change without notice. –4– REV. A AD9891/AD9895 AD9895–ANALOG SPECIFICATIONS Parameter Min CDS Gain Allowable CCD Reset Transient Max Input Range before Saturation Max CCD Black Pixel Amplitude PIXEL GAIN AMPLIFIER (PxGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (PxGA Code 32) Med Gain (PxGA Code 0) Max Gain (PxGA Code 31) VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Low Gain (VGA Code 70) Max Gain (VGA Code 1023) * Max ± 200 1.0 1.6 –2.5 +3.5 +9.5 dB dB dB 1.6 2.0 Input signal characteristics* Default setting V p-p V p-p Steps 1024 Guaranteed 2 36 dB dB 256 Steps 0 255 LSB LSB Measured at ADC output 12 ± 0.5 Guaranteed 2.0 ± 1.0 5 38.5 Bits LSB V 2.0 1.0 V V 6 39.5 0.2 0.8 40 7 40.5 500mV TYP RESET TRANSIENT 1V MAX INPUT SIGNAL RANGE Specifications subject to change without notice. REV. A Notes V p-p V p-p Steps 64 Guaranteed Input signal characteristics defined as follows: 200mV MAX OPTICAL BLACK PIXEL Unit dB mV V p-p mV 1.0 VOLTAGE REFERENCE Reference Top Voltage (VRT) Reference Bottom Voltage (VRB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code 70) Max Gain (VGA Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Typ 0 500 BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level Max Clamp Level A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage (AVDD1, AVDD2 = 3.0 V, fCLI = 30 MHz, TMIN to TMAX, unless otherwise noted.) –5– dB dB % LSB rms dB Includes entire signal chain Includes 4 dB default PxGA gain Gain = (0.035
Code) + 3.55 dB 12 dB gain applied AC grounded input, 6 dB gain applied Measured with step change on supply AD9891/AD9895 TIMING SPECIFICATIONS (CL = 20 pF, AVDD = DVDD = DRVDD = 3.0 V, fCLI = 20 MHz [AD9891] or 30 MHz [AD9895], unless otherwise noted.) Parameter Symbol MASTER CLOCK, CLI (Figure 7) CLI Clock Period, AD9891 CLI High/Low Pulsewidth, AD9891 CLI Clock Period, AD9895 CLI High/Low Pulsewidth, AD9895 Delay from CLI Rising Edge to Internal Pixel Position 0 Min 50 20 33.3 13 tCONV tCONV AFE SAMPLE LOCATION1 (Figure 10) SHP Sample Edge to SHD Sample Edge, AD9891 SHP Sample Edge to SHD Sample Edge, AD9895 DATA OUTPUTS (Figure 12) Output Delay from DCLK Rising Edge1 Pipeline Delay from SHP/SHD Sampling SERIAL INTERFACE (Figures 52 and 53) Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read tS1 tS1 Max Unit 16.7 6 ns ns ns ns ns 4 2 10 20 Pixels Pixels 20 13 25 16.7 ns ns 8 9 ns Cycles tCLIDLY AFE CLAMP PULSES1 (Figure 13) CLPDM Pulsewidth CLPOB Pulsewidth2 Typ tOD 25 10 10 10 10 10 10 fSCLK tLS tLH tDS tDH tDV MHz ns ns ns ns ns NOTES 1 Parameter is programmable. 2 Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance. ABSOLUTE MAXIMUM RATINGS Parameter AVDD1, AVDD2 TCVDD HVDD RGVDD DVDD DRVDD RG Output H1–H4 Output Digital Outputs Digital Inputs SCK, SL, SDATA VRT, VRB BYP1–BYP3, CCDIN Junction Temperature Lead Temperature, 10 sec With Respect To Min Max AVSS TCVSS HVSS RGVSS DVSS DRVSS RGVSS HVSS DVSS DVSS DVSS AVSS AVSS –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +3.9 +3.9 +5.5 +5.5 +3.9 +3.9 RGVDD + 0.3 HVDD + 0.3 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 350 PACKAGE THERMAL CHARACTERISTICS Thermal Resistance JA = 61°C/W JC = 29.7°C/W Unit V V V V V V V V V V V V V °C °C ORDERING GUIDE Model Temperature Range AD9891KBC –20°C to +85°C AD9895KBC –20°C to +85°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9891 and AD9895 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –6– Package Description Package Option CSPBGA CSPBGA BC-64 BC-64 WARNING! ESD SENSITIVE DEVICE REV. A AD9891/AD9895 AD9891 PIN CONFIGURATION A1 CORNER INDEX AREA 1 2 3 4 5 6 7 8 9 10 AD9891 TOP VIEW (Not to Scale) A B C D E F G H J K PIN FUNCTION DESCRIPTIONS 1 Pin Mnemonic Type2 Description Pin Mnemonic Type2 Description A1 VD DO B1 HD DO C1 C2 SYNC LD/FD DI DO D1 D2 DO DO E1 E2 F2 DCLK CLPOB/ PBLK NC NC DO/SDO Vertical Sync Pulse (Input for Slave Mode, Output for Master Mode) Horizontal Sync Pulse (Input for Slave Mode, Output for Master Mode) External System Sync Input Line or Field Designator Output Data Clock Output CLPOB or PBLK Output K9 J9 K10 J10 H10 H9 G10 G9 F10 F9 E10 E9 D9 D10 VSG5 VSG6 VSG7 VSG8 H1 H2 HVDD HVSS H3 H4 RGVDD RGVSS RG CLO DO DO DO DO DO DO P P DO DO P P DO DO F1 G2 G1 H2 H1 J2 J1 K2 K1 K3 K4 J3 J4 D1 D2 D3 D4 D5 D6 D7 D8 D9 DRVDD DRVSS VSUB SUBCK DO DO DO DO DO DO DO DO DO P P DO DO C10 B10 C9 CLI TCVDD TCVSS DI P P A10 B9 A9 B8 A8 A7 B7 B6 A6 AVDD1 AVSS1 BYP1 BYP2 CCDIN BYP3 AVDD2 AVSS2 REFB P P AO AO AI AO P P AO K5 J5 K6 J6 K7 V1 V2 V3 V4 VSG1/V5 DO DO DO DO DO J7 VSG2/V6 DO A5 B5 A4 B4 A3 B3 B2 A2 REFT SL SDI SCK MSHUT STROBE DVSS DVDD AO DI DI DI DO DO P P K8 VSG3/V7 DO CCD Sensor Gate Pulse 5 CCD Sensor Gate Pulse 6 CCD Sensor Gate Pulse 7 CCD Sensor Gate Pulse 8 CCD Horizontal Clock 1 CCD Horizontal Clock 2 H1–H4 Driver Supply H1–H4 Driver Ground CCD Horizontal Clock 3 CCD Horizontal Clock 4 RG Driver Supply RG Driver Ground CCD Reset Gate Clock Reference Clock Output for Crystal Reference Clock Input Analog Supply for Timing Core Analog Ground for Timing Core Analog Supply for AFE Analog Ground for AFE Analog Circuit Bypass Analog Circuit Bypass CCD Signal Input Analog Circuit Bypass Analog Supply for AFE Analog Ground for AFE Voltage Reference Bottom Bypass Voltage Reference Top Bypass 3-Wire Serial Load Pulse 3-Wire Serial Data Input 3-Wire Serial Clock Mechanical Shutter Pulse Strobe Pulse Digital Ground Digital Supply for VSG, V1–V4, HD, VD, MSHUT, STROBE, and Serial Interface J8 VSG4/V8 DO REV. A DO Not Internally Connected Not Internally Connected Data Output (LSB) (also Serial Data Output3) Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output (MSB) Data Output Driver Supply Data Output Driver Ground CCD Substrate Bias CCD Substrate Clock (E-Shutter) CCD Vertical Transfer Clock CCD Vertical Transfer Clock CCD Vertical Transfer Clock CCD Vertical Transfer Clock CCD Sensor Gate Pulse 1 (also V54) CCD Sensor Gate Pulse 2 (also V64) CCD Sensor Gate Pulse 3 (also V74) CCD Sensor Gate Pulse 4 (also V84) 1 2 3 4 NOTES 1 See Figure 50 for circuit configuration. 2 AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, P = Power. 3 In Register Readback Mode 4 In Frame Transfer CCD Mode –7– AD9891/AD9895 AD9895 PIN CONFIGURATION A1 CORNER INDEX AREA 1 2 3 4 5 6 7 8 9 10 AD9895 TOP VIEW (Not to Scale) A B C D E F G H J K PIN FUNCTION DESCRIPTIONS 1 Pin Mnemonic Type2 Description Pin Mnemonic Type2 Description A1 VD DO B1 HD DO C1 C2 SYNC LD/FD DI DO D1 D2 DO DO E2 E1 F2 DCLK CLPOB/ PBLK DO D1 D2/SDO Vertical Sync Pulse (Input for Slave Mode, Output for Master Mode) Horizontal Sync Pulse (Input for Slave Mode, Output for Master Mode) External System Sync Input Line or Field Designator Output Data Clock Output CLPOB or PBLK Output K9 J9 K10 J10 H10 H9 G10 G9 F10 F9 E10 E9 D9 D10 VSG5 VSG6 VSG7 VSG8 H1 H2 HVDD HVSS H3 H4 RGVDD RGVSS RG CLO DO DO DO DO DO DO P P DO DO P P DO DO F1 G2 G1 H2 H1 J2 J1 K2 K1 K3 K4 J3 J4 D3 D4 D5 D6 D7 D8 D9 D10 D11 DRVDD DRVSS VSUB SUBCK DO DO DO DO DO DO DO DO DO P P DO DO C10 B10 C9 CLI TCVDD TCVSS DI P P A10 B9 A9 B8 A8 A7 B7 B6 A6 AVDD1 AVSS1 BYP1 BYP2 CCDIN BYP3 AVDD2 AVSS2 REFB P P AO AO AI AO P P AO K5 J5 K6 J6 K7 V1 V2 V3 V4 VSG1/V5 DO DO DO DO DO J7 VSG2/V6 DO A5 B5 A4 B4 A3 B3 B2 A2 REFT SL SDI SCK MSHUT STROBE DVSS DVDD AO DI DI DI DO DO P P K8 VSG3/V7 DO CCD Sensor Gate Pulse 5 CCD Sensor Gate Pulse 6 CCD Sensor Gate Pulse 7 CCD Sensor Gate Pulse 8 CCD Horizontal Clock 1 CCD Horizontal Clock 2 H1–H4 Driver Supply H1–H4 Driver Ground CCD Horizontal Clock 3 CCD Horizontal Clock 4 RG Driver Supply RG Driver Ground CCD Reset Gate Clock Reference Clock Output for Crystal Reference Clock Input Analog Supply for Timing Core Analog Ground for Timing Core Analog Supply for AFE Analog Ground for AFE Analog Circuit Bypass Analog Circuit Bypass CCD Signal Input Analog Circuit Bypass Analog Supply for AFE Analog Ground for AFE Voltage Reference Bottom Bypass Voltage Reference Top Bypass 3-Wire Serial Load Pulse 3-Wire Serial Data Input 3-Wire Serial Clock Mechanical Shutter Pulse Strobe Pulse Digital Ground Digital Supply for VSG, V1–V4, HD, VD, MSHUT, STROBE, and Serial Interface J8 VSG4/V8 DO DO DO DO Data Output (LSB) Data Output Data Output (also Serial Data Output3) Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output (MSB) Data Output Driver Supply Data Output Driver Ground CCD Substrate Bias CCD Substrate Clock (E-Shutter) CCD Vertical Transfer Clock CCD Vertical Transfer Clock CCD Vertical Transfer Clock CCD Vertical Transfer Clock CCD Sensor Gate Pulse 1 (also V54) CCD Sensor Gate Pulse 2 (also V64) CCD Sensor Gate Pulse 3 (also V74) CCD Sensor Gate Pulse 4 (also V84) 1 2 3 4 NOTES 1 See Figure 50 for circuit configuration. 2 AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, DIO = Digital Input/Output, P = Power. 3 In Register Readback Mode 4 In Frame Transfer CCD Mode –8– REV. A AD9891/AD9895 SPECIFICATION DEFINITIONS Differential Nonlinearity (DNL) percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC’s full-scale range. An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC Full Scale/2n codes) when n is the bit resolution of the ADC. For the AD9891, 1 LSB is 2 mV, while for the AD9895, 1 LSB is 0.5 mV. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9891/AD9895 from a true straight line. The point used as “zero scale” occurs 0.5 LSB before the first code transition. “Positive full scale” is defined as a level 1 and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. EQUIVALENT CIRCUITS DVDD AVDD1 330 R AVSS1 DVSS AVSS1 Figure 1. CCDIN DVDD Figure 3. Digital Inputs HVDD OR RGVDD DRVDD DATA RG, H1–H4 THREESTATE DOUT DVSS ENABLE HVSS OR RGVSS DRVSS Figure 2. Digital Data Outputs REV. A OUTPUT Figure 4. H1–H4, RG Drivers –9– AD9891/AD9895–Typical Performance Characteristics 440 725 RGVDD = HVDD = 5.0V RGVDD = HVDD = 5.0V 650 VDD = 3.0V 320 VDD = 3.3V POWER DISSIPATION – mW VDD = 3.3V 360 VDD = 2.7V 280 575 VDD = 3.0V 500 425 240 VDD = 2.7V 350 200 10 15 SAMPLE RATE – MHz 275 10 20 TPC 1. AD9891 Power vs. Sample Rate 20 SAMPLE RATE – MHz 30 TPC 4. AD9895 Power vs. Sample Rate 1.0 1.0 0.5 0.5 0 0 –0.5 –0.5 –1.0 –1.0 0 200 400 600 800 0 1000 TPC 2. AD9891 Typical DNL Performance 800 1600 2400 3200 4000 TPC 5. AD9895 Typical DNL Performance 24 4 21 18 OUTPUT NOISE – LSB 3 OUTPUT NOISE – LSB POWER DISSIPATION – mW 400 2 15 12 9 6 1 3 0 0 0 200 400 600 VGA GAIN CODE – LSB 800 0 1000 TPC 3. AD9891 Output Noise vs. VGA Gain 200 400 600 VGA GAIN CODE – LSB 800 1000 TPC 6. AD9895 Output Noise vs. VGA Gain –10– REV. A AD9891/AD9895 SYSTEM OVERVIEW Figure 5 shows the typical system block diagram for the AD9891/ AD9895 used in Master Mode. The CCD output is processed by the AD9891/AD9895’s AFE circuitry, which consists of a CDS, PxGA, VGA, black level clamp, and an A/D converter. The digitized pixel information is sent to the digital image processor chip, which performs the post-processing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9891/AD9895 from the system microprocessor, through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor or external crystal, the AD9891/ AD9895 generates all of the CCD’s horizontal and vertical clocks and all internal AFE clocks. External synchronization is provided by a SYNC pulse from the microprocessor, which will reset internal counters and resync the VD and HD outputs. V-DRIVER The H-drivers for H1–H4 and RG are included in the AD9891/ AD9895, allowing these clocks to be directly connected to the CCD. H-drive voltage of up to 5 V is supported. An external V-driver is required for the vertical transfer clocks, the sensor gate pulses, and the substrate clock. The AD9891/AD9895 also includes programmable MSHUT and STROBE outputs, which may be used to trigger mechanical shutter and strobe (flash) circuitry. Figure 6 shows the horizontal and vertical counter dimensions for the AD9891/AD9895. All internal horizontal and vertical clocking is programmed using these dimensions to specify line and pixel locations. V1–V4, VSG1–VSG8, SUBCK MAXIMUM FIELD DIMENSIONS H1–H4, RG, VSUB CCDIN CCD AD989x MSHUT STROBE SERIAL INTERFACE DOUT DCLK CLPOB/PBLK LD/FD HD, VD CLI DIGITAL IMAGE PROCESSING ASIC 12-BIT HORIZONTAL = 4096 PIXELS MAX SYNC P 12-BIT VERTICAL = 4096 LINES MAX Figure 5. Typical System Block Diagram, Master Mode Alternatively, the AD9891/AD9895 may be operated in Slave Mode, in which the VD and HD are provided externally from the image processor. In this mode, all AD9891/AD9895 timing will be synchronized with VD and HD. REV. A Figure 6. Vertical and Horizontal Counters –11– AD9891/AD9895 The AD9891/AD9895 also includes a master clock output, CLO, which is the inverse of CLI. This output is intended to be used as a crystal driver. A crystal can be placed between the CLI and CLO Pins to generate the master clock for the AD9891/AD9895. For more information on using a crystal, see Figure 51. PRECISION TIMING HIGH SPEED TIMING GENERATION The AD9891/AD9895 generates flexible, high speed timing signals using the Precision Timing core. This core is the foundation for generating the timing used for both the CCD and the AFE: the reset gate RG, horizontal drivers H1–H4, and the SHP/SHD sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling. High Speed Clock Programmability The high speed timing of the AD9891/AD9895 operates the same in either Master or Slave Mode configuration. Timing Resolution The Precision Timing core uses a 1
master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 7 illustrates how the internal timing core divides the master clock period into 48 steps or edge positions. Using a 20 MHz CLI frequency, the edge resolution of the Precision Timing core is 1 ns. If a 1
system clock is not available, it is also possible to use a 2
reference clock by programming the CLIDIVIDE Register (Addr x01F). The AD9891/ AD9895 will then internally divide the CLI frequency by two. P[0] POSITION P[12] Figure 8 shows how the high speed clocks RG, H1–H4, SHP, and SHD are generated. The RG pulse has programmable rising and falling edges, and may be inverted using the polarity control. The horizontal clocks H1 and H3 have programmable rising and falling edges and polarity control. The H2 and H4 clocks are always inverses of H1 and H3, respectively. Table I summarizes the high speed timing registers and their parameters. Figure 9 shows the typical 2-phase H-clock arrangement in which H3 and H4 are programmed for the same edge location as H1 and H2. The edge location registers are six bits wide, but there are only 48 valid edge locations available. Therefore, the register values are mapped into four quadrants, with each quadrant containing 12 edge locations. Table II shows the correct register values for P[24] P[36] P[48] = P[0] CLI tCLIDLY 1 PIXEL PERIOD NOTES PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (tCLIDLY = 6ns TYP). Figure 7. High Speed Clock Resolution from CLI Master Clock Input 3 CCD SIGNAL 4 1 2 RG 5 6 H1 H2 7 8 H3 H4 PROGRAMMABLE CLOCK POSITIONS: 1: RG RISING EDGE 2: RG FALLING EDGE 3: SHP SAMPLE LOCATION 4: SHD SAMPLE LOCATION 5: H1 RISING EDGE POSITION AND 6: H1 FALLING EDGE POSITION (H2 IS INVERSE OF H1) 7: H3 RISING EDGE POSITION AND 8: H3 FALLING EDGE POSITION (H4 IS INVERSE OF H3) Figure 8. High Speed Clock Programmable Locations –12– REV. A AD9891/AD9895 the corresponding edge locations. Figure 10 shows the range and default locations of the high speed clock signals. in an H1/H2 crossover voltage at approximately 50% of the output swing. The crossover voltage is not programmable. H-Driver and RG Outputs Digital Data Outputs In addition to the programmable timing positions, the AD9891/ AD9895 features on-chip output drivers for the RG and H1–H4 outputs. These drivers are powerful enough to directly drive the CCD inputs. The H-driver current can be adjusted for optimum rise/fall time into a particular load by using the DRV Registers (Addr x0E1 to x0E4). The RG drive current is adjustable using the RGDRV Register (Addr x0E8). Each 3-bit DRV Register is adjustable in 3.5 mA increments, with the minimum setting of 0 equal to OFF or three-state, and the maximum setting of 7 equal to 24.5 mA. The AD9891/AD9895 data output and DCLK phase are programmable using the DOUTPHASE Register (Addr x01D). Any edge from 0 to 47 may be programmed, as shown in Figure 12. Normally, the DOUT and DCLK signals will track in phase, based on the DOUTPHASE Register contents. The DCLK output phase can also be held fixed with respect to the data outputs, by changing the DCLKMODE Register (Addr x01E) HIGH. In this mode, the DCLK output will remain at a fixed phase equal to CLO (the inverse of CLI) while the data output phase is still programmable. As shown in Figure 11, the H2 and H4 outputs are inverses of H1 and H3, respectively. The internal propagation delay resulting from the signal inversion is less than 1 ns, which is significantly less than the typical rise time driving the CCD load. This results There is a fixed output delay from the DCLK rising edge to the DOUT transition, called tOD. This delay can be programmed to four values between 0 ns and 12 ns, using the DOUT_DELAY Register (Addr x032). The default value is 8 ns. Table I. H1–H4, RG, SHP, and SHD Timing Parameters Register Length Range Description POL POSLOC 1b 6b High/Low 0–47 Edge Location NEGLOC DRV 6b 3b 0–47 Edge Location 0–7 Current Steps Polarity Control for H1, H3, and RG (0 = No Inversion, 1 = Inversion) Positive Edge Location for H1, H3, and RG Sample Location for SHP, SHD Negative Edge Location for H1, H3, and RG Drive Current for H1–H4 and RG Outputs (3.5 mA per Step) CCD SIGNAL RG H1/H3 H2/H4 USING THE SAME TOGGLE POSITIONS FOR H1 AND H3 GENERATES STANDARD 2-PHASE H-CLOCKING. Figure 9. 2-Phase H-Clock Operation Table II. Precision Timing Edge Locations Quadrant Edge Location (Dec) Register Value (Dec) Register Value (Bin) I II III IV 0 to 11 12 to 23 24 to 35 36 to 47 0 to 11 16 to 27 32 to 43 48 to 59 000000 to 001011 010000 to 011011 100000 to 101011 110000 to 111011 REV. A –13– AD9891/AD9895 P[0] POSITION P[12] P[24] P[48] = P[0] P[36] PIXEL PERIOD RGr[0] RGf[12] RG Hf[24] Hr[0] H1/H3 SHP[28] tS1 CCD SIGNAL SHD[48] NOTES ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 48 POSITIONS WITHIN ONE PIXEL PERIOD. DEFAULT POSITIONS FOR EACH SIGNAL ARE SHOWN. Figure 10. High Speed Clock Default and Programmable Locations tRISE H1/H3 H2/H4 tPD < tRISE tPD H1/H3 H2/H4 FIXED CROSSOVER VOLTAGE Figure 11. H-Clock Inverse Phase Relationship P[0] P[12] P[24] P[36] P[48] = P[0] PIXEL PERIOD DCLK tOD DOUT NOTES DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. WITHIN 1 CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 48 DIFFERENT LOCATIONS. OUTPUT DELAY (tOD) FROM DCLK RISING EDGE TO DOUT RISING EDGE IS PROGRAMMABLE. Figure 12. Digital Output Phase Adjustment –14– REV. A AD9891/AD9895 To simplify the programming requirements, the CLPDM signal will track the CLPOB signal by default. If separate control of the CLPDM signal is desired, the SINGLE_CLAMP Register (Addr x031) should be set LOW. HORIZONTAL CLAMPING AND BLANKING The AD9891/AD9895’s horizontal clamping and blanking pulses are fully programmable to suit a variety of applications. As with the vertical timing generation, individual sequences are defined for each signal, which are then organized into multiple regions during image readout. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout in order to accommodate different image transfer timing and high speed line shifts. Individual HBLK Sequences The HBLK programmable timing shown in Figure 14 is similar to CLPOB, CLPDM, and PBLK. However, there is no start polarity control. Only the toggle positions are used to designate the start and the stop positions of the blanking period. Additionally, there is a polarity control, HBLKMASK, that designates the polarity of the horizontal clock signals H1–H4 during the blanking period. Setting HBLKMASK high will set H1 = H3 = Low and H2 = H4 = High during the blanking, as shown in Figure 15. Up to four individual sequences are available for HBLK. Individual CLPOB, CLPDM, and PBLK Sequences The AFE horizontal timing consists of CLPOB, CLPDM, and PBLK, as shown in Figure 13. These three signals are independently programmed using the registers in Table III. SPOL is the start polarity for the signal, and TOG1 and TOG2 are the first and second toggle positions of the pulse. All three signals are active low and should be programmed accordingly. Up to four individual sequences can be created for each signal. Horizontal Sequence Control The AD9891/AD9895 use sequence change positions (SCP) and sequence pointers (SPTR) to organize the individual hori- HD CLPOB CLPDM PBLK 1 2 3 CLAMP CLAMP PROGRAMMABLE SETTINGS: 1: START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW) 2: 1ST TOGGLE POSITION 3: 2ND TOGGLE POSITION Figure 13. Clamp and Preblank Pulse Placement HD 1 2 BLANK HBLK BLANK PROGRAMMABLE SETTINGS: 1: 1ST TOGGLE POSITION = START OF BLANKING 2: 2ND TOGGLE POSITION = END OF BLANKING Figure 14. Horizontal Blanking (HBLK) Pulse Placement HD HBLK H1/H3 H1/H3 H2/H4 THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1) Figure 15. HBLK Masking Control REV. A –15– AD9891/AD9895 zontal sequences. Up to four SCPs are available to divide the readout into four separate regions, as shown in Figure 16. The SCP0 is always hard-coded to line 0, and SCP1–SCP3 are register programmable. During each region bound by the SCP, the SPTR Registers designate which sequence is used by each signal. CLPOB and CLPDM share the same SCP, PBLK has a separate set of SCP, and HBLK shares the vertical RCP (see Vertical Timing Generation section). For example, CLPSCP1 will define Region 0 for CLPOB and CLPDM, and in that region any of the four individual CLPOB and CLPDM sequences may be selected with the SPTR Registers. The next SCP defines a new region, and in that region each signal can be assigned to a different individual sequence. Because HBLK shares the vertical RCP, there are up to eight regions where HBLK sequences may be changed using the eight HBLKSPTR Registers. Table III. CLPOB, CLPDM, and PBLK Individual Sequence Parameters Register Length Range Description SPOL TOG1 TOG2 1b 12b 12b High/Low 0–4095 Pixel Location 0–4095 Pixel Location Starting Polarity of Vertical Transfer Pulse for Sequences 0–3 First Toggle Position within Line for Sequences 0–3 Second Toggle Position within Line for Sequences 0–3 Table IV. HBLK Individual Sequence Parameters Register Length Range Description HBLKMASK HBLKTOG1 HBLKTOG2 1b 12b 12b High/Low 0–4095 Pixel Location 0–4095 Pixel Location Masking Polarity for H1 for Sequences 0–3 (0 = H1 Low, 1 = H1 High) First Toggle Position within Line for Sequences 0–3 Second Toggle Position within Line for Sequences 0–3 Table V. Horizontal Sequence Control Parameters for CLPOB, CLPDM, and PBLK Register Length SCP1–SCP3 12b SPTR0–SPTR3 2b Range Description 0–4095 Line Number 0–3 Sequence Number CLPOB/PBLK SCP to Define Horizontal Regions 0–3 Sequence Pointer for Horizontal Regions 0–3 Table VI. Horizontal Sequence Control Parameters for HBLK Register Length Range Description VTPRCP1– VTPRCP7 HBLKSPTR0– HBLKSPTR7 12b 0–4095 Line Number Vertical Region Change Positions (See Table IX.) 2b 0–3 Sequence Number Sequence Pointer for HBLK Regions 0–7 SINGLE FIELD (1 VD INTERVAL) SEQUENCE CHANGE POSITION #0 (V-COUNTER = 0) CLAMP AND PBLK SEQUENCE REGION 1 SEQUENCE CHANGE POSITION #1 CLAMP AND PBLK SEQUENCE REGION 2 SEQUENCE CHANGE POSITION #2 CLAMP AND PBLK SEQUENCE REGION 3 SEQUENCE CHANGE POSITION #3 CLAMP AND PBLK SEQUENCE REGION 4 UP TO FOUR INDIVIDUAL HORIZONTAL CLAMP AND BLANKING REGIONS MAY BE PROGRAMMED WITHIN A SINGLE FIELD, USING THE SEQUENCE CHANGE POSITIONS. Figure 16. Clamp and Blanking Sequence Flexibility –16– REV. A AD9891/AD9895 VERTICAL TIMING GENERATION The AD9891/AD9895 provide a very flexible solution for generating vertical CCD timing and can support multiple CCDs and different system architectures. The 4-phase vertical transfer clocks V1–V4 are used to shift each line of pixels into the horizontal output register of the CCD. The AD9891/AD9895 allow these outputs to be individually programmed into different pulse patterns. Vertical sequence control registers then organize the individual vertical pulses into the desired CCD vertical timing arrangement. sequences are created by using the Vertical Transfer Pulse (VTP) Registers. These sequences are a essentially a “pool” of pulse patterns that may be assigned to any of the V1-V4 outputs. Second, individual regions are built by assigning a sequence to each of the V1–V4 outputs. Up to five unique regions may be specified. Finally, the readout of the entire field is constructed by combining one or more of the individual regions sequentially. With up to eight region areas available, different steps of the readout such as high speed line shifts and vertical image transfer can be supported. Figure 17 shows an overview of how the vertical timing is generated in three basic steps. First, the individual pulse patterns or CREATE THE INDIVIDUAL VERTICAL SEQUENCES (MAXIMUM OF 12 SEQUENCES). SEQUENCE 0 SEQUENCE 1 SEQUENCE 2 BUILD THE INDIVIDUAL VERTICAL REGIONS BY ASSIGNING EACH SEQUENCE TO V1–V4 OUTPUTS (MAXIMUM OF 5 REGIONS). SEQUENCE 3 SEQUENCE 4 REGION 0 SEQUENCE 5 V1 (SEQ 0) V2 (SEQ 0*) SEQUENCE 6 SEQUENCE 7 V3 (SEQ 1) SEQUENCE 8 V4 (SEQ 1*) SEQUENCE 9 REGION 1 SEQUENCE 10 V1 (SEQ 2) V2 (SEQ 3) SEQUENCE 11 V3 (SEQ 4) V4 (SEQ 5) BUILD THE ENTIRE FIELD READOUT BY COMBINING MULTIPLE REGIONS (MAXIMUM OF 8 COMBINATIONS). REGION 4 V1 (SEQ 6) V2 (SEQ 6*) USE REGION 2 FOR LINES 1 TO 20 V3 (SEQ 7) USE REGION 1 FOR LINE 21 V4 (SEQ 7*) *SEQUENCES MAY BE SHIFTED AND/OR INVERTED USE REGION 0 FOR LINES 22 TO 2000 USE REGION 2 FOR LINES 2001 TO 2020 Figure 17. Summary of Vertical Timing Generation REV. A –17– AD9891/AD9895 Individual Vertical Sequences To generate the individual vertical sequences or patterns shown in Figure 18, five registers are required for each sequence. Table VII summarizes these registers and their respective bit lengths. The start polarity (VTPPOL) determines the starting polarity of the vertical sequence and can be programmed high or low. The first toggle position (VTPTOG1) and second toggle position (VTPTOG2) are the pixel locations within the line where the pulse transitions. A third toggle position (VTPTOG3) is also available for sequences 0 through 7. All toggle positions are 10-bit values, which limits the placement of a pulse to within 1024 pixels of a line. A separate register, VSTART, sets the start position of the sequence within the line (see Individual Vertical Regions section). The Length (VTPLEN) Register determines the number of pixels between each of the pulse repetitions, if any repetitions have been programmed. The number of repetitions (VTPREP) simply determines the number of pulse repetitions desired within a single line. Programming “1” for VTPREP gives a single pulse, while setting to “0” will provide a fixed dc output based on the start polarity value. There is a total of 12 individual sequences that may be programmed. When specifying the individual regions, each sequence may be assigned to any of the V1–V4 outputs. For example, Figure 19 shows a typical 4-phase V-clock arrangement. Two different sequences are needed to generate the different pulsewidths. The use of individual start positions for V1–V4 allows the four outputs to be generated from two sequences. Figure 20 shows a slightly different V-clock arrangement in which V2, V3, and V4 are simply shifted and/or inverted versions of V1. Only one individual sequence is needed because all signals have the same pulsewidth. The invert sequence registers (VINV) are used for V3 and V4 (see Table VII). Note that for added flexibility, the VTPPOL Registers (Start Polarity) may be used as an extra toggle position. Table VII. Individual VTP Sequence Parameters Register Length Range Description VTPPOL VTPTOG1 VTPTOG2 VTPTOG3 VTPLEN VTPREP 1b 10b 10b 10b 10b 12b High/Low 0–1023 Pixel Location 0–1023 Pixel Location 0–1023 Pixel Location 0–1023 Pixels 0–4095 Pulses Starting Polarity of Vertical Transfer Pulse for Each Sequence 0–11 First Toggle Position within Line for Each Sequence 0–11 Second Toggle Position within Line for Each Sequence 0–11 Third Toggle Position within Line for Each Sequence 0–7 Length between Pulse Repetitions for Each Sequence 0–11 Number of Pulse Repetitions for Each Sequence 0–11 (0 = DC Output) START POSITION OF SEQUENCE IS INDIVIDUALLY PROGRAMMABLE FOR EACH V1–V4 OUTPUT HD 5 4 V1–V4 1 2 3 PROGRAMMABLE SETTINGS FOR EACH SEQUENCE: 1: START POLARITY 2: 1ST TOGGLE POSITION 3: 2ND TOGGLE POSITION (THERE IS ALSO A 3RD TOGGLE POSITION AVAILABLE FOR SEQUENCES 0 TO 7) 4: LENGTH BETWEEN REPEATS 5: NUMBER OF REPEATS Figure 18. Individual Vertical Sequence Programmability HD V1 V1 USES SEQUENCE 0 V2 V2 USES SEQUENCE 0, WITH DIFFERENT START POSITION V3 V3 USES SEQUENCE 1 V4 V4 USES SEQUENCE 1, WITH DIFFERENT START POSITION Figure 19. Example of Separate V1–V4 Signals Using Two Individual Sequences –18– REV. A AD9891/AD9895 Individual Vertical Regions The AD9891/AD9895 arranges the individual sequences into regions through the use of Sequence Pointers (SPTR). Within each region, different sequences may be assigned to each V-clock output. Figure 21 shows the programmability of each region and Table VIII summarizes the registers needed for generating each region. For each individual region, the line length (in pixels) is programmable using the HDLEN Registers. Each region can have a different line length to accommodate various image readout techniques. The maximum number of pixels per line is 4096. Also unique to each region are the sequence start positions for each V-output, which are programmed using the VSTART Registers. Each VSTART is a 12-bit value, allowing the start position to be placed anywhere in the line. There are five HDLEN Registers, one for each region. There is a total of 20 VSTART Registers: one for each V1–V4 output, for five different regions. The Sequence Pointer registers VxSPTRFIRST and VxSPTRSECOND assign the individual vertical sequences to each of the V-clock outputs (V1–V4) within a given region. Typically, only the SPTRFIRST Registers are used, with the SPTRSECOND Registers reserved for generating line-by-line alternation (see Vertical Sequence Alternation). Any of the 12 individual sequences may also be inverted using the VxINVFIRST and VxINVSECOND Registers, effectively doubling the number of sequences available. There is one SPTRFIRST Register for each V-output, for a total of four registers per region. If all five regions are used, there is a total of 20 SPTRFIRST Registers. There is also the same number of SPTRSECOND Registers, if alternation is required. Note that the SPTR Registers are four bits wide; if a value greater than 11 is programmed, the Vx output will be dc at the level of the VxINV Register. Note that the last line of the field is separately programmable using the HDLASTLEN Register. HD V1 V1 USES SEQUENCE 2 V2 V2 USES SEQUENCE 2, WITH DIFFERENT START POSITION V3 V3 USES SEQUENCE 2, INVERTED V4 V4 USES SEQUENCE 2, INVERTED, WITH DIFFERENT START POSITION Figure 20. Example of Inverted V1–V4 Signals Using One Individual Sequence with Inversion 1 HD 2 3 V1–V4 SEQUENCES A, B, C, D PROGRAMMABLE SETTINGS FOR EACH REGION: 1: START POSITION OF SELECTED SEQUENCE IS SEPARATELY PROGRAMMABLE FOR EACH OUTPUT 2: HD LINE LENGTH 3: SEQUENCE POINTERS (SPTR) TO SELECT AN INDIVIDUAL SEQUENCE FOR EACH OUTPUT 4: ANY SEQUENCES MAY ALSO BE ALTERNATED FOR ADDITIONAL FLEXIBILITY Figure 21. Individual Vertical Region Programmability REV. A –19– AD9891/AD9895 Table VIII. Individual Vertical Region Parameters Register Length Range Description HDLEN 12b VxSTART 12b VxSPTRFIRST 4b 0–4095 Pixels 0–4095 Pixel Location Sequence 0–11 VxINVFIRST High/Low HD Line Length for Lines in Each Region 0–4 Sequence Start Position for Each Vx Output in Each Region 0–4 Sequence Pointer for Vx Output during Each Region 0–4 (Can Be Used with SPTRSECOND for Alternation, See Text) When High, the Polarity of Sequence VxSPTRFIRST Is Inverted 1b x is the V-output from 1–4. Complete Field: Combining the Regions The individual regions are combined into a complete field readout by using region change positions (RCP) and region pointers (REGPTR). Figure 22 shows how each field is divided into multiple regions. This allows the user to change the vertical timing during various stages of the image readout. The boundaries of each region are defined by the sequence change positions (RCP). Each RCP is a 12-bit value representing the line number bounding the region. A total of seven RCPs allow up to eight different region areas in the field to be defined. The first RCP is always hard-coded to zero, and the remaining seven are register programmable. Note that there are only five possible individual regions that can be defined, but the eight region areas allow the same region to be used in more than one place during the field. Within each region area, the region pointers specify which of the five individual regions will be used. There are eight region pointers, one for each region area. Table IX summarizes the registers for the region change positions and region pointers. SINGLE FIELD (1 VD INTERVAL) REGION CHANGE POSTION #0 (V-COUNTER = 0) USE THE REGION SPECIFIED BY REGION POINTER 0 REGION CHANGE POSTION #1 USE THE REGION SPECIFIED BY REGION POINTER 1 REGION CHANGE POSTION #2 USE THE REGION SPECIFIED BY REGION POINTER 2 REGION CHANGE POSTION #3 USE THE REGION SPECIFIED BY REGION POINTER 3 REGION CHANGE POSTION #4 USE THE REGION SPECIFIED BY REGION POINTER 4 REGION CHANGE POSTION #5 USE THE REGION SPECIFIED BY REGION POINTER 5 REGION CHANGE POSTION #6 USE THE REGION SPECIFIED BY REGION POINTER 6 REGION CHANGE POSTION #7 USE THE REGION SPECIFIED BY REGION POINTER 7 UP TO EIGHT V-CLOCK REGION AREAS MAY BE DEFINED WITHIN ONE FIELD BY USING THE REGION CHANGE POSITION AND THE REGION POINTERS. Figure 22. Complete Field Using Multiple Region Areas Table IX. Complete Vertical Field Registers Register Length Range Description VTPRCP VTPREGPTR 12b 3b 0–4095 Line Location Region 0–4 Region Change Position for each Region Area in Field Region Pointer for each Region Area of Field –20– REV. A AD9891/AD9895 Vertical Sequence Alternation The AD9891/AD9895 also supports line-by-line alternation of vertical sequences within any region, as shown in Figure 23. Table X summarizes the additional registers used to support different alternation patterns. To create an alternating vertical pattern, the VxSPTRFIRST and VxSPTRSECOND Registers are programmed with the desired sequences to be alternated. The VTPALT Register must be set HIGH for that region to use alternation. If VTPALT is LOW, then the VxSPTRSECOND Registers will be ignored. Figure 24 shows an example of lineby-line alternation. SINGLE FIELD (1 VD INTERVAL) REGION CHANGE POSTION #0 NO ALTERNATION ONLY FIRST LINES ARE USED REGION CHANGE POSITION #1 FIRST LINES LINE-BY-LINE ALTERNATION SECOND LINES REGION CHANGE POSTION #2 NO ALTERNATION ONLY FIRST LINES ARE USED WHEN THE VTPALT REGISTER IS LOW (NO ALTERNATION), ONLY THE FIRST LINES ARE USED. Figure 23. Use of Line Alteration in Vertical Sequencing USE SECOND V SEQUENCES USE FIRST V SEQUENCES USE FIRST V SEQUENCES HD V1 V2 V3 V4 SEQUENCES MAY BE ALTERNATED WITHIN A REGION BY USING THE SPTRFIRST AND SPTRSECOND REGISTERS. Figure 24. Example of Line Alteration within a Region Table X. Vertical Sequence Alternation Parameters Register Length Range Description VTPALT VxSPTRFIRST VxINVFIRST VxSPTRSECOND VxINVSECOND 1b 4b 1b 4b 1b Enabled/Disabled Sequence 0–11 High/Low Sequence 0–11 High/Low Enables the Line-by-Line Alternation (1 = Enabled) SPTR for Vx Output during Each Region 0–4 for FIRST Lines When High, the Polarity of VxSPTRFIRST Is Inverted SPTR for Vx Output during Each Region 0–4 for SECOND Lines When High, the Polarity of VxSPTRSECOND Is Inverted x is the V-output from 1–4. REV. A –21– AD9891/AD9895 Second Vertical Sequence During VSG Lines Most CCDs require additional vertical timing during the sensor gate line. The AD9891/AD9895 supports the option to output a second set of sequences for V1–V4 during the line when the sensor gates VSG1–VSG4 are active. Figure 25 shows a typical VSG line, which includes two separate sets of vertical sequences on V1– V4. The sequences at the start of the line are the same as those generated in the previous line. But the second sequence only occurs in the line where the VSG signals are active. To select the sequences used for the second sequence, the registers in Table XI are used. To enable the second set of sequences during the VSG line, the VTP_SGLINEMODE is set HIGH. As with the standard vertical regions, each V1–V4 output has an individual start position, programmed in the VxSTART_SGLINE Registers. Each V1–V4 output can select from the pool of 12 unique sequences using individual sequence pointer registers, VxSPTR_SGLINE. Also, any sequence may be inverted for a particular V1–V4 output by using the VxINV_SGLINE Registers. Vertical Sweep Mode Operation The AD9891/AD9895 contains a special mode of vertical timing operation called Sweep Mode. This mode is used to generate a large number of repetitive pulses that span across multiple HD lines. One example of where this mode may be needed is at the start of the CCD readout operation. At the end of the image exposure, but before the image is transferred by the sensor gate pulses, the vertical interline CCD Registers should be “clean” of all charge. This can be accomplished by quickly shifting out any charge with a long series of pulses on the V1–V4 outputs. Depending on the vertical resolution of the CCD, up to two or three thousand clock cycles will be needed to shift the charge out of each vertical CCD line. This operation will span across multiple HD line lengths. Normally, the AD9891/AD9895 sequences are contained within one HD line length. But when Sweep Mode is enabled, the HD boundaries will be ignored until the region is finished. To enable Sweep Mode within any region, program the appropriate SWEEP (0–4) Registers to HIGH. Figure 26 shows an example of the Sweep Mode operation. The number of vertical pulses needed will depend on the vertical resolution of the CCD. The V1–V4 output signals are generated using the Individual Vertical Sequence Registers (shown in Table VII). A single pulse is created using the first, second, and third toggle positions, and then the number of repeats is set to the number of vertical shifts required by the CCD. The maximum number of repeats is 4096 in this mode, using the VTPREP Register. This produces a pulse train of the appropriate length. Normally, the pulse train would be truncated at the end of the HD line length. But with Sweep Mode enabled for this region, the HD boundaries will be ignored. In Figure 26, the sweep region occupies 23 HD lines. After the Sweep Mode region is completed, normal sequence operation will resume in the next region. Table XI. Second Vertical Sequence Registers During SG Lines Register Name Length Range Description VTP_SGLINEMODE 1b HIGH/LOW To Turn on Second Sequences during SG Line, Set = HIGH VxSTART_SGLINE 12b 0–4095 Pixel Location Sequence Start Position for Each Vx Output for SG Line Sequence VxSPTR_SGLINE 4b 0–11 Sequence # Sequence Pointer for Vx Output during second SG Line Sequence VxINV_SGLINE 1b HIGH/LOW When HIGH, the Polarity of Sequence VxSPTRFIRST Is Inverted x is the V-output from 1–4. –22– REV. A AD9891/AD9895 HD SENSOR GATE LINE VSG1– VSGX V1 V2 V3 V4 2ND GROUP OF V-SEQUENCES ARE OUTPUT DURING VSG LINE Figure 25. Example of Second Sequences During Sensor Gate Line VD HD LINE 0 LINE 1 LINE 2 LINE 24 LINE 25 V1–V4 REGION AREA 0 REGION AREA 1: SWEEP REGION Figure 26. Example of Sweep Region for High Speed Vertical Shift REV. A –23– REGION AREA 2 AD9891/AD9895 The example shown in Figure 27 illustrates this operation. The first toggle position is 2 and the second toggle position is 9. In Nonmultiplier Mode, this would cause the V-sequence to toggle at pixel 2 and then pixel 9 within a single HD line. However, now toggle positions are multiplied by the VTPLEN = 4, so the first toggle occurs at pixel count = 8, and the second toggle occurs at pixel count = 36. Sweep Mode should be enabled to allow the toggle positions to cross the HD line boundaries. Vertical Multiplier Mode To generate very wide vertical timing pulses, a vertical region may be configured into Multiplier Mode. This mode uses the vertical sequence registers in a slightly different manner. Multiplier Mode can be used to support unusual CCD timing requirements, such as vertical pulses that are wider than a single HD line length. The start polarity and toggle positions are still used in the same manner as the standard sequence generation, but the length is used differently. Instead of using the pixel counter (HD counter) to specify the toggle position locations (VTPTOG1, 2, 3) of the sequence, VTP length (VTPLEN) is multiplied by the VTPTOG position to allow very long sequences to be generated. To calculate the exact toggle position, counted in pixels after the start position: Frame Transfer CCD Mode The AD9891/AD9895 may also be configured for use with frame transfer CCDs. In Frame Transfer CCD (FTCCD) Mode, an additional four vertical outputs are available for a total of eight outputs (V1–V8). In this case, V1–V4 are used for clocking the active image area, and V5–V8 are used for clocking the storage area. In FTCCD Mode, the sequences assigned to the V1–V4 outputs are duplicated at the V5–V8 outputs to allow the storage area to be clocked along with the image area. Individual masking of the V1–V4 and V5–V8 outputs allows for vertical decimation techniques during transfer from the image to the storage area. The additional outputs V5–V8 are available on four of the sensor gate output pins, VSG1–VSG4. Figure 28 shows an example of the eight V-clocks configured for use with a frame transfer CCD. Multiplier Toggle Position = VTPTOG × VTPLEN Because the VTPTOG Register is multiplied by VTPLEN, the resolution of the toggle position placement is reduced. If VTPLEN = 4, the toggle position accuracy is now reduced to 4-pixel steps instead of single pixel steps. Table XII summarizes how the Individual Vertical Sequence Registers are programmed for Multiplier Mode operation. Note that the bit ranges for the VTPTOG and VTPREP Registers differ from the normal operation shown in Table VII. In Multiplier Mode, the VTPREP Register should always be programmed to the same value as the highest toggle position register. START POSITION OF SEQUENCE IS INDIVIDUALLY PROGRAMMABLE FOR EACH V1–V4 OUTPUT HD 5 3 5 VTPLEN 1 2 3 4 1 2 3 4 1 PIXELS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 4 2 3 4 4 V1–V4 1 2 2 MULTIPLIER MODE VERTICAL SEQUENCE PROPERTIES: 1: START POLARITY (ABOVE: STARTPOL = 0) 2: 1ST, 2ND, AND 3RD TOGGLE POSITIONS (ABOVE: VTPTOG1 = 2, VTPTOG2 = 9) 3: LENGTH OF VTP COUNTER (ABOVE: VTPLEN = 4). THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES. 4: TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (VTPTOG  VTPLEN) 5: ENABLE SWEEP REGION ALLOWS THE COUNTERS TO CROSS THE HD BOUNDARIES Figure 27. Example of Multiplier Region for Wide Vertical Pulse Timing Table XII. Multiplier Mode and Sequence Register Parameters Register Length Range Description MULTI VTPPOL VTPTOG1 VTPTOG2 VTPTOG3 VTPLEN VTPREP 1b 1b 12b 12b 12b 10b 12b HIGH/LOW HIGH/LOW 0–4095 Pixel Location 0–4095 Pixel Location 0–4095 Pixel Location 0–1023 Pixels 0–4096 High Enables Multiplier Mode for Each Region 0–4 Starting Polarity of Vertical Transfer Pulse for Each Sequence 0–11 First Toggle Position for Each Sequence 0–11 Second Toggle Position for Each Sequence 0–11 Third Toggle Position for Each Sequence 0–7 “Multiplier” Factor for Repetition Counter Should Be Programmed to the Same Value as the Highest Toggle Position –24– REV. A AD9891/AD9895 HD V1 V1 USES SEQUENCE 0 V2 V2 USES SEQUENCE 0 V3 V3 USES SEQUENCE 1 V4 V4 USES SEQUENCE 1 ACTIVE IMAGE AREA V5 USES SEQUENCE 0 V5 V6 V6 USES SEQUENCE 0 V7 V7 USES SEQUENCE 1 V8 V8 USES SEQUENCE 1 STORAGE AREA Figure 28. Example of Frame Transfer CCD Mode using V1–V8 The frame transfer CCD also requires additional timing control when decimating the image for Preview Mode. The AD9891/AD9895 contain registers to independently stop the operation of the V5–V8 outputs while the V1–V4 outputs continue to run or to stop the V1–V4 outputs, while the V5–V8 outputs remain operational. The FREEZE and RESUME Registers specify the pixel locations within each line of a region where the V1–V4 or V5–V8 clock outputs will start to hold their state, and where they will resume normal operation. FREEZE and RESUME can be used in any region during the frame readout. Vertical Sensor Gate (Shift Gate) Timing With an interline CCD, the vertical sensor gates (VSG) are used to transfer the pixel charges from the light-sensitive image area into the light-shielded vertical registers. When a mechanical shutter is not being used, this transfer will effectively end the exposure period during the image acquisition. From the light-shield vertical registers, the image is then read out line-by-line by using the vertical transfer pulses V1–V4 in conjunction with the high speed horizontal clocks. VD 4 HD VSG1–VSG8 1 2 3 PROGRAMMABLE SETTINGS FOR EACH SEQUENCE: 1: START POLARITY OF PULSE 3: 2ND TOGGLE POSITION 2: 1ST TOGGLE POSITION 4: ACTIVE LINE FOR VSG PULSE WITHIN THE FIELD Figure 29. Vertical Sensor Gate Pulse Placement Table XIII. Sensor Gate Register Parameters Register Length Range Description SGPOL SGTOG1 SGTOG2 SGACTLINE SGSEL SGMASK 1b 12b 12b 12b 2b 8b High/Low 0–4095 Pixel Location 0–4095 Pixel Location 0–4095 Pixel Location Sequence 0–3 8 Individual Bits Sensor Gate Starting Polarity for Sequence 0–3 First Toggle Position for Sequence 0–11 Second Toggle Position for Sequence 0–11 Line in Field where VSG1–VSG8 Are Active Selects Sequence 0–3 for VSG1–VSG8 Masking for any of VSG1–VSG8 Signals (0 = On, 1 = Mask) REV. A –25– AD9891/AD9895 Table XIII contains the summary of the VSG Registers. The AD9891/AD9895 has eight SG outputs, VSG1–VSG8. Each of the outputs can be assigned to one of four programmed sequences by using the SGSEL1–SGSEL8 Registers. Each sequence is generated in the same manner as the individual vertical sequences, with a programmable start polarity (SGPOL), first toggle position (SGTOG1), and second toggle position (SGTOG2). The active line where the VSG1–VSG8 pulses occur is programmable using the two SGACTLIN Registers. Additionally, any of the VSG1–VSG8 pulses may be individually disabled by using the SGMASK Register. The masking allows all of the different SG sequences to be preprogrammed and the appropriate pulses for odd or even fields can be masked. SHUTTER TIMING CONTROL CCD image exposure time is controlled through use of the substrate clock signal (SUBCK), which pulses the CCD substrate to clear out accumulated charge. The AD9891/AD9895 supports three types of electronic shuttering: Normal Shutter Mode, High Precision Shutter Mode, and Low Speed Shutter Mode. Along with the SUBCK pulse placement, the AD9891/AD9895 can accommodate different progressive and interlaced readout modes. Additionally, the AD9891/AD9895 provides output signals to control an external mechanical shutter, strobe (flash), and the CCD bias for still mode readout (VSUB). ters (see Table XIV). The number of SUBCK pulses per field is programmed in the SUBCKNUM Register. As shown in Figure 30, the SUBCK pulses will always begin on the line after the sensor gates occur, specified by the SGACTLINE Register (Addr x265 and Addr x266). The SUBCKPOL, SUBCK1TOG, SUBCK2TOG, and SUBCKNUM Registers are updated at the start of the line after the sensor gate line. All other shutter mode registers are updated with the majority of the AD9891/AD9895’s registers at the VD/HD falling edge. High Precision Shutter Mode High precision shuttering is controlled in the same way as normal shuttering but requires a second set of toggle registers. In this mode, the SUBCK still pulses once per line, but the last SUBCK in the field will have an additional SUBCK pulse whose location is determined by the SUBCK2TOG1 and SUBCK2TOG2 Registers (see Figure 31). Finer resolution of the exposure time is possible using this mode. Leaving both SUBCK2TOG Registers set to 4095 (x3F) will disable the High Precision Mode (default setting). Low Speed Shutter Mode Normal Shutter Mode Figure 30 shows the VD and SUBCK output for Normal Shutter Mode. The SUBCK will pulse once per line, and the total number of repetitions within the field is programmable. The pulse polarity, width, and line location is programmable using the SUBCKPOL, SUBCK1TOG1, and SUBCK1TOG2 Regis- For normal exposure times less than one field interval, the EXPOSURE Register will be set to 0. Exposure times greater than one field interval can be achieved by writing a value greater than zero to the EXPOSURE Register. As shown in Figure 32, this shutter mode will suppress the SUBCK and VSG outputs for up to 4095 fields (VD periods). The VD and HD outputs may be suppressed during the exposure period by programming the VDHDOFF Register to 1. VD HD VSG1– VSG8 tEXP tEXP SUBCK SUBCK PROGRAMMABLE SETTINGS: 1: PULSE POLARITY USING THE SUBCKPOL REGISTER 2: NUMBER OF PULSES WITHIN THE FIELD USING THE SUBCKNUM REGISTER 3: PIXEL LOCATION OF PULSE WITHIN THE LINE AND PULSE WIDTH PROGRAMMED USING SUBCK1 TOGGLE POSITION REGISTERS Figure 30. Normal Shutter Mode VD HD VSG1– VSG8 tEXP tEXP SUBCK NOTES 1. 2ND SUBCK PULSE IS ADDED IN THE LAST SUBCK LINE. 2. LOCATION OF 2ND PULSE IS FULLY PROGRAMMABLE USING THE SUBCK2 TOGGLE POSITION REGISTERS. Figure 31. High Precision Shutter Mode –26– REV. A AD9891/AD9895 SUBCK Suppression VSUB Control Normally, the SUBCKs will begin to pulse on the line following the sensor gate line (VSG). With some CCDs, the SUBCKs need to be suppressed for one or more lines following the VSG line. The SUBCKSUPPRESS Register allows for the suppression the SUBCK pulses for up to 63 lines following the VSG line. The CCD readout bias (VSUB) can be programmed to accommodate different CCDs. Figure 35 shows two different modes that are available. In Mode 0, VSUB goes active during the field of the last SUBCK when the exposure begins. The on-position (rising edge in Figure 35) is programmable to any line within the field. VSUB will remain active until the end of the image readout. In Mode 1, the VSUB is not activated until the start of the readout. Readout After Exposure A write to the EXPOSURE Register will designate the number fields in the exposure time (tEXP) from 0 to 4095. After the exposure, the readout of the CCD data occurs. During readout, the SUBCK output may need to be further suppressed until the readout is completed. The READOUT Register specifies the number of additional fields after the exposure to continue the suppression of SUBCK. READOUT can be programmed for zero to seven additional fields and should be preprogrammed at start-up, not at the same time as the exposure write. A typical interlaced CCD frame readout mode will generally require two additional fields of SUBCK suppression (READOUT = 2). Note that a write to the EXPOSURE Register acts as a trigger for readout after the exposure is completed. If no write to the EXPOSURE Register occurs, than the READOUT Register will have no effect. See Figure 35 for an example of triggering the exposure and subsequent readout. MSHUT and STROBE Control MSHUT and STROBE operation is shown in Figures 33, 34, and 35. Table XV shows the registers parameters for controlling the MSHUT and STROBE outputs. The MSHUT output is switched on with the MSHUTON Registers, and it will remain on until the location specified in the MSHUTOFF Registers. The location of MSHUTOFF is fully programmable to anywhere within the exposure period, using the FD (field), LN (line), and PX (pixel) Registers. The STROBE pulse is defined by the ON and OFF positions. STROBON_FD is the field in which the STROBE is turned on, measured from the field containing the last SUBCK before exposure begins. The STROBON_ LN and STROBON_PX Registers give the line and pixel positions with respect to STROBON_FD. The STROBE off position is programmable to any field, line, and pixel location with respect to the field of the last SUBCK. VD VSG1– VSG8 tEXP SUBCK NOTES 1. SUBCK MAY BE SUPPRESSED FOR MULTIPLE FIELDS BY PROGRAMMING THE EXPOSURE REGISTER GREATER THAN ZERO. 2. ABOVE EXAMPLE USES EXPOSURE = 1. 3. VD/HD OUTPUTS MAY ALSO BE SUPPRESSED USING THE VDHDOFF REGISTER = 1. Figure 32. Low Speed Shutter Mode Using EXPOSURE Register Table XIV. Electronic Shutter Mode Register Parameters Register Length Range Description SUBCKPOL* SUBCK1TOG1* SUBCK1TOG2* SUBCK2TOG1* SUBCK2TOG2* SUBCKNUM* SUBCKSUPPRESS* EXPOSURE 1b 12b 12b 12b 12b 12b 6b 12b HIGH/LOW 0–4095 Pixel Location 0–4095 Pixel Location 0–4095 Pixel Location 0–4095 Pixel Location 0–4095 # of Pulses 0–63 # of Pulses 0–4095 # of Fields VDHDOFF READOUT 1b 3b ON/OFF 0–7 # of Fields SUBCK Start Polarity for SUBCK1 and SUBCK2 SUBCK First Toggle Position SUBCK Second Toggle Position Second SUBCK First Toggle Position (for High Precision Mode) Second SUBCK Second Toggle Position (for High Precision Mode) Total Number of SUBCKs per Field (at 1 Pulse per Line) Number of SUBCK’s to Suppress after VSG Line Number of Fields to Suppress to SUBCK and VSG; Triggers Readout to Occur after tEXP Disable VD/HD Output during Exposure (1 = On, 0 = Off) Number of Fields to Suppress SUBCK after Exposure (for Readout) *Register is not VD/HD updated but is updated at the start of line after sensor gate line. REV. A –27– AD9891/AD9895 VD VSG1– VSG8 tEXP SUBCK MSHUT 1 2 3 MSHUT PROGRAMMABLE SETTINGS: 1: ACTIVE POLARITY 2: ON-POSITION IS VD UPDATED AND MAY BE SWITCHED ON AT ANY TIME 3: OFF-POSITION CAN BE PROGRAMMED ANYWHERE FROM THE FIELD OF LAST SUBCK UNTIL THE FIELD BEFORE READOUT Figure 33. MSHUT Output Programmability VD VSG1– VSG8 tEXP SUBCK STROBE 1 2 3 STROBE PROGRAMMABLE SETTINGS: 1: ACTIVE POLARITY 2: ON-POSITION WITH RESPECT TO TO FIELD OF LAST SUBCK 3: OFF-POSITION CAN BE PROGRAMMED ANYWHERE DURING THE EXPOSURE TIME Figure 34. STROBE Output Programmability Table XV. VSUB, MSHUT, and STROBE Register Parameters Register Length Range Description TRIGGER VSUBMODE VSUBKEEPON VSUBPOL VSUBON MSHUTON MSHUTONPOS_LN MSHUTONPOS_LN MSHUTPOL MSHUTOFF_FD MSHUTOFF_LN MSHUTOFF_PX STROBPOL STROBON_FD STROBON_LN STROBON_PX STROBOFF_FD STROBOFF_LN STROBOFF_PX 3b 1b 1b 1b 12b 1b 12b 12b 1b 12b 12b 12b 1b 12b 12b 12b 12b 12b 12b On/Off for Three Signals HIGH/LOW HIGH/LOW HIGH/LOW 0–4095 Line Location ON/OFF 0–4095 Line Location 0–4095 Pixel Location HIGH/LOW 0–4095 Field Location 0–4095 Line Location 0–4095 Pixel Location HIGH/LOW 0–4095 Field Location 0–4095 Line Location 0–4095 Pixel Location 0–4095 Field Location 0–4095 Line Location 0–4095 Pixel Location 1-Bit Triggers for VSUB[0], MSHUT[1], and STROBE[2] VSUB Mode (0 = Mode 0, 1 = Mode 1) (See Figure 27) Sets VSUB to Stay Active after Readout When High VSUB Active Polarity VSUB On Position. Active starting in any line of field. MSHUT Signal Enable (1 = Active or “Open”) MSHUT Line Location MSHUTON Pixel Location MSHUT Active Polarity Field Location to Switch OFF MSHUT. (Inactive or “Closed”) Line Location to Switch OFF MSHUT. (Inactive or “Closed”) Pixel Location to Switch OFF MSHUT. (Inactive or “Closed”) STROBE Active Polarity STROBE ON Field Location, with Respect to Last SUBCK Field STROBE ON Line Location STROBE ON Pixel Location STROBE OFF Field Location, with Respect to Last SUBCK Field STROBE OFF Location STROBE OFF Location –28– REV. A AD9891/AD9895 SERIAL WRITES ODD VD EVEN IMAGE READOUT VSG tEXP SUBCK STROBE MSHUT OPEN MECHANICAL SHUTTER VSUB MODE 0 CLOSED OPEN MODE 1 Figure 35. Exposure and Readout of Interlaced Frame STROBE output turns ON at the location specified in the STROBON Registers (Addr x294 to Addr x299). Example of Exposure and Readout of Interlaced Frame Figure 35 shows the sequence of events for a typical exposure and readout operation using a mechanical shutter and strobe. The register values for the VSUB, MSHUT, and STROBE toggle positions may be previously loaded at any time, prior to triggering these functions. Additional register writes are required to configure the vertical clock outputs, V1–V4, which are not described here. 4: STROBE output turns OFF at the location specified in the STROBEOFF Registers (Addr x29A to Addr x29F). 5: MSHUT Output turns OFF at the location specified in the MSHUTOFF Registers (Addr x28D to Addr x292). 0: Write to the READOUT Register (Addr x281) to specify the number of fields to further suppress SUBCK while the CCD data is readout. In this example, READOUT = 2. 6: Write to the SGACTLINE Register (Addr x253 and Addr x254) and SGMASK Register to configure the sensor gates for EVEN field readout. 1: Write to the EXPOSURE Register (Addr x27D) to start the exposure and specify the number of fields to suppress SUBCK and VSG outputs during exposure. In this example, EXPOSURE = 2. 7: VD/HD falling edge will update the serial writes from 6. 8: Write to the SGACTLINE Register and SGMASK Register to reconfigure the sensor gates for Draft/Preview Mode output. Write to the MSHUTON Register (Addr x287) to reopen the mechanical shutter for Draft/Preview Mode. Write to the TRIGGER Register (Addr x280) to enable the STROBE, MSHUT, and VSUB signals. To trigger all three signals (as in Figure 36) the register TRIGGER = 7. Write to the SGACTLINE Register (Addr x265 and Addr x266) and SGMASK Register (Addr x26F and Addr x270) to configure the sensor gates for ODD field readout (interlaced CCD). 9: VD/HD falling edge will update the serial writes from 8. 10: VSG outputs returns to Draft/Preview Mode timing. SUBCK output resumes operation. MSHUT output returns to the ON position (Active or “Open”). 2: VD/HD falling edge will update the serial writes from 1. VSUB output returns to the OFF position (Inactive). 3: If VSUB Mode = 0, VSUB output turns ON at the line specified in the VSUBON Register (Addr x272 and Addr x273). REV. A –29– AD9891/AD9895 system black level. Another advantage of removing this offset at the input stage is to maximize system headroom. Some area CCDs have large black level offset voltages, which, if not corrected at the input stage, can significantly reduce the available headroom in the internal circuitry when higher VGA gain settings are used. ANALOG FRONT END DESCRIPTION AND OPERATION The AD9891/AD9895 AFE signal processing chain is shown in Figure 36. Each processing step is essential in achieving a high quality image from the raw CCD pixel data. AFE Register details are shown in Table XXXI. DC Restore The input clamp is controlled by the CLPDM signal, which is fully programmable (see Horizontal Clamping and Blanking section). System timing examples are shown in the Horizontal Timing Sequence Example section. It is recommended that the CLPDM pulse be used during valid CCD dark pixels. CLPDM may be used during the optical black pixels, either together with CLPOB or separately. The CLPDM pulse should be a minimum of 4 pixels wide. To reduce the large dc offset of the CCD output signal, a dcrestore circuit is used with an external 0.1 µF series coupling capacitor. This restores the dc level of the CCD signal to approximately 1.5 V, to be compatible with the 3 V analog supply of the AD9891/AD9895. Correlated Double Sampler The CDS circuit samples each CCD pixel twice to extract the video information and reject low frequency noise. The timing shown in Figure 10 illustrates how the two internally generated CDS clocks, SHP and SHD, are used to sample the reference level and the data level, respectively, of the CCD signal. The placement of the SHP and SHD sampling edges is determined by the setting of the SHPPOSLOC and SHDPOSLOC Registers located at Addr 0xE9 and Addr 0xEA, respectively. Placement of these two clock signals is critical in achieving the best performance from the CCD. PxGA The PxGA provides separate gain adjustment for the individual color pixels. A programmable gain amplifier with four separate values, the PxGA has the capability to “multiplex” its gain value on a pixel-to-pixel basis (see Figure 37). This allows lower output color pixels to be gained up to match higher output color pixels. Also, the PxGA may be used to adjust the colors for white balance, reducing the amount of digital processing that is needed. The four different gain values are switched according to the “color steering” circuitry. Seven different color steering modes for different types of CCD color filter arrays are programmed in the AD9891/AD9895 AFE CTLMODE Register, at Addr 0x06 (see Figures 39a–39g for internal color steering timing). For Input Clamp A line-rate input clamping circuit is used to remove the CCD’s optical black offset. This offset exists in the CCD’s shielded black reference pixels. The AD9891/AD9895 remove this offset in the input stage to minimize the effect of a gain change on the 1.0F REFT 1.0F REFB 2.0V 1.0V DC RESTORE INTERNAL VREF 1.5V SHP SHD –2dB TO +10dB 0.1F CCDIN CDS 0dB TO 36dB 10 CLPDM VGA GAIN REGISTER INPUT OFFSET CLAMP 0.1F 0.1F 0.1F 8-BIT DAC 10 or 12 DOUT OPTICAL BLACK CLAMP CLPOB PBLK DIGITAL FILTER BYP1 8 BYP2 BYP3 OUTPUT DATA LATCH ADC VGA PxGA DOUT PHASE 2V FULL SCALE SHP SHD DOUT PHASE PRECISION TIMING GENERATION CLPDM CLPOB PBLK CLAMP LEVEL REGISTER V-H TIMING GENERATION Figure 36. AFE Block Diagram –30– REV. A AD9891/AD9895 example, the Mosaic Separate Steering Mode accommodates the popular “Bayer” arrangement of Red, Green, and Blue filters (see Figure 38a). The same Bayer pattern can also be interlaced, and the Mosaic Interlaced Mode should be used with this type of CCD (see Figure 38b). The color steering performs the proper multiplexing of the R, G, and B gain values (loaded into the PxGA gain registers) and is synchronized by the vertical (VD) and horizontal (HD) sync pulses. The PxGA gain for each of the four channels is variable from –2 dB to +10 dB, controlled in 64 steps through the serial interface. The PxGA gain curve is shown in Figure 40. VD 3 COLOR STEERING CONTROL HD SHP/SHD PxGA STEERING MODE SELECTION MOSAIC SEPARATE COLOR STEERING MODE CCD: PROGRESSIVE BAYER R Gr R Gr LINE0 GAIN0, GAIN1, GAIN0, GAIN1, ... Gb B Gb B LINE1 GAIN2, GAIN3, GAIN2, GAIN3, ... R Gr R Gr LINE2 GAIN0, GAIN1, GAIN0, GAIN1, ... Gb B Gb B Figure 38a. CCD Color Filter Example: Progressive Scan MOSAIC INTERLACED COLOR STEERING MODE CCD: INTERLACED BAYER EVEN FIELD CONTROL REGISTER BITS D0:D2 R Gr R Gr LINE0 GAIN0, GAIN1, GAIN0, GAIN1, ... R Gr R Gr LINE1 GAIN0, GAIN1, GAIN0, GAIN1, ... R Gr R Gr LINE2 GAIN0, GAIN1, GAIN0, GAIN1, ... R Gr R Gr 2 GAIN0 GAIN1 4:1 MUX 6 CDS PxGA GAIN REGISTERS GAIN2 ODD FIELD GAIN3 VGA PxGA Figure 37. PxGA Block Diagram FLD Gb B Gb B LINE0 GAIN2, GAIN3, GAIN2, GAIN3, ... Gb B Gb B LINE1 GAIN2, GAIN3, GAIN2, GAIN3, ... Gb B Gb B LINE2 GAIN2, GAIN3, GAIN2, GAIN3, ... Gb B Gb B Figure 38b. CCD Color Filter Example: Interlaced ODD FIELD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 0 1 2 3 2 3 0 1 0 1 0 1 0 1 2 3 2 3 0 1 0 1 0 NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE. 2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “0101” AND “2323” LINES. 3. FLD STATUS IS IGNORED. Figure 39a. Mosaic Separate Color Steering Mode ODD FIELD FLD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 0 1 0 1 0 1 0 1 0 1 2 3 2 3 2 3 2 NOTES 1. FLD FALLING EDGE (START OF ODD FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “0101” LINE. 2. FLD RISING EDGE (START OF EVEN FIELD) WILL RESET THE PxGA GAIN REGISTER STEERING TO “2323” LINE. 3. HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO EITHER “0” (FLD = ODD) OR “2” (FLD = EVEN). Figure 39b. Mosaic Interlaced Color Steering Mode REV. A –31– 3 2 3 2 3 0 AD9891/AD9895 FLD ODD FIELD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 0 1 1 2 1 2 0 1 0 1 0 1 0 1 1 2 1 2 0 1 0 1 0 0 1 2 0 0 0 1 2 0 0 0 1 2 3 0 NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN STEERING TO “0101” LINE. 2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN STEERING BETWEEN “0101” AND “1212” LINES. 3. ALL FIELDS WILL HAVE THE SAME PxGA GAIN STEERING PATTERN (FLD STATUS IS IGNORED). Figure 39c. Mosaic Repeat Color Steering Mode FLD ODD FIELD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 2 0 0 1 2 0 0 1 2 0 0 1 2 0 0 1 2 0 NOTES 1. EACH LINE FOLLOWS “012012” STEERING PATTERN. 2. VD AND HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO GAIN REGISTER “0.” 3. FLD STATUS IS IGNORED. Figure 39d. 3-Color 1-Color Steering Mode FLD ODD FIELD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 2 0 2 1 0 2 0 1 2 0 0 1 2 0 2 1 0 2 NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “012012” LINE. 2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “012012” AND “210210” LINES. 3. FLD STATUS IS IGNORED. Figure 39e. 3-Color 2-Color Steering Mode FLD ODD FIELD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 NOTES 1. EACH LINE FOLLOWS “01230123” STEERING PATTERN. 2. VD AND HD FALLING EDGES WILL RESET THE PxGA GAIN REGISTER STEERING TO GAIN REGISTER “0.” 3. FLD STATUS IS IGNORED. Figure 39f. 4-Color 1-Color Steering Mode –32– REV. A AD9891/AD9895 FLD ODD FIELD EVEN FIELD VD HD PxGA GAIN REGISTER X X 0 1 2 3 2 3 0 1 0 1 2 3 0 1 2 3 2 3 0 1 0 1 2 3 0 NOTES 1. VD FALLING EDGE WILL RESET THE PxGA GAIN REGISTER STEERING TO “01230123” LINE. 2. HD FALLING EDGES WILL ALTERNATE THE PxGA GAIN REGISTER STEERING BETWEEN “01230123” AND “23012301” LINES. 3. FLD STATUS IS IGNORED. Figure 39g. 4-Color 2-Color Steering Mode The VGA gain curve follows a “linear-in-dB” characteristic. The exact VGA gain can be calculated for any gain register value by using the equation: 10 8 Gain = (0.035 × Code ) + 3.55 PxGA GAIN – dB 6 where the code range is 0 to 1023. PxGA default gain is included. 4 The gain accuracy specifications include the PxGA gain of approximately 4 dB, for a total gain range of 6 dB to 40 dB. 2 Optical Black Clamp 0 –2 –4 32 (100000) 40 48 58 0 8 16 24 31 (011111) PxGA GAIN REGISTER CODE Figure 40. PxGA Gain Curve 36 VGA GAIN – dB 30 24 18 12 6 0 0 127 255 383 511 639 767 VGA GAIN REGISTER CODE 895 1023 Figure 41. VGA Gain Curve (PxGA not included) Variable Gain Amplifier The VGA stage provides a gain range of 2 dB to 36 dB, programmable with 10-bit resolution through the serial digital interface. Combined with approximately 4 dB from the PxGA stage, the total gain range for the AD9891/AD9895 is 6 dB to 40 dB. The minimum gain of 6 dB is needed to match a 1 V input signal with the ADC full-scale range of 2 V. When compared to 1 V full-scale systems (such as ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB. REV. A The optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the CCD’s black level. During the optical black (shielded) pixel interval on each line, the ADC output is compared with a fixed black level reference selected by the user in the Clamp Level Register. The clamp level is programmable in 256 steps, with a range between 0 LSB and 63.75 LSB in the AD9891 and between 0 LSB and 255 LSB in the AD9895. The resulting error signal is filtered to reduce noise, and the correction value is applied to the ADC input through a D/A converter. Normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. If external digital clamping is used during the post- processing, the AD9891/AD9895 optical black clamping may be disabled using Bit D5 in the Operation Register (see Serial Interface Timing and Register Listing sections). When the loop is disabled, the Clamp Level Register may still be used to provide programmable offset adjustment. The optical black clamp is controlled by the CLPOB signal, which is fully programmable (see Horizontal Clamping and Blanking section). System timing examples are shown in the Horizontal Timing Sequence Example section. The CLPOB pulse should be placed during the CCD’s optical black pixels. It is recommended that the CLPOB pulse duration be at least 20 pixels wide. Shorter pulsewidths may be used, but the ability to track low frequency variations in the black level will be reduced. A/D Converter The AD9891 uses a high a performance 10-bit ADC architecture, optimized for high speed and low power, while the AD9895 uses a 12-bit ADC architecture. Differential nonlinearity (DNL) performance is typically better than 0.5 LSB for both products. The ADC uses a 2 V input range. Better noise performance results from using a larger ADC fullscale range. –33– AD9891/AD9895 VDD (INPUT) CLI (INPUT) tPWR SERIAL WRITES SYNC (INPUT) 1V VD (OUTPUT) ODD FIELD EVEN FIELD 1H HD (OUTPUT) H2/H4 DIGITAL OUTPUTS H1/H3, RG, DCLK CLOCKS ACTIVE WHEN OUT_CONT REGISTER IS UPDATED AT VD/HD EDGE Figure 42. Recommended Power-Up Sequence and Synchronization, Master Mode 9. Write to desired registers to configure high speed timing, horizontal timing, vertical timing, and shutter timing. POWER-UP AND SYNCHRONIZATION Recommended Power-Up Sequence for Master Mode When the AD9891/AD9895 are powered up, the following sequence is recommended (refer to Figure 42 for each step). 10. If SYNC is HIGH at power-up, then bring SYNC input LOW. Also, SYNC may be held low from power-up. 1. Turn on power supplies for the AD9891/AD9895. 11. Write a “1” to the OUT_CONT Register (Addr x018). This will allow the outputs to become active after SYNC rising edge. 2. Apply the master clock input CLI. 3. Reset and initialize the internal AD9891/AD9895 Registers. First, write a “1” to the SW_RESET Register (Addr x017) followed by a “0” to the same register. Next, write “110101” (53 decimal) to the INITIAL1 Register (Addr x02B) followed by “000100” (4 decimal) to the INTIAL2 Register (Addr x010). This sequence of writes must always be done in the proper order: Addr x017 Data 000001 Addr x017 Data 000000 Addr x02B Data 110101 Addr x010 Data 000100 12. Write a “0” to the PREVENTUPDATE Register (Addr x01B). This will allow the serial information to be updated at the next VD/HD falling edge. 13. Bring SYNC back HIGH. This will cause the internal counters to reset to “0” and start VD/HD operation. VD/HD edge allows register updates to occur, including OUT_CONT, which enables all clock outputs. SYNC During Master Mode Operation 4. Configure the AD9891/AD9895 for Master Mode timing by writing a “1” to the MASTER Register (Addr x0EB). 5. By default, the internal timing core is held in a reset state with TGCORE_RSTB Register = “0.” Write a “1” to the TGCORE_RSTB Register (Addr x029) to start the internal timing core operation. 6. Write a “1” to the PREVENTUPDATE Register (Addr x01B). This will prevent any updating of the serial register data. The SYNC input may be used any time during operation to resync the AD9891/AD9895 counters with external timing, as shown in Figure 43. The operation of the digital outputs may be suspended during the SYNC operation by setting the SYNCSUSPEND Register (Addr x026) to a “1.” Synchronization in Slave Mode When the AD9891/AD9895 is used in Slave Mode, the VD and HD inputs are used to synchronize the internal counters. Following a falling edge of VD, there will be a latency of eight master clock cycles (CLI) after the falling edge of HD until the internal H-counter will be reset. The reset operation is shown in Figure 44. 7. Write a “1” to the SYNCENABLE Register (Addr x024). This will allow the external SYNC to be used. 8. Write a “1” to the SYNCSUSPEND Register (Addr x026). This will cause the outputs to be suspended during the SYNC operation (see Figure 43). –34– REV. A AD9891/AD9895 SYNC VD SUSPEND HD H124, RG, V1–V4, VSG, SUBCK NOTES 1. SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO ZERO. 2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR x025). 3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR x026). 4. IF SYNCSUSPEND = 1, VERTICAL CLOCKS AND H1–H2, RG ARE HELD AT THEIR DEFAULT POLARITIES. 5. IF SYNCSUSPEND = 0, THEN ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL SYNC RESET EDGE. Figure 43. SYNC Timing to Synchronize AD989x with External Timing VD H-COUNTER RESET HD 3ns MIN CLI H-COUNTER (PIXEL COUNTER) X X X X X X X X X 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 1 2 3 PxGA GAIN REGISTER X X X X X X X X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 2 3 2 3 4 NOTES 1. INTERNAL H-COUNTER IS RESET 8 CLOCK CYCLES AFTER THE HD FALLING EDGE. 2. PxGA STEERING IS SYNCHRONIZED WITH THE RESET OF THE INTERNAL H-COUNTER (MOSAIC SEPARATE MODE IS SHOWN). Figure 44. External VD/HD and Internal H-Counter Synchronization, SLAVE Mode POWER-DOWN MODE OPERATION The AD9891/AD9895 contain three different power-down modes to optimize the overall power dissipation in a particular application. Bits [1:0] of the OPRMODE Register control the power-down state of the device: OPR_MODE [1:0] = 00 = Normal Operation (full power) OPR_MODE[1:0] = 01 = Power-Down 1 Mode OPR_MODE[1:0] = 10 = Power-Down 2 Mode OPR_MODE[1:0] = 11 = Power-Down 3 Mode (lowest overall power) REV. A Table XVI summarizes the operation of each power-down mode. Note that in any mode, the OUT_CONT Register takes priority over the power-down modes where the digital output states are concerned. Power-Down 3 Mode has the lowest power consumption, and it even powers down the crystal oscillator circuit between CLI and CLO. Thus, if CLI and CLO are being used with a crystal to generate the master clock, this circuit will be powered down and there will be no clock signal. When returning from Power-Down 3 Mode to normal operation, the timing core must be reset at least 500 ms after the OPR_MODE Register is written to. This will allow sufficient time for the crystal circuit to settle. –35– AD9891/AD9895 Table XVI. Power-Down Mode Operation I/O Block OUT_CONT== LOW1 Power-Down 11 Power-Down 21, 2 Power-Down 31, 3, 4 AFE ON OFF OFF OFF Timing Core ON ON OFF OFF CLO Oscillator ON ON ON OFF V1 LOW LOW LOW LOW V2 LOW LOW LOW LOW V3 HIGH HIGH HIGH LOW V4 HIGH HIGH HIGH LOW VSG1 HIGH HIGH HIGH LOW VSG2 HIGH HIGH HIGH LOW VSG3 HIGH HIGH HIGH LOW VSG4 HIGH HIGH HIGH LOW VSG5 HIGH HIGH HIGH LOW VSG6 HIGH HIGH HIGH LOW VSG7 HIGH HIGH HIGH LOW VSG8 HIGH HIGH HIGH LOW SUBCK HIGH HIGH HIGH LOW VSUB LOW LOW LOW LOW MSHUT LOW LOW LOW LOW STROBE LOW LOW LOW LOW H1 LOW LOW LOW (3.5 mA) Hi-Z H2 HIGH HIGH HIGH (3.5 mA) Hi-Z H3 LOW LOW LOW (3.5 mA) Hi-Z H4 HIGH HIGH HIGH (3.5 mA) Hi-Z RG LOW LOW LOW (3.5 mA) Hi-Z LD/FD LOW LOW LOW LOW CLPOB/ PBLK HIGH HIGH HIGH LOW VD vdhdpol running vdhdpol LOW HD vdhdpol running vdhdpol LOW DCLK LOW running LOW LOW CLO running running running HIGH DOUT LOW LOW LOW LOW NOTES 1 First column represents the defaults when OUT_CONT==LO (OUT_CONT takes precedence). Power-Down 1, 2, and 3 are direct decodes of the OPR MODE Register Bits [1:0]. These polarities assume OUT_CONT==HI. 2 Power-Down 2 will set H[1,2,3,4]DRV and RGDRV to 3’h1 (3.5 mA). Power -Down 3 will three-state the H and RG clocks (set H[1,2,3,4]DRV and RGDRV to 3’h0). 3 Both the Timing Core and the CLO Oscillator will be powered down in Power-Down 3. 4 To exit Power-Down 3, first write a 2’b00 to OPRMODE[1:0] (will wake up the oscillator and the timing core), then reset the timing core after ~500 µs to guarantee lock. –36– REV. A AD9891/AD9895 HORIZONTAL TIMING SEQUENCE EXAMPLE Figure 45 shows an example CCD layout. The horizontal register contains 28 dummy pixels that will occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at the front of the readout and two at the back of the readout. The horizontal direction has four OB pixels in the front and 48 in the back. To configure the AD9891/AD9895 horizontal signals for this CCD, three sequences can be used. Figure 46 shows the first sequence to be used during vertical blanking. During this time, there are no valid OB pixels from the sensor, so the CLPOB and CLPDM signals are not used. In some cases, if the horizontal clocks are used during this time, the CLPDM signal may be used to keep the AD9891/AD9895’s input clamp partially settled. PBLK may be enabled during this time because no valid data is available. Figure 47 shows the recommended sequence for the vertical OB interval. The clamp signals are used across the whole lines in order to stabilize the clamp loops of the AD9891/AD9895. Figure 48 shows the recommended sequence for the effective pixel readout. The 48 OB pixels at the end of each line are used for the CLPOB and CLPDM signals. SEQUENCE 2 (OPTIONAL) 2 VERTICAL OB LINES USE SEQUENCE 3 EFFECTIVE IMAGE AREA V 10 VERTICAL OB LINES USE SEQUENCE 2 H 48 OB PIXELS 4 OB PIXELS HORIZONTAL CCD REGISTER 28 DUMMY PIXELS Figure 45. Example CCD Configuration SEQUENCE 1: VERTICAL BLANKING CCDIN INVALID PIX VERTICAL SHIFT DUMMY INVALID PIXELS SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM CLPDM PULSE MAY BE USED DURING HORIZONTAL DUMMY PIXELS IF THE H-CLOCKS ARE USED DURING VERTICAL BLANKING. Figure 46. Horizontal Sequences During Vertical Blanking REV. A –37– VERT SHIFT AD9891/AD9895 SEQUENCE 2: VERTICAL OPTICAL BLACK LINES CCDIN OPTICAL BLACK VERTICAL SHIFT DUMMY OPTICAL BLACK VERT SHIFT SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM Figure 47. Horizontal Sequences During Vertical Optical Black Pixels SEQUENCE 3: EFFECTIVE PIXEL LINES OB CCDIN OPTICAL BLACK VERTICAL SHIFT DUMMY EFFECTIVE PIXELS OPTICAL BLACK VERT SHIFT SHP SHD H1/H3 H2/H4 HBLK PBLK CLPOB CLPDM Figure 48. Horizontal Sequences During Effective Pixels –38– REV. A AD9891/AD9895 Region Area 2 is the sensor gate line, where the VSG pulses transfer the image into the vertical CCD registers. This region will require the use of the second vertical sequence for SG lines. VERTICAL TIMING EXAMPLE Figure 49 shows an example CCD timing chart for an interlaced readout. Each field can be broken down into four separate region areas. The vertical region change positions (RCPs) will set the line boundaries for each region area, and the region pointers will assign a unique region to each region area. Region Area 3 also uses the standard single line vertical shift timing, the same timing as Region Area 1. In summary, three unique regions are required to support the four region areas, since Region Areas 1 and 3 use the same timing. Region Area 0 is a high speed vertical shift region. Sweep Mode can be used to generate this timing operation, with the desired number of high speed vertical pulses needed to “clean” the charge from the CCD’s vertical registers. Some of the timing parameters will need to be adjusted to read out the second field, such as the sensor gate pulse and line location. Region Area 1 consists of only two lines and uses standard single line vertical shift timing. The timing of this region area will be the same as the timing in Region Area 3. EXPOSURE PERIOD (tEXP) INTERLACED READOUT PERIOD VD HD V1/VSG1 V2 V3/VSG2 V4 SUBCK MSHUT OPEN CLOSE OPEN REGION AREA 0 REGION AREA 3 REGION AREA 1 REGION AREA 2 Figure 49. Vertical Timing Example—Separate Regions REV. A –39– n–2 n 2 4 6 8 10 12 14 16 18 20 CCD OUT n–3 n–1 1 3 5 7 9 11 13 15 17 19 VSUB AD9891/AD9895 The H1–H4 and RG traces should be designed to have low inductance to avoid excessive distortion of the signals. Heavier traces are recommended because of the large transient current demand on H1–H4 by the CCD. If possible, physically locating the AD9891/AD9895 closer to the CCD will reduce the inductance on these lines. As always, the routing path should be as direct as possible from the AD9891/AD9895 to the CCD. CIRCUIT LAYOUT INFORMATION The AD9891/AD9895 Typical Circuit Connection is shown in Figure 50. Note that Pins E1 and E2 will be No Connects when using the AD9891. The PCB layout is critical in achieving good image quality from the AD989x products. All of the supply pins, particularly the AVDD1, TCVDD, RGVDD, and HVDD supplies, must be decoupled to ground with good quality high frequency chip capacitors. The decoupling capacitors should be located as close as possible to the supply pins and should have a very low impedance path to a continuous ground plane. There should also be a 4.7 µF or larger value bypass capacitor for each main supply—AVDD, RGVDD, HVDD, and DRVDD —although this is not necessary for each individual pin. In most applications, it is easier to share the supply for RGVDD and HVDD, which may be done as long as the individual supply pins are separately bypassed. A separate 3 V supply may also be used for DRVDD, but this supply pin should still be decoupled to the same ground plane as the rest of the chip. A separate ground for DRVSS is not recommended. The AD9891/AD9895 also contains an on-chip oscillator for driving an external crystal. Figure 51 shows an example application using a typical 18 MHz crystal. For the exact values of the external resistors and capacitors, it is best to consult with the crystal manufacturer’s data sheet. AD9891/AD9895 C10 CLI CLO 1M The analog bypass pins (BYP1–3, VRB, VRT) should also be carefully decoupled to ground as close as possible to their respective pins. The analog input (CCDIN) capacitor should also be located close to the pin. 20pF 500 20pF 18MHz XTAL Figure 51. Crystal Driver Application 3V ANALOG SUPPLY TO STROBE CIRCUIT 0.1F TO MECHANICAL SHUTTER CIRCUIT EXTERNAL SYNC FROM ASIC/DSP SL B5 A4 SCK SDI A3 B4 B3 LD/FD STROBE MSHUT C2 SYNC CLPOB/PBLK D2 A1 C1 DVSS DVDD VD B2 A2 DCLK HD B1 D1 D1 D0(LSB) A10 B10 J3 C9 J4 C10 K5 D10 REFT 1F REFB 1F + 4.7F AVSS2 3V ANALOG SUPPLY AVDD2 BYP3 0.1F CCDIN BYP2 0.1F BYP1 0.1F 0.1F OUTPUT FROM CCD 0.1F AVSS1 3V ANALOG SUPPLY AVDD1 TCVDD TCVSS CLI 0.1F MASTER CLOCK INPUT CLO RGVDD + 4.7F RG 5V RG SUPPLY E9 F9 F10 G10 D9 G9 E10 K6 H9 J5 J6 V3 B9 K4 RGVSS H4 H3 HVDD H2 HVSS H1 VSG8 VSG7 VSG5 0.1F V4 VSUB TO CCD K3 A9 H10 V2 TOP VIEW (Not to Scale) J10 V1 AD9895 K1 K10 VSUB SUBCK B8 K2 VSG6 4.7F J1 VSG4/V8 + DRVSS A8 VSG3/V7 0.1F J2 J9 DRVDD A7 VSG2/V6 3V DRIVER SUPPLY (MSB) D11 H1 VSG1/V5 10 DATA OUTPUTS B7 K9 D10 B6 H2 J8 D9 A6 G1 K8 D8 A5 G2 J7 D7 E2 F2 D5 D6 SERIAL INTERFACE TO ASIC OR DSP F1 K7 D3 E1 D2 LINE/FIELD/CLAMP SYNC TO ASIC/DSP D4 3 5 9 0.1F V1–V4, VSG1–VSG4, SUBCK TO V-DRIVER RG, H1–H4 TO CCD 5 + 4.7F 5V H1–H4 SUPPLY Figure 50. AD9891/AD9895 Typical Circuit Configuration –40– REV. A AD9891/AD9895 bits located in the higher of the two addresses. For example, the six LSBs of the OPRMODE Register, OPRMODE[5:0], are located at Addr 0x00. The most significant six bits of the OPRMODE Register, OPRMODE[11:6], are located at Addr 0x1. The following rules must be followed when accessing double-wide registers: SERIAL INTERFACE TIMING All of the internal registers of the AD9891/AD9895 are accessed through a 3-wire serial interface. Each register consists of a 10-bit address and a 6-bit data-word. Both the 10-bit address and 6-bit data-word are written starting with the LSB. To write to each register, a 16-bit operation is required, as shown in Figure 52. Although many registers are less than six bits wide, all six bits must be written to for each register. If the register is only two bits wide, then the upper four bits are Don’t Cares and can be filled with 0s during the serial write operation. If less than six bits are written, the register will not be updated with new data. 1. When accessing a double-wide register, BOTH addresses must be written to. 2. The lower of the two consecutive addresses for the doublewide register must be written to first. In the example of the OPRMODE Register, the contents of Addr 0x00 must be written first followed by the contents of Addr 0x01. The register will be internally updated after the completion of the write to Register 0x01, either at the next SL rising edge or the next VD/HD falling edge depending on the register. Because of the large number of registers in the AD9891/AD9895, Figure 53 shows a more efficient way to write to the registers, using the AD9891/AD9895’s address auto-increment capability. Using this method, the lowest desired address is written first, followed by multiple 6-bit data-words. Each new 6-bit data-word will automatically be written to the next highest register address. By eliminating the need for each 10-bit address to be written, faster register loading is accomplished. Address auto-increment may be used starting with any register location and may be used to write to as few as two registers or as many as the entire register space. 3. A single write to the lower of the two consecutive addresses of a double-wide register that is not followed by a write to the higher address of the registers is not supported. This will not update the register. 4. A single write to the higher of the two consecutive addresses of a double-wide register that is not preceded by a write to the lower of the two addresses is not supported. Although the write to the higher address will update the full doublewide register, the lower six bits of the register will be written with an indeterminate value if the lower address was not written to first. Notes About Accessing a Double-Wide Register There are many double-wide registers in the AD9891/ AD9895. These registers are configured into two consecutive 6-bit registers with the least significant six bits located in the lower of the two addresses and the remaining most significant SDATA A0 A1 A2 A3 tDS A4 A5 A6 A7 A8 A9 D0 D1 D2 D3 D4 D5 tDH SCK tLH tLS SL SL UPDATED VD/HD UPDATED VD HD NOTES SDATA BITS ARE LATCHED ON SCK RISING EDGES. EACH INTERNAL REGISTER IS PRELOADED WITH NEW DATA AT SL RISING EDGE. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER. Figure 52. Serial Write Operation DATA FOR STARTING REGISTER ADDRESS SDATA A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 D0 D1 D2 D3 D4 DATA FOR NEXT REGISTER ADDRESS D5 D0 D1 D2 D3 SCK SL NOTES MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN FOLLOWED BY MULTIPLE 6-BIT DATA-WORDS. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 6-BIT DATA-WORD. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE. Figure 53. Continuous Serial Write Operation REV. A –41– D4 D5 D0 AD9891/AD9895 NOTES ON REGISTER LISTING Table XVIII. SG-Line Updated Registers 1. Registers larger than six bits occupy two adjacent addresses. When writing to these registers, the lower address containing the least significant data bits should be written to first. The data for both addresses should be written to avoid corruption of register data. 2. All addresses and default values are expressed in hexadecimal. 3. All registers are VD/HD updated as shown in Figure 52, except for the registers indicated in Table XVII, which are SL updated. Register SUBCKPOL SUBCK1TOG1 SUBCK1TOG2 SUBCK2TOG1 SUBCK2TOG2 SUBCKNUM SUBCKSUPPRESS 4. The registers indicated in Table XVIII are not updated by SL or VD/HD, but are updated at the HD line following the VSG line. Description SUBCK Start Polarity SUBCK First Toggle Position SUBCK Second Toggle Position Second SUBCK First Toggle Position Second SUBCK Second Toggle Position Total Number of SUBCKs per Field Number of SUBCKs to Suppress after VSG Line Table XVII. SL-Updated Register Register Description OPRMODE CTLMODE SW_RESET READBACK AFE Operation Modes AFE Control Modes Software Reset Bit Enables Serial Register Readback Mode Resets Internal Field Pulse. Retimes the H1 HBLK to Internal Clock Retimes the H3 HBLK to Internal Clock External Synchronization Enable External SYNC Active Polarity SYNC Suspend while Active Reset Bar Signal for Internal TG Core Frame Transfer CCD Mode H1/H2 Polarity Control H1 Positive Edge Location H1 Negative Edge Location H3/H4 Polarity Control H3 Positive Edge Location H3 Negative Edge Location H1 Drive Current H2 Drive Current H3 Drive Current H4 Drive Current RG Polarity RG Positive Edge Location RG Negative Edge Location SHP Sample Location SHD Sample Location VD/HD Master/Slave Timing Mode VD/HD Active Polarity Sets CLPDM = CLPOB Sets the Output Delay of DOUT Powers Down the CLO Oscillator VD/HD Active Polarity FIELDVAL H1HBLKRETIME H3HBLKRETIME SYNCENABLE SYNCPOL SYNCSUSPEND TG_CORE RSTB FFTRANCCD H12POL H1POSLOC H1NEGLOC H34POL H3POSLOC H3NEGLOC H1DRV H2DRV H3DRV H4DRV RGPOL RGPOSLOC RGNEGLOC SHPLOC SHDLOC MASTER VDHDPOL SINGLE_CLAMP DOUT_DELAY OSC_PWRDOWN VDHDPOL –42– REV. A AD9891/AD9895 Table XIX. AFE Register Map Address Content Bit Width Default Value Register Name Register Description 00 01 02 03 04 05 06 07 08 09 0A [5:0] [1:0] [5:0] [3:0] [5:0] [1:0] [5:0] [5:0] [5:0] [5:0] [5:0] 6 2 6 4 6 2 6 6 6 6 6 10 00 05 01 00 02 00 00 00 00 00 OPRMODE[5:0] OPRMODE[7:6] CCDGAIN[5:0] CCDGAIN[9:6] REFBLACK[5:0] REFBLACK[7:6] CTLMODE PXGA GAIN0 PXGA GAIN1 PXGA GAIN2 PXGA GAIN3 AFE Operation Mode (See Table XXXI.) VGA Gain (Defaults to 2 dB) Black Clamp Level Control Mode (See Table XXXI.) PxGA Color 0 Gain PxGA Color 1 Gain PxGA Color 2 Gain PxGA Color 3 Gain Table XX. MISCELLANEOUS/EXTRA Register Map Address Content Bit Width Default Value Register Name Register Description 010 017 018 019 [5:0] [0] [0] [5:0] 6 1 1 6 00 00 00 00 INTIAL2 SW_RESET OUT_CONT UPDATE[5:0] See Power-Up Sequence. Should be set to “4.” Software Reset (1 = Reset All Registers to Default) Output Control (0 = Make All Outputs DC Inactive) Serial Data Update Control. Sets the line (HD) within the field for the serial data update to occur. 01A 01B 01C 01D 01E [5:0] [0] [0] [5:0] [0] 6 1 1 6 1 00 00 00 00 00 UPDATE[11:6] PREVENTUPDATE READBACK DOUTPHASE DCLKMODE 01F 020 [0] [0] 1 1 00 00 CLIDIVIDE DISABLERESTORE 021 [0] 1 01 FIELDVAL 022 023 024 025 026 027 028 [0] [0] [0] [0] [0] [0] [0] 1 1 1 1 1 1 1 00 00 00 00 00 00 00 H1HBLKRETIME H3HBLKRETIME SYNCENABLE SYNCPOL SYNCSUSPEND OUTPUTLD OUTPUTPBLK 029 [0] 1 00 TGCORE_RSTB 02A [0] 1 00 FTRANCCD 02B 031 [5:0] [0] 6 1 00 01 INTIAL1 SINGLE_CLAMP 032 [1:0] 2 02 DOUT_DELAY 033 [0] 1 01 OSC_PWRDOWN REV. A –43– Prevents the Update of the VD Updated Registers Serial Interface Readback Enable DOUT Phase Control DCLK Mode (0 = DCLK Tracks DOUT Phase, 1 = DCLK Is CLO, i.e., CLI Inverse) Divide CLI Input Clock by 2 Disable CCDIN DC Restore Circuit during PBLK (1 = Disable) Reset Internal Field Pulse Value (0 = Next Field Odd, 1 = Next Field Even) Re-time H1/H2 HBLK to Internal H1 Clock Re-time H3/H4 HBLK to Internal H3 Clock External Synchronization Enable (1 = Enable) SYNC Active Polarity (0 = Active LOW) Suspend Clocks during SYNC Active (1 = Suspend) Assign LD/FD Output (0 = FD, 1 = LD) Assign CLPOB/PBLK Output (0 = CLPOB, 1 = PBLK) TG Core Reset_bar (0 = Hold TG Core in Reset, 1 = Resume Operation) Frame Transfer CCD Mode (1 = VSG1–VSG4 Become V5–V8 Out) See Power-Up Sequence. Should be set to “53.” CLPDM = CLPOB when Set to 1 (Only CLPOB Registers Used). Delay from DCLK to DOUT (0 = No Delay, 1 = 4 ns, 2 = 8 ns, 3 = 12 ns) CLO Oscillator Power-Down (0 = Oscillator Is Powered Down) AD9891/AD9895 Table XXI. CLPDM/CLPOB Shared Register Map Address Content 064 065 066 067 068 069 06A 06B 06C 06D 06E 06F 070 071 072 073 074 [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] Bit Width Default Value Register Name Register Description 0 00 CLPSCP0 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F 3F CLPSCP1[5:0] CLPSCP1[11:6] CLPSCP2[5:0] CLPSCP2[11:6] CLPSCP3[5:0] CLPSCP3[11:6] CLPMASK0[5:0] CLPMASK0[11:6] CLPMASK1[5:0] CLPMASK1[11:6] CLPMASK2[5:0] CLPMASK2[11:6] CLPMASK3[5:0] CLPMASK3[11:6] CLPMASK4[5:0] CLPMASK4[11:6] CLPOB/DM Sequence-Change Position #0 (Hard-Coded to 0) CLPOB/CLPDM Sequence-Change Position #1 CLPOB/CLPDM Sequence-Change Position #2 CLPOB/CLPDM Sequence-Change Position #3 CLPOB/CLPDM Masking Line #0 CLPOB/CLPDM Masking Line #1 CLPOB/CLPDM Masking Line #2 CLPOB/CLPDM Masking Line #3 CLPOB/CLPDM Masking Line #4 Table XXII. CLPDM Register Map Address 075 076 077 078 079 07A 07B 07C 07D 07E 07F 080 081 082 083 084 085 086 087 088 089 08A 08B 08C Content Bit Width Default Value Register Name Register Description [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [1:0] [1:0] [1:0] [1:0] 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 2 2 2 2 01 2E 00 06 03 00 3F 3F 3F 3F 00 3F 3F 3F 3F 00 3F 3F 3F 3F 00 00 00 00 CLPDMSPOL0 CLPDMTOG1_0[5:0] CLPDMTOG1_0[11:6] CLPDMTOG2_0[5:0] CLPDMTOG2_0[11:6] CLPDMSPOL1 CLPDMTOG1_1[5:0] CLPDMTOG1_1[11:6] CLPDMTOG2_1[5:0] CLPDMTOG2_1[11:6] CLPDMSPOL2 CLPDMTOG1_2[5:0] CLPDMTOG1_2[11:6] CLPDMTOG2_2[5:0] CLPDMTOG2_2[11:6] CLPDMSPOL3 CLPDMTOG1_3[5:0] CLPDMTOG1_3[11:6] CLPDMTOG2_3[5:0] CLPDMTOG2_3[11:6] CLPDMSPTR0 CLPDMSPTR1 CLPDMSPTR2 CLPDMSPTR3 Sequence #0: Start Polarity for CLPDM Sequence #0: Toggle Position 1 for CLPDM –44– Sequence #0: Toggle Position 2 for CLPDM Sequence #1: Start Polarity for CLPDM Sequence #1: Toggle Position 1 for CLPDM Sequence #1: Toggle Position 2 for CLPDM Sequence #2: Start Polarity for CLPDM Sequence #2: Toggle Position 1 for CLPDM Sequence #2: Toggle Position 2 for CLPDM Sequence #3: Start Polarity for CLPDM Sequence #3: Toggle Position 1 for CLPDM Sequence #3: Toggle Position 2 for CLPDM CLPDM CLPDM CLPDM CLPDM Sequence Sequence Sequence Sequence Pointer Pointer Pointer Pointer for for for for Region Region Region Region #0 #1 #2 #3 REV. A AD9891/AD9895 Table XXIII. CLPOB Register Map Address Content Bit Width Default Value Register Name Register Description 08D 08E 08F 090 091 092 093 094 095 096 097 098 099 09A 09B 09C 09D 09E 09F 0A0 0A1 0A2 0A3 0A4 [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [1:0] [1:0] [1:0] [1:0] 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 2 2 2 2 01 0A 00 2F 00 00 3F 3F 3F 3F 00 3F 3F 3F 3F 00 3F 3F 3F 3F 00 00 00 00 CLPOBPOL0 CLPOBTOG1_0[5:0] CLPOBTOG1_0[11:6] CLPOBTOG2_0[5:0] CLPOBTOG2_0[11:6] CLPOBPOL1 CLPOBTOG1_1[5:0] CLPOBTOG1_1[11:6] CLPOBTOG2_1[5:0] CLPOBTOG2_1[11:6] CLPOBPOL2 CLPOBTOG1_2[5:0] CLPOBTOG1_2[11:6] CLPOBTOG2_2[5:0] CLPOBTOG2_2[11:6] CLPOBSPOL3 CLPOBTOG1_3[5:0] CLPOBTOG1_3[11:6] CLPOBTOG2_3[5:0] CLPOBTOG2_3[11:6] CLPOBSPTR0 CLPOBSPTR1 CLPOBSPTR2 CLPOBSPTR3 Sequence #0: Start Polarity for CLPOB Sequence #0: Toggle Position 1 for CLPOB Sequence #0: Toggle Position 2 for CLPOB Sequence #1: Start Polarity for CLPOB Sequence #1: Toggle Position 1 for CLPOB Sequence #1: Toggle Position 2 for CLPOB Sequence #2: Start Polarity for CLPOB Sequence #2: Toggle Position 1 for CLPOB Sequence #2: Toggle Position 2 for CLPOB Sequence #3: Start Polarity for CLPOB Sequence #3: Toggle Position 1 for CLPOB Sequence #3: Toggle Position 2 for CLPOB CLPOB CLPOB CLPOB CLPOB Sequence Sequence Sequence Sequence Pointer Pointer Pointer Pointer for for for for Region Region Region Region #0 #1 #2 #3 Table XXIV. HBLK Register Map* Address Content Bit Width Default Value Register Name Register Description 0A5 0A6 0A7 0A8 0A9 0AA 0AB 0AC 0AD 0AE 0AF 0B0 0B1 0B2 0B3 0B4 0B5 0B6 0B7 0B8 0B9 0BA 0BB 0BC [0] [0] [5:0] [5:0] [5:0] [5:0] [0] [0] [5:0] [5:0] [5:0] [5:0] [0] [0] [5:0] [5:0] [5:0] [5:0] [0] [0] [5:0] [5:0] [5:0] [5:0] 1 1 6 6 6 6 1 1 6 6 6 6 1 1 6 6 6 6 1 1 6 6 6 6 01 01 34 00 2C 02 00 00 3F 3F 3F 3F 00 00 3F 3F 3F 3F 00 00 3F 3F 3F 3F HBLKMASK_H1_0 HBLKMASK_H3_0 HBLKTOG1_0[5:0] HBLKTOG1_0[11:6] HBLKTOG2_0[5:0] HBLKTOG2_0[11:6] HBLKMASK_H1_1 HBLKMASK_H3_1 HBLKTOG1_1[5:0] HBLKTOG1_1[11:6] HBLKTOG2_1[5:0] HBLKTOG2_1[11:6] HBLKMASK_H1_2 HBLKMASK_H3_2 HBLKTOG1_2[5:0] HBLKTOG1_2[11:6] HBLKTOG2_2[5:0] HBLKTOG2_2[11:6] HBLKMASK_H1_3 HBLKMASK_H3_3 HBLKTOG1_3[5:0] HBLKTOG1_3[11:6] HBLKTOG2_3[5:0] HBLKTOG2_3[11:6] Sequence #0: H1 Masking Polarity for HBLK Sequence #0: H3 Masking Polarity for HBLK Sequence #0: Toggle Position 1 for HBLK *HBLK Sequence-Change Positions shared with the vertical transfer pulses. REV. A –45– Sequence #0: Toggle Position 2 for HBLK Sequence #1: H1 Masking Polarity for HBLK Sequence #1: H3 Masking Polarity for HBLK Sequence #1: Toggle Position 1 for HBLK Sequence #1: Toggle Position 2 for HBLK Sequence #2: H1 Masking Polarity for HBLK Sequence #2: H3 Masking Polarity for HBLK Sequence #2: Toggle Position 1 for HBLK Sequence #2: Toggle Position 2 for HBLK Sequence #3: H1 Masking Polarity for HBLK Sequence #3: H3 Masking Polarity for HBLK Sequence #3: Toggle Position 1 for HBLK Sequence #3: Toggle Position 2 for HBLK AD9891/AD9895 Table XXV. PBLK Register Map Address Content 0BD 0BE 0BF 0C0 0C1 0C2 0C3 0C4 0C5 0C6 0C7 0C8 0C9 0CA 0CB 0CC 0CD 0CE 0CF 0D0 [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] 0D1 0D2 0D3 0D4 0D5 0D6 0D7 0D8 0D9 0DA [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] [5:0] [5:0] [1:0] Bit Width Default Value Register Name Register Description 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 0 00 10 03 3F 3F 00 3F 3F 3F 3F 00 3F 3F 3F 3F 00 3F 3F 3F 3F 00 PBLKSPOL0 PBLKTOG1_0[5:0] PBLKTOG1_0[11:6] PBLKBTOG2_0[5:0] PBLKBTOG2_0[11:6] PBLKSPOL1 PBLKTOG1_1[5:0] PBLKTOG1_1[11:6] PBLKTOG2_1[5:0] PBLKTOG2_1[11:6] PBLKSPOL2 PBLKTOG1_2[5:0] PBLKTOG1_2[11:6] PBLKTOG2_2[5:0] PBLKTOG2_2[11:6] PBLKSPOL3 PBLKTOG1_3[5:0] PBLKTOG1_3[11:6] PBLKTOG2_3[5:0] PBLKTOG2_3[11:6] PBLKSCP0 Sequence #0: Start Polarity for PBLK Sequence #0: Toggle Position 1 for PBLK 2 6 6 2 6 6 2 6 6 2 00 3F 3F 00 3F 3F 00 3F 3F 00 PBLKSPTR0 PBLKSCP1[5:0] PBLKSCP1[11:6] PBLKSPTR1 PBLKSCP2[5:0] PBLKSCP2[11:6] PBLKSPTR2 PBLKSCP3[5:0] PBLKSCP3[11:6] PBLKSPTR3 Sequence #0: Toggle Position 2 for PBLK Sequence #1: Start Polarity for PBLK Sequence #1: Toggle Position 1 for PBLK Sequence #1: Toggle Position 2 for PBLK Sequence #2: Start Polarity for PBLK Sequence #2: Toggle Position 1 for PBLK Sequence #2: Toggle Position 2 for PBLK Sequence #3: Start Polarity for PBLK Sequence #3: Toggle Position 1 for PBLK Sequence #3: Toggle Position 2 for PBLK PBLK Sequence-Change Position #0 (Hard-Coded to 0) PBLK Sequence Pointer for Region #0 PBLK Sequence-Change Position #1 PBLK Sequence Pointer for Region #1 PBLK Sequence-Change Position #2 PBLK Sequence Pointer for Region #2 PBLK Sequence-Change Position #3 PBLK Sequence Pointer for Region #3 Table XXVI. H1–H4, RG, SHP, SHD Register Map Address Content Bit Width Default Value Register Name Register Description 0DB [0] 1 01 H12POL 0DC 0DD 0DE [5:0] [5:0] [0] 6 6 1 00 20 01 H1POSLOC H1NEGLOC H34POL 0DF 0E0 0E1 [5:0] [5:0] [2:0] 6 6 3 00 20 03 H3POSLOC H3NEGLOC H1DRV 0E2 0E3 0E4 0E5 [2:0] [2:0] [2:0] [0] 3 3 3 1 03 03 03 01 H2DRV H3DRV H4DRV RGPOL 0E6 OE7 0E8 [5:0] [5:0] [2:0] 6 6 3 00 10 02 RGPOSLOC RGNEGLOC RGDRV 0E9 0EA [5:0] [5:0] 6 6 24 00 SHPPOSLOC SHDPOSLOC H1/H2 Polarity Control (0 = Inversion, 1 = No Inversion) H1 Positive Edge Location H1 Negative Edge Location H3/H4 Polarity Control (0 = Inversion, 1 = No Inversion) H3 Positive Edge Location H3 Negative Edge Location H1 Drive Strength (0 = Off, 1 = 3.5 mA, 2 = 7 mA, 3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA) H2 Drive Strength H3 Drive Strength H4 Drive Strength RG Polarity Control (0 = Inversion, 1 = No Inversion) RG Positive Edge Location RG Negative Edge Location RG Drive Strength (0 = Off, 1 = 3.5 mA, 2 = 7 mA, 3 = 10.5 mA, 4 = 14 mA, 5 = 17.5 mA, 6 = 21 mA, 7 = 24.5 mA) SHP (Positive) Edge Sampling Location SHD (Positive) Edge Sampling Location –46– REV. A AD9891/AD9895 Table XXVII. HD/VD Register Map Address Content Bit Width Default Value Register Name Register Description 0EB [0] 1 00 MASTER 0EC [0] 1 00 VDHDPOL 0ED 0EE 0EF 0F0 0F1 0F2 [5:0] [5:0] [4:0] [5:0] [5:0] [5:0] 6 6 6 6 6 6 09 07 04 33 01 38 VDRISE VDLEN[5:0] VDLEN[11:6] HDRISE[5:0] HDRISE[11:6] HDLASTLEN[5:0] VD/HD Master or Slave Timing (0 = Slave, 1 = Master) VD/HD Active Polarity (0 = Low Active, 1 = High Active) VD Rising Edge Location (HD Location in Field) VD Field Length (Number of Lines per Field) 0F3 [5:0] 6 11 HDLASTLEN[11:6] HD Rising Edge Location (Pixel Location in Line) HD Last Line Length (Number of Pixels in Last Line of Field) Table XXVIII. V1–V8 Register Map Address Content Bit Width Default Value Register Name Register Description 0F4 0F5 0F6 0F7 0F8 0F9 0FA 0FB 0FC 0FD 0FE 0FF 100 101 102 103 104 105 106 107 108 109 10A 10B 10C 10D 10E 10F 110 111 112 113 114 115 116 117 118 119 11A 11B [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [3:0] [5:0] [11:6] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [3:0] [5:0] [11:6] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [3:0] [5:0] [11:6] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] 1 6 6 6 6 6 6 6 4 6 6 1 6 6 6 6 6 6 6 4 6 6 1 6 6 6 6 6 6 6 4 6 6 1 6 6 6 6 6 6 00 05 00 12 00 3F 3F 24 00 03 00 00 17 00 3F 3F 3F 3F 24 00 03 00 01 16 02 2C 04 28 05 28 05 01 00 01 1A 01 30 03 2C 04 VTPPOL0 VTPTOG1_0[5:0] VTPTOG1_0[11:6] VTPTOG2_0[5:0] VTPTOG2_0[11:6] VTPTOG3_0[5:0] VTPTOG3_0[11:6] VTPLEN0[5:0] VTPLEN0[9:6] VTPREP0[5:0] VTPREP0[11:6] VTPPOL1 VTPTOG1_1[5:0] VTPTOG1_1[11:6] VTPTOG2_1[5:0] VTPTOG2_1[11:6] VTPTOG3_1[5:0] VTPTOG3_1[11:6] VTPLEN1[5:0] VTPLEN1[9:6] VTPREP1[5:0] VTPREP1[11:6] VTPPOL2 VTPTOG1_2[5:0] VTPTOG1_2[11:6] VTPTOG2_2[5:0] VTPTOG2_2[11:6] VTPTOG3_2[5:0] VTPTOG3_2[11:6] VTPLEN2[5:0] VTPLEN2[9:6] VTPREP2[5:0] VTPREP2[11:6] VTPPOL3 VTPTOG1_3[5:0] VTPTOG1_3[11:6] VTPTOG2_3[5:0] VTPTOG2_3[11:6] VTPTOG3_3[5:0] VTPTOG3_3[11:6] Sequence #0: Start Polarity Sequence #0: Toggle Position 1 REV. A –47– Sequence #0: Toggle Position 2 Sequence #0: Toggle Position 3 Sequence #0: Total Length Sequence #0: Repetitions Sequence #1: Start Polarity Sequence #1: Toggle Position 1 Sequence #1: Toggle Position 2 Sequence #1: Toggle Position 3 Sequence #1: Total Length Sequence #1: Repetitions Sequence #2: Start Polarity Sequence #2: Toggle Position 1 Sequence #2: Toggle Position 2 Sequence #2: Toggle Position 3 Sequence #2: Total Length Sequence #2: Repetitions Sequence #3: Start Polarity Sequence #3: Toggle Position 1 Sequence #3: Toggle Position 2 Sequence #3: Toggle Position 3 AD9891/AD9895 Table XXVIII. V1–V8 Register Map (continued) Address Content Bit Width Default Value Register Name Register Description 11C 11D 11E 11F 120 121 122 123 124 125 126 127 128 129 12A 12B 12C 12D 12E 12F 130 131 132 133 134 135 136 137 138 139 13A 13B 13C 13D 13E 13F 140 141 142 143 144 145 146 147 148 149 14A 14B 14C 14D 14E 14F 150 151 152 153 [5:0] [3:0] [5:0] [11:6] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [3:0] [5:0] [11:6] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [3:0] [5:0] [11:6] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [3:0] [5:0] [11:6] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [3:0] [5:0] [11:6] [0] [5:0] [3:0] [5:0] [3:0] [5:0] [3:0] [5:0] 6 4 6 6 1 6 6 6 6 6 6 6 4 6 6 1 6 6 6 6 6 6 6 4 6 6 1 6 6 6 6 6 6 6 4 6 6 1 6 6 6 6 6 6 6 4 6 6 1 6 4 6 4 6 4 6 2C 04 01 00 00 34 02 0A 05 06 06 06 06 01 00 00 12 03 2C 04 28 05 28 05 01 00 00 3F 3F 3F 3F 3F 3F 00 00 00 00 00 3F 3F 3F 3F 3F 3F 00 00 00 00 00 3F 3F 3F 3F 00 00 00 VTPLEN3[5:0] VTPLEN3[9:6] VTPREP3[5:0] VTPREP3[11:6] VTPPOL4 VTPTOG1_4[5:0] VTPTOG1_4[11:6] VTPTOG2_4[5:0] VTPTOG2_4[11:6] VTPTOG3_4[5:0] VTPTOG3_4[11:6] VTPLEN4[5:0] VTPLEN4[9:6] VTPREP4[5:0] VTPREP4[11:6] VTPPOL5 VTPTOG1_5[5:0] VTPTOG1_5[11:6] VTPTOG2_5[5:0] VTPTOG2_5[11:6] VTPTOG3_5[5:0] VTPTOG3_5[11:6] VTPLEN5[5:0] VTPLEN5[9:6] VTPREP5[5:0] VTPREP5[11:6] VTPPOL6 VTPTOG1_6[5:0] VTPTOG1_6[11:6] VTPTOG2_6[5:0] VTPTOG2_6[11:6] VTPTOG3_6[5:0] VTPTOG3_6[11:6] VTPLEN6[5:0] VTPLEN6[9:6] VTPREP6[5:0] VTPREP6[11:6] VTPPOL7 VTPTOG1_7[5:0] VTPTOG1_7[11:6] VTPTOG2_7[5:0] VTPTOG2_7[11:6] VTPTOG3_7[5:0] VTPTOG3_7[11:6] VTPLEN7[5:0] VTPLEN7[9:6] VTPREP7[5:0] VTPREP7[11:6] VTPPOL8 VTPTOG1_8[5:0] VTPTOG1_8[9:6] VTPTOG2_8[5:0] VTPTOG2_8[9:6] VTPLEN8[5:0] VTPLEN8[9:6] VTPREP8 Sequence #3: Total Length –48– Sequence #3: Repetitions Sequence #4: Start Polarity Sequence #4: Toggle Position 1 Sequence #4: Toggle Position 2 Sequence #4: Toggle Position 3 Sequence #4: Total Length Sequence #4: Repetitions Sequence #5: Start Polarity Sequence #5: Toggle Position 1 Sequence #5: Toggle Position 2 Sequence #5: Toggle Position 3 Sequence #5: Total Length Sequence #5: Repetitions Sequence #6: Start Polarity Sequence #6: Toggle Position 1 Sequence #6: Toggle Position 2 Sequence #6: Toggle Position 3 Sequence #6: Total Length Sequence #6: Repetitions Sequence #7: Start Polarity Sequence #7: Toggle Position 1 Sequence #7: Toggle Position 2 Sequence #7: Toggle Position 3 Sequence #7: Total Length Sequence #7: Repetitions Sequence #8: Start Polarity Sequence #9: Toggle Position 1 Sequence #8: Toggle Position 2 Sequence #8: Total Length Sequence #8: Repetitions REV. A AD9891/AD9895 Table XXVIII. V1–V8 Register Map (continued) Bit Width Default Value Register Name Register Description [0] [5:0] [3:0] [5:0] [3:0] [5:0] [3:0] [5:0] [0] [5:0] [3:0] [5:0] [3:0] [5:0] [3:0] [5:0] [0] [5:0] [3:0] [5:0] [3:0] [5:0] [3:0] [5:0] 1 6 4 6 4 6 4 6 1 6 4 6 4 6 4 6 1 6 4 6 4 6 4 6 0 00 3F 3F 3F 3F 00 00 00 00 3F 3F 3F 3F 00 00 00 00 3F 3F 3F 3F 00 00 00 00 VTPPOL8 VTPTOG1_9[5:0] VTPTOG1_9[9:6] VTPTOG2_9[5:0] VTPTOG2_9[9:6] VTPLEN9[5:0] VTPLEN9[9:6] VTPREP9 VTPPOL10 VTPTOG1_10[5:0] VTPTOG1_10[6:0] VTPTOG2_10[5:0] VTPTOG2_10[9:6] VTPLEN10[5:0] VTPLEN10[9:6] VTPREP10 VTPPOL11 VTPTOG1_11[5:0] VTPTOG1_11[9:6] VTPTOG2_11[5:0] VTPTOG2_11[9:6] VTPLEN11[5:0] VTPLEN11[9:6] VTPREP11 VTPRCP0 Sequence #9: Start Polarity Sequence #9: Toggle Position 1 [2:0] [5:0] [5:0] [2:0] [5:0] [5:0] [2:0] [5:0] [5:0] [2:0] [5:0] [5:0] [2:0] [5:0] [5:0] [2:0] [5:0] [5:0] [2:0] [5:0] [5:0] [2:0] [0] [0] [5:0] [5:0] [1:0] [0] [3:0] 3 6 6 3 6 6 3 6 6 3 6 6 3 6 6 3 6 6 3 6 6 3 1 1 6 6 2 1 4 00 3F 3F 00 3F 3F 00 3F 3F 00 3F 3F 00 3F 3F 00 3F 3F 00 3F 3F 00 00 00 30 23 00 00 00 VTPREGPTR0 VTPRCP1[5:0] VTPRCP1[11:6] VTPREGPTR1 VTPRCP2[5:0] VTPRCP2[11:6] VTPREGPTR2 VTPRCP3[5:0] VTPRCP3[11:6] VTPREGPTR3 VTPRCP4[5:0] VTPRCP4[11:6] VTPREGPTR4 VTPRCP5[5:0] VTPRCP5[11:6] VTPREGPTR5 VTPRCP6[5:0] VTPRCP6[11:6] VTPREGPTR6 VTPRCP7[5:0] VTPRCP7[11:6] VTPREGPTR7 SWEEP0 MULTI0 HDLEN0[5:0] HDLEN0[11:6] HBLKSPTR0 VTPALT0 V1SPTRFIRST0 Address Content 154 155 156 157 158 159 15A 15B 15C 15D 15E 15F 160 161 162 163 164 165 166 167 168 169 16A 16B 16C 16D 16E 16F 170 171 172 173 174 175 176 177 178 179 17A 17B 17C 17D 17E 17F 180 181 182 183 184 185 186 187 188 REV. A –49– Sequence #9: Toggle Position 2 Sequence #9: Total Length Sequence #9: Repetitions Sequence #10: Start Polarity Sequence #10: Toggle Position 1 Sequence #10: Toggle Position 2 Sequence #10: Total Length Sequence #10: Repetitions Sequence #11: Start Polarity Sequence #11: Toggle Position 1 Sequence #11: Toggle Position 2 Sequence #11: Total Length Sequence #11: Repetitions V Region-Change Position #0 (Hard-Coded to 0) V Region Pointer for Sequence-Change Position #0 V Region-Change Position #1 V Region Pointer for Sequence-Change Position #1 V Region-Change Position #2 V Region Pointer for Sequence-Change Position #2 V Region-Change Position #3 V Region Pointer for Sequence-Change Position #3 V Region-Change Position #4 V Region Pointer for Sequence-Change Position #4 V Region-Change Position #5 V Region Pointer for Sequence-Change Position #5 V Region-Change Position #6 V Region Pointer for Sequence-Change Position #6 V Region-Change Position #7 V Region Pointer for Sequence-Change Position #7 V Sweep for Region #0 V Multiplier for Region #0 Region #0 HD Line Length HBLK Sequence for Region #0 VTP Sequence Alternation for Region #0 V1 Sequence for Region #0 (1st Lines) AD9891/AD9895 Table XXVIII. V1–V8 Register Map (continued) Address Content Bit Width Default Value Register Name Register Description 189 18A 18B 18C 18D 18E 18F 190 191 192 193 194 195 196 197 198 199 19A 19B 19C 19D 19E 19F 1A0 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 1A9 1AA 1AB 1AC 1AD 1AE 1AF 1B0 1B1 1B2 1B3 1B4 1B5 1B6 1B7 1B8 1B9 1BA 1BB 1BC 1BD 1BE [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [0] [0] [5:0] [5:0] [1:0] [0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] 1 4 1 6 6 4 1 4 1 6 6 4 1 4 1 6 6 4 1 4 1 6 6 6 6 6 6 6 6 6 6 1 1 6 6 2 1 4 1 4 1 6 6 4 1 4 1 6 6 4 1 4 1 6 00 00 00 34 00 00 00 00 00 3D 00 01 00 00 00 34 00 01 00 00 00 3D 00 00 00 00 00 00 00 00 00 00 00 3F 3F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 V1INVFIRST0 V1SPTRSECOND0 V1INVSECOND0 V4_7START4[5:0] V1_5START0[11:6] V2SPTRFIRST0 V2INVFIRST0 V2SPTRSECOND0 V2INVSECOND0 V4_7START4[5:0] V2_6START0[11:6] V3SPTRFIRST0 V3INVFIRST0 V3SPTRSECOND0 V3INVSECOND0 V4_7START4[5:0] V3_7START0[11:6] V4SPTRFIRST0 V4INVFIRST0 V4SPTRSECOND0 V4INVSECOND0 V4_8START0[5:0] V4_8START0[11:6] V1_4FREEZE0[5:0] V1_4FREEZE0[11:6] V1_4RESUME0[5:0] V1_4RESUME0[11:6] V5_8FREEZE0[5:0] V5_8FREEZE0[11:6] V5_8RESUME0[5:0] V5_8RESUME0[11:6] SWEEP1 MULTI1 HDLEN1[5:0] HDLEN1[11:6] HBLKSPTR1 VTPALT1 V1SPTRFIRST1 V1INVFIRST1 V1SPTRSECOND1 V1INVSECOND1 V1_5START1[5:0] V1_5START1[11:6] V2SPTRFIRST1 V2INVFIRST1 V2SPTRSECOND1 V2INVSECOND1 V2_6START1[5:0] V2_6START1[11:6] V3SPTRFIRST1 V3INVFIRST1 V3SPTRSECOND1 V3INVSECOND1 V3_7START1[5:0] V1 Sequence Inversion for Region #0 (First Lines) V1 Sequence for Region #0 (Second Lines) V1 Sequence Inversion for Region #0 (Second Lines) V1 and V5 Sequence Start for Region #0 –50– V2 Sequence for Region #0 (First Lines) V2 Sequence Inversion for Region #0 (First Lines) V2 Sequence for Region #0 (Second Lines) V2 Sequence Inversion for Region #0 (Second Lines) V2 and V6 Sequence Start for Region #0 V3 Sequence for Region #0 (First Lines) V3 Sequence Inversion for Region #0 (First Lines) V3 Sequence for Region #0 (Second Lines) V3 Sequence Inversion for Region #0 (Second Lines) V3 and V7 Sequence Start for Region #0 V4 Sequence for Region #0 (First Lines) V4 Sequence Inversion for Region #0 (First Lines) V4 Sequence for Region #0 (Second Lines) V4 Sequence Inversion for Region #0 (Second Lines) V4 and V8 Sequence Start for Region #0 V1–V4 Freeze Start Position for Region #0 V1–V4 Resume Start Position for Region #0 V5–V8 Freeze Start Position for Region #0 V5–V8 Resume Start Position for Region #0 V Sweep for Region #1 V Multiplier for Region #1 Region #1 HD Line Length HBLK Sequence for Region #1 V Sequence Alternation for Region #1 V1 Sequence for Region #1 (First Lines) V1 Sequence Inversion for Region #1 (First Lines) V1 Sequence for Region #1 (Second Lines) V1 Sequence Inversion for Region #1 (Second Lines) V1 and V5 Sequence Start for Region #1 V2 Sequence for Region #1 (First Lines) V2 Sequence Inversion for Region #1 (First Lines) V2 Sequence for Region #1 (Second Lines) V2 Sequence Inversion for Region #1 (Second Lines) V2 and V6 Sequence Start for Region #1 V3 Sequence for Region #1 (First Lines) V3 Sequence Inversion for Region #1 (First Lines) V3 Sequence for Region #1 (Second Lines) V3 Sequence Inversion for Region #1 (Second Lines) V3 and V7 Sequence Start for Region #1 REV. A AD9891/AD9895 Table XXVIII. V1–V8 Register Map (continued) Address Content Bit Width Default Value Register Name 1BF 1C0 1C1 1C2 1C3 1C4 1C5 1C6 1C7 1C8 1C9 1CA 1CB 1CC 1CD 1CE 1CF 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9 1DA 1DB 1DC 1DD 1DE 1DF 1E0 1E1 1E2 1E3 1E4 1E5 1E6 1E7 1E8 1E9 1EA 1EB 1EC 1ED 1EE 1EF 1F0 1F1 1F2 1F3 1F4 1F5 [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [0] [0] [5:0] [5:0] [1:0] [0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [0] [0] 6 4 1 4 1 6 6 6 6 6 6 6 6 6 6 1 1 6 6 2 1 4 1 4 1 6 6 4 1 4 1 6 6 4 1 4 1 6 6 4 1 4 1 6 6 6 6 6 6 6 6 6 6 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3F 3F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 V3_7START1[11:6] V4SPTRFIRST1 V4INVFIRST1 V4SPTRSECOND1 V4INVSECOND1 V4_8START1[5:0] V4_8START1[11:6] V1_4FREEZE1[5:0] V1_4FREEZE1[11:6] V1_4RESUME1[5:0] V1_4RESUME1[11:6] V5_8FREEZE1[5:0] V5_8FREEZE1[11:6] V5_8RESUME1[5:0] V5_8RESUME1[11:6] SWEEP2 MULTI2 HDLEN2[5:0] HDLEN2[11:6] HBLKSPTR2 VTPALT2 V1SPTRFIRST2 V1INVFIRST2 V1SPTRSECOND2 V1INVSECOND2 V1_5START2[5:0] V1_5START2[11:6] V2SPTRFIRST2 V2INVFIRST2 V2SPTRSECOND2 V2INVSECOND2 V2_6START2[5:0] V2_6START2[11:6] V3SPTRFIRST2 V3INVFIRST2 V3SPTRSECOND2 V3INVSECOND2 V3_7START2[5:0] V3_7START2[11:6] V4SPTRFIRST2 V4INVFIRST2 V4SPTRSECOND2 V4INVSECOND2 V4_8START2[5:0] V4_8START2[11:6] V1_4FREEZE2[5:0] V1_4FREEZE2[11:6] V1_4RESUME2[5:0] V1_4RESUME2[11:6] V5_8FREEZE2[5:0] V5_8FREEZE2[11:6] V5_8RESUME2[5:0] V5_8RESUME2[11:6] SWEEP3 MULTI3 REV. A –51– Register Description V4 Sequence for Region #1 (First Lines) V4 Sequence Inversion for Region #1 (First Lines) V4 Sequence for Region #1 (Second Lines) V4 Sequence Inversion for Region #1 (Second Lines) V4 and V8 Sequence Start for Region #1 V1–V4 Freeze Start Position for Region #1 V1–V4 Resume Start Position for Region #1 V5–V8 Freeze Start Position for Region #1 V5–V8 Resume Start Position for Region #1 V Sweep for Region #2 V Multiplier for Region #2 Region #2 HD Line Length HBLK Sequence for Region #2 V Sequence Alternation for Region #2 V1 Sequence for Region #2 (First Lines) V1 Sequence Inversion for Region #2 (First Lines) V1 Sequence for Region #2 (Second Lines) V1 Sequence Inversion for Region #2 (Second Lines) V1 and V5 Sequence Start for Region #2 V2 Sequence for Region #2 (First Lines) V2 Sequence Inversion for Region #2 (First Lines) V2 Sequence for Region #2 (Second Lines) V2 Sequence Inversion for Region #2 (Second Lines) V2 and V6 Sequence Start for Region #2 V3 Sequence for Region #2 (First Lines) V3 Sequence Inversion for Region #2 (First Lines) V3 Sequence for Region #2 (Second Lines) V3 Sequence Inversion for Region #2 (Second Lines) V3 and V7 Sequence Start for Region #2 V4 Sequence for Region #2 (First Lines) V4 Sequence Inversion for Region #2 (First Lines) V4 Sequence for Region #2 (Second Lines) V4 Sequence Inversion for Region #2 (Second Lines) V4 and V8 Sequence Start for Region #2 V1–V4 Freeze Start Position for Region #2 V1–V4 Resume Start Position for Region #2 V5–V8 Freeze Start Position for Region #2 V5–V8 Resume Start Position for Region #2 V Sweep for Region #3 V Multiplier for Region #3 AD9891/AD9895 Table XXVIII. V1–V8 Register Map (continued) Address Content Bit Width Default Value Register Name Register Description 1F6 1F7 1F8 1F9 1FA 1FB 1FC 1FD 1FE 1FF 200 201 202 203 204 205 206 207 208 209 20A 20B 20C 20D 20E 20F 210 211 212 213 214 215 216 217 218 219 21A 21B 21C 21D 21E 21F 220 221 222 223 224 225 226 227 228 229 22A 22B 22C [5:0] [5:0] [1:0] [0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [0] [0] [5:0] [5:0] [1:0] [0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [3:0] 6 6 2 1 4 1 4 1 6 6 4 1 4 1 6 6 4 1 4 1 6 6 4 1 4 1 6 6 6 6 6 6 6 6 6 6 1 1 6 6 2 1 4 1 4 1 6 6 4 1 4 1 6 6 4 3F 3F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 3F 3F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 HDLEN3[5:0] HDLEN3[11:6] HBLKSPTR3 VTPALT3 V1SPTRFIRST3 V1INVFIRST3 V1SPTRSECOND3 V1INVSECOND3 V1_5START3[5:0] V1_5START3[11:6] V2SPTRFIRST3 V2INVFIRST3 V2SPTRSECOND3 V2INVSECOND3 V2_6START3[5:0] V2_6START3[11:6] V3SPTRFIRST3 V3INVFIRST3 V3SPTRSECOND3 V3INVSECOND3 V3_7START3[5:0] V3_7START3[11:6] V4SPTRFIRST3 V4INVFIRST3 V4SPTRSECOND3 V4INVSECOND3 V4_8START3[5:0] V4_8START3[11:6] V1_4FREEZE3[5:0] V1_4FREEZE3[11:6] V1_4RESUME3[5:0] V1_4RESUME3[11:6] V5_8FREEZE3[5:0] V5_8FREEZE3[11:6] V5_8RESUME3[5:0] V5_8RESUME3[11:6] SWEEP4 MULTI4 HDLEN4[5:0] HDLEN4[11:6] HBLKSPTR4 VTPALT4 V1SPTRFIRST4 V1INVFIRST4 V1SPTRSECOND4 V1INVSECOND4 V1_5START4[5:0] V1_5START4[11:6] V2SPTRFIRST4 V2INVFIRST4 V2SPTRSECOND4 V2INVSECOND4 V2_6START4[5:0] V2_6START4[11:6] V4SPTRFIRST4 Region #3 HD Line Length –52– HBLK Sequence for Region #3 VTP Sequence Alternation for Region #3 V1 Sequence for Region #3 (First Lines) V1 Sequence Inversion for Region #3 (First Lines) V1 Sequence for Region #3 (Second Lines) V1 Sequence Inversion for Region #3 (Second Lines) V1 and V5 Sequence Start for Region #3 V2 Sequence for Region #3 (First Lines) V2 Sequence Inversion for Region #3 (First Lines) V2 Sequence for Region #3 (Second Lines) V2 Sequence Inversion for Region #3 (Second Lines) V2 and V6 Sequence Start for Region #3 V3 Sequence for Region #3 (First Lines) V3 Sequence Inversion for Region #3 (First Lines) V3 Sequence for Region #3 (Second Lines) V3 Sequence Inversion for Region #3 (Second Lines) V3 and V7 Sequence Start for Region #3 V4 Sequence for Region #3 (First Lines) V4 Sequence Inversion for Region #3 (First Lines) V4 Sequence for Region #3 (Second Lines) V4 Sequence Inversion for Region #3 (Second Lines) V4 and V8 Sequence Start for Region #3 V1–V4 Freeze Start Position for Region #3 V1–V4 Resume Start Position for Region #3 V5–V8 Freeze Start Position for Region #3 V5–V8 Resume Start Position for Region #3 V Sweep for Region #4 V Multiplier for Region #4 Region #4 HD Line Length HBLK Sequence for Region #4 VTP Sequence Alternation for Region #4 V1 Sequence for Region #4 (First Lines) V1 Sequence Inversion for Region #4 (First Lines) V1 Sequence for Region #4 (Second Lines) V1 Sequence Inversion for Region #4 (Second Lines) V1 and V5 Sequence Start for Region #4 V2 Sequence for Region #4 (First Lines) V2 Sequence Inversion for Region #4 (First Lines) V2 Sequence for Region #4 (Second Lines) V2 Sequence Inversion for Region #4 (Second Lines) V2 and V6 Sequence Start for Region #4 V4 Sequence for Region #4 (First Lines) REV. A AD9891/AD9895 Table XXVIII. V1–V8 Register Map (continued) Address Content Bit Width Default Value Register Name Register Description 22D 22E 22F 230 231 232 233 234 235 236 237 238 239 23A 23B 23C 23D 23E 23F 240 241 242 243 244 245 246 247 248 249 24A 24B 24C 24D 24E 24F 250 [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [3:0] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [0] [3:0] [0] [5:0] [5:0] [3:0] [0] [5:0] [5:0] [3:0] [0] [5:0] [5:0] [3:0] [0] [5:0] [5:0] 1 4 1 6 6 4 1 4 1 6 6 6 6 6 6 6 6 6 6 1 4 1 6 6 4 1 6 6 4 1 6 6 4 1 6 6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 02 00 10 10 03 00 2A 11 04 00 32 0F 05 00 2E 10 V4INVFIRST4 V4SPTRSECOND4 V4INVSECOND4 V4_7START4[5:0] V4_7START4[11:6] V4SPTRFIRST4 V4INVFIRST4 V4SPTRSECOND4 V4INVSECOND4 V4_8START4[5:0] V4_8START4[11:6] V1_4FREEZE4[5:0] V1_4FREEZE4[11:6] V1_4RESUME4[5:0] V1_4RESUME4[11:6] V5_8FREEZE4[5:0] V5_8FREEZE4[11:6] V5_8RESUME4[5:0] VTP5_8RESUME4[11:6] VTP_SGLINEMODE V1SPTR_SGLINE V1INV_SGLINE V1START_SGLINE[5:0] V1START_SGLINE[11:6] V2SPTR_SGLINE V2INV_SGLINE V2START_SGLINE[5:0] V2START_SGLINE[11:6] V3SPTR_SGLINE V3INV_SGLINE V3START_SGLINE[5:0] V3START_SGLINE[11:6] V4SPTR_SGLINE V4INV_SGLINE V4START_SGLINE[5:0] V4START_SGLINE[11:6] V4 Sequence Inversion for Region #4 (First Lines) V4 Sequence for Region #4 (Second Lines) V4 Sequence Inversion for Region #4 (Second Lines) V4 and V7 Sequence Start for Region #4 REV. A –53– V4 Sequence for Region #4 (First Lines) V4 Sequence Inversion for Region #4 (First Lines) V4 Sequence for Region #4 (Second Lines) V4 Sequence Inversion for Region #4 (Second Lines) V4 and V8 Sequence Start for Region #4 V1–V4 Freeze Start Position for Region #4 V1–V4 Resume Start Position for Region #4 V5–V8 Freeze Start Position for Region #4 V5–V8 Resume Start Position for Region #4 VTP Second Sequence Output Enable during SGLINE V1 Second Sequence V1 Second Sequence Inversion V1 Start Position of Second V Pulse V2 Second Sequence V2 Second Sequence Inversion V2 Start Position of Second V Pulse V3 Second Sequence V3 Second Sequence Inversion V3 Start Position of Second VTP Pulse V4 Second Sequence V4 Second Sequence Inversion V4 Start Position of Second VTP Pulse AD9891/AD9895 Table XXIX. VSG1–VSG8 Register Map Address Content Bit Width Default Value Register Name Register Description 251 252 253 254 255 256 257 258 259 25A 25B 25C 25D 25E 25F 260 261 262 263 264 265 266 267 268 269 26A 26B 26C 26D 26E 26F 270 [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [0] [5:0] [5:0] [5:0] [5:0] [5:0] [4:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [1:0] [5:0] [1:0] 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 1 6 6 6 6 6 6 2 2 2 2 2 2 2 2 6 2 01 22 13 1E 14 01 0C 11 08 12 01 3F 3F 3F 3F 01 3F 3F 3F 3F 00 00 00 00 00 00 01 01 01 01 00 00 SGPOL0 SGTOG1_0[5:0] SGTOG1_0[11:6] SGTOG2_0[5:0] SGTOG2_0[11:6] SGPOL1 SGTOG1_1[5:0] SGTOG1_1[11:6] SGTOG2_1[5:0] SGTOG2_1[11:6] SGPOL2 SGTOG1_2[5:0] SGTOG1_2[11:6] SGTOG2_2[5:0] SGTOG2_2[11:6] SGPOL3 SGTOG1_3[5:0] SGTOG1_3[11:6] SGTOG2_3[5:0] SGTOG2_3[11:6] SGACTLINE[5:0] SGACTLINE11:6] SGSEL1 SGSEL2 SGSEL3 SGSEL4 SGSEL5 SGSEL6 SGSEL7 SGSEL8 SGMASK[5:0] SGMASK[7:6] Sequence #0: Start Polarity Sequence #0: Toggle Position 1 Sequence #0: Toggle Position 2 Sequence #1: Start Polarity Sequence #1: Toggle Position 1 Sequence #1: Toggle Position 2 Sequence #2: Start Polarity Sequence #2: Toggle Position 1 Sequence #2: Toggle Position 2 Sequence #3: Start Polarity Sequence #3: Toggle Position 1 Sequence #3: Toggle Position 2 VSG Active Line VSG1 Sequence Selector VSG2 Sequence Selector VSG3 Sequence Selector VSG4 Sequence Selector VSG5 Sequence Selector VSG6 Sequence Selector VSG7 Sequence Selector VSG8 Sequence Selector VSG Masking (0 = Output, 1 = Mask) Table XXX. SUBCK, VSUB, MSHUT Register Map Address Content Bit Width Default Value Register Name Register Description 271 272 273 274 275 276 277 278 279 27A 27B 27C 27D [0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] [5:0] 1 6 6 6 6 6 6 6 6 6 6 6 6 01 0B 01 05 02 3F 3F 3F 3F 3F 00 00 00 SUBCKPOL SUBCK1TOG1[5:0] SUBCK1TOG1[11:6] SUBCK1TOG2[5:0] SUBCK1TOG2[11:6] SUBCK2TOG1[5:0] SUBCK2TOG1[11:6] SUBCK2TOG2[5:0] SUBCK2TOG2[11:6] SUBCKNUM[5:0] SUBCKNUM[11:6] SUBCKSUPPRESS EXPOSURE[5:0] SUBCK Start Polarity First SUBCK Toggle Position 1 27E 27F 280 [5:0] [0] [2:0] 6 1 3 00 00 00 EXPOSURE[11:6] VDHDOFF TRIGGER 281 282 [2:0] [0] 3 1 02 00 READOUT VSUBMODE Disable VD and HD during Exposure VSUB (TRIGGER[0]), MSHUT (TRIGGER[1]), STROBE (TRIGGER[2]) Trigger SUBCK Suppression after Exposure during Readout VSUB Readout Mode –54– REV. A First SUBCK Toggle Position 2 Second SUBCK Toggle Position 1 Second SUBCK Toggle Position 2 Number of SUBCKs per Field Number of SUCKs to Suppress after VSG Line Number of Fields to Suppress SUBCK/VSG (Exposure Time) AD9891/AD9895 Table XXX. SUBCK, VSUB, MSHUT Register Map (continued) Address Content Bit Width Default Value Register Name Register Description 283 [0] 1 00 VSUBKEEPON 284 285 286 287 288 289 [0] [5:0] [5:0] [0] [0] [5:0] 1 6 6 1 1 6 01 00 00 00 01 00 VSUB Off Mode (0 = Turn Off after Readout or Next VD, 1 = Keep Active beyond Readout) VSUB Active Polarity VSUB On Position 28A 28B [5:0] [5:0] 6 6 00 00 28C 28D [5:0] [5:0] 6 6 00 00 28E 28F [5:0] [5:0] 6 6 00 00 290 291 [5:0] [5:0] 6 6 00 00 292 293 294 [5:0] [0] [5:0] 6 1 6 00 01 00 295 296 [5:0] [5:0] 6 6 00 00 297 298 [5:0] [5:0] 6 6 00 00 299 29A [5:0] [5:0] 6 6 00 00 29B 29C [5:0] [5:0] 6 6 00 00 29D 29E [5:0] [5:0] 6 6 00 00 29F [5:0] 6 00 VSUBPOL VSUBON[5:0] VSUBON[11:6] MSHUTON MSHUT Enable (VD Aligned) MSHUTPOL MSHUT Active Polarity MSHUTONPOS_LN[5:0] MSHUT On Line Position (In Terms of HDs from VD Update) MSHUTONPOS_LN[11:6] MSHUTONPOS_PIX[5:0] MSHUT On Pixel Position (In Terms of Pixels from HD On Position) MSHUTONPOS_PIX[11:6] MSHUTOFF_FD[5:0] MSHUT Field Off Position (In Terms of VDs from Field Containing Last SUBCK) MSHUTOFF_FD[11:6] MSHUTOFF_LN[5:0] MSHUT Line Off Position (In Terms of HDs from VD Aligned Off Position) MSHUTOFF_LN[11:6] MSHUTOFF_PX[5:0] MSHUT Pixel Off Position (In Terms of Pixels from HD Aligned Off Position) MSHUTOFF_PX[11:6] STROBPOL STROBE Active Polarity STROBON_FD[5:0] STROBE Field On Position (In Terms of VDs from Field Containing Last SUBCK) STROBON_FD[11:6] STROBON_LN[5:0] STROBE Line On Position (In Terms of HDs from VD Aligned On Position) STROBON_LN[11:6] STROBON_PX[5:0] STROBE Pixel On Position (In Terms of Pixels from HD Aligned On Position) STROBON_PX[11:6] STROBOFF_FD[5:0] STROBE Field Off Position (In Terms of VDs from Field Containing Last SUBCK) STROBOFF_FD[11:6] STROBOFF_LN[5:0] STROBE Line Off Position (In Terms of HDs from VD Aligned Off Position) STROBOFF_LN[11:6] STROBOFF_PX[5:0] STROBE Pixel Off Position (In Terms of Pixels from HD Aligned Off Position) STROBOFF_PX[11:6] REV. A –55– AD9891/AD9895 Table XXXI. AFE Register Breakdown Bit Width Content Default Value Register Name Register Description OPRMODE [7:0] [1:0] 8’h0 2’h0 2’h1 2’h2 2’h3 POWERDOWN[1:0] [2] [3] [4] [5] [6] [7] DISBLACK Test Mode Test Mode Test Mode Test Mode Test Mode Serial Address: 10’h0{OPRMODE[5:0]}, 10’h1{OPRMODE[7:6]} Normal Operation Standby1 (See Standby Modes Table) Standby2 (See Standby Modes Table) Standby3 (See Standby Modes Table) Disable Black Loop Clamping (HIGH Active) Test Mode—Should Be Set LOW Test Mode—Should Be Set HIGH Test Mode—Should Be Set LOW Test Mode—Should Be Set LOW Test Mode—Should Be Set LOW CTLMODE [5:0] [2:0] [3] [4] [5] 6’h0 3’h0 3’h1 3’h2 3’h3 3’h4 3’h5 3’h6 3’h7 1’h0 1’h1 1’h0 1’h1 CTLMODE[2:0] ENABLEPXGA OUTPUTLAT TRISTATEOUT –56– Serial Address: 10’h6{CLTMODE[5:0]} OFF Mosaic Separate VD Selected/Mosaic Interlaced Mosaic Repeat 3-Color 3-Color II 4-Color 4-Color II Enable PxGA (HIGH Active) Latch Output Data on Selected DOUT Edge Leave Output Latch Transparent ADC Outputs Are Driven ADC Outputs Are Three-Stated REV. A AD9891/AD9895 OUTLINE DIMENSIONS 64-Lead Plastic Ball Grid Array [CSPBGA] (BC-64) Dimensions shown in millimeters A1 CORNER INDEX AREA 9.00 BSC SQ 10 9 8 7 6 5 4 3 A1 BOT TOM VIEW TOP VIEW 0.90 REF SQ 2 1 A B C D E F G H J K 7.20 BSC DETAIL A DETAIL A 0.85 MIN 0.25 MIN 1.70 MAX 0.12 MAX COPLANARITY 0.55 SEATING 0.50 PLANE 0.45 BALL DIAMETER 0.80 BSC COMPLIANT TO JEDEC STANDARDS MO-205-AB Revision History Location Page 8/02—Data Sheet changed from REV. 0 to REV. A. Added AD9895 part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal REV. A –57– –58– PRINTED IN U.S.A. C02817–0–8/02(A)