AD9901KPZ

a Ultrahigh Speed Phase/Frequency Discriminator AD9901 PHASE-LOCKED LOOP FEATURES Phase and Frequency Detection ECL/TTL/CMOS Compatible Linear Transfer Function No “Dead Zone” MIL-STD-883 Compliant Versions Available REFERENCE INPUT LOWPASS FILTER VCO OSCILLATOR OUTPUT AD9901 APPLICATIONS Low Phase Noise Reference Loops Fast-Tuning “Agile” IF Loops Secure “Hopping” Communications Coherent Radar Transmitter/Receiver Chains 1/N OPTIONAL 1/N PRESCALER TYPICAL OF DIGITAL PLLs GENERAL DESCRIPTION The AD9901 is a digital phase/frequency discriminator capable of directly comparing phase/frequency inputs up to 200 MHz. Processing in a high speed trench-oxide isolated process, combined with an innovative design, gives the AD9901 a linear detection range, free of indeterminate phase detection zones common to other digital designs. With a single +5 V supply, the AD9901 can be configured to operate with TTL or CMOS logic levels; it can also operate with ECL inputs when operated with a –5.2 V supply. The open-collector outputs allow the output swing to be matched to post-filtering input requirements. A simple current setting resistor controls the output stage current range, permitting a reduction in power when operated at lower frequencies. A major feature of the AD9901 is its ability to compare phase/frequency inputs at standard IF frequencies without prescalers. Excessive phase uncertainty which is common with standard PLL configurations is also eliminated. The AD9901 provides the locking speed of traditional phase/frequency discriminators, with the phase stability of analog mixers. The AD9901 is available as a commercial temperature range device, 0°C to +70°C, and as a military temperature device, –55°C to +125°C. The commercial versions are packaged in a 14-lead ceramic DIP and a 20-lead PLCC. The AD9901 Phase/Frequency Discriminator is available in versions compliant with MIL-STD-883. Refer to the Analog Devices Military Products Databook or current AD9901/883B data sheet for specifications. FUNCTIONAL BLOCK DIAGRAM D Q D Q REFERENCE FREQUENCY DISCRIMINATOR FLIP-FLOP Q R REFERENCE INPUT FLIP-FLOP REFERENCE INPUT Q D Q XOR OSCILLATOR INPUT FLIP-FLOP OSCILLATOR INPUT OUTPUT OUTPUT Q S Q OSCILLATOR FREQUENCY DISCRIMINATOR FLIP-FLOP Q D REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 AD9901–SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS 1 Operating Temperature Range AD9901KQ/KP . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature2 Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Ceramic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175°C Lead Soldering Temperature (10 sec) . . . . . . . . . . . . .+300°C Positive Supply Voltage (+VS for TTL Operation) . . . . . +7 V Negative Supply Voltage (–VS for ECL Operation) . . . . . –7 V Input Voltage Range (TTL Operation) . . . . . . . 0 V to +5.5 V Differential Input Voltage (ECL Operation) . . . . . . . . . . 4.0 V ISET Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mA Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA ELECTRICAL CHARACTERISTICS (ⴞV = +5.0 V [for TTL] or –5.2 V [for ECL], unless otherwise noted) S Commercial Temperature 0ⴗC to +70ⴗC AD9901KQ/KP Temp Test Level INPUT CHARACTERISTICS TTL Input Logic “1” Voltage TTL Input Logic “0” Voltage TTL Input Logic “1” Current3 TTL Input Logic “0” Current3 ECL Differential Switching Voltage ECL Input Current Full Full Full Full Full Full VI VI VI VI VI VI 2.0 OUTPUT CHARACTERISTICS Peak-to-Peak Output Voltage Swing4 TTL Output Compliance Range ECL Output Compliance Range IOUT Range Internal Reference Voltage Full Full Full Full Full VI V V V VI 1.6 AC CHARACTERISTICS Linear Phase Detection Range4 40 kHz 30 MHz 70 MHz Functionality @ 70 MHz +25°C +25°C +25°C +25°C V V V I 360 320 270 Pass/Fail +25°C Full +25°C Full +25°C I I I I V 43.5 43.5 42.5 42.5 218 POWER SUPPLY CHARACTERISTICS TTL Supply Current (+5.0 V)5, 6 ECL Supply Current (–5.2 V)5, 6 Nominal Power Dissipation Min Typ Max 0.8 0.6 1.6 300 20 0.42 1.8 3–7 ±2 0.9–11 0.47 2.0 0.52 Units V V mA mA mV µA V V V mA V Degrees Degrees Degrees 54.0 54.0 52.5 52.5 mA mA mA mA mW NOTES 1 Absolute maximum ratings are limiting values, to be applied individually, and beyond which the service ability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Maximum junction temperature should not exceed +175 °C for ceramic packages, +150°C for plastic packages. Junction temperature can be calculated by: tJ = PD (θ JA) +tA = PD (θJC) +tC where: PD = power dissipation θJA = thermal impedance from junction to air (°C/W) θJC = thermal impedance from junction to case ( °C/W) tA = ambient temperature (°C) tC = case temperature (°C) typical thermal impedances: AD9901 Ceramic DIP = θJA = 74°C/W; θ JC = 21°C/W AD9901 LCC = θ JA = 80°C/W; θJC = 19°C/W AD9901 PLCC = θ JA = 88.2°C/W; θJC = 45.2°C/W 3 VL = +0.4 V; VH = +2.4 V. 4 RSET = 47.5 Ω; R L = 182 Ω. 5 lncludes load current of 10 mA (load resistors = 182 Ω). 6 Supply should remain stable within ± 5% for normal operation. Specifications subject to change without notice. –2– REV. B AD9901 INPUT/OUTPUT EQUIVALENT CIRCUITS (Based on DIP Pinouts) TTL MODE = +VS (+5.0V) ECL MODE = GROUND +5.0V VCO/REF, INPUT 5/12 VCO/REF, INPUT 4/13 VCO/REF, INPUT 3/14 RSET 0.47V REFERENCE –5.2V TTL MODE = GROUND ECL MODE = VS (–5.2V) TTL Input ECL Input AD9901 BURN-IN CIRCUIT Output DIE LAYOUT AND MECHANICAL INFORMATION (Based on DIP ECL Pinouts) REFERENCE IN (–VS) GND (REFERENCE IN) DA3 50V 180V 1kV OUTPUT GND (REFERENCE IN) –VS (–5.2V) VMID +VS (GND) RSET GND (–VS) 0.01mF GND (–VS) VS (–VS) +VS (GND) GND (VCO IN) GND (VCO IN) VCO IN (–VS) OUTPUT AD9901 REG DA2 1kV 180V VMID ALL RESISTORS 65% ALL CAPACITORS 620% ALL SUPPLY VOLTAGES 65% VMID = –1.3V 65% ECL HIGH DA2 ECL LOW STATIC: DA2 = ECL HIGH; DA3 = ECL LOW Die Dimensions . . . . . . . . . . . . . . . . . 63 × 118 × 16 (± 2) mils Pad Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 × 4 mils Metalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Aluminum Backing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . None Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –VS Passivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nitride Die Attach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gold Eutectic Bond Wire . . . . . . . . 1.25 mil Aluminum; Ultrasonic Bonding DYNAMIC: ECL HIGH ECL HIGH DA3 ECL LOW ORDERING GUIDE Model Temperature Ranges Package Descriptions Package Options AD9901KQ AD9901KP AD9901TQ/883 1 AD9901TE/8831 0°C to +70°C 0°C to +70°C –55°C to +125°C –55°C to +125°C 14-Lead Cerdip 20-Lead Plastic Leaded Chip Carrier 14-Lead Cerdip 20-Terminal Ceramic Leadless Chip Carrier Q-14 P-20A Q-14 E-20A NOTE 1 For specifications, refer to Analog Devices Military Products Databook. REV. B –3– AD9901 TTL/CMOS MODE FUNCTIONAL PIN DESCRIPTIONS ECL MODE FUNCTIONAL PIN DESCRIPTIONS GROUND –VS Negative supply connection, nominally –5.2 V for ECL operation. BIAS Connect to –5.2 V for ECL operation. VCO INPUT Inverted side of ECL compatible differential input, normally connected to the VCO output signal. VCO INPUT Noninverted side of ECL-compatible differential input, normally connected to the VCO output signal. OUTPUT The noninverted output. In ECL mode, the output swing is approximately 0 V to –1.8 V. GROUND Ground connections for AD9901. Connect all grounds together and to low-impedance ground plane as close to the device as possible. RSET External RSET connection. The current through the RSET resistor is equal to the maximum full-scale output current. RSET should be connected to –VS through an external resistor in ECL mode. ISET = 0.47 V/RSET = ILOAD (max). OUTPUT The inverted output. In ECL mode, the output swing is approximately 0 V to –1.8 V. REFERENCE INPUT Noninverted side of ECL-compatible differential input, normally connected to the reference input signal. The VCO INPUT and the REFERENCE INPUT are equivalent to one another. REFERENCE INPUT Inverted side of ECL-compatible differential input, normally connected to the reference input signal. The VCO INPUT and the REFERENCE INPUT are equivalent. Ground connections for AD9901. Connect all grounds together and to low impedance ground plane as close to the device as possible. +VS Positive supply connection; nominally +5.0 V for TTL operation. BIAS Connect to +VS (+5 V) for TTL operation. VCO INPUT TTL compatible input; normally connected to the VCO output signal. VCO INPUT and REFERENCE INPUT are equivalent to one another. OUTPUT The noninverted output. In TTL/CMOS mode, the output swing is approximately +3.2 V to +5 V. RSET External RSET connection. The current through the RSET resistor is equal to the maximum full-scale output current. RSET should be connected to ground through an external resistor in TTL mode. ISET = 0.47 V/RSET = ILOAD (max). OUTPUT The inverted output. In TTL/CMOS mode, the output swing is approximately +3.2 V to +5 V. REFERENCE INPUT TTL compatible input, normally connected to the reference input signal. The VCO INPUT and the REFERENCE INPUT are equivalent. +VS R2 REFERENCE OUTPUT +VS OUTPUT –VS R1 REFERENCE REFERENCE INPUT –VS INPUT RSET AD9901 R2 R1 OUTPUT RSET AD9901 REG BIAS +VS VCO INPUT OUTPUT REG +VS BIAS R3 VCO VCO –VS OUTPUT INPUT INPUT R3 –VS +VS Figure 1. TTL Mode (Based on DIP Pinouts) Figure 2. ECL Mode (Based on DIP Pinouts) –4– REV. B AD9901 EXPLANATION OF TEST LEVELS Test Level I – 100% production tested. II – 100% production tested at +25°C, and sample tested at specified temperatures. III – Sample tested only. IV – Parameter is guaranteed by design and characterization testing. V – Parameter is a typical value only. VI – All devices are 100% production tested at +25°C. 100% production tested at temperature extremes for extended temperature devices; sample tested at temperature extremes for commercial/industrial devices. PIN CONFIGURATIONS ECL DIP Pinouts TTL DIP Pinouts GROUND 1 14 BIAS 2 13 GROUND 3 12 AD9901 GROUND –VS 1 14 REFERENCE INPUT GROUND BIAS 2 13 REFERENCE INPUT VCO INPUT REFERENCE INPUT GROUND 4 TOP VIEW 11 +VS (Not to Scale) 10 VCO INPUT 5 OUTPUT OUTPUT 6 +VS 7 GROUND 8 –VS VCO INPUT 4 11 GROUND OUTPUT 6 9 RSET GROUND 7 8 –VS AD9901 TOP VIEW (Not to Scale) 10 –VS 5 OUTPUT RSET 9 12 3 20 19 GROUND 4 NC 5 AD9901 GROUND 6 TOP VIEW (Not to Scale) NC 7 VCO INPUT 8 18 REFERENCE INPUT 17 NC 16 +VS VCO INPUT 4 NC 5 15 NC VCO INPUT 6 14 OUTPUT REFERENCE INPUT 1 NC GROUND 2 –VS NC 3 BIAS GROUND GROUND BIAS TTL LCC Pinouts REFERENCE INPUT ECL LCC Pinouts 3 2 1 20 19 AD9901 TOP VIEW (Not to Scale) NC 7 REV. B 9 10 11 12 13 NC NC GROUND RSET NC = NO CONNECT +VS NC 8 14 OUTPUT GROUND 15 NC 14 OUTPUT RSET –VS REFERENCE INPUT NC REFERENCE INPUT 15 GROUND OUTPUT +VS 3 2 1 20 19 PIN 1 IDENTIFIER VCO INPUT 4 VCO INPUT 5 AD9901 –VS 6 TOP VIEW (Not to Scale) OUTPUT 7 NC 8 NC = NO CONNECT –5– 9 10 11 12 13 RSET TOP VIEW (Not to Scale) OUTPUT 7 NC 16 –VS AD9901 VCO INPUT 6 REFERENCE INPUT 17 18 NC GROUND 5 NC PIN 1 IDENTIFIER GROUND 4 BIAS GROUND 19 –VS GROUND 20 NC NC 1 NC 16 10 11 12 13 GROUND BIAS GROUND 2 –VS ECL PLCC Pinouts TTL PLCC Pinouts 3 9 NC = NO CONNECT NC RSET GROUND 10 11 12 13 NC 9 +VS NC = NO CONNECT OUTPUT –VS 8 18 17 18 –VS 17 NC 16 GROUND 15 NC 14 OUTPUT AD9901 THEORY OF OPERATION REFERENCE INPUT A phase detector is one of three basic components of a phaselocked loop (PLL); the other two are a filter and a tunable oscillator. A basic PLL control system is shown in Figure 3. OSCILLATOR INPUT REFERENCE FLIP-FLOP OUTPUT REFERENCE INPUT LOWPASS FILTER VCO OSCILLATOR FLIP-FLOP OUTPUT OSCILLATOR OUTPUT 1/N Figure 6. Timing Waveforms (φOUT Lags φIN) OPTIONAL 1/N PRESCALER TYPICAL OF DIGITAL PLLs Figure 3. Phase-Locked Loop Control System The function of the phase detector is to generate an error signal that is used to retune the oscillator frequency whenever its output deviates from a reference input signal. The two most common methods of implementing phase detectors are (1) an analog mixer and (2) a family of sequential logic circuits known as digital phase detectors. The AD9901 is a digital phase detector. As illustrated in the block diagram of the unit, straightforward sequential logic design is used. The main components include four “D” flip-flops, an exclusive-OR gate (XOR) and some combinational output logic. The circuit operates in two distinct modes: as a linear phase detector and as a frequency discriminator. oscillator leading the reference frequency; and with the oscillator lagging. This output pulse train is low-pass filtered to extract the dc mean value [Kφ (φI – φO)] where Kφ is a proportionality constant (phase gain). At or near lock (Figures 4, 5 and 6), only the two input flipflops and the exclusive-OR gate (the phase detection circuit) are active. The input flip-flops divide both the reference and oscillator frequencies by a factor of two. This insures that inputs to the exclusive-OR are square waves, regardless of the input duty cycles of the frequencies being compared. This division-by-two also moves the nonlinear detection range to the ends of the range rather than near lock, which is the case with conventional digital phase detectors. Figure 7 illustrates the constant gain near lock. When the reference and oscillator are very close in frequency, only the phase detection circuit is active. If the two inputs are substantially different in frequency, the frequency discrimination circuit overrides the phase detector portion to drive the oscillator frequency toward the reference frequency and put it within range of the phase detector. 2 OUTPUT VOLTAGE SWING FO = 70MHz Input signals to the AD9901 are pulse trains, and its output duty cycle is proportional to the phase difference of the oscillator and reference inputs. Figures 4, 5 and 6 illustrate, respectively, the input/output relationships at lock; with the FO = 200MHz OSCILLATOR INPUT TYPICAL PHASE DETECTOR GAIN IS 0.2865V/RAD DVOUT = 1.8V 0 –2p REFERENCE FLIP-FLOP OUTPUT –p PHASE DIFFERENCE AT INPUTS 0 Figure 7. Phase Gain Plot DC MEAN VALUE XORGATE OUTPUT Figure 4. AD9901 Timing Waveforms at “Lock” REFERENCE INPUT OSCILLATOR INPUT When the two square waves are combined by the XOR, the output has a 50% duty cycle if the reference and oscillator inputs are exactly 180° out of phase; under these conditions, the AD9901 is operating in a locked mode. Any shift in the phase relationship between these input signals causes a change in the output duty cycle. Near lock, the frequency discriminator flipflops provide constant HIGH levels to gate the XOR output to the final output. The duty cycle of the AD9901 is a direct measure of the phase difference between the two input signals when the unit is near lock. The transfer function can be stated as [Kφ(φI – φO](V/RAD), where Kφ is the allowable output voltage range of the AD9901 divided by 2 π. REFERENCE FLIP-FLOP OUTPUT OSCILLATOR FLIP-FLOP OUTPUT FO = 50MHz 1 REFERENCE INPUT OSCILLATOR FLIP-FLOP OUTPUT DC MEAN VALUE XORGATE OUTPUT AD9901 DC MEAN VALUE XORGATE OUTPUT Figure 5. Timing Waveforms (φ OUT Leads φ IN) For a typical output swing of 1.8 V, the transfer function can be stated as (1.8 V/2 π = 0.285 V/RAD). Figure 7 shows the relationship of the dc mean value of the AD9901 output as a function of the phase difference of the two inputs. –6– REV. B AD9901 500mV 500mV 500mV 100 100 90 100 90 90 10 10 10 0% 0% 0% Figure 8. AD9901 Output Waveform (FO > FI ) 165 It is important to note that the slope of the transfer function is constant near its midpoint. Many digital phase comparators have an area near the lock point where their gain goes to zero, resulting in a “dead zone.” This causes increased phase noise (jitter) at the lock point. 155 VCO FREQUENCY – MHz 145 The AD9901 avoids this dead zone by shifting it to the endpoints of the transfer curve, as indicated in Figure 7. The increased gain at either end increases the effective error signal to pull the oscillator back into the linear region. This does not affect phase noise, which is far more dependent upon lock region characteristics. It should be noted, however, that as frequency increases, the linear range is decreased. At the ends of the detection range, the reference and oscillator inputs approach phase alignment. At this point, slew rate limiting in the detector effectively increases phase gain. This decreases the linear detection by nominally 3.6 ns. Therefore, the typical detection range can be found by calculating [(1/F – 3.6 ns)/(1/F)] × 360°. As an example, at 200 MHz the linear phase detection range is ±50°. Away from lock, the AD9901 becomes a frequency discriminator. Any time either the reference or oscillator input occurs twice before the other, the Frequency High or Frequency Low flip-flop is clocked to logic LOW. This overrides the XOR output and holds the output at the appropriate level to pull the oscillator toward the reference frequency. Once the frequencies are within the linear range, the phase detector circuit takes over again. Combining the frequency discriminator with the phase detector eliminates locking to a harmonic of the reference. Figure 8 shows the effect of the “Frequency Low” flip-flop when the oscillator frequency is much lower than the reference input. The narrow pulses, which result from cycles when two positive reference-input transitions occur before a positive VCO edge, increase the dc mean value. Figure 9 illustrates the inverse effect when the “Frequency High” flip-flop reacts to a much higher VCO frequency. Figure 10. AD9901 Output Waveform (FO = FI = 50 MHz) 135 125 115 105 95 85 75 65 –1 0 1 2 3 4 5 VARACTORS TUNING VOLTAGE – Volts 6 Figure 11. VCO Frequency vs. Voltage Next, the range of frequencies over which the VCO is to operate is examined to assure that it lies on a linear portion of the transfer curve. In this case, frequencies from 100 MHz to 120 MHz result from tuning voltages of approximately +1.5 V to +2.5 V. Because the nominal output swing of the AD9901 is 0 V to –1.8 V, an inverting amplifier with a gain of 2 follows the loop filter. As shown in the illustration, a simple passive RC low-pass filter made up of two resistors and a tantalum capacitor eliminates the need for an expensive high speed op amp active-filter design. In this passive-filter second-order-loop system, where n = 2, the damping factor is equal to: δ = 0.5 [KOK d /n(τ1 + τ2)]1/2 [τ2 + (n/KO Kd)] and the values for τ1 and τ2 are the low-pass filter’s time constants R1C and R2C. The gain of 2 of the inverting stage, when combined with the phase detector’s gain, gives: Kd = 0.572 V/RAD Figure 10 shows the output waveform at lock for 50 MHz operation. This output results when the phase difference between reference and oscillator is approximately – πRad. With KO = 115.2 MRAD/s/V, τ1 equals 1.715s, and τ2 equals 3.11 × 10–4s for the required damping factor of 0.7. The illustrated values of 30 Ω (R1), 160 Ω (R2), and 10 µF (C) in the diagram approximate these time constants. The gain of the RC filter is: VO/VI = (1 + sR2C)/[1 + s(R1 + R2)C]. AD9901 APPLICATIONS Where KOKd >> ωn, the system’s natural frequency: The figure below illustrates a phase-locked loop (PLL) system utilizing the AD9901. The first step in designing this type of circuit is to characterize the VCO’s output frequency as a function of tuning voltage. The transfer function of the oscillator in the diagram is shown in Figure 11. For general information about phase-locked loop design, the user is advised to consult the following references: Gardner, Phase-Lock Techniques (Wiley); or Best, Phase Locked Loops (McGraw-Hill). REV. B ωn = [KOK d /n(τ1 + τ2)]1/2 = 4.5 kHz. –7– AD9901 REFERENCE INPUT 55MHz AD96685 OFFSET –5.2V +5.0V 182V REF REF –5.2V AD9901 OUTPUT OUTPUT OSC OUT AD9901 1kV AD741 30V 390V 10mF RSET AD741 LOOP FILTER –5.2V DIP PINOUTS 2kV 160kV OUT OSC 47.5V –5.2V 1kV C1272b–0–1/99 +VS OSCILLATOR OUTPUT 110MHz MV1404 OSCILLATOR MC1648 DIVIDEBY-TWO ALTERNATE HIGH LEVEL OUTPUT CIRCUIT (6VS TYPICALLY +15V TO +60V) 51kV MV1404 50V 50V 50V 100nH –5.2V –5.2V –2V –2V Figure 12. Phased-Locked Loop Using AD9901 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead Cerdip (Q-14) 0.005 (0.13) MIN 0.098 (2.49) MAX 14 8 1 7 0.310 (7.87) 0.220 (5.59) 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 0.100 0.070 (1.78) SEATING PLANE (2.54) 0.030 (0.76) BSC 20-Terminal Ceramic Leadless Chip Carrier (E-20A) 0.075 (1.91) REF 0.100 (2.54) 0.064 (1.63) 0.358 (9.09) 0.358 (9.09) 0.342 (8.69) MAX SQ SQ 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.088 (2.24) 0.054 (1.37) 20-Lead Plastic Leaded Chip Carrier (P-20A) 0.200 (5.08) BSC 19 18 20 1 BOTTOM VIEW 14 13 0.055 (1.40) 0.045 (1.14) 0.015 (0.38) MIN 0.048 (1.21) 0.042 (1.07) 0.028 (0.71) 0.022 (0.56) 0.056 (1.42) 0.042 (1.07) 19 18 PIN 1 IDENTIFIER (PINS DOWN) 8 9 9 0.020 (0.50) R 45° TYP 0.150 (3.81) BSC –8– 0.025 (0.63) 0.015 (0.38) 3 4 TOP VIEW 0.050 (1.27) BSC 8 0.180 (4.57) 0.165 (4.19) 0.048 (1.21) 0.042 (1.07) 0.100 (2.54) BSC 3 4 0.015 (0.38) 0.008 (0.20) 15° 0° 0.021 (0.53) 0.013 (0.33) 0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.050 (1.27) BSC 14 13 0.356 (9.04) SQ 0.350 (8.89) 0.395 (10.02) SQ 0.385 (9.78) 0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16) REV. B PRINTED IN U.S.A. PIN 1 0.785 (19.94) MAX