AD9915/PCBZ

Data Sheet AD9915 2.5 GSPS Direct Digital Synthesizer with 12-Bit DAC FEATURES ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► ► FUNCTIONAL BLOCK DIAGRAM 2.5 GSPS internal clock speed Integrated 12-bit DAC Frequency tuning resolution to 135 pHz 16-bit phase tuning resolution 12-bit amplitude scaling Programmable modulus Automatic linear and nonlinear frequency sweeping capability 32-bit parallel datapath interface 8 frequency/phase offset profiles Phase noise: −128 dBc/Hz (1 kHz offset at 978 MHz) Wideband SFDR < −57 dBc Serial or parallel input/output control 1.8 V/3.3 V power supplies Software and hardware controlled power-down 88-lead LFCSP package PLL REF CLK multiplier Phase modulation capability Amplitude modulation capability Multichip synchronization Figure 1. APPLICATIONS ► ► ► ► ► ► ► Agile LO frequency synthesis Programmable clock generator FM chirp source for radar and scanning systems Test and measurement equipment Acousto-optic device drivers Polar modulator Fast frequency hopping Rev. G DOCUMENT FEEDBACK TECHNICAL SUPPORT Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Data Sheet AD9915 TABLE OF CONTENTS Features................................................................ 1 Applications........................................................... 1 Functional Block Diagram......................................1 General Description...............................................4 Specifications........................................................ 5 DC Specifications............................................... 5 AC Specifications............................................... 6 Absolute Maximum Ratings...................................9 Thermal Performance.........................................9 ESD Caution.......................................................9 Pin Configuration and Function Descriptions...... 10 Typical Performance Characteristics................... 12 Equivalent Circuits...............................................16 Theory of Operation.............................................17 Single Tone Mode.............................................17 Profile Modulation Mode...................................17 Digital Ramp Modulation Mode........................ 17 Parallel Data Port Modulation Mode.................17 Programmable Modulus Mode......................... 18 Mode Priority.................................................... 18 Functional Block Detail........................................ 20 DDS Core......................................................... 20 12-Bit DAC Output............................................21 DAC Calibration Output....................................21 Reconstruction Filter........................................ 21 Clock Input (REF_CLK/REF_CLK)...................22 Output Shift Keying (OSK)............................... 23 Digital Ramp Generator (DRG)........................ 24 Power-Down Control........................................ 29 Programming and Function Pins......................... 31 Serial Programming.............................................34 Control Interface—Serial Input/Output............. 34 General Serial Input/Output Operation.............34 Instruction Byte.................................................34 Serial Input/Output Port Pin Descriptions.........34 Serial Input/Output Timing Diagrams............... 35 MSB/LSB Transfers..........................................35 Parallel Programming (8-/16-Bit)......................... 36 Multiple Chip Synchronization............................. 37 Register Map and Bit Descriptions...................... 40 Register Bit Descriptions.................................. 44 Outline Dimensions............................................. 51 Ordering Guide.................................................51 Evaluation Boards............................................ 51 REVISION HISTORY 6/2022—Rev. F to Rev. G Changes to Base DDS Power, PLL Disabled Parameter and Base DDS Power, PLL Enabled Parameter, Table 1.........................................................................................................................................5 Changes to SCLK Clock Rate (1/tCLK) Parameter and Data Latency (Pipeline Delay) Parameter, Table 2.... 6 Changes to Table 5........................................................................................................................................ 10 Change to Figure 6 Caption and Figure 12 Caption...................................................................................... 12 Change to Figure 22...................................................................................................................................... 15 Change to Profile Modulation Mode Section..................................................................................................17 Changes to Digital Ramp Modulation Mode Section..................................................................................... 17 Changes to Parallel Data Clock (SYNC_CLK) Section..................................................................................17 Changes to Programmable Modulus Mode Section...................................................................................... 18 Changes to Reconstruction Filter Section......................................................................................................21 Changes to REF_CLK/REF_CLK Overview Section and Figure 32.............................................................. 22 Changes to Direct Driven REF_CLK/REF_CLK Section............................................................................... 22 Changes to Phase-Locked Loop (PLL) Multiplier Section............................................................................. 22 Changes to PLL Lock Indication Section....................................................................................................... 23 Changes to DRG Overview Section and Table 9........................................................................................... 24 Added Table 10; Renumbered Sequentially...................................................................................................24 Changes to DRG Slope Control Section........................................................................................................25 Changes to DRG Limit Control Section......................................................................................................... 26 Changes to Figure 38.................................................................................................................................... 26 Changes to No-Dwell Ramp Generation Section...........................................................................................27 Changes to Figure 39.................................................................................................................................... 28 Changes to DROVER Pin Section................................................................................................................. 29 analog.com Rev. G | 2 of 51 Data Sheet AD9915 TABLE OF CONTENTS Changes to Frequency Jumping Capability in DRG Mode Section .............................................................. 29 Changes to Figure 40.................................................................................................................................... 29 Changes to Power-Down Control Section .................................................................................................... 29 Changes to Programming and Function Pins Section................................................................................... 31 Changes to Multiple Chip Synchronization Section....................................................................................... 37 Changes to Figure 48 and Figure 49............................................................................................................. 38 Changes to Table 17...................................................................................................................................... 40 Changes to Table 18...................................................................................................................................... 45 Changes to Table 19...................................................................................................................................... 46 Changes to Table 20...................................................................................................................................... 47 Changes to Lower Frequency Jump Register—Address 0x09 Section and Table 27................................... 49 Changes to Upper Frequency Jump Register—Address 0x0A Section and Table 28................................... 49 Changes to Table 30...................................................................................................................................... 49 analog.com Rev. G | 3 of 51 Data Sheet AD9915 GENERAL DESCRIPTION The AD9915 is a direct digital synthesizer (DDS) featuring a 12‑bit DAC. The AD9915 uses advanced DDS technology, coupled with an internal high speed, high performance DAC to form a digitally programmable, complete high frequency synthesizer capable of generating a frequency agile analog output sinusoidal waveform at up to 1.0 GHz. The AD9915 enables fast frequency hopping and fine tuning resolution (64‑bit capable using programmable modulus mode). The AD9915 also offers fast phase and amplitude hopping capability. The frequency tuning and control words are loaded into the AD9915 via a serial or parallel input/output port. The AD9915 also supports a user defined linear sweep mode of operation for generating linear swept waveforms of frequency, phase or amplitude. A high speed, 32-bit parallel data input port is included, enabling high data rates for polar modulation schemes and fast reprogramming of the phase, frequency, and amplitude tuning words. The AD9915 is specified to operate over the extended industrial temperature range (see the Absolute Maximum Ratings section). Figure 2. Detailed Block Diagram analog.com Rev. G | 4 of 51 Data Sheet AD9915 SPECIFICATIONS DC SPECIFICATIONS AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT = 20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. Table 1. Parameter Min Typ Max Unit Test Conditions/Comments SUPPLY VOLTAGE DVDD_I/O DVDD AVDD (3.3 V) 3.135 1.71 3.135 3.30 1.80 3.30 3.465 1.89 3.465 V V V 1.71 1.80 1.89 V 20 270 640 mA mA mA 148 mA Pin 16, Pin 83 Pin 6, Pin 23, Pin 73 Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin 60 Pin 32, Pin 56, Pin 57 See also the total power dissipation specifications Pin 16, Pin 83 Pin 6, Pin 23, Pin 73 Pin 34, Pin 36, Pin 39, Pin 40, Pin 43, Pin 47, Pin 50, Pin 52, Pin 53, Pin 60 Pin 32, Pin 56, Pin 57 AVDD (1.8 V) SUPPLY CURRENT IDVDD_I/O IDVDD IAVDD(3.3V) IAVDD(1.8V) TOTAL POWER DISSIPATION Base DDS Power, PLL Disabled 2138 2797 mW Base DDS Power, PLL Enabled 2237 2890 mW Linear Sweep Additional Power Modulus Additional Power Amplitude Scaler Additional Power Full Power-Down Mode 28 20 138 400 616 mW mW mW mW CMOS LOGIC INPUTS Input High Voltage (VIH) Input Low Voltage (VIL) Input Current (IINH, IINL) Maximum Input Capacitance (CIN) CMOS LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) REF CLK INPUT CHARACTERISTICS REF CLK Multiplier Bypassed Input Capacitance Input Resistance Internally Generated DC Bias Voltage Differential Input Voltage REF CLK Multiplier Enabled Input Capacitance Input Resistance Internally Generated DC Bias Voltage Differential Input Voltage analog.com 2.0 ±60 3 2.7 1 1.4 2 0.8 1 1.4 2 0.8 2.5 GHz, single-tone mode, programmable modulus disabled, linear sweep disabled, amplitude scaler disabled 2.5 GHz, single-tone mode, programmable modulus disabled, linear sweep disabled, amplitude scaler disabled Manual or automatic Using either the power-down and enable register or the EXT_PWR_DWN pin DVDD_I/O 0.8 ±200 V V µA pF DVDD_I/O 0.4 V V IOH = 1 mA IOL = 1 mA REF CLK inputs must always be ac-coupled (both single-ended and differential) Single-ended, each pin Differential 1.5 pF kΩ V V p-p Single-ended, each pin Differential 1.5 pF kΩ V V p-p At VIN = 0 V and VIN = DVDD_I/O Rev. G | 5 of 51 Data Sheet AD9915 SPECIFICATIONS AC SPECIFICATIONS AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V ± 5%, AVDD3 (3.3 V) and DVDD_I/O (3.3 V) = 3.3 V ± 5%, TA = 25°C, RSET = 3.3 kΩ, IOUT = 20 mA, external reference clock frequency = 2.5 GHz with reference clock (REF CLK) multiplier bypassed, unless otherwise noted. Table 2. Parameter REF CLK INPUT REF CLK Multiplier Bypassed Input Frequency Range Duty Cycle Minimum Differential Input Level System Clock (SYSCLK) PLL Enabled VCO Frequency Range VCO Gain (KV) Maximum PFD Rate CLOCK DRIVERS SYNC_CLK Output Driver Frequency Range Duty Cycle Rise Time/Fall Time (20% to 80%) SYNC_OUT Output Driver Frequency Range Duty Cycle Rise Time (20% to 80%) Fall Time (20% to 80%) DAC OUTPUT CHARACTERISTICS Output Frequency Range (1st Nyquist Zone) Output Resistance Output Capacitance Full-Scale Output Current Gain Error Output Offset Voltage Compliance Range Wideband SFDR 122.5 MHz Output 305.3 MHz Output 497.5 MHz Output 978.2 MHz Output Narrow-Band SFDR 122.5 MHz Output 305.3 MHz Output 497.5 MHz Output 978.2 MHz Output DIGITAL TIMING SPECIFICATIONS Time Required to Enter Power-Down Time Required to Leave Power-Down Minimum Master Reset time Maximum DAC Calibration Time (tCAL) analog.com Min Typ Max Unit Test Conditions/Comments Input frequency range 500 45 632 2500 55 2400 2500 60 125 45 50 650 MHz % mV p-p Maximum fOUT is 0.4 × fSYSCLK Equivalent to 316 mV swing on each leg MHz MHz/V MHz 156 55 MHz % ps 6.5 66 MHz % ps ps 1250 MHz Ω 10 pF load 33 1350 1670 0 50 1 20.48 +10 0.6 AVDD + 0.50 −10 AVDD − 0.50 pF mA % FS μA V −67 −66 −59 −60 dBc dBc dBc dBc −95 −95 −95 −92 dBc dBc dBc dBc 45 250 ns ns SYSCLK cycles µs 24 188 CFR2 register, Bit 9 = 1 10 pF load 10 pF load Single-ended (each pin internally terminated to AVDD (3.3 V)) Range depends on DAC RSET resistor See the Typical Performance Characteristics section 0 MHz to 1250 MHz 0 MHz to 1250 MHz 0 MHz to 1250 MHz 0 MHz to 1250 MHz See the Typical Performance Characteristics section ±500 kHz ±500 kHz ±500 kHz ±500 kHz Power-down mode loses DAC/PLL calibration settings Must recalibrate DAC/PLL See the DAC Calibration Output section for formula; Bit 6 in Register 0x1B = 0 Rev. G | 6 of 51 Data Sheet AD9915 SPECIFICATIONS Table 2. Parameter Min Typ Maximum PLL Calibration Time (tREF_CLK) Maximum Profile Toggle Rate PARALLEL PORT TIMING Write Timing Address Setup Time to WR Active Address Hold Time to WR Inactive Data Setup Time to WR Inactive Data Hold Time to WR Inactive WR Minimum Low Time WR Minimum High Time Minimum WR Time Read Timing Address to Data Valid Address Hold to RD Inactive RD Active to Data Valid RD Inactive to Data Tristate RD Minimum Low Time RD Minimum High Time SERIAL PORT TIMING SCLK Clock Rate (1/tCLK) SCLK Pulse Width High, tHIGH SCLK Pulse Width Low, tLOW SDIO to SCLK Setup Time, tDS SDIO to SCLK Hold Time, tDH SCLK Falling Edge to Valid Data on SDIO/ SDO, tDV CS to SCLK Setup Time, tS CS to SCLK Hold Time, tH CS Minimum Pulse Width High, tPWH DATA PORT TIMING D[31:0] Setup Time to SYNC_CLK D[31:0] Hold Time to SYNC_CLK F[3:0] Setup Time to SYNC_CLK F[3:0] Hold Time to SYNC_CLK IO_UPDATE Pin Setup Time to SYNC_CLK IO_UPDATE Pin Hold Time to SYNC_CLK Profile Pin Setup Time to SYNC_CLK Profile Pin Hold Time to SYNC_CLK DR_CTL/DR_HOLD Setup Time to SYNC_CLK DR_CTL/DR_HOLD Hold Time to SYNC_CLK DATA LATENCY (PIPELINE DELAY) Single Tone Mode or Profile Mode (Matched Latency Disabled) Frequency Phase analog.com Max Unit Test Conditions/Comments 16 8 2 ms ms SYNC_CLK period PFD rate = 25 MHz PFD rate = 50 MHz 1 0 2.1 3.8 10.5 ns ns ns ns ns ns ns 92 0 69 50 69 50 ns ns ns ns ns ns 80 MHz 0 78 ns ns ns ns ns 0 3.8 1.5 5.1 4.9 4 0 4 2 0 2 0 2 0 2 0 2 0 SCLK duty cycle = 50%; maximum SCLK rate applies only to write cycles; read cycles are constrained to