AD9948

10-Bit CCD Signal Processor with Precision Timing ™ Core AD9948 FEATURES Correlated Double Sampler (CDS) 0 dB to 18 dB Pixel Gain Amplifier (PxGA®) 6 dB to 42 dB 10-Bit Variable Gain Amplifier (VGA) 10-Bit 25 MSPS A/D Converter Black Level Clamp with Variable Level Control Complete On-Chip Timing Driver Precision Timing Core with 800 ps Resolution On-Chip 3 V Horizontal and RG Drivers 40-Lead LFCSP Package APPLICATIONS Digital Still Cameras High Speed Digital Imaging Applications GENERAL DESCRIPTION The AD9948 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to 25 MHz, the AD9948 consists of a complete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with 800 ps resolution. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 25 MHz 10-bit A/D converter. The timing driver provides the high speed CCD clock drivers for RG and H1–H4. Operation is programmed using a 3-wire serial interface. Packaged in a space-saving 40-lead LFCSP package, the AD9948 is specified over an operating temperature range of –20° C to +85° C. FUNCTIONAL BLOCK DIAGRAM REFT REFB 0dB TO 18dB CDS PxGA 6dB TO 42dB VGA VREF 10-BIT ADC 10 DOUT CCDIN CLAMP INTERNAL CLOCKS HBLK CLP/PBLK RG H1–H4 4 HORIZONTAL DRIVERS PRECISION TIMING CORE CLI AD9948 SYNC GENERATOR INTERNAL REGISTERS HD VD SL SCK SDATA R EV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved. AD9948–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) HVDD (H1–H4 Drivers) RGVDD (RG Driver) DRVDD (D0–D9 Drivers) DVDD (All Other Digital) POWER DISSIPATION 25 MHz, HVDD = RGVDD = 3 V, 100 pF H1–H4 Loading* Total Shutdown Mode *The total power dissipated by the HVDD supply may be approximated using the equation Min –20 –65 25 2.7 2.7 2.7 2.7 2.7 Typ Max +85 +150 Unit °C °C MHz 3.0 3.0 3.0 3.0 3.0 220 1 3.6 3.6 3.6 3.6 3.6 V V V V V mW mW Total HVDD Power = (CLOAD × HVDD × Pixel Frequency) × HVDD × ( Number of H − Outputs Used ) Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply will reduce the power dissipation. Specifications subject to change without notice. DIGITAL SPECIFICATIONS Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance (TMIN to TMAX, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, CL = 20 pF, unless otherwise noted.) Symbol VIH VIL IIH IIL CIN VOH VOL Min 2.1 0.6 10 10 10 2.2 0.5 Typ Max Unit V V µA µA pF V V LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA CLI INPUT High Level Input Voltage (TCVDD/2 + 0.5 V) Low Level Input Voltage RG AND H-DRIVER OUTPUTS High Level Output Voltage (RGVDD – 0.5 V and HVDD – 0.5 V) Low Level Output Voltage Maximum Output Current (Programmable) Maximum Load Capacitance Specifications subject to change without notice. VIH–CLI VIL–CLI 1.85 0.85 V V VOH VOL 2.2 0.5 30 100 V V mA pF –2– R EV. 0 AD9948 ANALOG SPECIFICATIONS Parameter CDS Gain Allowable CCD Reset Transient* Max Input Range before Saturation* Max CCD Black Pixel Amplitude* PIXEL GAIN AMPLIFIER (PxGA) Gain Control Resolution Gain Monotonicity Min Gain Max Gain VARIABLE GAIN AMPLIFIER (VGA) Max Input Range Max Output Range Gain Control Resolution Gain Monotonicity Gain Range Min Gain (VGA Code 0) Max Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Min Clamp Level (0) Max Clamp Level (255) A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE VGA Gain Accuracy Min Gain (Code 0) Max Gain (Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) *Input signal characteristics defined as follows: (TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 25 MHz, Typical Timing Specifications, unless otherwise noted.) Min Typ 0 500 1.0 ± 50 256 0 18 1.0 2.0 1024 Guaranteed 6 42 256 0 63.75 10 –1.0 Max Unit dB mV V p-p mV Steps dB dB V p-p V p-p Steps Notes dB dB Steps Measured at ADC output LSB LSB Bits LSB V V V Specifications include entire signal chain ± 0.5 Guaranteed 2.0 2.0 1.0 +1.0 5.0 40.5 5.5 41.5 0.2 0.25 50 6.0 42.5 dB dB % LSB rms dB 12 dB gain applied AC grounded input, 6 dB gain applied Measured with step change on supply 500mV TYP RESET TRANSIENT 50mV MAX OPTICAL BLACK PIXEL 1V MAX INPUT SIGNAL RANGE Specifications subject to change without notice. R EV. 0 –3– AD9948 TIMING SPECIFICATIONS Parameter MASTER CLOCK (CLI) (See Figure 4) CLI Clock Period CLI High/Low Pulsewidth Delay from CLI to Internal Pixel Period Position CLPOB Pulsewidth (Programmable)* SAMPLE CLOCKS (See Figure 6) SHP Rising Edge to SHD Rising Edge DATA OUTPUTS (See Figures 7a and 7b) Output Delay From Programmed Edge Pipeline Delay SERIAL INTERFACE Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read Specifications subject to change without notice. (CL = 20 pF, fCLI = 25 MHz, Serial Timing in Figure 3, unless otherwise noted.) Symbol tCLI tADC tCLIDLY tCOB tS1 tOD 2 17 Min 40 16 Typ Max Unit ns ns ns Pixels ns ns Cycles MHz ns ns ns ns ns 20 6 20 20 6 11 24 fSCLK tLS tLH tDS tDH tDV 10 10 10 10 10 10 *Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference. ABSOLUTE MAXIMUM RATINGS * Parameter AVDD, TCVDD HVDD, RGVDD DVDD, DRVDD Any VSS Digital Outputs CLPOB/PBLK, HBLK SCK, SL, SDATA RG H1–H4 REFT, REFB, CCDIN Junction Temperature Lead Temperature (10 sec) With Respect To AVSS HVSS, RGVSS DVSS, DRVSS Any VSS DRVSS DVSS DVSS RGVSS HVSS AVSS Min –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 Max +3.9 +3.9 +3.9 +0.3 DRVDD + 0.3 DVDD + 0.3 DVDD + 0.3 RGVDD + 0.3 HVDD + 0.3 AVDD + 0.3 150 300 Unit V V V V V V V V V V °C °C *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE THERMAL CHARACTERISTICS Thermal Resistance Model AD9948KCP AD9948KCPRL AD9948KCPZ* AD9948KCPZRL* Temperature Range –20°C to +85°C –20°C to +85°C –20°C to +85°C –20°C to +85°C Package Package Description Option LFCSP LFCSP LFCSP LFCSP CP-40 CP-40 CP-40 CP-40 40-Lead LFCSP Package JA = 27°C/W* * JA is measured using a 4-layer PCB with the exposed paddle soldered to the board. *This is a lead free product. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9948 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– R EV. 0 AD9948 PIN CONFIGURATION 39 CLP/PBLK 38 HBLK 37 DVDD 36 DVSS 33 SCK 32 SDI 40 NC 35 HD 34 VD 31 SL NC (LSB) D0 D1 D2 DRVSS DRVDD D3 D4 D5 1 2 3 4 5 6 7 8 9 PIN 1 IDENTIFIER 30 29 28 27 REFB REFT AVSS CCDIN AVDD CLI TCVDD TCVSS RGVDD RG AD9948 TOP VIEW 26 25 24 23 22 21 D6 10 (MSB) D9 13 H1 14 H2 15 HVSS 16 HVDD 17 D7 11 D8 12 H3 18 H4 19 PIN FUNCTION DESCRIPTIONS Pin No. 2–4 5 6 7–13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 1, 40 Mnemonic D0–D2 DRVSS DRVDD D3–D9 H1 H2 HVSS HVDD H3 H4 RGVSS RG RGVDD TCVSS TCVDD CLI AVDD CCDIN AVSS REFT REFB SL SDI SCK VD HD DVSS DVDD HBLK CLP/PBLK NC Type* DO P P DO DO DO P P DO DO P DO P P P DI P AI P AO AO DI DI DI DI DI P P DI DO Description Data Outputs (D0 is LSB) Digital Driver Ground Digital Driver Supply Data Outputs (D9 is MSB) CCD Horizontal Clock 1 CCD Horizontal Clock 2 H1–H4 Driver Ground H1–H4 Driver Supply CCD Horizontal Clock 3 CCD Horizontal Clock 4 RG Driver Ground CCD Reset Gate Clock RG Driver Supply Analog Ground for Timing Core Analog Supply for Timing Core Master Clock Input Analog Supply for AFE Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor) Analog Ground for AFE Reference Top Decoupling (Decouple with 1.0 µF to AVSS) Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS) 3-Wire Serial Load 3-Wire Serial Data Input 3-Wire Serial Clock Vertical Sync Pulse Horizontal Sync Pulse Digital Ground Digital Supply Optional HBLK Input CLPOB or PBLK Output Not Internally Connected *Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. R EV. 0 –5– RGVSS 20 AD9948 TERMINOLOGY Differential Nonlinearity (DNL) Total Output Noise An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit resolution indicates that all 1024 codes, respectively, must be present over all operating conditions. Peak Nonlinearity The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB, and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC full scale/ 2n codes) Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9948 from a true straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1 LSB and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately gained up to fill the ADC’s full-scale range. EQUIVALENT CIRCUITS AVDD where n is the bit resolution of the ADC. For the AD9948, 1 LSB is approximately 1.95 mV. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. DVDD R 330 AVSS AVSS Circuit 1. CCDIN (Pin 27) AVDD DVSS Circuit 4. Digital Inputs (Pins 31–35, 38) 330 CLI 1.4V 25k HVDD or RGVDD DATA AVSS Circuit 2. CLI (Pin 25) DVSS DRVDD ENABLE OUTPUT DATA HVSS or RGVSS THREESTATE DOUT Circuit 5. H1–H4 and RG (Pins 14, 15, 18, 19, 21) DVSS DRVSS Circuit 3. Data Outputs D0–D9 (Pins 2–4, 7–13) –6– R EV. 0 Typical Performance Characteristics–AD9948 1.0 0.5 DNL (LSB) 0 –0.5 –1.0 0 200 400 600 ADC OUTPUT CODE 800 1000 TPC 1. Typical DNL 10 7.5 OUTPUT NOISE (LSB) 5.0 2.5 0 0 200 400 600 VGA GAIN CODE (LSB) 800 1000 TPC 2. Output Noise vs. VGA Gain 275 250 POWER DISSIPATION (mW) 225 VDD = 3.3V 200 VDD = 3.0V 175 VDD = 2.7V 150 125 100 10 15 20 SAMPLE RATE (MHz) 25 TPC 3. Power Curves R EV. 0 –7– AD9948 SYSTEM OVERVIEW V-DRIVER V1–Vx, VSG1–VSGx, SUBCK H1–H4, RG DOUT CCDIN generates the high speed CCD clocks and all internal AFE clocks. All AD9948 clocks are synchronized with VD and HD. All of the AD9948’s horizontal pulses (CLPOB, PBLK, and HBLK) are programmed and generated internally. The H-drivers for H1–H4 and RG are included in the AD9948, allowing these clocks to be connected directly to the CCD. H-drive voltage of 3 V is supported in the AD9948. CCD AD9948 INTEGRATED AFE + TD HD, VD DIGITAL IMAGE PROCESSING ASIC Figure 2a shows the horizontal and vertical counter dimensions for the AD9948. All internal horizontal clocking is programmed using these dimensions to specify line and pixel locations. MAXIMUM FIELD DIMENSIONS CLI SERIAL INTERFACE Figure 1. Typical Application 12-BIT HORIZONTAL = 4096 PIXELS MAX Figure 1 shows the typical system application diagram for the AD9948. The CCD output is processed by the AD9948’s AFE circuitry, which consists of a CDS, a PxGA, a VGA, a black level clamp, and an A/D converter. The digitized pixel information is sent to the digital image processor chip, where all postprocessing and compression occurs. To operate the CCD, CCD timing parameters are programmed into the AD9948 from the image processor through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor, the AD9948 12-BIT VERTICAL = 4096 LINES MAX Figure 2a. Vertical and Horizontal Counters MAX VD LENGTH IS 4095 LINES VD MAX HD LENGTH IS 4095 PIXELS HD CLI Figure 2b. Maximum VD/HD Dimensions –8– R EV. 0 AD9948 SERIAL INTERFACE TIMING COMPLETE REGISTER LISTING All of the internal registers of the AD9948 are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit dataword are written starting with the LSB. To write to each register, a 32-bit operation is required, as shown in Figure 3a. Although many registers are less than 24 bits wide, all 24 bits must be written for each register. If the register is only 16 bits wide, then the upper eight bits are don’t cares and may be filled with zeros during the serial write operation. If fewer than 24 bits are written, the register will not be updated with new data. Figure 3b shows a more efficient way to write to the registers by using the AD9948’s address auto-increment capability. Using this method, the lowest desired address is written first, followed by multiple 24-bit data-words. Each new 24-bit data-word will be written automatically to the next highest register address. By eliminating the need to write each 8-bit address, faster register loading is achieved. Address auto-increment may be used starting with any register location, and may be used to write to as few as two registers or as many as the entire register space. All addresses and default values are expressed in hexadecimal. All registers are VD/HD updated as shown in Figure 3a, except for the registers indicated in Table I, which are SL updated. Table I. SL-Updated Registers Register OPRMODE CTLMODE SW_RESET TGCORE _RSTB PREVENTUPDATE VDHDEDGE FIELDVAL HBLKRETIME CLPBLKOUT CLPBLKEN H1CONTROL RGCONTROL DRVCONTROL SAMPCONTROL DOUTPHASE Description AFE Operation Modes AFE Control Modes Software Reset Bit Reset Bar Signal for Internal TG Core Prevents Update of Registers VD/HD Active Edge Resets Internal Field Pulse Retimes the HBLK to Internal Clock CLP/BLK Output Pin Select Enables CLP/BLK Output Pin H1/H2 Polarity Control H1 Positive Edge Location H1 Negative Edge Location H1 Drive Current H2 Drive Current 8-BIT ADDRESS SDATA A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 24-BIT DATA D3 ... ... ... ... ... D21 D22 D23 tDS SCK 1 2 3 4 tDH 5 6 7 8 9 10 11 12 30 31 32 tLS SL tLH SL UPDATED VD/HD UPDATED VD HD NOTES 1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES. 2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA. 3. IF THE REGISTER LENGTH IS