AD9949KCPRL

12-Bit CCD Signal Processor with Precision Timing Core AD9949 FEATURES New AD9949A supports CCD line length > 4096 pixels Correlated double sampler (CDS) 0 dB to 18 dB pixel gain amplifier (PxGA®) 6 dB to 42 dB 10-bit variable gain amplifier (VGA) 12-bit, 36 MSPS analog-to-digital converter (ADC) Black level clamp with variable level control Complete on-chip timing driver Precision Timing™ core with < 600 ps resolution On-chip 3 V horizontal and RG drivers 40-lead LFCSP package GENERAL DESCRIPTION The AD9949 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to 36 MHz, the AD9949 consists of a complete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with < 600 ps resolution. The analog front end includes black level clamping, CDS, PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver provides the high speed CCD clock drivers for RG and H1 to H4. Operation is programmed using a 3-wire serial interface. Packaged in a space-saving, 40-lead LFCSP package, the AD9949 is specified over an operating temperature range of −20°C to +85°C. APPLICATIONS Digital still cameras High speed digital imaging applications FUNCTIONAL BLOCK DIAGRAM REFT REFB 0dB TO 18dB CCDIN CDS PxGA 6dB TO 42dB VGA VREF 12-BIT ADC 12 DOUT CLAMP INTERNAL CLOCKS HBLK CLP/PBLK RG H1 TO H4 4 HORIZONTAL DRIVERS PRECISION TIMING CORE CLI AD9949 SYNC GENERATOR INTERNAL REGISTERS 03751-001 HD VD SL SCK SDATA Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD9949 TABLE OF CONTENTS Specifications..................................................................................... 3 General Specifications ................................................................. 3 Digital Specifications ................................................................... 3 Analog Specifications................................................................... 4 Timing Specifications .................................................................. 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Terminology ...................................................................................... 8 Equivalent Input/Output Circuits .................................................. 9 Typical Performance Characteristics ........................................... 10 System Overview ............................................................................ 11 H-Counter Behavior .................................................................. 11 Serial Interface Timing .................................................................. 12 Complete Register Listing ............................................................. 13 Precision Timing High Speed Timing Generation...................... 18 Timing Resolution...................................................................... 18 High Speed Clock Programmability ........................................ 18 H-Driver and RG Outputs ........................................................ 19 Digital Data Outputs.................................................................. 19 Horizontal Clamping and Blanking ............................................. 21 Individual CLPOB and PBLK Sequences................................ 21 Individual HBLK Sequences..................................................... 21 Generating Special HBLK Patterns .............................................. 23 Horizontal Sequence Control ................................................... 23 External HBLK Signal................................................................ 23 H-Counter Synchronization ..................................................... 24 Power-Up Procedure...................................................................... 25 Recommended Power-Up Sequence ....................................... 25 Analog Front End Description and Operation .......................... 26 DC Restore .................................................................................. 26 Correlated Double Sampler ...................................................... 26 PxGA............................................................................................ 26 Variable Gain Amplifier ............................................................ 29 ADC ............................................................................................. 29 Optical Black Clamp .................................................................. 29 Digital Data Outputs.................................................................. 29 Applications Information .............................................................. 30 Circuit Configuration ................................................................ 30 Grounding and Decoupling Recommendations.................... 30 Driving the CLI Input................................................................ 31 Horizontal Timing Sequence Example.................................... 31 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34 REVISION HISTORY 11/04—Data Sheet Changed from Rev. A to Rev. B Changes to Ordering Guide .......................................................... 35 9/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Changes to Analog Specifications .................................................. 4 Changes to Terminology Section.................................................... 9 Added H-Counter Behavior Section............................................ 12 Changes to Table 7.......................................................................... 14 Changes to Table 12 ....................................................................... 17 Changes to Table 15 ....................................................................... 17 Changes to H-Counter Sync Section ........................................... 24 Changes to Recommended Power-Up Sequence Section ......... 25 Changes to Ordering Guide .......................................................... 35 5/03—Revision 0: Initial Version Rev. B | Page 2 of 36 AD9949 SPECIFICATIONS GENERAL SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD, TCVDD (AFE, Timing Core) HVDD (H1 to H4 Drivers) RGVDD (RG Driver) DRVDD (D0 to D11 Drivers) DVDD (All Other Digital) POWER DISSIPATION 36 MHz, HVDD = RGVDD = 3 V, 100 pF H1 to H4 Loading1 Total Shutdown Mode Min −20 −65 36 2.7 2.7 2.7 2.7 2.7 3.0 3.0 3.0 3.0 3.0 320 1 Typ Max +85 +150 Unit °C °C MHz V V V V V mW mW 3.6 3.6 3.6 3.6 3.6 1 The total power dissipated by the HVDD supply may be approximated using the equation Total HVDD Power = (CLOAD x HVDD x Pixel Frequency) x HVDD x (Number of H – Outputs Used) Reducing the H-loading, using only two of the outputs, and/or using a lower HVDD supply, reduces the power dissipation. DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = DRVDD = HVDD = RGVDD = 2.7 V, CL = 20 pF, unless otherwise noted. Table 2. Parameter LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS High Level Output Voltage, IOH = 2 mA Low Level Output Voltage, IOL = 2 mA CLI INPUT High Level Input Voltage (TCVDD/2 + 0.5 V) Low Level Input Voltage RG AND H-DRIVER OUTPUTS High Level Output Voltage (RGVDD – 0.5 V and HVDD – 0.5 V) Low Level Output Voltage Maximum Output Current (Programmable) Maximum Load Capacitance Symbol VIH VIL IIH IIL CIN VOH VOL Min 2.1 0.6 10 10 10 2.2 0.5 Typ Max Unit V V µA µA pF V V VIH–CLI VIL–CLI 1.85 0.85 V V VOH VOL 2.2 0.5 30 100 V V mA pF Rev. B | Page 3 of 36 AD9949 ANALOG SPECIFICATIONS TMIN to TMAX, AVDD = DVDD = 3.0 V, fCLI = 36 MHz, typical timing specifications, unless other wise noted. Table 3. Parameter CDS Gain Allowable CCD Reset Transient1 Maximum Input Range before Saturation1 Maximum CCD Black Pixel Amplitude1 PIXEL GAIN AMPLIFIER (P×GA) Gain Control Resolution Gain Monotonicity Minimum Gain Maximum Gain VARIABLE GAIN AMPLIFIER (VGA) Maximum Input Range Maximum Output Range Gain Control Resolution Gain Monotonicity Gain Range Minimum Gain (VGA Code 0) Maximum Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level (0) Maximum Clamp Level (255) A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Integral Nonlinearity (INL) Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE VGA Gain Accuracy Minimum Gain (Code 0) Maximum Gain (Code 1023) Peak Nonlinearity, 500 mV Input Signal Total Output Noise Power Supply Rejection (PSR) Min Typ 0 500 1.0 ±50 256 0 18 1.0 2.0 1024 Guaranteed 6 42 256 0 255 12 −1.0 Max Unit dB mV V p-p mV Steps dB dB V p-p V p-p Steps Notes dB dB Steps Measured at ADC output LSB LSB Bits LSB LSB V V V Specifications include entire signal chain ±0.5 Guaranteed 2.0 2.0 1.0 +1.0 8 5.0 40.5 5.5 41.5 0.15 0.8 50 6.0 42.5 0.6 dB dB % LSB rms dB 12 dB gain applied AC grounded input, 6 dB gain applied Measured with step change on supply 1 Input signal characteristics defined as follows: 50mV MAX OPTICAL BLACK PIXEL 1V MAX INPUT SIGNAL RANGE 03751-002 500mV TYP RESET TRANSIENT Rev. B | Page 4 of 36 AD9949 TIMING SPECIFICATIONS CL = 20 pF, fCLI = 36 MHz, unless otherwise noted. Table 4. Parameter MASTER CLOCK (CLI) (See Figure 16) CLI Clock Period CLI High/Low Pulse Width Delay from CLI to Internal Pixel Period Position CLPOB PULSE WIDTH (PROGRAMMABLE)1 SAMPLE CLOCKS (See Figure 18) SHP Rising Edge to SHD Rising Edge DATA OUTPUTS (See Figure 19 and Figure 20) Output Delay From Programmed Edge Pipeline Delay SERIAL INTERFACE (SERIAL TIMING SHOWN IN Figure 14 and Figure 15) Maximum SCK Frequency SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold SCK Falling Edge to SDATA Valid Read Symbol tCLI tADC tCLIDLY tCOB tS1 tOD Min 27.8 11.2 2 12.5 Typ Max Unit ns ns ns Pixels ns ns Cycles MHz ns ns ns ns ns 13.9 6 20 13.9 6 11 16.6 fSCLK tLS tLH tDS tDH tDV 10 10 10 10 10 10 1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference. Rev. B | Page 5 of 36 AD9949 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD and TCVDD HVDD and RGVDD DVDD and DRVDD Any VSS Digital Outputs CLPOB/PBLK and HBLK SCK, SL, and SDATA RG H1 to H4 REFT, REFB, and CCDIN Junction Temperature Lead Temperature (10 s) With Respect to AVSS HVSS, RGVSS DVSS, DRVSS Any VSS DRVSS DVSS DVSS RGVSS HVSS AVSS Rating −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to DRVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to RGVDD + 0.3 V −0.3 V to HVDD + 0.3 V −0.3 V to AVDD + 0.3 V 150°C 300°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only ; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 40-Lead LFCSP Package: θJA = 27°C/W1. 1 θJA is measured using a 4-layer PCB with the exposed paddle soldered to the board. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. B | Page 6 of 36 AD9949 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 40 D0 (LSB) 39 CLP/PBLK 38 HBLK 37 DVDD 36 DVSS 35 HD 34 VD 33 SCK 32 SDI 31 SL D1 1 D2 2 D3 3 D4 4 DRVSS 5 DRVDD 6 D5 7 D6 8 D7 9 D8 10 PIN 1 INDICATOR AD9949 TOP VIEW 30 REFB 29 REFT 28 AVSS 27 CCDIN 26 AVDD 25 CLI 24 TCVDD 23 TCVSS 22 RGVDD 21 RG D9 11 D10 12 (MSB) D11 13 H1 14 H2 15 HVSS 16 HVDD 17 H3 18 H4 19 RGVSS 20 Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 to 4 5 6 7 to 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Mnemonic D1 to D4 DRVSS DRVDD D5 to D11 H1 H2 HVSS HVDD H3 H4 RGVSS RG RGVDD TCVSS TCVDD CLI AVDD CCDIN AVSS REFT REFB SL SDI SCK VD HD DVSS DVDD HBLK CLP/PBLK D0 Type1 DO P P DO DO DO P P DO DO P DO P P P DI P AI P AO AO DI DI DI DI DI P P DI DO DO Description Data Outputs Digital Driver Ground Digital Driver Supply Data Outputs (D11 is MSB) CCD Horizontal Clock 1 CCD Horizontal Clock 2 H1 to H4 Driver Ground H1 to H4 Driver Supply CCD Horizontal Clock 3 CCD Horizontal Clock 4 RG Driver Ground CCD Reset Gate Clock RG Driver Supply Analog Ground for Timing Core Analog Supply for Timing Core Master Clock Input Analog Supply for AFE Analog Input for CCD Signal (Connect through Series 0.1 µF Capacitor) Analog Ground for AFE Reference Top Decoupling (Decouple with 1.0 µF to AVSS) Reference Bottom Decoupling (Decouple with 1.0 µF to AVSS) 3-Wire Serial Load 3-Wire Serial Data Input 3-Wire Serial Clock Vertical Sync Pulse Horizontal Sync Pulse Digital Ground Digital Supply Optional HBLK Input CLPOB or PBLK Output Data Output LSB 1 Type: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power. Rev. B | Page 7 of 36 03751-003 AD9949 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating conditions. Integral Nonlinearity (INL) INL is the deviation of each individual code measured from a true straight line from zero to full scale. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1 LSB and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9949 from a straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1 LSB and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the straight line reference. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is appropriately gained up to fill the ADC’s full-scale range. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage, using the relationship 1 LSB = (ADC full scale/2n codes) where n is the bit resolution of the ADC. For the AD9949, 1 LSB is approximately 0.488 mV. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in the data outputs for a given step change in the supply voltage. Rev. B | Page 8 of 36 AD9949 EQUIVALENT INPUT/OUTPUT CIRCUITS AVDD DVDD R 330Ω 03751-004 AVSS AVSS DVSS Figure 3. CCDIN (Pin 27) AVDD Figure 6. Digital Inputs (Pins 31 to 35, 38) HVDD OR RGVDD CLI 330Ω 25kΩ + 1.4V 03751-005 DATA AVSS ENABLE 03751-007 DOUT Figure 4. CLI (Pin 25) 03751-008 DVSS DRVDD HVSS OR RGVSS DATA Figure 7. H1 to H4 and RG (Pins 14 to 15, 18 to 19, 21) THREE-STATE DOUT DVSS DRVSS Figure 5. Data Outputs D0 to D11 (Pins 1 to 4, 7 to 13, 40) Rev. B | Page 9 of 36 03751-006 AD9949 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 400 POWER DISSIPATION (mW) 0.5 350 DNL (LSB) 300 VDD = 3.3V VDD = 3.0V 250 VDD = 2.7V 200 0 –0.5 03751-009 0 500 1000 1500 2000 2500 3000 ADC OUTPUT CODE 3500 4000 24 30 SAMPLE RATE (MHz) 36 Figure 8. Typical DNL 48 Figure 10. Power Curves 40 OUTPUT NOISE (LSB) 32 24 16 8 0 200 400 600 VGA GAIN CODE (LSB) 800 1000 Figure 9. Output Noise vs. VGA Gain 03751-010 0 Rev. B | Page 10 of 36 03751-011 –1.0 150 18 AD9949 SYSTEM OVERVIEW V-DRIVER V1 TO Vx, VSG1 TO VSGx, SUBCK H1 TO H4, RG DOUT CCDIN DIGITAL IMAGE PROCESSING ASIC H-COUNTER BEHAVIOR When the maximum horizontal count of 4096 pixels is exceeded, the H-counter in the AD9949 rolls over to zero and continues counting. It is, therefore, recommended that the maximum counter value not be exceeded. However, the newer AD9949A version behaves differently. In the AD9949A, the internal H-counter holds at its maximum count of 4095 instead of rolling over. This feature allows the AD9949A to be used in applications containing a line length greater than 4096 pixels. Although no programmable values for the horizontal blanking or clamping are available beyond pixel 4095, the H, RG, and AFE clocking continues to operate, sampling the remaining pixels on the line. MAXIMUM FIELD DIMENSIONS CCD AD9949 INTEGRATED AFE + TD HD, VD CLI SERIAL INTERFACE 03751-012 Figure 11. Typical Application The H-drivers for H1 to H4 and RG are included in the AD9949, allowing these clocks to be directly connected to the CCD. The H-drive voltage of 3 V is supported in the AD9949. Figure 12 shows the horizontal and vertical counter dimensions for the AD9949. All internal horizontal clocking is programmed using these dimensions to specify line and pixel locations. Figure 12. Vertical and Horizontal Counters MAX VD LENGTH IS 4095 LINES VD MAX HD LENGTH IS 4095 PIXELS HD Figure 13. Maximum VD/HD Dimensions Rev. B | Page 11 of 36 03751-014 CLI 03751-013 Figure 11 shows the typical system application diagram for the AD9949. The CCD output is processed by the AD9949’s AFE circuitr y, which consists of a CDS, a PxGA, a VGA, a black level clamp, and an ADC. The digitized pixel information is sent to the digital image processor chip where all postprocessing and compression occurs. To operate the CCD, CCD timing parameters are programmed into the AD9949 from the image processor through the 3-wire serial interface. From the system master clock, CLI, provided by the image processor, the AD9949 generates the high speed CCD clocks and all internal AFE clocks. All AD9949 clocks are synchronized with VD and HD. The AD9949’s horizontal pulses (CLPOB, PBLK, and HBLK) are programmed and generated internally. 12-BIT HORIZONTAL = 4096 PIXELS MAX 12-BIT VERTICAL = 4096 LINES MAX AD9949 SERIAL INTERFACE TIMING The AD9949’s internal registers are accessed through a 3-wire serial interface. Each register consists of an 8-bit address and a 24-bit data-word. Both the 8-bit address and 24-bit data-word are written starting with the LSB. To write to each register, a 32-bit operation is required, as shown in Figure 14. Although many registers are less than 24 bits wide, all 24 bits must be written for each register. If the register is only 16 bits wide, then the upper eight bits may be filled with zeros during the serial write operation. If fewer than 24 bits are written, the register will not be updated with new data. Figure 15 shows a more efficient way to write to the registers by using the AD9949’s address auto-increment capability. Using this method, the lowest desired address is written first, followed by multiple 24-bit data-words. Each new 24-bit data-word is written automatically to the next highest register address. By eliminating the need to write each 8-bit address, faster register loading is achieved. Address auto-increment may be used starting with any register location and may be used to write to as few as two registers or as many as the entire register space. 8-BIT ADDRESS SDATA A0 A1 A2 A3 A4 A5 A6 A7 D0 D1 D2 D3 24-BIT DATA ... ... D21 D22 D23 tDS SCK 1 2 3 4 5 6 tDH 7 8 9 10 11 12 30 31 32 tLS SL tLH ... ... SL UPDATED VD/HD UPDATED VD ... HD NOTES 1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES. 2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA. 3. IF THE REGISTER LENGTH IS