400 MSPS 14-Bit, 1.8 V CMOS
Direct Digital Synthesizer
AD9952
Data Sheet
FEATURES
APPLICATIONS
400 MSPS internal clock speed
Integrated 14-bit DAC
32-bit tuning word
Phase noise ≤ −120 dBc/Hz at 1 kHz offset (DAC output)
Excellent dynamic performance
>80 dB SFDR at 160 MHz (±100 kHz offset) AOUT
Serial input/output (I/O) control
1.8 V power supply
Software and hardware controlled power-down
48-lead TQFP_EP package
PLL REFCLK multiplier (4× to 20×)
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Multichip synchronization
High speed comparator (200 MHz toggle rate)
Agile LO frequency synthesis
Programmable clock generators
Test and measurement equipment
Acousto-optic device drivers
GENERAL DESCRIPTION
The AD9952 is a direct digital synthesizer (DDS) featuring a
14-bit DAC (digital-to-analog converter) and operating up to
400 MSPS. The AD9952 uses advanced DDS technology,
coupled with an internal high speed, high performance DAC to
form a digitally programmable, complete high frequency
synthesizer capable of generating a frequency-agile analog
output sinusoidal waveform at up to 200 MHz. The AD9952 is
designed to provide fast frequency hopping and fine tuning
resolution (32-bit frequency tuning word). The frequency
tuning and control words are loaded into the AD9952 via a
serial I/O port.
The AD9952 is specified to operate over the extended industrial
temperature range of −40°C to +105°C.
FUNCTIONAL BLOCK DIAGRAM
DDS CORE
AD9952
PHASE
ACCUMULATOR
19
14
COS(X)
DAC
14
SYNC_IN
OSK
TIMING AND CONTROL LOGIC
I/O UPDATE
M
U
X
PWRDWNCTL
0
SYNC
CONTROL REGISTERS
÷4
COMPARATOR
OSCILLATOR/BUFFER
4× TO 20×
CLOCK
MULTIPLIER
REFCLK
REFCLK
M
U
X
COMP_IN
COMP_IN
SYSTEM
CLOCK
COMP_OUT
ENABLE
CRYSTAL OUT
IOUT
IOUT
SYSTEM
CLOCK
AMPLITUDE
SCALE FACTOR
Z–1
CLEAR PHASE
ACCUMULATOR
DDS CLOCK
14
32
SYNC_CLK
DAC_R SET
PHASE
OFFSET
32
I/O PORT
RESET
03358-001
FREQUENCY
TUNING WORD
Z–1
Figure 1.
Rev. C
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Tel: 781.329.4700 ©2003–2017 Analog Devices, Inc. All rights reserved.
Technical Support
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AD9952
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Control Register Bit Descriptions ............................................ 16
Applications ....................................................................................... 1
Other Register Descriptions ..................................................... 18
General Description ......................................................................... 1
Modes of Operation ................................................................... 18
Functional Block Diagram .............................................................. 1
Programming Features .............................................................. 18
Revision History ............................................................................... 2
Synchronizing Multiple AD9952s ............................................ 20
Electrical Specifications ................................................................... 3
Serial Port Operation ................................................................. 20
Absolute Maximum Ratings............................................................ 6
Power-Down Functions ............................................................. 23
ESD Caution .................................................................................. 6
Layout Considerations ................................................................... 25
Pin Configuration and Function Descriptions ............................. 7
Suggested Application Circuits ..................................................... 26
Typical Performance Characteristics ............................................. 9
Outline Dimensions ....................................................................... 27
Equivalent Input/Output Circuits ................................................ 12
Ordering Guide .......................................................................... 27
Theory of Operation ...................................................................... 13
Component Blocks ..................................................................... 13
REVISION HISTORY
2/2017—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Ordering Guide .......................................................... 27
Changes to Figure 32...................................................................... 26
Added Exposed Pad Notation to Outline Dimensions ............. 27
Changes to Ordering Guide .......................................................... 27
5/2009—Rev. A to Rev. B
Changes to Comparator Input Characteristics,
Hysteresis Parameter, Table 1 .......................................................... 4
Changes to Pin Configuration and Function Descriptions
Section and Table 3 ........................................................................... 7
Changes to Table 5 .......................................................................... 15
Changes to Serial Interface Port Pin Description Section ........ 22
5/2006—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Electrical Specifications Section .................................3
Changes to Figure 3 ...........................................................................9
Changes to Serial Port Operation Section .................................. 20
Inserted Figure 24, Figure 25, and Figure 26 .............................. 21
12/2003—Revision 0: Initial Version
Rev. C | Page 2 of 28
Data Sheet
AD9952
ELECTRICAL SPECIFICATIONS
AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, DAC_RSET = 3.92 kΩ, external reference clock frequency = 400 MHz with
REFCLK multiplier disabled, unless otherwise noted. DAC output must be referenced to AVDD, not AGND.
Table 1.
Parameter
REF CLOCK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier Disabled
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Enabled @ 20×
Input Capacitance
Input Impedance
Duty Cycle
Duty Cycle with REFCLK Multiplier Enabled
REFCLK Input Power 1
DAC OUTPUT CHARACTERISTICS
Resolution
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
Residual Phase Noise @ 1 kHz Offset, 40 MHz AOUT
REFCLK Multiplier Enabled @ 20×
REFCLK Multiplier Enabled @ 4×
REFCLK Multiplier Disabled
Voltage Compliance Range
Wideband Spurious-Free Dynamic Range (SFDR)
1 MHz to 10 MHz Analog Out
10 MHz to 40 MHz Analog Out
40 MHz to 80 MHz Analog Out
80 MHz to 120 MHz Analog Out
120 MHz to 160 MHz Analog Out
Narrow-Band SFDR
40 MHz Analog Out (±1 MHz)
40 MHz Analog Out (±250 kHz)
40 MHz Analog Out (±50 kHz)
40 MHz Analog Out (±10 kHz)
80 MHz Analog Out (±1 MHz)
80 MHz Analog Out (±250 kHz)
80 MHz Analog Out (±50 kHz)
80 MHz Analog Out (±10 kHz)
120 MHz Analog Out (±1 MHz)
120 MHz Analog Out (±250 kHz)
120 MHz Analog Out (±50 kHz)
120 MHz Analog Out (±10 kHz)
160 MHz Analog Out (±1 MHz)
160 MHz Analog Out (±250 kHz)
160 MHz Analog Out (±50 kHz)
160 MHz Analog Out (±10 kHz)
Temp
Min
Full
Full
Full
25°C
25°C
25°C
25°C
Full
1
20
4
25°C
25°C
25°C
25°C
25°C
25°C
5
–10
25°C
25°C
25°C
25°C
Typ
Max
Unit
400
100
20
MHz
MHz
MHz
pF
kΩ
%
%
dBm
3
1.5
50
35
–15
0
14
10
65
+3
15
+10
0.6
1
2
5
–105
–115
–132
AVDD + 0.5
AVDD −
0.5
Bits
mA
%FS
µA
LSB
LSB
pF
dBc/Hz
dBc/Hz
dBc/Hz
V
25°C
25°C
25°C
25°C
25°C
73
67
62
58
52
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
87
89
91
93
85
87
89
91
83
85
87
89
81
83
85
87
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Rev. C | Page 3 of 28
AD9952
Data Sheet
Parameter
COMPARATOR INPUT CHARACTERISTICS
Input Capacitance
Input Resistance
Input Current
Hysteresis
COMPARATOR OUTPUT CHARACTERISTICS
Logic 1 Voltage, High Z Load
Logic 0 Voltage, High Z Load
Propagation Delay
Output Duty Cycle Error
Rise/Fall Time, 5 pF Load
Toggle Rate, High Z Load
Output Jitter 2
COMPARATOR NARROW-BAND SFDR
10 MHz (±1 MHz)
10 MHz (±250 kHz)
10 MHz (±50 kHz)
10 MHz (±10 kHz)
70 MHz (±1 MHz)
70 MHz (±250 kHz)
70 MHz (±50 kHz)
70 MHz (±10 kHz)
110 MHz (±1 MHz)
110 MHz (±250 kHz)
110 MHz (±50 kHz)
110 MHz (±10 kHz)
140 MHz (±1 MHz)
140 MHz (±250 kHz)
140 MHz (±50 kHz)
140 MHz (±10 kHz)
160 MHz (±1 MHz)
160 MHz (±250 kHz)
160 MHz (±50 kHz)
160 MHz (±10 kHz)
CLOCK GENERATOR OUTPUT JITTER 3
5 MHz AOUT
10 MHz AOUT
40 MHz AOUT
80 MHz AOUT
120 MHz AOUT
140 MHz AOUT
160 MHz AOUT
TIMING CHARACTERISTICS
Serial Control Bus
Maximum Frequency 4
Minimum Clock Pulse Width Low
Minimum Clock Pulse Width High
Maximum Clock Rise/Fall Time
Minimum Data Setup Time DVDD_I/O = 3.3 V 5 (TCSU, TDSU)
Minimum Data Setup Time DVDD_I/O = 1.8 V5 (TCSU, TDSU)
Minimum Data Hold Time (TDH)
Maximum Data Valid Time (TDV)
Temp
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
25°C
25°C
25°C
Min
Typ
Max
Unit
45
pF
kΩ
µA
mV
3
500
±12
30
1.6
0.4
3
±5
1
200
1
V
V
ns
%
ns
MHz
ps rms
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
80
85
90
95
80
85
90
95
80
85
90
95
80
85
90
95
80
85
90
95
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
25°C
25°C
25°C
100
60
50
50
50
50
50
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
ps rms
25
Mbps
ns
ns
ns
ns
ns
ns
ns
Full
Full
Full
Full
Full
Full
Full
Full
Rev. C | Page 4 of 28
7
7
2
3
5
0
25
Data Sheet
Parameter
Wake-Up Time 6
Minimum Reset Pulse Width High
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE to SYNC_CLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, SYNC_CLK Hold Time
Latency
I/O UPDATE to Frequency Change Propagation Delay
I/O UPDATE to Phase Offset Change Propagation Delay
I/O UPDATE to Amplitude Change Propagation Delay
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
Logic 0 Voltage
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
Logic 0 Voltage
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single-Tone Mode
Rapid Power-Down Mode
Full-Sleep Mode
SYNCHRONIZATION FUNCTION 8
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution 9
AD9952
Temp
Full
Full
Full
Full
Full
Min
5
4
6
0
Unit
ms
SYSCLK cycles 7
ns
ns
ns
25°C
25°C
25°C
24
24
16
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
25°C
25°C
25°C
25°C
25°C
25°C
25°C
1.25
25°C
25°C
1.35
25°C
25°C
2.8
Max
0.6
2.2
3
0.8
12
12
2
25°C
25°C
25°C
25°C
25°C
25°C
Typ
1
162
150
20
62.5
100
±1
V
V
V
V
µA
µA
pF
0.4
V
V
0.4
V
V
171
160
27
mW
mW
mW
MHz
MHz
SYSCLK cycles
To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude reduces the phase noise
performance of the device.
2
Represents the cycle-to-cycle residual jitter from the comparator alone.
3
Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.
4
The maximum frequency of the serial I/O port refers to the maximum speed of the port during a write operation. During a register readback, the maximum port speed
is restricted to 2 Mbps.
5
Setup time refers to the TCSU (setup time of the falling edge of CS to the SCLK rising edge) and TDSU (setup time of the data change on SDIO to the SCLK rising edge).
6
Wake-up time refers to the recovery from analog power-down modes (see the Power-Down Functions section). The longest time required is for the reference clock
multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DACBP and that the recommended PLL loop filter values are used.
7
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.
8
SYNC_CLK = ¼ SYSCLK rate. For SYNC_CLK rates ≥ 50 MHz, the high speed sync enable bit, CFR2 [11], should be set.
9
This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
1
Rev. C | Page 5 of 28
AD9952
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Maximum Junction Temperature
DVDD_I/O
AVDD, DVDD
Digital Input Voltage (DVDD_I/O = 3.3 V)
Digital Input Voltage (DVDD_I/O = 1.8 V)
Digital Output Current
Storage Temperature Range
Operating Temperature Range
Lead Temperature (10 sec Soldering)
θJA
θJC
Rating
150°C
4V
2V
–0.7 V to +5.25 V
–0.7 V to +2.2 V
5 mA
–65°C to +150°C
–40°C to +105°C
300°C
38°C/W
15°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. C | Page 6 of 28
Data Sheet
AD9952
SYNC_IN
DVDD_I/O
DGND
SDIO
45
44
43
42
41
SDO
SYNC_CLK
46
IOSYNC
OSK
47
SCLK
DGND
48
CS
DGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
40
39
38
37
I/O UPDATE
1
DVDD
2
35 PWRDWNCTL
DGND
3
34 DVDD
36 RESET
AVDD
4
33 DGND
AGND
5
32 AGND
AVDD
6
AD9952
31 COMP_IN
AGND
7
TOP VIEW
(Not to Scale)
30 COMP_IN
8
9
29 AVDD
28 COMP_OUT
16
17
18
19
20
21
22
23
24
IOUT
AGND
DACBP
DAC_RSET
15
IOUT
14
AVDD
13
AVDD
25 AVDD
AVDD
LOOP_FILTER 12
AGND
26 AGND
AGND
CLKMODESELECT 11
AVDD
27 AVDD
AGND
CRYSTAL OUT 10
03358-002
REFCLK
REFCLK
Figure 2. Pin Configuration
Note that the exposed paddle on the bottom of the package is a ground connection for the DAC and must be attached to AGND in
any board layout. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or 3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can
only be powered to 1.8 V.
Table 3. 48-Lead TQFP/EP
Pin No.
1
Mnemonic
I/O UPDATE
I/O
I
2, 34
3, 33, 42,
47, 48
4, 6, 13,
16, 18, 19,
25, 27, 29
5, 7, 14,
15, 17, 22,
26, 32
8
DVDD
DGND
I
I
Description
The rising edge transfers the contents of the internal buffer memory to the I/O registers. This pin
must be set up and held around the SYNC_CLK output signal.
Digital Power Supply Pins (1.8 V).
Digital Power Ground Pins.
AVDD
I
Analog Power Supply Pins (1.8 V).
AGND
I
Analog Power Ground Pins.
REFCLK
I
Complementary Reference Clock/Oscillator Input. When the REFCLK port is operated in singleended mode, REFCLK should be decoupled to AVDD with a 0.1 µF capacitor.
9
REFCLK
I
Reference Clock/Oscillator Input. See the Clock Input section for details on the oscillator/REFCLK
operation.
10
11
CRYSTAL OUT
CLKMODESELECT
O
I
12
LOOP_FILTER
I
20
21
IOUT
IOUT
O
O
Output of the Oscillator Section.
Control Pin for the Oscillator Section. When high, the oscillator section is enabled. When low, the
oscillator section is bypassed.
This pin provides the connection for the external zero compensation network of the REFCLK
multiplier’s PLL loop filter. The network consists of a 1 kΩ resistor in series with a 0.1 µF capacitor
tied to AVDD.
Complementary DAC Output. Should be biased through a resistor to AVDD, not AGND.
DAC Output. Should be biased through a resistor to AVDD, not AGND.
Rev. C | Page 7 of 28
AD9952
Data Sheet
Pin No.
23
24
Mnemonic
DACBP
DAC_RSET
I/O
I
I
28
30
31
35
36
COMP_OUT
COMP_IN
COMP_IN
PWRDWNCTL
RESET
O
I
I
I
I
37
IOSYNC
I
38
SDO
O
39
40
41
CS
SCLK
SDIO
I
I
I/O
43
44
DVDD_I/O
SYNC_IN
I
I
45
46
SYNC_CLK
OSK
O
I
Paddle
Exposed Paddle
I
Description
DAC Biasline Decoupling Pin. A 0.1 μF capacitor to AGND is recommended.
A resistor (3.92 kΩ nominal) connected from AGND to DAC_RSET establishes the reference current
for the DAC.
Comparator Output.
Comparator Input.
Comparator Complementary Input.
Input Pin Used as an External Power-Down Control. See Table 7 for additional information.
Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9952 to the initial state,
as described in the I/O port register map (see Table 5).
Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O
operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is
returned low. If unused, ground this pin; do not allow this pin to float.
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When
operated as a 2-wire serial port, this pin is unused and can be left unconnected.
This pin functions as an active low chip select that allows multiple devices to share the I/O bus.
This pin functions as the serial data clock for I/O operations.
When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only.
When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.
Digital Power Supply. For I/O cells only, 3.3 V.
Input signal used to synchronize multiple AD9952s. This input is connected to the SYNC_CLK
output of a master AD9952.
Clock output pin that serves as a synchronizer for external hardware.
Input pin used to control the direction of the shaped on-off keying function when programmed
for operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin
should be tied to DGND.
The exposed paddle on the bottom of the package is a ground connection for the DAC and must
be attached to AGND in any board layout. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or
3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can only be powered to 1.8 V.
Rev. C | Page 8 of 28
Data Sheet
AD9952
TYPICAL PERFORMANCE CHARACTERISTICS
MKR1 98.0MHz
–70.68dB
ATTEN 10dB
REF 0dBm
0
PEAK
LOG
–10
10dB/
–20
–20
–30
–30
MARKER
100.000000MHz
–70.68dB
–40
–50
–50
–60
W1 S2
S3 FC –70
AA
–80
1
–90
–100
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
03358-003
–90
–100
CENTER 100MHz
#RES BW 3kHz
REF 0dBm
0
PEAK
LOG
10dB/ –10
–20
MKR1 40.0MHz
–56.2dB
ATTEN 10dB
1R
–30
MARKER
80.000000MHz
–69.12dB
–40
–50
MARKER
40.000000MHz
–56.2dB
–40
–50
–60
W1 S2
S3 FC –70
AA
–80
1
–60
W1 S2
S3 FC –70
AA
–80
1
–90
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
–100
CENTER 100MHz
#RES BW 3kHz
Figure 4. FOUT = 10 MHz, FCLK = 400 MSPS, WBSFDR
REF 0dBm
0
PEAK
LOG
–10
10dB/
ATTEN 10dB
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
03358-007
CENTER 100MHz
#RES BW 3kHz
03358-004
–90
–100
Figure 7. FOUT = 120 MHz, FCLK = 400 MSPS, WBSFDR
MKR1 0Hz
–68.44dB
REF 0dBm
0
PEAK
LOG
10dB/ –10
1R
–20
ATTEN 10dB
MKR1 0Hz
–53.17dB
1R
–20
–30
–50
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
–20
–30
–40
VBW 3kHz
Figure 6. FOUT = 80 MHz, FCLK = 400 MSPS, WBSFDR
MKR1 80.0MHz
–69.12dB
ATTEN 10dB
1
CENTER 100MHz
#RES BW 3kHz
Figure 3. FOUT = 1 MHz, FCLK = 400 MSPS, WBSFDR
REF 0dBm
0
PEAK
1R
LOG
10dB/ –10
1R
MARKER
80.000000MHz
–61.55dB
–40
–60
W1 S2
S3 FC –70
AA
–80
MKR1 80.0MHz
–61.55dB
ATTEN 10dB
03358-006
REF 0dBm
0
PEAK
1R
LOG
–10
10dB/
–30
MARKER
40.000000MHz
–68.44dB
–40
–50
MARKER
80.000000MHz
–53.17dB
1
–60
–60
W1 S2
S3 FC –70
AA
–80
W1 S2
S3 FC –70
AA
–80
1
–90
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
Figure 5. FOUT = 40 MHz, FCLK = 400 MSPS, WBSFDR
–100
CENTER 100MHz
#RES BW 3kHz
VBW 3kHz
SPAN 200MHz
SWEEP 55.56 s (401 PTS)
Figure 8. FOUT = 160 MHz, FCLK = 400 MSPS, WBSFDR
Rev. C | Page 9 of 28
03358-008
CENTER 100MHz
#RES BW 3kHz
03358-005
–90
–100
AD9952
Data Sheet
ATTEN 10dB
1
MKR1 1.105MHz
–5.679dBm
REF –4dBm
0
PEAK
LOG
–10
10dB/
–20
–20
–30
–30
MARKER
1.105000MHz
–5.679dBm
–40
–50
–40
–50
W1 S2
S3 FC –70
AA
–80
–60
W1 S2
S3 FC –70
AA
–80
–90
ST
–100
–90
ST
–100
CENTER 1.105MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
03358-009
–60
REF 0dBm
0
PEAK
LOG
10dB/ –10
REF –4dBm
0
PEAK
LOG
10dB/ –10
1R
–20
–20
–30
–30
MARKER
40.000000MHz
–56.2dB
–40
–50
–40
–50
ATTEN 10dB
1
MKR1 120.205MHz
–6.825dBm
MARKER
120.205000MHz
–6.825dBm
–90
ST
–100
CENTER 10MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
03358-010
1
CENTER 120.2MHz
#RES BW 30Hz
Figure 10. FOUT = 10 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
REF 0dBm
0
PEAK
LOG
10dB/ –10
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
Figure 13. FOUT = 120.2 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
MKR1 39.905MHz
–5.347dBm
ATTEN 10dB
VBW 30Hz
03358-013
–90
–100
REF –4dBm
0
PEAK
LOG
10dB/ –10
1
–20
ATTEN 10dB
1
MKR1 600kHz
–0.911dB
–20
–30
–30
MARKER
39.905000MHz
–5.347dBm
–40
–50
–60
W1 S2
S3 FC –70
AA
–80
–90
–90
ST
–100
–100
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
03358-011
–60
W1 S2
S3 FC –70
AA
–80
CENTER 39.9MHz
#RES BW 30Hz
CENTER
160.5000000MHz
Figure 11. FOUT = 39.9 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
CENTER 160.5MHz
#RES BW 30Hz
VBW 30Hz
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
Figure 14. FOUT = 160 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
Rev. C | Page 10 of 28
03358-014
–50
SPAN 2MHz
SWEEP 199.2 s (401 PTS)
–60
W1 S2
S3 FC –70
AA
–80
–60
W1 S2
S3 FC –70
AA
–80
–40
VBW 30Hz
Figure 12. FOUT = 80.3 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
MKR1 85kHz
–93.01dB
ATTEN 10dB
MKR1 80.301MHz
–6.318dBm
MARKER
80.301000MHz
–6.318dBm
CENTER 80.25MHz
#RES BW 30Hz
Figure 9. FOUT = 1.1 MHz, FCLK = 400 MSPS, NBSFDR, ±1 MHz
1
ATTEN 10dB
03358-012
REF –4dBm
0
PEAK
LOG
–10
10dB/
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160
–170
10
L(f) (dBc/Hz)
0
–10
100
1k
10k
f (Hz)
100k
1M
10M
–120
–130
–140
–150
–160
–170
10
Figure 15. Residual Phase Noise with FOUT = 159.5 MHz, FCLK = 400 MSPS
(Green), 4 MSPS × 100 MSPS (Red), and 20 MSPS × 20 MSPS (Blue)
100
10k
1k
100k
1M
f (Hz)
03358-017
AD9952
03358-015
Figure 17. Residual Phase Noise with FOUT = 9.5 MHz, FCLK = 400 MSPS
(Green), 4 MSPS ×100 MSPS (Red), and 20 MSPS × 20 MSPS (Blue)
t1 = 3.156ns
t2 = 3.04ns
∆t = –116.0PS
1/∆t = –8.621GHz
FALL (R1) = 396.4PS
RISE(R2) = 464.3PS
R1
R2
CH1 200mVΩ
M 200PS 20.0GS/S
A CH1
708mV
IT 4.0PS/PT 3.1ns
03358-016
1
REF2 200mV 500ns
Figure 16. Residual Peak-to-Peak Jitter of DDS
and Comparator Operating Together at 160 MHz
M 500PS 20.0GS/S IT 10.0PS/PT –100PS
A CH1
708mV
Figure 18. Comparator Rise and Fall Time at 160 MHz
Rev. C | Page 11 of 28
03358-018
L(f) (dBc/Hz)
Data Sheet
AD9952
Data Sheet
EQUIVALENT INPUT/OUTPUT CIRCUITS
COMPARATOR
INPUTS
DIGITAL
INPUTS
DVDD_I/O
INPUT
COMP_IN
03358-021
COMP_IN
Figure 21. Comparator Inputs
03358-019
AVOID OVERDRIVING
DIGITAL INPUTS.
FORWARD-BIASING
ESD DIODES MAY
COUPLE DIGITAL NOISE
ONTO POWER PINS.
COMPARATOR
OUTPUT
Figure 19. Digital Inputs
AVDD
DIGITAL
OUTPUTS
IOUT
03358-022
IOUT
MUST TERMINATE
OUTPUTS TO AVDD FOR
CURRENT FLOW. DO
NOT EXCEED THE
OUTPUT VOLTAGE
COMPLIANCE RATING.
03358-020
Figure 22. Comparator Outputs
Figure 20. DAC Outputs
Rev. C | Page 12 of 28
Data Sheet
AD9952
THEORY OF OPERATION
COMPONENT BLOCKS
Clock Input
DDS Core
The AD9952 supports various clock methodologies. Support for
differential or single-ended input clocks and enabling of an onchip oscillator and/or a PLL multiplier is all controlled via userprogrammable bits. The AD9952 can be configured in one of
six operating modes to generate the system clock. The modes
are configured using the CLKMODESELECT pin, Control
Function Register 1 (CFR1) [4], and CFR2 [7:3]. Connect the
CLKMODESELECT external pin to logic high to enable the onchip crystal oscillator circuit. With the on-chip oscillator
enabled, connect an external crystal to the REFCLK and
REFCLKB inputs to produce a low frequency reference clock in
the range of 20 MHz to 30 MHz. The signal generated by the
oscillator is buffered before it is delivered to the rest of the chip.
This buffered signal is available via the CRYSTAL OUT pin.
CFR1 [4] can be used to enable or disable the buffer, turning on
or turning off the system clock. The oscillator itself is not
powered down to avoid long start-up times associated with
turning on a crystal oscillator. Writing CFR2 [9] to logic high
enables the crystal oscillator output buffer. Logic low at CFR2
[9] disables the oscillator output buffer.
The output frequency (fO) of the DDS is a function of the
frequency of the system clock (SYSCLK), the value of the
frequency tuning word (FTW), and the capacity of the
accumulator (232, in this case). The exact relationship is given
below with fS defined as the frequency of SYSCLK.
f O = (FTW )( f S )/ 2 32 with 0 ≤ FTW ≤ 2 31
f O = f S × (1 – (FTW / 2 32 )) with 2 31 < FTW < 2 32 – 1
The value at the output of the phase accumulator is translated to
an amplitude value via the COS(x) functional block and routed
to the DAC.
To introduce a phase offset, the phase offset word, or POW, is
used. The actual phase offset, F for the output of the DDS core,
is determined by the following relationship:
Φ = 360
POW
214
In certain applications, it is desirable to force the output signal
to zero phase. Setting the FTW or POW to 0 does not
accomplish this; it only results in the DDS core holding its
current phase value or continuing to run at the current phase,
respectively. To set the phase offset to zero, a control bit is
required to force the phase accumulator output to zero. The bits
to clear the phase accumulator are found in Control Function
Register 1, Bit [13] and Bit [8].
At power-up, the clear phase accumulator bit is set to Logic 1,
but the buffer memory for this bit is cleared (Logic 0).
Therefore, upon power-up, the phase accumulator remains clear
until the first I/O UPDATE is issued.
Phase-Locked Loop (PLL)
Connecting CLKMODESELECT to logic low disables the onchip oscillator and the oscillator output buffer. With the
oscillator disabled, an external oscillator must provide the
REFCLK and/or REFCLKB signals. For differential operation,
these pins are driven with complementary signals. For singleended operation, a 0.1 µF capacitor should be connected
between the unused pin and the analog power supply. With the
capacitor in place, the clock input pin bias voltage is 1.35 V. In
addition, the PLL can be used to multiply the reference
frequency by an integer value in the range of 4 (decimal) to 20
(decimal). Table 4 summarizes the clock modes of operation.
Note that the PLL multiplier is controlled via CFR2 [7:3],
independent of CFR1 [4].
The PLL allows multiplication of the REFCLK frequency.
Control of the PLL is accomplished by programming the 5-bit
REFCLK multiplier portion of Control Function Register 2
(CFR2), Bits [7:3].
When programmed for values ranging from 0x04 to 0x14
(4 decimal to 20 decimal), the PLL multiplies the REFCLK
input frequency by the corresponding decimal value. However,
the maximum output frequency of the PLL is restricted to
400 MHz. Whenever the PLL value is changed, the user should
be aware that time must be allocated to allow the PLL to lock
(approximately 1 ms).
The PLL is bypassed by programming a value outside the range
of 4 (decimal) to 20 (decimal). When bypassed, the PLL is shut
down to conserve power.
Rev. C | Page 13 of 28
AD9952
Data Sheet
Table 4. Clock Input Modes of Operation
CFR1 [4]
Low
Low
Low
Low
High
CLKMODESELECT
High
High
Low
Low
X
CFR2 [7:3]
3 < M < 21
M < 4 or M > 20
3 < M < 21
M < 4 or M > 20
X
Oscillator Enabled
Yes
Yes
No
No
No
System Clock
FCLK = FOSC × M
FCLK = FOSC
FCLK = FOSC × M
FCLK = FOSC
FCLK = 0
Frequency Range (MHz)
80 < FCLK < 400
20 < FCLK < 30
80 < FCLK < 400
10 < FCLK < 400
N/A
DAC Output
Comparator
The AD9952 incorporates an integrated 14-bit current output
DAC. Unlike most DACs, this output is referenced to AVDD,
not AGND.
Many applications require a square wave signal rather than a
sine wave. For example, in most clocking applications a high
slew rate helps to reduce phase noise and jitter. To support these
applications, the AD9952 includes an on-chip comparator. The
comparator has a bandwidth greater than 200 MHz and a
common-mode input range of 1.3 V to 1.8 V. By setting the
comparator power-down bit, CFR1 [6], the comparator can be
turned off to save on power consumption.
Two complementary outputs provide a combined full-scale
output current (IOUT). Differential outputs reduce the amount of
common-mode noise that might be present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. The
full-scale current is controlled by an external resistor (RSET)
connected between the DAC_RSET pin and the DAC ground
(AGND_DAC). The full-scale current is proportional to the
resistor value as follows:
RSET = 39.19 / IOUT
The maximum full-scale output current of the combined DAC
outputs is 15 mA, but limiting the output to 10 mA provides the
best spurious-free dynamic range (SFDR) performance. The DAC
output compliance range is AVDD + 0.5 V to AVDD – 0.5 V.
Voltages developed beyond this range cause excessive DAC
distortion and could potentially damage the DAC output
circuitry. Proper attention should be paid to the load termination
to keep the output voltage within this compliance range.
Serial I/O Port
The AD9952 serial port is a flexible, synchronous serial
communications port that allows easy interface to many
industry-standard microcontrollers and microprocessors. The
serial I/O port is compatible with most synchronous transfer
formats, including both the Motorola 6905/11 SPI® and Intel®
8051 SSR protocols.
The interface allows read/write access to all registers that configure
the AD9952. MSB first or LSB first transfer formats are supported.
The AD9952 serial interface port can be configured as a single pin
I/O (SDIO) that allows a 2-wire interface or two unidirectional pins
for in/out (SDIO/SDO), which in turn enable a 3-wire interface.
Two optional pins, IOSYNC and CS, enable greater flexibility for
system design in the AD9952. Please see the Serial Port Operation
section for details on how to program the AD9952 through the
serial I/O port.
Register Map and Descriptions
The register map is listed in Table 5.
Rev. C | Page 14 of 28
Data Sheet
AD9952
Table 5. Register Map
Register
Name
(Serial
Address)
Control
Function
Register 1
(CFR1)
Register
Address
(0x00)
Bit
Range
[7:0]
(MSB)
Bit 7
Digital
PowerDown
Bit 6
Comparator
PowerDown
Bit 5
DAC
PowerDown
[15:8]
Not Used
Not Used
Auto
Clr
Phase
Accum.
[23:16]
Automatic
Sync
Enable
Software
Manual
Sync
[31:24]
Control
Function
Register 2
(CFR2)
(0x01)
Amplitude
Scale
Factor
(ASF)
Amplitude
Ramp
Rate
(ARR)
Frequency
Tuning
Word 0
(FTW0)
(0x02)
[23:16]
[7:0]
[15:8]
(0x03)
[7:0]
(0x04)
[7:0]
[15:8]
[23:16]
[31:24]
[7:0]
[15:8]
Phase
Offset
Word
(POW)
[7:0]
[15:8]
(0x05)
Bit 4
Clock
Input
PowerDown
Enable
SINE
Output
Bit 3
External
PowerDown
Mode
Not
Used
Bit 2
Not Used
Bit 1
SYNC_CLK
Out
Disable
Clear
Phase
Accum.
SDIO
Input
Only
Default
Value
0x00
LSB
First
0x00
Not Used
Not Used
Load ARR
@ I/O
UPDATE
VCO
Range
0x00
OSK
Enable
Auto
OSK
Keying
Charge Pump
Current [1:0]
REFCLK Multiplier
0x00 or 0x01, or 0x02 or 0x03: Bypass Multiplier
0x04 to 0x14: 4× to 20× Multiplication
Not Used
High
Hardware CRYSTAL
Speed
Manual
OUT Pin
Sync
Sync
Active
Enable Enable
Not Used
Amplitude Scale Factor Register [7:0]
Amplitude Scale Factor Register [13:8]
Auto Ramp Rate Speed
Control [1:0]
Amplitude Ramp Rate Register [7:0]
Not Used [1:0]
(LSB)
Bit 0
Not
Used
Frequency Tuning Word 0 [7:0]
Frequency Tuning Word 0 [15:8]
Frequency Tuning Word 0 [23:16]
Frequency Tuning Word 0 [31:24]
Phase Offset Word 0 [7:0]
Phase Offset Word 0 [13:8]
Rev. C | Page 15 of 28
Not
Used
0x00
0x00
0x00
0x18
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
AD9952
Data Sheet
The CFR1 bits control the functions, features, and modes of the
AD9952. The functionality of each bit is detailed below.
CFR1 [22] = 1. The software controlled manual synchronization
feature is executed. The SYNC_CLK rising edge is advanced by
one SYNC_CLK cycle and this bit is cleared. To advance the
rising edge multiple times, this bit needs to be set for each
advance (see the Synchronizing Multiple AD9952 section)..
CFR1 [31:27]: Not Used
CFR1 [21:14]: Not Used
CFR1 [26]: Amplitude Ramp Rate Load Control Bit
CFR1 [13]: Auto-Clear Phase Accumulator Bit
CFR1 [26] = 0 (default). The amplitude ramp rate timer is
loaded only upon timeout (timer = 1) and is not loaded due to
an I/O UPDATE input signal.
CFR1 [13] = 0 (default). The current state of the phase
accumulator remains unchanged when the frequency tuning
word is applied.
CFR1 [26] = 1. The amplitude ramp rate timer is loaded upon
timeout (timer = 1) or at the time of an I/O UPDATE input
signal.
CFR1 [13] = 1. This bit synchronously clears the phase
accumulator automatically (by loadings 0s) for one cycle upon
reception of an I/O UPDATE signal.
CFR1 [25]: Shaped On-Off Keying Enable Bit
CFR1 [12]: Sine/Cosine Select Bit
CFR1 [25] = 0 (default). Shaped on-off keying is bypassed.
CFR1 [12] = 0 (default). The angle-to-amplitude conversion
logic employs a COSINE function.
CONTROL REGISTER BIT DESCRIPTIONS
Control Function Register 1 (CFR1)
CFR1 [25] = 1. Shaped on-off keying is enabled. When enabled,
CFR1 [24] controls the mode of operation for this function.
CFR1 [24]: Auto Shaped On-Off Keying Enable Bit (only
valid when CFR1[25] is active high)
CFR1 [12] = 1. The angle-to-amplitude conversion logic
employs a SINE function.
CFR1 [11]: Not Used
CFR1 [24] = 0 (default). When CFR1[25] is active, a Logic 0 on
CFR1[24] enables the manual shaped on-off keying operation.
Each amplitude sample sent to the DAC is multiplied by the
amplitude scale factor. See the Shaped On-Off Keying section
for details.
CFR1 [10]: Clear Phase Accumulator
CFR1 [10] = 0 (default). The phase accumulator functions as
normal.
CFR1 [10] = 1. The phase accumulator memory elements are
cleared and held clear until this bit is cleared.
CFR1 [24] = 1. When CFR1[25] is active, a Logic 1 on CFR1
[24] enables the auto shaped on-off keying operation. Toggling
the OSK pin high causes the output scalar to ramp up from zero
scale to the amplitude scale factor at a rate determined by the
amplitude ramp rate. Toggling the OSK pin low causes the
output to ramp down from the amplitude scale factor to zero
scale at the amplitude ramp rate (see the Shaped On-Off Keying
section).
CFR1 [9] = 0 (default). The SDIO pin has bidirectional
operation (2-wire serial programming mode).
CFR1 [23]: Automatic Synchronization Enable Bit
CFR1 [8]: LSB First
CFR1 [23] = 0 (default). The automatic synchronization feature
of multiple AD9952s is inactive.
CFR1 [8] = 0 (default). MSB first format is active.
CFR1 [23] = 1. The automatic synchronization feature of
multiple AD9952s is active. The device synchronizes its internal
synchronization clock (SYNC_CLK) to align to the signal
present on the SYNC_IN input (see the Synchronizing Multiple
AD9952 section).
CFR1 [22]: Software Manual Synchronization of Multiple
AD9952s
CFR1 [9]: SDIO Input Only
CFR1 [9] = 1. The serial data I/O pin (SDIO) is configured as
an input only pin (3-wire serial programming mode).
CFR1 [8] = 1. The serial interface accepts serial data in LSB-first
format.
CFR1 [7]: Digital Power-Down Bit
CFR1 [7] = 0 (default). All digital functions and clocks are active.
CFR1 [7] = 1. All non-I/O digital functionality is suspended,
lowering the power significantly.
CFR1 [22] = 0 (default). The manual synchronization feature is
inactive.
Rev. C | Page 16 of 28
Data Sheet
AD9952
CFR1 [6]: Comparator Power-Down Bit
CFR1 [6] = 0 (default). The comparator is enabled for operation.
CFR1 [6] = 1. The comparator is disabled and is in its lowest
power dissipation state.
CFR2 [11] = 1. The high speed sync enhancement is on. This bit
should be set when using the autosynchronization feature for
SYNC_CLK inputs beyond 50 MHz, (200 MSPS SYSCLK). See
the Synchronizing Multiple AD9952s section.
CFR2 [10]: Hardware Manual Sync Enable Bit
CFR1 [5]: DAC Power-Down Bit
CFR2 [10] = 0 (default). The hardware manual sync function is off.
CFR1 [5] = 0 (default). The DAC is enabled for operation.
CFR2 [10] = 1. The hardware manual sync function is enabled.
While this bit is set, a rising edge on the SYNC_IN pin causes
the device to advance the SYNC_CLK rising edge by one
REFCLK cycle. Unlike the software manual sync enable bit, this
bit does not self-clear. Once the hardware manual sync mode is
enabled, it stays enabled until this bit is cleared (see the
Synchronizing Multiple AD9952 section).
CFR1 [5] = 1. The DAC is disabled and is in its lowest power
dissipation state.
CFR1 [4]: Clock Input Power-Down Bit
CFR1 [4] = 0 (default). The clock input circuitry is enabled for
operation.
CFR1 [4] = 1. The clock input circuitry is disabled and the
device is in its lowest power dissipation state.
CFR2 [9]: CRYSTAL OUT Enable Bit
CFR2 [9] = 0 (default). The CRYSTAL OUT pin is inactive.
CFR1 [3]: External Power-Down Mode
CFR1 [3] = 0 (default). Selects the external rapid recovery
power-down mode. In this mode, when the PWRDWNCTL
input pin is high, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, PLL, oscillator, and
clock input circuitry are not powered down.
CFR1 [3] = 1. Selects the external full power-down mode. In
this mode, when the PWRDWNCTL input pin is high, all
functions are powered down. This includes the DAC and PLL,
which take a significant amount of time to power up.
CFR2 [9] = 1. The CRYSTAL OUT pin is active. When active,
the crystal oscillator circuitry output drives the CRYSTAL OUT
pin, which can be connected to other devices to produce a
reference frequency. The oscillator responds to crystals in the
range of 20 MHz to 30 MHz.
CFR2 [8]: Not Used
CFR2 [7:3]: Reference Clock Multiplier Control Bits
CFR1 [2]: Not Used
This 5-bit word controls the multiplier value out of the clockmultiplier (PLL) block. Valid values are 4 decimal to 20 decimal
(0x04 to 0x14). Values entered outside this range bypass the
clock multiplier. See the Phase-Locked Loop (PLL) section.
CFR1 [1]: SYNC_CLK Disable Bit
CFR2 [2]: VCO Range Control Bit
CFR1 [1] = 0 (default). The SYNC_CLK pin is active.
This bit is used to control the range setting on the VCO.
CFR2 [2] = 0 (default). The VCO operates in a range of 100
MHz to 250 MHz.
CFR1 [1] = 1. The SYNC_CLK pin assumes a static Logic 0
state to keep noise generated by the digital circuitry at a
minimum. However, the synchronization circuitry remains
active (internally) to maintain normal device timing.
CFR2 [2] = 1. The VCO operates in a range of 250 MHz to
400 MHz.
CFR1 [0]: Not Used, Leave at 0
CFR2 [1:0]: Charge Pump Current Control Bits
Control Function Register 2 (CFR2)
These bits are used to control the current setting on the charge
pump. The default setting, CFR2 [1:0], sets the charge pump
current to the default value of 75 µA. For each bit added (Bit 01,
Bit 10, and Bit 11), 25 µA of current is added to the charge
pump current: 100 µA, 125 µA, and 150 µA.
The CFR2 bits control the functions, features, and modes of the
AD9952, primarily related to the analog sections of the chip.
CFR2 [23:12]: Not Used
CFR2 [11]: High Speed Sync Enable Bit
CFR2 [11] = 0 (default). The high speed sync enhancement is off.
Rev. C | Page 17 of 28
AD9952
Data Sheet
OTHER REGISTER DESCRIPTIONS
PROGRAMMING FEATURES
Amplitude Scale Factor (ASF)
Phase Offset Control
The ASF register stores the 2-bit auto ramp rate speed value
and the 14-bit amplitude scale factor used in the output shaped
keying (OSK) operation. In auto OSK operation, ASF [15:14]
tell the OSK block how many amplitude steps to take for each
increment or decrement. ASF [13:0] sets the maximum value
for the OSK internal multiplier. In manual OSK mode, ASF
[15:14] have no effect. ASF [13:0] provide the output scale
factor directly. If the OSK enable bit is cleared, CFR1 [25] = 0,
this register has no effect on device operation.
A 14-bit phase offset (θ) can be added to the output of the phase
accumulator by means of the control registers. This feature
provides the user with two different methods of phase control.
Amplitude Ramp Rate (ARR)
The ARR register stores the 8-bit amplitude ramp rate used in
the auto OSK mode. This register programs the rate at which
the amplitude scale factor counter increments or decrements. If
the OSK is set to manual mode, or if OSK enable is cleared, this
register has no effect on device operation.
Frequency Tuning Word 0 (FTW0)
The frequency tuning word is a 32-bit register that controls the
rate of accumulation in the phase accumulator of the DDS core.
Its specific role depends on the device mode of operation.
Phase Offset Word (POW)
The phase offset word is a 14-bit register that stores a phase
offset value. This offset value is added to the output of the phase
accumulator to offset the current phase of the output signal. The
exact value of phase offset is given by the following formula:
POW
Φ = 14 × 360°
2
The first method is a static phase adjustment, where a fixed
phase offset is loaded into the appropriate phase offset register
and left unchanged. The result is that the output signal is offset
by a constant angle relative to the nominal signal. This allows
the user to phase align the DDS output with some external
signal, if necessary.
In the second method of phase control, the user regularly
updates the phase offset register via the I/O port. By properly
modifying the phase offset as a function of time, the user can
implement a phase modulated output signal. However, both the
speed of the I/O port and the frequency of SYSCLK limit the
rate at which phase modulation can be performed.
The AD9952 allows for a programmable continuous zeroing of
the phase accumulator as well as a clear and release or
automatic zeroing function. Each feature is individually
controlled via the CFR1 bits. CFR1 [13] is the automatic clear
phase accumulator bit. CFR1 [10] clears the phase accumulator
and holds the value to 0.
Continuous Clear Bit
The continuous clear bit is simply a static control signal that,
when active high, holds the phase accumulator at 0 for the
entire time the bit is active. When the bit goes low, inactive, the
phase accumulator is allowed to operate.
Clear and Release Function
Or
When set, the auto-clear phase accumulator clears and releases
the phase accumulator upon receiving an I/O UPDATE. The
automatic clearing function is repeated for every subsequent
I/O UPDATE until the appropriate auto-clear control bit is
cleared.
Φ 14
POW =
×2
360°
where Φ is the desired phase offset, in degrees.
MODES OF OPERATION
Shaped On-Off Keying
Single-Tone Mode
In single-tone mode, the DDS core uses a single tuning word.
Whatever value is stored in FTW0 is supplied to the phase
accumulator. This value can only be changed manually, which is
done by writing a new value to FTW0 and by issuing an I/O
UPDATE. Phase adjustment is possible through the phase
offset register.
The shaped on-off keying function of the AD9952 allows the
user to control the ramp-up and ramp-down time of an on-off
emission from the DAC. This function is used in burst
transmissions of digital data to reduce the adverse spectral
impact of short, abrupt bursts of data.
Auto and manual shaped on-off keying modes are supported.
The auto mode generates a linear scale factor at a rate
determined by the amplitude ramp rate (ARR) register
controlled by an external pin (OSK). Manual mode allows the
user to directly control the output amplitude by writing the
scale factor value into the amplitude scale factor (ASF) register.
Rev. C | Page 18 of 28
Data Sheet
AD9952
The shaped on-off keying function can be bypassed (disabled)
by clearing the OSK enable bit (CFR1 [25] = 0).
The modes are controlled by two bits located in the most
significant byte of the control function register (CFR). CFR1
[25] is the shaped on-off keying enable bit. When CFR1 [25] is
set, the output scaling function is enabled and CFR1 [25]
bypasses the function. CFR1 [24] is the internal shaped on-off
keying active bit. When CFR1 [24] is set, internal shaped on-off
keying mode is active; when CFR1 [24] is cleared, external
shaped on-off keying mode is active. CFR1 [24] is a don’t care if
the shaped on-off keying enable bit (CFR1 [25]) is cleared. The
power-up condition of the shaped on-off keying is disabled
(CFR1 [25] = 0). Figure 23 shows the block diagram of the OSK
circuitry.
Auto Shaped On-Off Keying Mode Operation
The auto shaped on-off keying mode is active when CFR1 [25]
and CFR1 [24] are set. When auto shaped on-off keying mode is
enabled, a single-scale factor is internally generated and applied
to the multiplier input for scaling the output of the DDS core
block (see Figure 23). The scale factor is the output of a 14-bit
counter that increments/decrements at a rate determined by the
contents of the 8-bit output ramp rate register. The scale factor
increases if the OSK pin is high and decreases if the OSK pin is
low. The scale factor is an unsigned value such that all 0s
multiply the DDS core output by 0 (decimal) and 0x3FFF
multiplies the DDS core output by 16,383 (decimal).
To use the full amplitude (14-bits) with fast ramp rates, the
internally generated scale factor step size is controlled via the
ASF [15:14]. Table 6 describes the increment/decrement step
size of the internally generated scale factor per the ASF [15:14].
A special feature of this mode is that the maximum output
amplitude allowed is limited by the contents of the amplitude
scale factor register. This allows the user to ramp to a value less
than full scale.
Table 6. Auto Scale Factor Internal Step Size
ASF [15:14] (Binary)
00
01
10
11
OSK Ramp Rate Timer
The OSK ramp rate timer is a loadable down counter that
generates the clock signal to the 14-bit counter, which, in turn,
generates the internal scale factor. The ramp rate timer is loaded
with the value of the ASFR every time the counter reaches 1
(decimal). This load and countdown operation continues for as
long as the timer is enabled, unless the timer is forced to load
before reaching a count of 1.
If the load OSK timer bit (CFR1 [26]) is set, the ramp rate timer
is loaded upon an I/O UPDATE or upon reaching a value of 1.
The ramp timer can be loaded before reaching a count of 1 by
three methods.
The first method of loading is by changing the OSK input pin.
When the OSK input pin changes state, the ASFR value is
loaded into the ramp rate timer, which then proceeds to count
down as normal.
The second method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is if the load OSK timer bit
(CFR1 [26]) is set and an I/O UPDATE is issued.
The last method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is when going from the
inactive auto shaped on-off keying mode to the active auto
shaped on-off keying mode; that is, when the sweep enable bit is
being set.
DDS CORE
0
TO DAC
AUTO DESK
ENABLE
CFR1[24]
1
COS(X)
Increment/Decrement Size
1
2
4
8
OSK ENABLE
CFR[25]
OSK PIN
1
0
OUT
LOAD OSK TIMER
CFR1[26]
AMPLITUDE RAMP
RATE REGISTER
(ASF)
0
AMPLITUDE SCALE
FACTOR REGISTER
(ASF)
SYNC_CLK
1
HOLD
UP/DN
LOAD
INC/DEC ENABLE
DATA
EN
CLOCK
AUTO SCALE
FACTOR GENERATOR
RAMP RATE TIMER
Figure 23. On-Off Shaped Keying, Block Diagram
Rev. C | Page 19 of 28
03358-023
0
AD9952
Data Sheet
External Shaped On-Off Keying Mode Operation
The external shaped on-off keying mode is enabled by writing
CFR1 [25] to a Logic 1 and writing CFR1 [24] to a Logic 0. When
configured for external shaped on-off keying, the content of the
ASFR becomes the scale factor for the data path. The scale factors
are synchronized to SYNC_CLK via the I/O UPDATE
functionality.
SYNCHRONIZING MULTIPLE AD9952s
The AD9952 product allows easy synchronization of multiple
AD9952s. There are three modes of synchronization available to
the user: an automatic synchronization mode, a software
controlled manual synchronization mode, and a hardware
controlled manual synchronization mode. In all cases, to
synchronize two or more devices, the following considerations
must be observed. First, all units must share a common clock
source. Trace lengths and path impedance of the clock tree must
be designed to keep the phase delay of the different clock
branches as closely matched as possible. Second, the I/O
UPDATE signal’s rising edge must be provided synchronously
to all devices in the system. Finally, regardless of the internal
synchronization method used, the DVDD_I/O supply should
be set to 3.3 V for all devices that are to be synchronized.
AVDD and DVDD should be left at 1.8 V.
In automatic synchronization mode, one device is chosen as a
master; the other devices are slaved to this master. When
configured in this mode, the slaves automatically synchronize their
internal clocks to the SYNC_CLK output signal of the master
device. To enter automatic synchronization mode, set the slave
device’s automatic synchronization bit (CFR1 [23] = 1). Connect
the SYNC_IN input(s) to the master SYNC_CLK output. The
slave device continuously updates the phase relationship of its
SYNC_CLK until it is in phase with the SYNC_IN input, which
is the SYNC_CLK of the master device. When attempting to
synchronize devices running at SYSCLK speeds beyond 250 MSPS,
the high speed sync enhancement enable bit should be set (CFR2
[11] = 1).
In software manual synchronization mode, the user forces the
device to advance the SYNC_CLK rising edge one SYSCLK cycle
(¼ SYNC_CLK period). To activate the manual synchronization
mode, set the slave device’s software manual synchronization bit
(CFR1 [22] = 1). The bit (CFR1 [22]) is cleared immediately. To
advance the rising edge of the SYNC_CLK multiple times, this bit
needs to be set multiple times.
In hardware manual synchronization mode, the SYNC_IN input
pin is configured such that it advances the rising edge of the
SYNC_CLK signal each time the device detects a rising edge on
the SYNC_IN pin. To put the device into hardware manual
synchronization mode, set the hardware manual synchronization
bit (CFR2 [10] = 1). Unlike the software manual synchronization
bit, this bit does not self-clear.
Once the hardware manual synchronization mode is enabled, all
rising edges detected on the SYNC_IN input cause the device to
advance the rising edge of the SYNC_CLK by one SYSCLK cycle
until this enable bit is cleared (CFR2 [10] = 0).
Using a Single Crystal to Drive Multiple AD9952 Clock
Inputs
The AD9952 crystal oscillator output signal is available on the
CRYSTAL OUT pin, enabling one crystal to drive multiple
AD9952s. To drive multiple AD9952s with one crystal, the
CRYSTAL OUT pin of the AD9952 using the external crystal
should be connected to the REFCLK input of the other AD9952.
The CRYSTAL OUT pin is static until the CFR2 [9] bit is set,
enabling the output. The drive strength of the CRYSTAL OUT
pin is typically very low, so this signal should be buffered prior
to using it to drive any loads.
SERIAL PORT OPERATION
The operations of the AD9952 are controlled by setup data and
parameters loaded into the device by means of a serial I/O port.
The internal control structure is organized as a series of
registers. Each register is double-buffered. New data is first
stored in I/O buffers as it is received. Subsequently, the data is
transferred to the internal registers that actually control the
device operation. While the I/O buffers are receiving new data,
the old data that is already in the control registers continues to
be used until the I/O buffers are transferred into the control
registers. The transfer from I/O buffer to control registers
requires an I/O update event. This event is triggered by sending
a pulse to the I/O UPDATE pin.
Step 1: Writing Data Through the Serial I/O Port to the
I/O Buffers
There are two phases to a serial I/O communication cycle:
•
Phase 1: Instruction (one byte)
•
Phase 2: Data (one or more bytes)
Phase 1 is the instruction byte, clocked in by the first eight
rising edges of SCLK. This single byte provides the AD9952
serial port controller with the information that it needs
regarding the upcoming data phase, Phase 2. This information
tells the serial port controller whether the data is a read or a
write operation, as well as the address of the intended register.
Once the controller knows the register address, the number of
bytes of data to be expected is calculated automatically.
The number of bytes transferred during Phase 2 depends on the
particular register being accessed. For example, when the Control
Function Register 2 is accessed, the data consists of three bytes (or
24 bits). However, if the Frequency Tuning Word 0 register is
accessed, the data is four bytes (or 32 bits). Step 1 is complete
when both the instruction byte and the required number of data
bytes are written to or read from.
Rev. C | Page 20 of 28
Data Sheet
AD9952
Instruction Byte Details
The instruction byte contains the following information.
(MSB)
D7
R/W
D6
X
D5
X
D4
A5
D3
A4
D2
A3
D1
A2
(LSB)
D0
A1
R/W—Bit 7 of the instruction byte determines whether a read or
write data transfer occurs after the instruction byte write. Logic
High indicates a read operation; a Logic 0 indicates a write
operation.
X, X—Bit 6 and Bit 5, respectively, of the instruction byte are
don’t care.
SYNC_CLK
I/O UPDATE
TSU
DVDD I/O =
3.3V
1.8V
I/O UPDATE TO
SYNC_CLK SETUP TIME =
4ns
6ns
Figure 24. Setup Time for I/O Update Pulse for Synchronous Data Transfer
To transfer data without having to monitor the SYNC_CLK
signal and without having to guarantee setup time, an alternate
method is to provide an I/O update pulse for more than one
SYNC_CLK period (more than four SYSCLK periods)
asynchronously. If this is done, the I/O update pulse overlaps
with at least one SYNC_CLK rising edge. However, there is no
guarantee of which SYNC_CLK rising edge transfers the I/O
buffer data to the registers. This method introduces an
ambiguity of one SYNC_CLK cycle (four SYSCLK cycles) in the
calculation of the propagation delay and should be avoided if
propagation delay of data transfers is an important
consideration. This method is shown in Figure 25.
SYNC_CLK
I/O UPDATE
I/O UPDATE HIGH PULSE GREATER THAN 1 SYNC_CLK PERIOD
A5, A4, A3, A2, A1—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0,
respectively, of the instruction byte determine which register is
accessed during the data transfer portion of the communication
cycle.
Step 2: Transfer of I/O Buffers to Registers
03358-025
All data written into the serial port is clocked into the I/O
buffer on the rising edge of SCLK. All data read back from the
serial port is clocked out on the falling edge of SCLK. Note that
the readback operation reads data from registers, not the I/O
buffers. If new data has been written to an I/O buffer, but an
I/O update has not occurred, the old data stored in the register
is read back (see Step 2: Transfer of I/O Buffers to Registers).
Also, the serial I/O port speed of 25 Mbps refers solely to the
speed of SCLK during a write operation. As the AD9952 does
not generate data, the readback operation is considered a debug
feature and is not supported beyond 1 Mbps.
As shown in Figure 24, the I/O update pulse is sampled
synchronously by the AD9952 on the rising edge of
SYNC_CLK. Therefore, the I/O update pulse needs to be set up
to the rising edge of the SYNC_CLK signal.
03358-026
After the completion of Phase 2, the AD9952 serial port
controller expects the next eight SCLK rising edges to be a new
instruction byte, followed by an appropriate number of data
bytes. See the Example Operation section of this document for
details.
Figure 25. I/O Update Pulse in Asynchronous Data Transfer
It should be noted that the exact transfer of data from the I/O
buffers to the registers actually occurs one SYNC_CLK cycle
after the I/O update signal is detected by the AD9952, as shown
in Figure 26.
When the desired setup data is written via the serial port to the I/O
buffers, the registers must be updated by issuing an I/O update
signal on the I/O UPDATE pin. The I/O update signal consists of a
logic high pulse (DVDD_I/O) on the I/O UPDATE pin.
Rev. C | Page 21 of 28
AD9952
Data Sheet
SYSCLK
A
B
A
B
SYNC_CLK
I/O UPDATE
DATA IN
REGISTERS
DATA 1
DATA 2
DATA 3
DATA 0
DATA 1
DATA 2
03358-031
DATA IN
I/O BUFFERS
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE I/O BUFFERS AT POINT B.
Figure 26. Timing of I/O Update Signal vs. Actual Register Update
Serial Interface Port Pin Description
●●●
SCLK
●●●
●●●
SDIO
TCSU
TDSU
TDH
DVDD I/O = 3.3V
DVDD I/O = 1.8V
TCSU = 3ns
TDSU = 3ns
TDH = 0ns
TCSU = 5ns
TDSU = 5ns
TDH = 0ns
TDH
03358-032
CS—Chip Select Bar. CS is active low input that allows more
than one device on the same serial communication line. The
SDO pin and SDIO pin go to a high impedance state when this
input is high. If driven high during any communication cycle,
the cycle is suspended until CS is reactivated low. Chip select
can be tied low in systems that maintain control of SCLK.
When toggling CS, it is important that care is taken to meet the
clock setup time with respect to the falling edge of CS and TCSU
(see Figure 27).
CS
Figure 27. Serial Port I/O Setup (TCSU, TDSU) and Hold (TDH) Times
SCLK
SDIO—Serial Data I/O. Data is always written into the AD9952
on this pin. However, this pin can be used as a bidirectional
data line. Bit 9 of Register 0x00 controls the configuration of
this pin. The default is Logic 0, which configures the SDIO pin
as bidirectional. In order to guarantee proper serial I/O port
operation (see Figure 27), data on this pin must be set up and held
to the rising edge of SCLK on read operations.
SDIO
SDO
TDV = 25ns
03358-033
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9952 and to run the internal state
machines. SCLK maximum frequency is 25 MHz.
Figure 28. Serial Port I/O Data Valid Time (TDV) During Readback
MSB/LSB Transfers
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In
the case where the AD9952 operates in a single bidirectional
I/O mode, this pin does not output data and is set to a high
impedance state.
The AD9952 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. The
control register, Register 0x00, Bit 8, controls this functionality.
The default value of Register 0x00 [8] is low (MSB first).
IOSYNC—Synchronizes the I/O port state machines without
affecting the registers’ contents. An active high input on the
IOSYNC pin causes the current communication cycle to abort.
After IOSYNC returns low (Logic 0), another communication
cycle can begin, starting with the instruction byte write.
When the control register (0x00 [8]) is set high, the AD9952
serial port is in LSB-first format. The instruction byte must be
written in the format indicated by the control register (0x00
[8]), and the instruction byte must be written from least
significant bit to most significant bit (right to left in the table
located in the Instruction Byte Details section).
Note that even in LSB-first mode, the two respective phases of
the communication cycle, the instruction byte phase and the
data communication phase, retain their respective positions.
Rev. C | Page 22 of 28
Data Sheet
AD9952
When in LSB-first mode, the device reads the instruction byte
first (LSB to MSB), then calculates the expected number of
bytes from the address provided, and then receives/provides
data from the referenced register in LSB-first format (LSB to
MSB of the register selected).
Example Operation
In this example, the amplitude scale factor is calculated and
written to present a 45° phase offset on the output of the
AD9952. First, the default MSB-first case is considered. Then,
the alternate LSB-first method is presented. For the purpose of
the example, the following assumptions are made:
•
The microcontroller is currently meeting the setup and
hold times for the serial I/O port (this is a software only
example).
•
The phase offset change needs to occur at a known point
in time (the data transfer needs to be synchronous).
•
No other values are written or altered during the example.
MSB-First Mode (Default) Case
First, the phase offset word (POW) needs to be calculated. Per
the formula in the Phase Offset Word (POW) section, the POW
is calculated to be 45/360 × 214 or 2048 (h’800).
Next, the instruction byte to write to the POW needs to be sent.
The first bit is 0, to indicate a write. The next two bits are don’t
care bits, and are set to 0. The last 5 bits correspond to the POW
address, which is h’05. This makes the instruction byte:
b’00001001.
Next, the data calculated in Step 1 is sent to the part. The POW
is 2 bytes wide. To make the 14-bit value fit into the 16-bit
register, the 2 MSBs are padded with don’t care bits. In this
example, the don’t care bits are assumed to be 0. The 2 data
bytes therefore are b’00001000 00000000.
Once the 24 bits of data are sent to the part (8 bits of instruction
byte and 16 bits of data), the phase offset word I/O buffer is
changed, but the change has not been made in the phase offset
word (POW) register. As no other data is being written in this
example, the I/O update pulse, which is 1.5 SYNC_CLK cycles
in duration, is sent to the I/O update pin. This transfers the data
from the POW I/O buffer to the POW register.
LSB First Mode Case
The values calculated in the MSB-first mode case are still valid.
The order of the bits in the instruction byte and in the data
bytes for the POW need to be reversed.
Finally, as before, the I/O update pin is pulsed with a high signal
for duration of 1.5 SYNC_CLK cycles, to transfer the contents
of the POW I/O buffer to the POW register.
POWER-DOWN FUNCTIONS
The AD9952 supports an externally controlled or hardware
power-down feature as well as the more common software
programmable power-down features found in other Analog
Devices DDS products.
The software control power-down allows the DAC, comparator,
PLL, input clock circuitry, and digital logic to be individually
powered down via unique control bits (CFR1 [7:4]). With the
exception of CFR1 [6], these bits are not active when the
externally controlled power-down pin (PWRDWNCTL) is high.
External power-down control is supported on the AD9952 via
the PWRDWNCTL input pin.
When the PWRDWNCTL input pin is high, the AD9952 enters
a power-down mode based on the CFR1 [3] bit. When the
PWRDWNCTL input pin is low, the external power-down
control is inactive.
When the CFR1 [3] bit is 0 and the PWRDWNCTL input pin is
high, the AD9952 is put into a fast recovery power-down mode.
In this mode, the digital logic and the DAC digital logic are
powered down. The DAC bias circuitry, comparator, PLL,
oscillator, and clock input circuitry is not powered down. The
comparator can be individually powered down by setting the
comparator power-down bit, CFR1 [6] = 1.
When the CFR1 [3] bit is high, and the PWRDWNCTL input
pin is high, the AD9952 is put into the full power-down mode.
In this mode, all functions are powered down. This includes the
DAC and PLL, which take a significant amount of time to
power up.
When the PWRDWNCTL input pin is high, the individual
power-down bits (CFR1 [7] and CFR1 [5:4]) are invalid (don’t
care) and unused. When the PWRDWNCTL input pin is low, the
individual power-down bits control the power-down modes of
operation.
Note that the power-down signals are all designed such that a
Logic 1 indicates the low power mode and a Logic 0 indicates
the active or power-up mode.
Table 7 indicates the logic level for each power-down bit that
drives out of the AD9952 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
First, the instruction byte is sent. Because the part is now in
LSB-first mode, the value sent is b’10010000.
Next, the data bytes are sent in LSB-first mode: b’00000000
00010000.
Rev. C | Page 23 of 28
AD9952
Data Sheet
Table 7. Power-Down Control Functions
Control
PWRDWNCTL = 0 CFR1 [3] don’t care
Mode Active
Software control
PWRDWNCTL = 1 CFR1 [3] = 0
External control,
fast recovery power-down mode
PWRDWNCTL = 1 CFR1 [3] = 1
External control,
full power-down mode
Rev. C | Page 24 of 28
Description
Digital power-down = CFR1 [7]
Comparator power-down = CFR1 [6]
DAC power-down = CFR1 [5]
Input clock power-down = CFR1 [4]
Digital power-down = 1’b1
Comparator power-down = 1’b0 or CFR1 [6]
DAC power-down = 1’b0
Input clock power-down = 1’b0
Digital power-down = 1’b1
Comparator power-down = 1’b1
DAC power-down = 1’b1
Input clock power-down = 1’b1
Data Sheet
AD9952
LAYOUT CONSIDERATIONS
For the best performance, the following layout guidelines
should be observed. Always provide the analog power supply
(AVDD) and the digital power supply (DVDD) on separate
supplies, even if just from two different voltage regulators
driven by a common supply. Likewise, the ground connections
(AGND, DGND) should be kept separate as far back to the
source as possible (for example, separate the ground planes on a
localized board, even if the grounds connect to a common point
in the system). Bypass capacitors should be placed as close to
the supply pin as possible. Usually, a multitiered bypassing
scheme consisting of a small high frequency capacitor (100 pF)
placed close to the supply pin and progressively larger capacitors
(0.1 µF, 10 µF) placed further away from the actual supply source
works best.
Rev. C | Page 25 of 28
AD9952
Data Sheet
SUGGESTED APPLICATION CIRCUITS
MODULATED/
DEMODULATED
SIGNAL
AD9952
03358-027
RF/IF INPUT
LPF
REFCLK
Figure 29. Synchronized LO for Upconversion/Down Conversion
PHASE
COMPARATOR
LOOP
FILTER
VCO
AD9952
FILTER
03358-028
REF
SIGNAL
TUNING
WORD
Figure 30. Digitally Programmable Divide-by-N Function in PLL
TUNING WORD
IOUT
LPF
IOUT
LPF
AD9952 DDS
AD9952
03358-029
ON-CHIP
COMPARATOR
CMOS LEVEL CLOCK
Figure 31. Frequency Agile Clock Generator
FREQUENCY
TUNING
WORD
PHASE
OFFSET
WORD 1
I/I-BAR
BASEBAND
REFCLK
AD9952 DDS
IOUT
IOUT
LPF
REFCLK
CRYSTAL OUT
SYNC OUT
RF OUT
SYNC IN
AD9952 DDS
IOUT
IOUT
LPF
REFCLK
FREQUENCY
TUNING
WORD
PHASE
OFFSET
WORD 2
Q/Q-BAR
BASEBAND
Figure 32. Two AD9952s Synchronized to Provide I Carriers and
Q Carriers with Independent Phase Offsets for Nulling
Rev. C | Page 26 of 28
03358-030
CRYSTAL
Data Sheet
AD9952
OUTLINE DIMENSIONS
9.00
BSC SQ
1.20
MAX
BOTTOM VIEW
(PINS UP)
37
36
48
1
37
36
48
1
7.00
BSC SQ
PIN 1
3.50
SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
EXPOSED
PAD
12
13
VIEW A
25
24
25
24
0.50 BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
12
13
0.27
0.22
0.17 FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MS-026-ABC
011708-A
0.75
0.60
0.45
Figure 33. 48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9952YSVZ
AD9952YSVZ-REEL7
AD9954/PCBZ
1
Temperature
Range
–40°C to +105°C
–40°C to +105°C
Package Description
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
48-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
Evaluation Board Used for the AD9952
Z = RoHS Compliant Part.
Rev. C | Page 27 of 28
Ordering
Quantity
500
Package
Option
SV-48-4
SV-48-4
AD9952
Data Sheet
NOTES
©2003–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03358-0-2/17(C)
Rev. C | Page 28 of 28
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