Data Sheet
ADA4097-1/ADA4097-2
50 V, 130 kHz, 32.5 µA per Channel, Robust, Over-The-Top, Precision Op Amps
FEATURES
►
►
►
►
►
►
►
►
►
►
►
►
►
►
►
►
►
►
Battery and power supply monitoring
► Front-end amplifiers in abusive environments
► 4 mA to 20 mA transmitters
►
Ultrawide common-mode input range: −VS − 0.1 V to −VS + 70 V
Wide power supply voltage range: +3 V to +50 V (to ±25 V for
PSRR)
Low power supply current: 32.5 µA (typical)
Low input offset voltage: ±60 µV maximum
Low input offset voltage drift: ±1 µV/°C maximum (B grade)
Low input voltage noise
► 6 Hz typical 1/f noise corner
1000 nV p-p typical at 0.1 Hz to 10 Hz
GBP: 130 kHz typical for fTEST = 250 Hz
Slew rate: 0.1 V/µs typical at ΔVOUT = 4 V
Low power supply current shutdown: 20 µA maximum
Low input offset current: ±300 pA maximum
Large signal voltage gain: 120 dB minimum for ΔVOUT = 3.5 V
CMRR: 120 dB minimum at VCM = −0.1 V to +70 V
PSRR: 123 dB minimum at VSY = +3 V to ±25 V
Input overdrive tolerant with no phase reversal
±2 kV HBM and ±1.25 kV FICDM
Wide temperature range: −55°C to +150°C (H grade)
Shutdown feature available for single 6-lead TSOT and dual
10-lead LFCSP packages
APPLICATIONS
Industrial sensor conditioning
► Supply current sensing
TYPICAL APPLICATION CIRCUIT
►
GENERAL DESCRIPTION
The ADA4097-1/ADA4097-2 are single and dual robust, precision,
rail-to-rail input and output operational amplifiers (op amps) with
inputs that operate from −VS to +VS and beyond, which are referred
to in this data sheet as Over-The-Top™. The devices feature offset
voltages of 5 V
Input Current Noise
f = 100 Hz
Over-The-Top
f = 100 Hz, VCM > 5 V
DYNAMIC PERFORMANCE
Slew Rate
ΔVOUT = 4 V
TMIN < TA < TMAX
Gain Bandwidth Product (GBP) Test frequency (fTEST) = 250 Hz
TMIN < TA < TMAX
Phase Margin
Typ
±30
0.25
0.175
±100
±0.025
120
101
115
110
−0.1
120
114
96
90
H Grade
Typ
Max
Unit
±60
±130
±20
±60
±160
µV
µV
±60
±160
±60
±550
±1
±0.3
±10
1.5
2.25
1
10
±300
±5
±0.065
±0.095
±30
±60
±185
±60
±600
±1.5
±0.3
±25
1.5
2.5
1
10
±300
±10
±0.065
±0.2
µV
µV
µV
µV
µV/°C
nA
nA
µA
µA
µA
µA
pA
nA
µA
µA
dB
145
+70
108
±30
±0.1
±0.1
0.25
0.125
±100
±0.025
100
115
107
−0.1
120
112
96
86
1000
6
53
65
0.05
0.5
0.025
0.018
120
100
0.1
130
58
0.8
0.001
120
134
140
Min
0.025
0.015
120
100
145
134
+70
140
dB
dB
dB
V
dB
108
dB
dB
dB
1000
6
53
65
0.05
0.5
nV p-p
Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
0.1
V/µs
V/µs
kHz
kHz
Degrees
130
58
Rev. A | 3 of 31
Data Sheet
ADA4097-1/ADA4097-2
SPECIFICATIONS
Table 1.
B Grade
Test Conditions/Comments
1% Settling Time
0.1% Settling Time
Total Harmonic Distortion Plus
Noise (THD + N)
Channel Separation
INPUT CHARACTERISTICS
Input Resistance
ΔVOUT = ±2 V
ΔVOUT = ±2 V
f = 1 kHz, VOUT = 2 V p-p, RLOAD
= 10 kΩ, bandwidth = 80 kHz
f = 1 kHz, RLOAD = 2 kΩ
70
100
0.05
70
100
0.05
µs
µs
%
115
115
dB
Differential mode
Common mode
Differential mode, VCM > 5 V
Common mode, VCM > 5 V
Differential mode
Common mode
10
>1
60
>1
1
3
10
>1
60
>1
1
3
MΩ
GΩ
kΩ
GΩ
pF
pF
Over-The-Top
Input Capacitance
SHDN AND SHDNx PINS
Input Logic Low
Input Logic High
Response Time
Pull-Down Current
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
Output Voltage Swing High
Short-Circuit Current
Output Pin Leakage During
Shutdown
Min
Amplifier active, SHDN and
SHDNx pin voltage (VSHDN) <
−VS + 0.5 V, TMIN < TA < TMAX
Amplifier shutdown, VSHDN > −VS −VS + 1.5
+ 1.5 V, TMIN < TA < TMAX
Amplifier active to shutdown
Amplifier shutdown to active
VSHDN = −VS + 0.5 V, TMIN < TA <
TMAX
VSHDN = −VS + 1.5 V, TMIN < TA <
TMAX
Overdrive voltage (VOD4) =
30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, sink current (ISINK)
= 5 mA
TMIN < TA < TMAX
VOD = 30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, source current
(ISOURCE) = 5 mA
TMIN < TA < TMAX
ISOURCE
TMIN< TA < TMAX
ISINK
TMIN < TA < TMAX
VSHDN = −VS + 1.5 V
Typ
H Grade
Parameter
Supply Current per Channel
analog.com
Guaranteed by power supply
rejection ratio (PSRR)
Amplifier active
TMIN < TA < TMAX
Min
Typ
−VS + 0.5
2.5
100
0.6
Unit
−VS + 0.5
V
V
3
2.5
100
0.6
3
µs
µs
µA
0.3
2.5
0.3
2.5
µA
15
40
15
40
mV
240
45
325
240
50
325
mV
mV
400
5
15
700
mV
mV
mV
mV
1100
±100
mV
mA
mA
mA
mA
nA
±10
±10
µA
50
50
50
50
V
V
36
60
µA
µA
2.5
570
380
5
10
700
2.5
570
1000
20
10
35
10
Max
−VS + 1.5
30
20
6
35
6
40
±5
TMIN < TA < TMAX
POWER SUPPLY
Maximum Operating Voltage5
VSY Range
Max
3
32.5
±100
36
55
30
40
±5
3
32.5
Rev. A | 4 of 31
Data Sheet
ADA4097-1/ADA4097-2
SPECIFICATIONS
Table 1.
B Grade
Parameter
PSRR
THERMAL SHUTDOWN6
Temperature
Hysteresis
Operating Temperature
Test Conditions/Comments
Amplifier shutdown,VSHDN = −VS
+ 1.5 V
TMIN < TA < TMAX
VSY = +3 V to ±25 V
TMIN < TA < TMAX
Min
H Grade
Typ
Max
12
20
Min
Max
Unit
12
20
µA
22.5
µA
dB
dB
22.5
123
120
145
TJ
123
120
175
20
TA
Typ
145
175
20
−40
+125
−55
+150
°C
°C
°C
1
Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 1 are determined by test
capability and are not necessarily indicative of actual device performance.
2
Offset voltage drift is guaranteed through lab characterization and is not production tested.
3
Test accuracy is limited by high speed production test equipment repeatability. Bench measurements indicate that the input offset current in Over-The-Top configuration is
typically controlled to under 50 nA at +25°C and 100 nA over the −55°C < TA < +150°C temperature range.
4
VOD is +30 mV for VOUT high and −30 mV for VOUT low.
5
Maximum operating voltage is limited by the time-dependent dielectric breakdown (TDDB) of the on-chip capacitor oxides. The amplifier tolerates temporary transient
overshoot up to the specified absolute maximum rating, but the dc supply voltage must be limited to the maximum operating voltage.
6
Thermal shutdown is lab characterized only and is not tested in production.
±15 V SUPPLY
VCM = 0 V, SHDN pin (ADA4097-1) and SHDNx pins (ADA4097-2 for the 10-lead LFCSP only) are open, RLOAD = 499 kΩ to ground, and TA =
25°C, unless otherwise noted.
Table 2.
B Grade
Parameter
Test Conditions/Comments
Min
DC PERFORMANCE
VOS1
Input Offset Voltage Drift2
Input Bias Current (IB)
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
TMIN < TA < TMAX
analog.com
Max
±20
±60
±150
±60
±150
±1
±0.3
±10
±0.3
±10
±0.3
±5
±0.3
±5
±0.1
±0.1
±0.1
IOS
CMRR
Typ
±20
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
±0.1
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
VCM = −14.75 V to +13.25 V
TMIN < TA < TMAX
VCM = −15.1 V to +13.25 V
TMIN < TA < TMAX
VCM = −15.1 V to +55 V
TMIN < TA < TMAX
±0.1
117
109
117
93
117
101
H Grade
135
135
140
Min
Typ
Max
Unit
±20
±60
±175
±60
±175
±1.5
±0.3
±25
±0.3
±25
±0.3
±10
±0.3
±10
µV
µV
µV
µV
µV/°C
nA
nA
nA
nA
nA
nA
nA
nA
dB
dB
dB
dB
dB
dB
±20
±0.1
±0.1
±0.1
±0.1
±0.1
117
109
117
92
117
100
135
135
140
Rev. A | 5 of 31
Data Sheet
ADA4097-1/ADA4097-2
SPECIFICATIONS
Table 2.
B Grade
Parameter
Common-Mode Input Range
AOL
NOISE PERFORMANCE
Input Voltage Noise
Over-The-Top
Input Current Noise
Over-The-Top
DYNAMIC PERFORMANCE
Slew Rate
GBP
Phase Margin
1% Settling Time
0.1% Settling Time
THD + N
Channel Separation
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
SHDN AND SHDNx PINS
Input Logic Low
Input Logic High
Response Time
Pull-Down Current
OUTPUT CHARACTERISTICS
Output Voltage Swing Low
Output Voltage Swing High
analog.com
Test Conditions/Comments
Min
Guaranteed by CMRR tests
ΔVOUT = 25 V
TMIN < TA < TMAX
ΔVOUT = 25 V, RLOAD =10 kΩ
TMIN < TA < TMAX
−15.1
120
114
100
94
f = 0.1 Hz to 10 Hz
1/f noise corner
f = 100 Hz
f = 100 Hz, VCM > +VS
f =100 Hz
f = 100 Hz, VCM > +VS
ΔVOUT = 25 V
TMIN < TA < TMAX
fTEST = 250 Hz
TMIN < TA < TMAX
0.03
0.02
125
100
Differential mode
Common mode
Differential mode
Common mode
VOD3 = 30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, ISINK = 5 mA
TMIN < TA < TMAX
VOD = 30 mV, no load
TMIN < TA < TMAX
VOD = 30 mV, ISOURCE = 5 mA
TMIN < TA < TMAX
H Grade
Max
Min
+55
−15.1
120
112
100
90
150
108
1000
6
53
65
0.05
0.5
ΔVOUT = ±2 V
ΔVOUT = ±2 V
f = 1 kHz, VOUT = 5.6 V p-p, RLOAD =
10 kΩ, bandwidth = 80 kHz
f = 1 kHz, RLOAD = 2 kΩ
Amplifier active, VSHDN < −VS +
0.5 V
Amplifier shutdown, VSHDN > −VS +
1.5 V
Amplifier active to shutdown
Amplifier shutdown to active
VSHDN = −VS + 0.5 V, TMIN < TA <
TMAX
VSHDN = −VS + 1.5 V, TMIN < TA <
TMAX
Typ
0.1
0.03
0.015
125
100
Typ
Max
Unit
+55
V
dB
dB
dB
dB
150
108
1000
6
53
65
0.05
0.5
nV p-p
Hz
nV/√Hz
nV/√Hz
pA/√Hz
pA/√Hz
0.1
59
70
100
0.1
59
70
100
0.1
V/µs
V/µs
kHz
kHz
Degrees
µs
µs
%
115
115
dB
10
>1
1
3
10
>1
1
3
MΩ
GΩ
pF
pF
130
130
−VS + 0.5
−VS + 1.5
−VS + 0.5
−VS + 1.5
2.5
100
0.3
V
V
3
2.5
100
0.3
3
µs
µs
µA
0.6
2.5
0.6
2.5
µA
15
40
45
325
380
10
15
700
1000
15
40
50
325
400
10
20
700
1100
mV
mV
mV
mV
mV
mV
mV
mV
240
2.5
570
240
2.5
570
Rev. A | 6 of 31
Data Sheet
ADA4097-1/ADA4097-2
SPECIFICATIONS
Table 2.
B Grade
Parameter
Short-Circuit Current
POWER SUPPLY
Maximum Operating Voltage4
VSY Range
Supply Current per Channel
PSRR
THERMAL SHUTDOWN5
Temperature
Hysteresis
Operating Temperature
Test Conditions/Comments
Min
Typ
ISOURCE
TMIN < TA < TMAX
ISINK
TMIN < TA < TMAX
20
10
35
10
30
Guaranteed by PSRR
Amplifier active
TMIN < TA < TMAX
VSY = ±25 V
TMIN < TA < TMAX
Amplifier shutdown, VSHDN = −VS +
1.5 V
TMIN < TA < TMAX
VSY = 3 V to 50 V
TMIN < TA < TMAX
45
3
40
42
15
50
50
44
65
48
70
22.5
Min
Typ
20
6
35
6
30
123
120
145
3
40
42
15
123
120
175
20
−40
Max
50
50
44
70
48
75
22.5
V
V
µA
µA
µA
µA
µA
25
µA
dB
dB
145
175
20
+125
−55
Unit
mA
mA
mA
mA
45
25
TJ
TA
H Grade
Max
+150
°C
°C
°C
1
Thermoelectric voltages present in the high speed production test limit the measurement accuracy of this parameter. The limits shown in Table 2 are determined by test
capability and are not necessarily indicative of actual device performance.
2
Offset voltage drift is guaranteed through lab characterization and is not production tested.
3
VOD is +30 mV for VOUT high and −30 mV for VOUT low.
4
Maximum operating voltage is limited by the TDDB of the on-chip capacitor oxides. The amplifier tolerates temporary transient overshoot up to the specified absolute
maximum rating and the dc supply voltage must be limited to the maximum operating voltage.
5
Thermal shutdown is lab characterized only and is not tested in production.
analog.com
Rev. A | 7 of 31
Data Sheet
ADA4097-1/ADA4097-2
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage1
Transient
Continuous
Power Dissipation (PD)
Differential Input Voltage
±IN and ±INx Pin Voltage2
Continuous
Survival
±IN and ±INx Pin Current2
SHDN and SHDNx Pin Voltage3
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
TJ
Rating
60 V
50 V
See Figure 3
±80 V
−10 V to +80 V
−15 V to +80 V
10 mA
−0.3 V to +60 V
−65°C to +150°C
−55°C to +150°C
300°C
175°C
1
Maximum supply voltage is limited by the TDDB of the on-chip capacitor oxides. The amplifiers tolerate temporary transient overshoot up to the specified
transient maximum rating. The continuous operating supply voltage must be
limited to no more than 50 V.
2
±IN refers to the +IN and −IN pins on the ADA4097-1, and ±INx refers to the
+IN1, −IN1, +IN2, and −IN2 pins on the ADA4097-2.
3
SHDN is Pin 5 on the ADA4097-1, and SHDNx refers to the SHDN1 and
SHDN2 pins (Pin 5 and Pin 6, respectively) on the ADA4097-2 (10-lead
LFCSP).
Stresses at or above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating
only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.
TJ exceeding 125°C promotes accelerated aging. The ADA4097-1/
ADA4097-2 demonstrate ±25 V supply operation beyond 1000
hours at TA = 150°C.
MAXIMUM POWER DISSIPATION
The maximum safe PD on the devices is limited by the associated
rise in either TC or TJ on the die. At approximately TC = 150°C,
which is the glass transition temperature, the properties of the
plastic changes. Exceeding this temperature limit, even temporarily,
may change the stresses that the package exerts on the die, which
permanently shifts the parametric performance of the ADA4097-1/
ADA4097-2. Exceeding TJ = 175°C for an extended period may
result in changes in the silicon devices and may potentially cause
failure of the devices.
The PD on the package is the sum of the quiescent power dissipation and the power dissipated in the package due to the output load
drive. The quiescent power is expressed as VSY × ISY, where ISY is
the quiescent current.
analog.com
The PD due to the load drive depends on the application. The PD
due to load drive is calculated by multiplying the load current by
the associated voltage drop across the devices. RMS voltages and
currents must be used in these calculations.
Airflow increases heat dissipation, effectively reducing θJA. Additional metal that is directly in contact with the package leads from
metal traces through vias, ground, and power planes reduces θJA.
Figure 3 shows the maximum PD vs. TA for the single 6-lead TSOT
package on a JEDEC standard, 4‑layer board, with −VS connected
to a pad that is thermally connected to a printed circuit board (PCB)
plane. θJA values are approximations.
Figure 3. Maximum Power Dissipation vs. Ambient Temperature
THERMAL RESISTANCE
Thermal performance is directly linked to PCB design and operating
environment. Careful attention to PCB thermal design is required.
θJA is the junction to ambient thermal resistance, and θJC is the
junction-to-case thermal resistance.
Table 4. Thermal Resistance
Package Type
θJA
θJC
Unit
UJ-6
R-8
RM-8
05-08-1699
192
120
163
43
51
38
40
5.5
°C/W
°C/W
°C/W
°C/W
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD-sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charged device model (FICDM) per ANSI/ESDA/JEDEC JS-002.
Rev. A | 8 of 31
Data Sheet
ADA4097-1/ADA4097-2
ABSOLUTE MAXIMUM RATINGS
ESD Ratings for ADA4097-1/ADA4097-2
Table 5. ADA4097-1 6-Lead TSOT, ADA4097-2 8-Lead SOIC_N, ADA4097-2
8-Lead MSOP, and ADA4097-2 10-Lead LFCSP
ESD Model
Withstand Threshold (kV)
Class
HBM
FICDM
±2
±1.25
3A
3
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although
this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
analog.com
Rev. A | 9 of 31
Data Sheet
ADA4097-1/ADA4097-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration for the ADA4097-1 6-Lead TSOT
Table 6. Pin Function Descriptions for ADA4097-1 6-Lead TSOT
Pin No.
Mnemonic
Description
1
2
VOUT
−VS
3
4
5
+IN
−IN
SHDN
6
+VS
Amplifier Output.
Negative Power Supply. In single-supply applications, the −VS pin is normally soldered to a low impedance ground plane. In split-supply
applications, bypass the −VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the −VS pin as possible.
Noninverting Input of the Amplifier.
Inverting Input of the Amplifier.
Op Amp Shutdown. The threshold for shutdown is approximately 1 V above the negative supply. If the SHDN pin is hard tied to −VS or floating,
the amplifier is active. If the SHDN pin is asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state, and the output of the
amplifier goes to a high impedance state. If the SHDN pin is left floating, it is recommended to connect a small capacitor of 1 nF between the
SHDN pin and the −VS pin to prevent signals from the −IN pin from capacitively coupling to the SHDN pin.
Positive Power Supply. Bypass the +VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the +VS pin as
possible.
Figure 5. Pin Configuration for ADA4097-2 8-Lead SOIC_N and 8-Lead MSOP
Table 7. Pin Function Descriptions for ADA4097-2 8-Lead SOIC_N and 8-Lead MSOP
Pin No.
Mnemonic
Description
1
2
3
4
VOUT1
−IN1
+IN1
−VS
5
6
7
8
+IN2
−IN2
VOUT2
+VS
Amplifier Output, Channel 1.
Inverting Input of the Amplifier, Channel 1.
Noninverting Input of the Amplifier, Channel 1.
Negative Power Supply. In single-supply applications, the −VS pin is normally soldered to a low impedance ground plane. In split-supply
applications, bypass the −VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the −VS pin as possible.
Noninverting Input of the Amplifier, Channel 2.
Inverting Input of the Amplifier, Channel 2.
Amplifier Output, Channel 2.
Positive Power Supply. Bypass the +VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the +VS pin as
possible.
analog.com
Rev. A | 10 of 31
Data Sheet
ADA4097-1/ADA4097-2
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 6. Pin Configuration for ADA4097-2 10-Lead LFCSP
Table 8. Pin Function Descriptions for ADA4097-2 10-Lead LFCSP
Pin No.
Mnemonic
Description
1
2
3
4
VOUT1
−IN1
+IN1
−VS
5
SHDN1
6
SHDN2
7
8
9
10
+IN2
−IN2
VOUT2
+VS
Amplifier Output, Channel 1.
Inverting Input of the Amplifier, Channel 1.
Noninverting Input of the Amplifier, Channel 1.
Negative Power Supply. In single-supply applications, the −VS pin is normally soldered to a low impedance ground plane. In split-supply
applications, bypass the −VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the −VS pin as possible.
Op Amp Shutdown, Channel 1. The threshold for shutdown is approximately 1 V above the negative supply. If the SHDN1 pin is hard tied to the
−VS pin or floating, the amplifier is active. If the SHDN1 pin is asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state,
and the output of the amplifier goes to a high impedance state. If the SHDN1 pin is left floating, it is recommended to connect a small capacitor
of 1 nF between the SHDN1 pin and the −VS pin to prevent signals from the −INx pins from capacitively coupling to the SHDN1 pin.
Op Amp Shutdown, Channel 2. The threshold for shutdown is approximately 1 V above the negative supply. If the SHDN2 pin is hard tied to the
−VS pin or floating, the amplifier is active. If the SHDN2 pin is asserted high (VSHDN > −VS + 1.5 V), the amplifier is placed in a shutdown state,
and the output of the amplifier goes to a high impedance state. If the SHDN2 pin is left floating, it is recommended to connect a small capacitor
of 1 nF between the SHDN2 pin and the −VS pin to prevent signals from the −INx pins from capacitively coupling to the SHDN2 pin.
Noninverting Input of the Amplifier, Channel 2.
Inverting Input of the Amplifier, Channel 2.
Amplifier Output, Channel 2.
Positive Power Supply. Bypass the +VS pin with a capacitance of at least 0.1 μF to a low impedance ground plane, as close to the +VS pin as
possible.
Exposed Pad. Connect the exposed pad to −VS.
EPAD
analog.com
Rev. A | 11 of 31
Data Sheet
ADA4097-1/ADA4097-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. Supply Current vs. Supply Voltage
Figure 10. Shutdown Supply Current vs. Supply Voltage
Figure 8. Supply Current vs. Temperature Across Various Supply Voltages
Figure 11. Typical Distribution of Input Offset Voltage, VSY = 5 V
Figure 9. Supply Current vs. VSHDN with Respect to −VS
Figure 12. Typical Distribution of Input Offset Voltage with VSY = ±15 V
analog.com
Rev. A | 12 of 31
Data Sheet
ADA4097-1/ADA4097-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 13. Typical Distribution of Input Offset Voltage with VSY = ±25 V
Figure 16. Offset Voltage vs. Temperature with VSY = ±25 V
Figure 14. Midsupply Offset Voltage vs. Temperature with VSY = 5 V
Figure 17. Midsupply Input Bias Current vs. Temperature with VSY = 5 V
Figure 15. Offset Voltage vs. Temperature with VSY = ±15 V
Figure 18. Input Bias Current vs. Temperature with VSY = ±15 V
analog.com
Rev. A | 13 of 31
Data Sheet
ADA4097-1/ADA4097-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 19. Offset Voltage vs. Temperature with VCM = 6 V, Over-The-Top
Figure 22. Input Bias Current vs. Temperature with VCM = 6 V, Over-The-Top
Figure 20. Offset Voltage vs. Temperature with VCM = 70 V
Figure 23. Input Bias Current vs. Temperature Across Various VCM
Figure 21. Typical Distribution of Input Bias Current, VSY = 5 V
Figure 24. Input Bias Current vs. Temperature Across Various Supply
Voltages
analog.com
Rev. A | 14 of 31
Data Sheet
ADA4097-1/ADA4097-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 25. Offset Voltage vs. Temperature Across Various Supply Voltages
Figure 26. Offset Voltage vs. Input Common-Mode Voltage from
Normal Operation to Over-The-Top Operation
Figure 27. Offset Voltage vs. Input Common-Mode Voltage over
the Input Common-Mode Range
analog.com
Figure 28. Input Bias Current vs. Input Common-Mode Voltage from
Normal Operation to Over-The-Top Operation
Figure 29. Offset Voltage vs. Input Common-Mode Voltage for
Ground Sensing Applications
Figure 30. Input Bias Current vs. Input Common-Mode Voltage for Ground
Sensing Applications
Rev. A | 15 of 31
Data Sheet
ADA4097-1/ADA4097-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 31. Input Bias Current vs. Input Common-Mode Voltage
Figure 34. Offset Voltage vs. Supply Voltage
Figure 32. Supply Current vs. Minimum Supply Voltage
Figure 35. ΔOffset Voltage vs. VOUT Across Various RLOAD
Figure 33. Offset Voltage vs. Minimum Supply Voltage
Figure 36. ΔOffset Voltage vs. VOUT Across Various Temperatures
analog.com
Rev. A | 16 of 31
Data Sheet
ADA4097-1/ADA4097-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 37. SHDN/SHDNx Pin Current (ISHDN) vs. VSHDN with Respect to −VS
over Various Temperatures
Figure 40. Open-Loop Gain and Open-Loop Phase Margin vs. Frequency
Figure 41. Noninverting Small Signal Frequency Response
Figure 38. Output Swing Relative to Supply vs. Temperature
Figure 42. Inverting Small Signal Frequency Response
Figure 39. Gain Bandwidth vs. Temperature
analog.com
Rev. A | 17 of 31
Data Sheet
ADA4097-1/ADA4097-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 43. Output Noise vs. Frequency
Figure 46. Unity-Gain Large Signal Step Response
Figure 44. 0.1 Hz to 10 Hz Noise
Figure 47. THD + N vs. Frequency over Load
Figure 45. Unity-Gain Small Signal Step Response
Figure 48. THD + N vs. Output Amplitude
analog.com
Rev. A | 18 of 31
Data Sheet
ADA4097-1/ADA4097-2
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 49. THD + N vs. Output Amplitude and Load
Figure 52. Output Impedance vs. Frequency
Figure 50. CMRR vs. Frequency
Figure 51. PSRR vs. Frequency
analog.com
Rev. A | 19 of 31
Data Sheet
ADA4097-1/ADA4097-2
THEORY OF OPERATION
The ADA4097-1/ADA4097-2 are robust, voltage feedback amplifiers that combine unity-gain stability with low offset, low offset drift,
and 53 nV/√Hz of input voltage noise. Figure 55 shows a simplified
schematic of the devices. The ADA4097-1/ADA4097-2 have two
input stages: a common emitter differential input stage consisting of
the Q1 and Q2 PNP transistors that operate with the inputs biased
between −VS and 1 V below +VS, and a common base input stage
that consists of the Q3 to Q6 PNP transistors that operate when
the common-mode input is biased >+VS − 1 V. These input stages
result in two distinct operating regions, as shown in Figure 53.
the common emitter PNP input stage is active and the input bias
current is typically 15 V below −VS, at the
cost of stability and added thermal noise. The input stage of the
ADA4097-1/ADA4097-2 incorporates phase reversal protection to
prevent the output from phase reversing for inputs below −VS. The
ADA4097-1/ADA4097-2 op amp does not have clamping diodes
between the inputs and can be differentially over-driven up to 80 V
without damage, inducing parametric shifts, or drawing appreciable
input current. Figure 57 summarizes the input fault types that can
be applied to the ADA4097-1/ADA4097-2 without compromising
input integrity.
OVER-THE-TOP OPERATION
CONSIDERATIONS
When the ADA4097-1/ADA4097-2 input common-modes are biased
near or >+VS supply, the amplifiers operate in the Over-The-Top
configuration. The differential input pair that controls amplifier operation is the common base pair, Q3 to Q6 (see Figure 55).
Input bias currents change from
工商网监
湘ICP备2023018690号
